Electronic fuse, pre-charging circuit thereof and electronic fuse chip

Abstract

The invention discloses an electronic fuse, a pre-charging circuit thereof and an electronic fuse chip, the electronic fuse comprises a first power tube and a charge pump circuit, the first power tube is connected between a voltage input end and a voltage output end, and the voltage output end is connected with a capacitive load to supply power to the capacitive load. The input end of the charge pump circuit is connected with a voltage input end, the output end is used for outputting a first power supply voltage, the pre-charging circuit comprises a first current source, the power supply end of the first current source is connected with the output end of the charge pump circuit, and the current output end is connected with the control end of a first power tube; according to the first pulse signal, whether the charge pump circuit and the first current source are enabled or not is controlled so as to pre-charge the capacitive load, the charge pump circuit outputs first power supply voltage when being enabled, after the first current source is started, the first power tube is driven to be conducted so as to generate pre-charging current, and the pre-charging current pre-charges the capacitive load. According to the invention, the pre-charging of the large capacitive load can be safely realized.

Description

Technical Field

[0001] The present invention relates to the technical field of fuses, and in particular to an electronic fuse and a pre-charging circuit thereof, and an electronic fuse chip. Background Art

[0002] The electronic fuse of the prior art generally uses a P-type MOSFET (metal oxide semiconductor field effect transistor) connected between the voltage input terminal and the capacitive load to realize the pre-charging of the capacitive load. Figure 1 , Figure 1 A circuit structure diagram of an electronic fuse 100 of the prior art is shown. The electronic fuse 100 includes a first power tube Q1, a sampling resistor Rcs and an electronic fuse chip IC1. The first power tube Q1 and the sampling resistor Rcs are connected in series between a voltage input terminal and a voltage output terminal. The voltage of the voltage input terminal is an input voltage Vin, and the voltage of the voltage output terminal is an output voltage Vout. The voltage output terminal is connected to a capacitive load C1 to supply power to the capacitive load C1. The pre-charging circuit 11 in the electronic fuse chip IC1 includes a P-type MOSFET Q2, a resistor R1 and a switch S1. A first end of the P-type MOSFET Q2 is connected to the voltage input terminal, and a second end is connected to the voltage output terminal. One end of the switch S1 is connected to a control end of the P-type MOSFET Q2, and the other end is grounded. The conduction of the switch S1 is controlled by a control circuit 14, thereby controlling the conduction of the P-type MOSFET Q2 to generate a pre-charging current Iprec1 flowing through the P-type MOSFET Q2 to pre-charge the capacitive load C1.

[0003] However, when the capacitance of the capacitive load C1 increases, the pre-charge current Iprec1 needs to be further increased. However, due to the large on-resistance of the P-type MOSFET Q2, the P-type MOSFET Q2 will generate more heat, which may easily burn out the chip. Therefore, the pre-charge current Iprec1 cannot be, for example, above 300mA. If the capacitive load has a mF level capacitance, the existing solution requires multiple P-type MOSFETs to be connected in parallel for pre-charging, which leads to a surge in cost and volume, and is prone to burning out the chip due to heat problems. Therefore, a new solution is needed to realize the pre-charging function of the electronic fuse under large capacitive loads. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide an electronic fuse and a pre-charging circuit thereof, and an electronic fuse chip, so as to solve the technical problems existing in the prior art that multiple P-type MOSFETs need to be connected in parallel to pre-charge a larger capacitive load, which leads to a surge in cost and volume, and is prone to burning the chip due to heat problems.

[0005] The technical solution of the present invention is that, in a first aspect, a pre-charging circuit of an electronic fuse is provided, wherein the electronic fuse comprises a first power tube and a charge pump circuit, wherein the first power tube is connected between a voltage input terminal and a voltage output terminal, the voltage output terminal is connected to a capacitive load to supply power to the capacitive load, the input terminal of the charge pump circuit is connected to the voltage input terminal, and the output terminal is used to output a first power supply voltage, and the pre-charging circuit comprises:

[0006] A first current source, wherein a power supply end of the first current source is connected to an output end of the charge pump circuit, and a current output end is connected to a control end of the first power tube;

[0007] Whether the charge pump circuit and the first current source are enabled is controlled according to the first pulse signal to realize pre-charging of the capacitive load, wherein the charge pump circuit outputs the first supply voltage when enabled, and after the first current source is started, the first power tube is driven to conduct to generate a pre-charging current, and the pre-charging current is used to pre-charge the capacitive load.

[0008] Optionally, the charge pump circuit is enabled when the first pulse signal is in a first level state, and the first current source is enabled during at least a partial time period when the first pulse signal is in the first level state.

[0009] Optionally, the pre-charging circuit further includes:

[0010] A pre-charge control circuit is used to generate a pre-charge control signal according to the first pulse signal, and the control end of the first current source receives the pre-charge control signal so that the first current source is enabled during a time period when the first pulse signal is in a first level state and the pre-charge current is less than a pre-charge current threshold.

[0011] Optionally, the pre-charge current threshold is set according to the capacitance of the capacitive load.

[0012] Optionally, the electronic fuse further includes a current detection circuit, and the current detection circuit is used to output a current detection signal capable of representing a current flowing through the first power tube.

[0013] The pre-charge control circuit generates the pre-charge control signal according to the first pulse signal and the current detection signal to control the first current source to be enabled during a time period when the first pulse signal is in a first level state and the current detection signal is less than a first threshold, wherein when the current detection signal is equal to the first threshold, it indicates that the pre-charge current is equal to the pre-charge current threshold.

[0014] Optionally, the pre-charge control circuit includes:

[0015] a comparison circuit, wherein a first input terminal receives the current detection signal, a second input terminal receives the first threshold value, and an output terminal outputs a comparison signal according to a comparison result of the current detection signal and the first threshold value;

[0016] A logic circuit has a first input terminal receiving the first pulse signal, a second input terminal receiving the comparison signal, and an output terminal outputting the pre-charge control signal.

[0017] Optionally, the logic circuit includes:

[0018] A counting circuit, wherein a set terminal receives the comparison signal, a reset terminal receives the first pulse signal, and an output terminal outputs a counting signal, wherein the counting signal is set to 1 in response to a jump of the comparison signal when the current detection signal rises to the first threshold value, and is reset to zero in response to a jump of the first pulse signal from a first level state to a second level state;

[0019] A logic subcircuit outputs the precharge control signal according to the first pulse signal and the counting signal, wherein the precharge control signal controls the first current source to be enabled during a time period when the first pulse signal is in a first level state and the counting signal is 0.

[0020] Optionally, the logic circuit includes:

[0021] A trigger, a first end receives the first pulse signal, a second end receives the comparison signal, and an output end outputs the pre-charge control signal, the pre-charge control signal flips to a level state for controlling the first current source to be enabled in response to the first pulse signal jumping to a first level state, and flips to a level state for controlling the first current source to be turned off in response to the comparison signal jumping when the current detection signal rises to the first threshold.

[0022] Optionally, the pre-charging circuit further includes:

[0023] The selection circuit has an input terminal receiving at least two different thresholds and an output terminal outputting the first threshold. The selection circuit selects one of the at least two different thresholds as the first threshold output.

[0024] Optionally, the pre-charge control circuit generates the pre-charge control signal based on the first pulse signal and a first time threshold, and the pre-charge control signal controls the first current source to be enabled during a time period when the first pulse signal is in a first level state and the duration of the first level state is less than the first time threshold, wherein when the duration of the first pulse signal in the first level state is equal to the first time threshold, the corresponding pre-charge current is equal to the pre-charge current threshold.

[0025] Optionally, at least part of the pre-charging circuit is integrated into an electronic fuse chip.

[0026] The electronic fuse chip comprises a pre-charging pin. When the capacitive load needs to be pre-charged, the first pulse signal is input to the pre-charging pin.

[0027] Optionally, when the electronic fuse chip is in standby mode, the first pulse signal is input to the pre-charge pin.

[0028] Optionally, the capacitance of the capacitive load is greater than or equal to 1 mF.

[0029] In a second aspect, the present invention further provides an electronic fuse chip, wherein the electronic fuse chip includes at least a portion of the circuit in the pre-charging circuit.

[0030] In a third aspect, the present invention further provides an electronic fuse, wherein the electronic fuse comprises the pre-charging circuit.

[0031] Compared with the prior art, the circuit structure of the present invention has the following advantages: the first pulse signal is used to control whether the first current source in the charge pump circuit and the pre-charging circuit is enabled to realize pre-charging of the capacitive load; after the first current source is started, the first power tube is driven to conduct to generate a pre-charging current for pre-charging the capacitive load C1; since the pre-charging current is the current flowing through the first power tube, the pre-charging current can be set to be large enough to safely realize pre-charging of a large capacitive load; and the pre-charging circuit of the present invention can start to provide the first pulse signal when the electronic fuse chip is in the standby mode to realize pre-charging, which greatly improves the flexibility of the pre-charging application of the electronic fuse. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of the circuit structure of an electronic fuse in the prior art;

[0033] Figure 2 is a schematic diagram of a circuit structure of an electronic fuse according to an embodiment of the present invention;

[0034] Figure 3Schematic diagram of the circuit structure of the pre-charging circuit of the first embodiment of the present invention;

[0035] Figure 4 Schematic diagram of the circuit structure of a pre-charging circuit according to a second embodiment of the present invention;

[0036] Figure 5 Based on Figure 4 A first circuit structure schematic diagram of a logic circuit;

[0037] Figure 6 Based on Figure 4 A second circuit structure schematic diagram of a logic circuit;

[0038] Figure 7a Based on Figure 5 or Figure 6 A schematic diagram of a waveform diagram;

[0039] Figure 7b Based on Figure 5 or Figure 6 Another waveform diagram of ;

[0040] Figure 8 Based on Figure 4 A third circuit structure diagram of a logic circuit;

[0041] Fig. 9 Schematic diagram of the circuit structure of a pre-charging circuit according to a third embodiment of the present invention;

[0042] Fig.10 Schematic diagram of the circuit structure of a pre-charging circuit according to a fourth embodiment of the present invention;

[0043] Fig.11a Based on Fig.10 A schematic diagram of a waveform diagram;

[0044] Fig.11b Based on Fig.10 Another waveform diagram of . DETAILED DESCRIPTION

[0045] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, but the present invention is not limited to these embodiments. The present invention covers any substitution, modification, equivalent method and scheme made within the spirit and scope of the present invention.

[0046] In order to make the public have a thorough understanding of the present invention, specific details are described in detail in the following preferred embodiments of the present invention, but those skilled in the art can fully understand the present invention without these detailed descriptions.

[0047] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. It should be noted that the accompanying drawings are all simplified and not in exact proportion, and are only used for the purpose of conveniently and clearly assisting in explaining the embodiments of the present invention.

[0048] First, please refer again to Figure 1 In the prior art, the electronic fuse chip IC1 includes, in addition to the pre-charging circuit 11, a charge pump circuit 12, a current detection circuit 13, a control circuit 14 and a second drive circuit 15. The input end of the charge pump circuit 12 is connected to the voltage input end to receive the input voltage Vin, and the output end is used to generate a first power supply voltage Vcp. When the charge pump circuit 12 is working, the charge pump circuit 12 performs a voltage boosting process to output a first power supply voltage Vcp with a voltage value higher than the input voltage Vin; the current detection circuit 13 is used to output a current detection signal CS, wherein the current detection signal CS is a signal representing the current flowing through the first power tube. For example, the current detection circuit 13 outputs the current detection signal CS by detecting the voltage across the sampling resistor Rcs; the power supply voltage is provided to the control circuit 14 through the VDD pin. When the electronic fuse chip IC1 is in the working mode, the control circuit 14 receives the current detection signal CS and generates a control signal. The first power supply voltage Vcp is used as the power supply voltage of the second drive circuit 15. The second drive circuit 15 receives the control signal and generates a signal for driving the first power tube Q1.

[0049] Figure 2 The circuit structure diagram of the electronic fuse 200 according to an embodiment of the present invention is shown. The electronic fuse 200 includes a first power tube Q1, a sampling resistor Rcs and an electronic fuse chip IC2. The first power tube Q1 and the sampling resistor Rcs are connected in series between the voltage input terminal and the voltage output terminal. The voltage at the voltage input terminal is the input voltage Vin, and the voltage at the voltage output terminal is the output voltage Vout. The voltage output terminal is connected to a capacitive load C1 to supply power to the capacitive load. One end of the capacitive load C1 receives the output voltage Vout, and the other end is grounded. The electronic fuse chip IC2 includes a pre-charging circuit 21, a charge pump circuit 22, a current detection circuit 23, a control circuit 24, and a second drive circuit 25. Comparison Figure 1It can be seen that the main difference between the electronic fuse chip IC2 of the present invention and the prior art is that the pre-charging circuit 21 and the charge pump circuit 22 are different from the prior art, and an additional pre-charging pin (i.e., PREC pin) is added. The pre-charging circuit 21 includes a first current source 211, the power supply end of the first current source 211 is connected to the output end of the charge pump circuit 22, and the current output end is connected to the control end of the first power tube Q1; when the capacitive load C1 needs to be pre-charged, a first pulse signal PWM is input to the pre-charging pin, and the charge pump circuit 22 and the first current source 211 are controlled to be enabled according to the first pulse signal PWM to achieve pre-charging of the capacitive load C1, wherein the charge pump circuit 22 outputs the first power supply voltage Vcp when enabled, and after the first current source 211 is started, the first power tube Q1 is driven to conduct to generate a pre-charging current Iprec2, and the pre-charging current Iprec2 is used to pre-charge the capacitive load C1. Further, the charge pump circuit 22 receives the first pulse signal PWM and is enabled when the first pulse signal PWM is in a first level state, and the first current source 211 is enabled during at least a portion of the time period when the first pulse signal PWM is in the first level state. Wherein, when the charge pump circuit 22 is enabled (working), the charge pump circuit 22 performs a voltage boost process to output a first power supply voltage Vcp having a voltage value higher than the input voltage Vin. By way of example, the first power tube Q1 includes an N-type MOSFET, the drain of the first power tube Q1 is connected to the voltage input terminal, the source is connected to the voltage output terminal, and the gate (i.e., the control terminal) is connected to the current output terminal of the first current source 211. After the first current source 211 is started, the gate-source voltage V GS When the gate-source voltage V GS When the current rises to the threshold voltage of the first power tube Q1, the first power tube Q1 is turned on. In addition, the current detection circuit 23, the control circuit 24, and the second drive circuit 25 in the electronic fuse chip IC2 are connected to the Figure 1The current detection circuit 13, the control circuit 14, and the second drive circuit 15 in the prior art shown are basically the same, and will not be repeated here. Since the pre-charging current Iprec2 in the present invention is the current flowing through the first power tube Q1, the pre-charging current Iprec2 can be set to be large enough to safely realize the pre-charging of a large capacitive load of mF level (for example, greater than or equal to 1mF). In addition, the present invention controls whether the charge pump circuit 22 and the first current source 211 are enabled according to the first pulse signal PWM to realize the pre-charging of the capacitive load C1, so it is not necessary to realize the pre-charging only when the electronic fuse chip IC1 is in the normal working mode (the charge pump circuit 12 continuously outputs the first power supply voltage Vcp, and the control circuit 14 works) as in the prior art. By using the technical solution of the present invention, the first pulse signal can be input to the pre-charging pin when the electronic fuse chip IC2 is in the standby mode (the charge pump circuit 22 is not enabled, and the control circuit 24 is not working) to realize the pre-charging, and the pre-charging circuit 21 can work under the condition that the control circuit 24 is not working, which greatly improves the flexibility of the electronic fuse pre-charging application.

[0050] It should be noted that Figure 2 The circuit structure shown is only an example and does not constitute a limitation to the present application. For example, in some other embodiments, the first power tube Q1 may be a GaN transistor, a SiC transistor, etc. in addition to a MOSFET; in some other embodiments, the sampling resistor Rcs and / or the first power tube Q1 may also be integrated into the electronic fuse chip IC2; in some other embodiments, the electronic fuse 200 may also not include the sampling resistor Rcs, and the first power tube Q1 is connected between the voltage input terminal and the voltage output terminal, and a sampling transistor (not shown in the figure) that forms a proportional current mirror with the first power tube Q1 is provided, and the current detection circuit 23 detects the current by The current passing through the sampling transistor is used to output a current detection signal CS; in some other embodiments, the VDD pin may not be set, but a linear voltage regulator circuit (not shown in the figure) may be set, the input end of the linear voltage regulator circuit is connected to the voltage input end to receive the input voltage Vin, and the output end is used to output a voltage signal for powering the control circuit 24; in some other embodiments, the charge pump circuit 22 may be set outside the electronic fuse chip IC2, or only part of the circuit of the charge pump circuit 22 may be integrated into the electronic fuse chip IC2; in some other embodiments, only part of the circuit of the pre-charge circuit 21 may be integrated into the electronic fuse chip IC2; and so on.

[0051] The circuit structure of the pre-charging circuit 21 is described below. Figure 3As shown, the pre-charging circuit 21 of the first embodiment of the present invention only includes a first current source 211. In one embodiment, the control end of the first current source 211 can be set to receive the first pulse signal PWM to control the first current source 211 to be enabled when the first pulse signal PWM is in the first level state. Of course, in another embodiment, the first current source 211 may not receive the first pulse signal PWM, but the charge pump circuit 22 is enabled when the first pulse signal PWM is in the first level state during the period when the charge pump circuit 22 receives the first pulse signal PWM, and outputs the first power supply voltage Vcp when enabled (that is, the charge pump circuit 22 outputs the first power supply voltage Vcp when the first pulse signal PWM is in the first level state), so as to automatically realize that the first current source 211 is enabled when the first pulse signal PWM is in the first level state. For example, the first current source 211 includes a first drive circuit 2111 and a second transistor Q3, wherein the first end of the second transistor Q3 is connected to the power supply end of the first current source 211, and the second end is connected to the current output end of the first current source 211, and the output end of the first drive circuit 2111 is connected to the control end of the second transistor Q3, wherein when the first current source 211 has a control end, the input end of the first drive circuit 2111 serves as the control end of the first current source 211. Figure 3 In the example, the second transistor Q3 is a P-type MOSFET, but the invention is not limited thereto. In other embodiments, the second transistor Q3 may also be an N-type MOSFET, or any other type of transistor.

[0052] During the pre-charging process, the pre-charging current Iprec2 can also be limited to further protect the electronic fuse. Figure 4 , Fig. 9 , Fig.10 This function can be realized by further providing a pre-charging control circuit 212 in the pre-charging circuit 21, wherein the pre-charging control circuit 212 is used to generate a pre-charging control signal V according to the first pulse signal PWM. LG , the control terminal of the first current source 211 receives the pre-charge control signal V LG , so that the first current source 211 is enabled during the time period when the first pulse signal is in the first level state and the pre-charge current Iprec2 is less than the pre-charge current threshold. Further, the pre-charge current threshold can be set according to the capacitance of the capacitive load.

[0053] Figure 4FIG. 2 shows a circuit structure diagram of a pre-charging circuit 21 of a second embodiment of the present invention. The first current source 211 of this embodiment is substantially the same as that of the first embodiment, and will not be described in detail herein. The difference is that this embodiment further includes a pre-charging control circuit 212. The pre-charging control circuit 212 of this embodiment generates a pre-charging control signal V according to the first pulse signal PWM and the current detection signal CS. LG , to control the first current source 211 to be enabled during the time period when the first pulse signal PWM is in the first level state and the current detection signal CS is less than the first threshold Vprec, wherein when the current detection signal CS is equal to the first threshold Vprec, it indicates that the pre-charge current Iprec2 is equal to the pre-charge current threshold mentioned above. By way of example, the pre-charge control circuit 212 includes a comparison circuit 2121 and a logic circuit 2122, wherein the first input terminal of the comparison circuit 2121 receives the current detection signal CS, the second input terminal receives the first threshold Vprec, and outputs a comparison signal V at its output terminal according to the comparison result of the current detection signal CS and the first threshold Vprec. CMP The first input terminal of the logic circuit 2122 receives the first pulse signal PWM, and the second input terminal receives the comparison signal V CMP , and according to the first pulse signal PWM and the comparison signal V CMP Perform logical processing to output the precharge control signal V at its output terminal LG .

[0054] Further, in some embodiments, reference Figure 5 , Figure 6 , Figure 7a and Figure 7b , the logic circuit 2122 includes a counting circuit 21221 and a logic subcircuit 21222. First, let me explain, Figure 5 , Figure 6 They are shown according to Figure 4 The first and second circuit structure diagrams of the logic circuit 2122 are as follows, Figure 7a , Figure 7b Shown according to Figure 5 or Figure 6 Schematic diagram of the waveform, where PWM represents the first pulse signal, V GS represents the gate-source voltage of the first power tube Q1, CS represents the current detection signal, Vprec represents the first threshold, V CMP represents the comparison signal, CT represents the counting signal output by the counting circuit 21221, V LG represents the pre-charge control signal, and Vout represents the output voltage output by the voltage output terminal. The set terminal of the counting circuit 21221 receives the comparison signal V CMPThe reset end receives the first pulse signal PWM, and the output end outputs the count signal CT. The count signal CT is set to 1 in response to the jump of the comparison signal when the current detection signal CS rises to the first threshold Vprec, and is reset in response to the first pulse signal PWM jumping from the first level state to the second level state; the logic sub-circuit 21222 outputs the pre-charge control signal V according to the first pulse signal PWM and the count signal CT. LG , where the precharge control signal V LG The first current source 211 is controlled to be enabled in a time period when the first pulse signal PWM is in the first level state and the counting signal CT is 0. For example, in one embodiment, Figure 5 As shown, the logic sub-circuit 21222 includes a first NOT gate U1 and an AND gate U2. The input end of the first NOT gate U1 receives the counting signal CT, and the output end outputs the negative signal of the counting signal CT; the first input end of the AND gate U2 receives the first pulse signal PWM, the second input end receives the negative signal of the counting signal CT, and the output end outputs the pre-charge control signal V LG In another embodiment, Figure 6 As shown, the logic sub-circuit 21222 includes a second NOT gate U3 and a NOR gate U4. The input end of the second NOT gate U3 receives the first pulse signal PWM, and the output end outputs the negative signal of the first pulse signal PWM; the first input end of the NOR gate U4 receives the negative signal of the first pulse signal PWM, the second input end receives the negative signal of the counting signal CT, and the output end outputs the pre-charge control signal V LG .

[0055] It should be noted that Figure 5 , Figure 6 , Figure 7a , Figure 7b , and the following Fig.11a , Fig.11b , the first level state of the first pulse signal PWM is a high level state, the second level state is a low level state, and when the charge pump circuit 22 is working, the pre-charge control signal V LG In some other embodiments, the first level state of the first pulse signal PWM can be set to a low level state, and the second level state can be set to a high level state; in some other embodiments, it can also be set that when the charge pump circuit 22 is enabled, the pre-charge control signal V LG When it is in a low level state, the first current source 211 can be enabled.

[0056] Combine the following Figures 4 to 7b , including Figure 5 or Figure 6 The working principle of the pre-charging circuit 21 of the logic circuit 2122 shown is introduced. Figure 7a The waveform diagram of the first pulse signal PWM when the pulse width is large is shown. In the time period t11-t13, the counting signal CT is 0, the first pulse signal PWM is in the first level state, and the pre-charge control signal V LG In order to control the high level state of the first current source 211, after the first current source 211 is started, the gate-source voltage V GS At t12, the gate-source voltage V GS When the voltage rises to the threshold voltage of the first power tube Q1, the first power tube Q1 is turned on, and the first power tube Q1 starts to generate a pre-charge current Iprec2. Since the pre-charge current Iprec2 pre-charges the capacitive load C1, the output voltage Vout starts to rise from time t12. In the time period t12-t13, as V GS The pre-charge current Iprec2 rises, and the current detection signal CS also rises accordingly with the rise of the pre-charge current Iprec2. At time t13, the current detection signal CS reaches the first threshold Vprec, and the comparison signal V CMP The level state jump occurs, and the counting signal CT responds to the comparison signal V CMP At the time of t12, the precharge control signal V LG The first current source 211 is turned off and the output voltage Vout stops rising. At time t14, the count signal CT is cleared in response to the first pulse signal PWM jumping from the first level state to the second level state. Since the count signal CT is 1 in the time period t13-t14, and the first pulse signal PWM is in the second level state in the time period t14-t15, the precharge control signal Vout is set to zero in the time period t13-t15. LG The first current source 211 is kept turned off until the first pulse signal PWM changes to the first level state again at time t15, and the pre-charging process is repeated again. Figure 7b FIG. 1 shows a waveform diagram of a first pulse signal PWM when the pulse width is small. Since the pulse width of the first pulse signal PWM is small, the current detection signal CS always fails to reach the first threshold value Vprec, so the counting signal CT is always 0, which is equivalent to the pre-charge control signal V LG The first current source 211 is controlled to be enabled during a time period when the first pulse signal PWM is in a first level state.

[0057] Figure 8 Shown according to Figure 4 A third circuit structure diagram of the logic circuit 2122, Figure 8The logic circuit 2122 in the embodiment includes a trigger U5, a first terminal of which receives a first pulse signal PWM, and a second terminal of which receives a comparison signal V CMP , the output terminal outputs the pre-charge control signal V LG , precharge control signal V LG In response to the first pulse signal PWM jumping to the first level state and flipping to the level state for controlling the first current source to be enabled, in response to the comparison signal V CMP When the current detection signal rises to the first threshold, the trigger U5 is flipped to a level state for controlling the first current source to be turned off. For example, the trigger U5 is an RS trigger, the set terminal S of the RS trigger receives the first pulse signal PWM, and the reset terminal R receives the comparison signal V CMP , the first output terminal (Q terminal) outputs the precharge control signal VLG. It is easy to understand that Figure 8 When the charge pump circuit 22 is working, the pre-charge control signal V LG When the first current source 211 is enabled, the pre-charge control signal V LG When the first current source 211 is in a low level state, for example, only Figure 8 Based on the circuit structure shown in the figure, the second output terminal ( Terminal) output electrical control signal V LG Further, when the first level state of the first pulse signal PWM is a high level state and the second level state is a low level state, the logic circuit 2122 further includes a rising edge detection circuit 21223, the input end of the rising edge detection circuit 21223 receives the first pulse signal PWM, and the output end is connected to the first end of the trigger U5. It is easy to understand that when the first level state of the first pulse signal PWM is a low level state and the second level state is a high level state, for example, it is only necessary to Figure 8 Based on the circuit structure shown in the figure, the rising edge detection circuit 21223 is replaced by a falling edge detection circuit (not shown in the figure). The waveform diagram of this embodiment is not shown in this application, and its related waveforms can be referenced. Figure 7a and Figure 7b When the pulse width of the first pulse signal PWM is large, the gate-source voltage V GS , current detection signal CS, comparison signal V CMP , precharge control signal V LG The waveform of the output voltage Vout output from the voltage output terminal can be referred to Figure 7a When the pulse width of the first pulse signal PWM is small, the pre-charge control signal V LGThe waveform and Figure 7b The waveforms in are different, and the other waveforms can refer to Figure 7b The corresponding waveform in the embodiment is the precharge control signal V LG At time t21, in response to the first pulse signal PWM jumping to the first level state, it jumps to the high level state. Since the current detection signal CS never reaches the first threshold value Vprec, the corresponding comparison signal will not have a level state jump, so the pre-charge control signal V LG Starting from time t21, it always maintains a high level state, relying on the charge pump circuit 22 being enabled when the first pulse signal is in the first level state (that is, the charge pump circuit 22 outputs the first supply voltage Vcp when the first pulse signal is in the first level state), so that the first current source 211 is enabled when the first pulse signal PWM is in the first level state.

[0058] Fig. 9 FIG. 2 is a schematic diagram showing the circuit structure of a pre-charging circuit 21 according to a third embodiment of the present invention. The pre-charging circuit 21 according to this embodiment is similar to the pre-charging circuit 21 of FIG. Figure 4 The second embodiment shown is basically the same and will not be described here. The difference is that the pre-charging circuit 21 in this embodiment also includes a selection circuit 213, the input end of the selection circuit 213 receives at least two different threshold values ​​Vprec1, Vprec2...Vprecn, where n is an integer greater than or equal to 2, and the output end outputs a first threshold value Vprec, and the selection circuit 213 selects one of the threshold values ​​from the at least two different threshold values ​​as the first threshold value output. Further, according to the capacitance value of the capacitive load C1, one of the appropriate threshold values ​​can be selected from the at least two different threshold values ​​as the first threshold value output, so as to set the size of the pre-charging current threshold value according to the capacitance value of the capacitive load C1. Specifically, the larger the capacitive load C1, the larger the threshold value can be selected from the at least two different threshold values ​​as the first threshold value, so as to achieve matching between the pre-charging current and the capacitive load.

[0059] Fig.10 FIG. 2 is a schematic diagram showing the circuit structure of the pre-charging circuit 21 of the fourth embodiment of the present invention. The pre-charging control circuit 212 of the present embodiment generates a pre-charging control signal V according to the first pulse signal PWM and the first time threshold Tth. LG , precharge control signal V LG The first current source 211 is controlled to be enabled within a time period when the first pulse signal PWM is in a first level state and the duration of the first level state is less than a first time threshold Tth, wherein when the duration of the first pulse signal in the first level state is equal to the first time threshold, the corresponding pre-charge current Iprec2 is equal to the pre-charge current threshold mentioned above. Fig.11a , Fig.11b is based on Fig.10 The waveform diagram of Fig.11a The waveform diagram of the first pulse signal PWM when the pulse width is greater than the first time threshold Tth, the pre-charge control signal V LG The first pulse signal PWM is in a high level state during a time period when the first pulse signal PWM is in the first level state and the duration of the first level state is less than the first time threshold Tth, and the first current source 211 is enabled during this time period. Fig.11b The waveform diagram of the first pulse signal PWM when the pulse width is less than the first time threshold Tth, the pre-charge control signal V LG The waveform of the first pulse signal PWM is consistent with that of the first pulse signal PWM, which is equivalent to the pre-charge control signal V LG The first current source 211 is enabled during the time period when the first pulse signal PWM is in the first level state. LG The pulse width is used to control the pre-charge current Iprec2. Since the duration of the first current source 211 being enabled in each first pulse signal cycle is limited, the magnitude of the pre-charge current can also be limited accordingly. It is easy to understand that in another embodiment, the pre-charge circuit 21 may also include a selection circuit (not shown in the figure), the input end of which receives at least two different time thresholds, and the output end outputs the first time threshold Tth, and one of the time thresholds is selected from the at least two different time thresholds as the first time threshold; further, according to the capacitance of the capacitive load C1, a suitable time threshold can be selected from the at least two different time thresholds as the first time threshold output to achieve matching between the pre-charge current and the capacitive load.

[0060] In summary, the present invention uses a first pulse signal to control whether the first current source in the charge pump circuit and the pre-charging circuit is enabled to achieve pre-charging of the capacitive load. After the first current source is started, the first power tube is driven to conduct to generate a pre-charging current. The pre-charging current is used to pre-charge the capacitive load. Since the pre-charging current is the current flowing through the first power tube, the pre-charging current can be set to be large enough to safely achieve pre-charging of a large capacitive load. During the pre-charging process, the first current source can also be set to be enabled during a time period when the first pulse signal is in a first level state and the pre-charging current is less than a pre-charging current threshold, so as to limit the size of the pre-charging current to further protect the electronic fuse. And by using the pre-charging circuit of the present invention, the first pulse signal can be provided when the electronic fuse chip is in standby mode to achieve pre-charging, which greatly improves the flexibility of the electronic fuse pre-charging application.

[0061] The above-described implementation methods do not constitute a limitation on the protection scope of the technical solution. Any modification, equivalent replacement and improvement made within the spirit and principle of the above-described implementation methods shall be included in the protection scope of the technical solution.

Claims

1. A pre-charging circuit for an electronic fuse, the electronic fuse comprising a first power tube and a charge pump circuit, the first power tube being connected between a voltage input terminal and a voltage output terminal, the voltage output terminal being connected to a capacitive load to supply power to the capacitive load, the input terminal of the charge pump circuit being connected to the voltage input terminal, and the output terminal being used to output a first supply voltage, characterized in that: The pre-charging circuit comprises: A first current source, wherein a power supply end of the first current source is connected to an output end of the charge pump circuit, and a current output end is connected to a control end of the first power tube; Whether the charge pump circuit and the first current source are enabled is controlled according to the first pulse signal to realize pre-charging of the capacitive load, wherein the charge pump circuit outputs the first supply voltage when enabled, and after the first current source is started, the first power tube is driven to conduct to generate a pre-charging current, and the pre-charging current is used to pre-charge the capacitive load.

2. The precharge circuit according to claim 1, characterized in that The charge pump circuit is enabled when the first pulse signal is in a first level state, and the first current source is enabled during at least a partial time period when the first pulse signal is in the first level state.

3. The precharge circuit according to claim 1, characterized in that: The pre-charging circuit also includes: A pre-charge control circuit is used to generate a pre-charge control signal according to the first pulse signal, and the control end of the first current source receives the pre-charge control signal so that the first current source is enabled during a time period when the first pulse signal is in a first level state and the pre-charge current is less than a pre-charge current threshold.

4. The precharge circuit according to claim 3, characterized in that: The pre-charge current threshold is set according to the capacitance of the capacitive load.

5. The precharge circuit according to claim 3, characterized in that: The electronic fuse further includes a current detection circuit, which is used to output a current detection signal capable of representing a current flowing through the first power tube. The pre-charge control circuit generates the pre-charge control signal according to the first pulse signal and the current detection signal to control the first current source to be enabled during a time period when the first pulse signal is in a first level state and the current detection signal is less than a first threshold, wherein when the current detection signal is equal to the first threshold, it indicates that the pre-charge current is equal to the pre-charge current threshold.

6. The precharge circuit according to claim 5, characterized in that: The pre-charge control circuit comprises: a comparison circuit, wherein a first input terminal receives the current detection signal, a second input terminal receives the first threshold value, and an output terminal outputs a comparison signal according to a comparison result of the current detection signal and the first threshold value; A logic circuit has a first input terminal receiving the first pulse signal, a second input terminal receiving the comparison signal, and an output terminal outputting the pre-charge control signal.

7. The precharge circuit according to claim 6, characterized in that: The logic circuit comprises: A counting circuit, wherein a set terminal receives the comparison signal, a reset terminal receives the first pulse signal, and an output terminal outputs a counting signal, wherein the counting signal is set to 1 in response to a jump of the comparison signal when the current detection signal rises to the first threshold value, and is reset to zero in response to a jump of the first pulse signal from a first level state to a second level state; A logic subcircuit outputs the precharge control signal according to the first pulse signal and the counting signal, wherein the precharge control signal controls the first current source to be enabled during a time period when the first pulse signal is in a first level state and the counting signal is 0.

8. The precharge circuit according to claim 6, characterized in that: The logic circuit comprises: A trigger, a first end receives the first pulse signal, a second end receives the comparison signal, and an output end outputs the pre-charge control signal, the pre-charge control signal flips to a level state for controlling the first current source to be enabled in response to the first pulse signal jumping to a first level state, and flips to a level state for controlling the first current source to be turned off in response to the comparison signal jumping when the current detection signal rises to the first threshold.

9. The precharge circuit according to claim 5, characterized in that: The pre-charging circuit also includes: The selection circuit has an input terminal receiving at least two different thresholds and an output terminal outputting the first threshold. The selection circuit selects one of the at least two different thresholds as the first threshold output.

10. The precharge circuit according to claim 3, characterized in that: The pre-charge control circuit generates the pre-charge control signal according to the first pulse signal and the first time threshold, and the pre-charge control signal controls the first current source to be enabled during a time period when the first pulse signal is in a first level state and the duration of the first level state is less than the first time threshold, wherein when the duration of the first pulse signal in the first level state is equal to the first time threshold, the corresponding pre-charge current is equal to the pre-charge current threshold.

11. The pre-charging circuit according to any one of claims 1 to 10, characterized in that: At least part of the pre-charging circuit is integrated into the electronic fuse chip. The electronic fuse chip comprises a pre-charging pin. When the capacitive load needs to be pre-charged, the first pulse signal is input to the pre-charging pin.

12. The precharge circuit according to claim 11, characterized in that: When the electronic fuse chip is in the standby mode, the first pulse signal is input to the pre-charge pin.

13. The precharge circuit according to claim 1, characterized in that: The capacitance of the capacitive load is greater than or equal to 1 mF.

14. An electronic fuse chip, characterized in that: The invention comprises at least a part of the pre-charging circuit as claimed in any one of claims 1 to 13.

15. An electronic fuse, characterized in that: Comprising a pre-charging circuit as described in any one of claims 1-13.

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