Semiconductor element driving device

Abstract

The purpose of the present invention is to provide a technique by which it is possible to determine whether or not an ASC mode is being executed by a secondary-side circuit. The semiconductor element driving device includes: a primary side circuit; a signal transmission circuit including an insulating element; and a secondary-side circuit that drives the semiconductor element on the basis of a plurality of transmission signals corresponding to the plurality of signals transmitted from the primary-side circuit via the signal transmission circuit. The secondary-side circuit includes an ASC mode determination circuit that determines whether the normal mode is being executed or the ASC mode is being executed on the basis of a transmission transition signal corresponding to the transition signal or the control transition signal among the plurality of transmission signals.

Description

Technical Field

[0001] The present invention relates to a semiconductor element driving device. Background Art

[0002] Various technologies have been proposed for semiconductor element driving devices that drive semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) of inverter systems. For example, a technology has been proposed in which a signal is transmitted from a primary side circuit to a secondary side circuit via an insulating element that can transmit the signal, thereby driving the semiconductor element by the secondary side circuit.

[0003] As an example, the following technology is proposed in Patent Document 1, that is, the primary side circuit transmits the second control signal for driving the semiconductor element in the ASC (Active Short Circuit) mode to the secondary side circuit in priority over the first control signal for driving the semiconductor element in the normal mode. That is, the technology is proposed that the primary side circuit that is not input with the second control signal and is input with the first control signal transmits the first control signal to the secondary side circuit, and the primary side circuit that is input with the second control signal transmits the second control signal to the secondary side circuit regardless of whether the first control signal is input.

[0004] Patent Document 1: International Publication No. 2023 / 105943

[0005] However, in the technology of Patent Document 1, the secondary side circuit cannot determine whether the normal mode or the ASC mode is being executed. Therefore, there is a problem that the secondary side circuit cannot distinguish the operation in the ASC mode from the operation in the normal mode. Summary of the invention

[0006] Therefore, the present invention has been made in view of the above-mentioned problem, and an object of the present invention is to provide a technology capable of determining whether or not the ASC mode is being executed by a secondary-side circuit.

[0007] The semiconductor element driving device according to the present invention comprises: a primary side circuit to which a plurality of signals are input, wherein the plurality of signals include a first control signal for controlling the driving of the semiconductor element in a normal mode, a second control signal for controlling the driving of the semiconductor element in an ASC mode, and a transition signal for transitioning from the normal mode to the ASC mode, or include the first control signal and a control transition signal corresponding to the second control signal and the transition signal; a signal transmission circuit including an insulating element capable of transmitting a signal; and a secondary side circuit that drives the semiconductor element based on a plurality of transmission signals corresponding to the plurality of signals transmitted from the primary side circuit via the signal transmission circuit, wherein the secondary side circuit includes:

[0008] An ASC mode determination circuit determines whether the normal mode or the ASC mode is being executed based on a transmission transition signal among the multiple transmission signals corresponding to the transition signal or the control transition signal; and a logic circuit drives the semiconductor element based on a first transmission control signal among the multiple transmission signals corresponding to the first control signal when the ASC mode determination circuit determines that the normal mode is being executed, and drives the semiconductor element based on a second transmission control signal among the multiple transmission signals corresponding to the second control signal or the control transition signal when the ASC mode determination circuit determines that the ASC mode is being executed.

[0009] Effects of the Invention

[0010] According to the present invention, the secondary side circuit includes an ASC mode determination circuit, which determines whether the normal mode or the ASC mode is being executed based on a transmission transition signal corresponding to a transition signal or a control transition signal among a plurality of transmission signals. According to such a structure, it is possible to determine whether the ASC mode is being executed by the secondary side circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a circuit diagram showing the structure of the semiconductor element driving device according to the first embodiment.

[0012] Figure 2 This is a timing chart showing the operation of the semiconductor element driving device according to the first embodiment.

[0013] Figure 3 1 is a timing chart showing the operation of the ASC mode determination circuit according to the first embodiment.

[0014] Figure 4This is a circuit diagram showing the structure of a semiconductor element driving device according to the second embodiment.

[0015] Figure 5 This is a timing chart showing the operation of the semiconductor element driving device according to the second embodiment.

[0016] Figure 6 This is a circuit diagram showing the structure of a semiconductor element driving device according to a third embodiment.

[0017] Figure 7 This is a timing chart showing the operation of the semiconductor element driving device according to the third embodiment.

[0018] Figure 8 This is a circuit diagram showing the structure of a semiconductor element driving device according to a fourth embodiment.

[0019] Fig. 9 This is a timing chart showing the operation of the semiconductor element driving device according to the fourth embodiment. DETAILED DESCRIPTION

[0020] Below, while referring to the attached Figure 1 The embodiments are described. The features described in the following embodiments are examples, and not all features are required. In addition, in the following description, the same or similar reference numerals are used for the same structural elements in multiple embodiments, and the different structural elements are mainly described.

[0021] <Implementation method 1>

[0022] Figure 1 : is a circuit diagram showing the structure of the semiconductor element driving device according to the first embodiment. Figure 1 The semiconductor element driving device includes: a primary side circuit 1 to which a plurality of signals are input; a secondary side circuit 5 to drive a semiconductor element (not shown); and a signal transmission circuit 3 including an insulating element capable of transmitting a signal from the primary side circuit 1 to the secondary side circuit 5. That is, Figure 1 The semiconductor element driving device is a gate driving IC with a built-in insulating element.

[0023] The plurality of signals input to the primary side circuit 1 are output from, for example, an ECU (Electronic Control Unit) and an MCU (Micro Controller Unit). The plurality of signals involved in the present embodiment 1 include a first control signal for controlling the drive of the semiconductor element in the normal mode, a second control signal for controlling the drive of the semiconductor element in the ASC (Active Short Circuit) mode, and a transition signal for transitioning from the normal mode to the ASC mode.

[0024] The primary side circuit 1 includes an IN terminal to which a first control signal is input, an ASC_IN terminal to which a second control signal is input, an ASC_EN terminal to which a transition signal is input, and modulation circuits 11, 12, 13, 14, 15. The modulation circuits 11, 12, 13, 14, 15 modulate a plurality of signals input to the primary side circuit 1 into modulated signals transmittable by the signal transmission circuit 3.

[0025] The signal transmission circuit 3 includes an insulating element (isolator) that can transmit a signal via an insulating portion such as a space. Figure 1 The structure of the transformers that are magnetically coupled to each other is used as an example for explanation, but is not limited thereto. For example, the insulating elements may be capacitors that are capacitively coupled to each other, or optical couplers that are optically coupled to each other.

[0026] The secondary side circuit 5 includes demodulation circuits 51, 52, 53, 54, 55, pulse recovery circuits 61, 62, ASC mode determination circuit 63, logic circuit 65, drive circuit 66, OUT terminal, ErrIN terminal and abnormality detection protection action circuit 64 as an abnormality detection circuit. In addition, the abnormality detection protection action circuit 64 and the ErrIN terminal are not necessarily provided.

[0027] The demodulation circuits 51 to 55 and the pulse restoration circuits 61 and 62 generate a plurality of transmission signals corresponding to a plurality of signals of the primary side circuit 1 based on the modulation signal transmitted from the primary side circuit 1 via the signal transmission circuit 3 .

[0028] In addition, in the present first embodiment, the waveform of the first transmission control signal corresponding to the first control signal among the plurality of transmission signals is substantially the same as the first control signal. The waveform of the second transmission control signal corresponding to the second control signal among the plurality of transmission signals is substantially the same as the second control signal. The waveform of the transmission transition signal corresponding to the transition signal among the plurality of transmission signals is different from the transition signal. As described below, the secondary side circuit 5 drives the semiconductor element based on the plurality of transmission signals including the first transmission control signal, the second transmission control signal, and the transmission transition signal.

[0029] The ASC mode determination circuit 63 determines whether the normal mode or the ASC mode is being executed based on the transmission transition signal corresponding to the transition signal of the ASC_EN terminal, and outputs a determination signal indicating the determination result.

[0030] The abnormality detection protection action circuit 64 obtains a signal indicating the operating state of the semiconductor element via the ErrIN terminal. The abnormality detection protection action circuit 64 detects the abnormality of the semiconductor element based on the signal and outputs an abnormality detection signal indicating the detection result of the abnormality of the semiconductor element. In addition, the abnormality of the semiconductor element may also include an abnormality of the semiconductor element driving device reflected in the operating state of the semiconductor element.

[0031] The logic circuit 65 is input with a first transmission control signal corresponding to the first control signal of the IN terminal, a second transmission control signal corresponding to the second control signal of the ASC_IN terminal, a determination signal from the ASC mode determination circuit 63, and an abnormality detection signal from the abnormality detection protection action circuit 64. The logic circuit 65 outputs a drive signal for driving a semiconductor element (not shown) from the drive circuit 66 via the OUT terminal based on the first transmission control signal, the second transmission control signal, the determination result of the ASC mode determination circuit 63, and the detection result of the abnormality detection protection action circuit 64.

[0032] In the first embodiment, when the ASC mode determination circuit 63 determines that the normal mode is being executed (i.e., the ASC mode is not being executed), the logic circuit 65 drives the semiconductor element based on the first transmission control signal in principle. However, when the ASC mode determination circuit 63 determines that the normal mode is being executed and the abnormality detection protection action circuit 64 detects an abnormality in the semiconductor element, the logic circuit 65 performs an action to protect the semiconductor element regardless of the first transmission control signal. The action to protect the semiconductor element is, for example, an action to stop the operation of the semiconductor element.

[0033] On the other hand, when the ASC mode determination circuit 63 determines that the ASC mode is being executed, the logic circuit 65 drives the semiconductor element based on the second transmission control signal instead of the first transmission control signal. In addition, when the ASC mode determination circuit 63 determines that the ASC mode is being executed and the abnormality detection protection action circuit 64 detects an abnormality in the semiconductor element, the logic circuit 65 does not perform an action to protect the semiconductor element, but drives the semiconductor element based on the second transmission control signal.

[0034] The semiconductor element not shown is driven by a drive signal output from the OUT terminal by the secondary side circuit 5. The semiconductor element is, for example, a semiconductor switching element of an inverter system that drives an inductive load such as a motor. The semiconductor element includes, for example, IGBT (Insulated Gate Bipolar Transistor), RC-IGBT (Reverse Conducting-IGBT), and MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The material of the semiconductor element may include conventional silicon (Si), or may include wide bandgap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), and diamond. When the semiconductor element is composed of a wide bandgap semiconductor, stable operation at high temperature and high voltage and high switching speed can be achieved.

[0035] Figure 2 1 is a timing diagram showing the operation of the semiconductor element driving device according to the first embodiment. The following describes the normal mode, the normal mode when an abnormality is detected, the ASC mode, and the ASC mode when an abnormality is detected. In the following description of each mode, repeated contents are appropriately omitted.

[0036] <Normal Mode>

[0037] The modulation circuit 11 generates a modulation signal based on the rising edge of the first control signal input to the IN terminal, and the modulation circuit 12 generates a modulation signal based on the falling edge of the first control signal input to the IN terminal. That is, the modulation circuits 11 and 12 generate modulation signals by edge-triggered modulation of the first control signal. The modulation signals generated by the modulation circuits 11 and 12 are provided to the demodulation circuits 51 and 52 respectively via the signal transmission circuit 3.

[0038] The demodulation circuits 51 and 52 output edge trigger signals equivalent to the modulation signals generated by the modulation circuits 11 and 12 to the S terminal and the R terminal of the pulse restoration circuit 61, respectively. The pulse restoration circuit 61 generates a first transmission control signal having a waveform substantially the same as the first control signal input to the primary side circuit 1 based on the edge trigger signals output from the demodulation circuits 51 and 52, and outputs it from the Q terminal to the logic circuit 65. According to such a configuration, the first transmission control signal corresponding to the first control signal can be transmitted from the primary side circuit 1 to the secondary side circuit 5 without damaging the square wave information of the first control signal while maintaining the insulation state between the primary side circuit 1 and the secondary side circuit 5.

[0039] The second control signal input to the ASC_IN terminal is also processed in the same manner as the first control signal. Specifically, the modulation circuit 13 generates a modulation signal based on the rising edge of the second control signal, and the modulation circuit 14 generates a modulation signal based on the falling edge of the second control signal. That is, the modulation circuits 13 and 14 generate modulation signals by edge-triggered modulation of the second control signal. The modulation signals generated by the modulation circuits 13 and 14 are provided to the demodulation circuits 53 and 54, respectively, via the signal transmission circuit 3.

[0040] The demodulation circuits 53 and 54 output edge trigger signals equivalent to the modulation signals generated by the modulation circuits 13 and 14 to the S terminal and the R terminal of the pulse restoration circuit 62. The pulse restoration circuit 62 generates a second transmission control signal having substantially the same waveform as the second control signal input to the primary side circuit 1 based on the edge trigger signals output from the demodulation circuits 53 and 54, and outputs the second transmission control signal to the logic circuit 65 from the Q terminal.

[0041] In the normal mode, a transition signal of an invalid signal (Low) is input to the ASC_EN terminal. If a transition signal of an invalid signal is input, the modulation circuit 15 outputs an invalid signal, and the invalid signal is transmitted to the demodulation circuit 55 via the signal transmission circuit 3. The demodulation circuit 55 outputs a transmission transition signal of the invalid signal to the ASC mode determination circuit 63. The ASC mode determination circuit 63 determines that the normal mode is being executed based on the transmission transition signal of the invalid signal, and outputs a determination signal of the invalid signal indicating the determination result to the logic circuit 65.

[0042] When the ASC mode determination circuit 63 determines that the normal mode is being executed, the logic circuit 65 discards the second transfer control signal corresponding to the second control signal and outputs a drive signal to the OUT terminal based on the first transfer control signal corresponding to the first control signal.

[0043] <Normal mode when an abnormality is detected>

[0044] When an abnormality occurs in a semiconductor element or the like in normal mode, a valid signal (High) is input to the ErrIN terminal of the secondary circuit 5. When a valid signal is input to the ErrIN terminal, the abnormality detection protection operation circuit 64 detects the abnormality of the semiconductor element and outputs an abnormality detection signal of a valid signal to the logic circuit 65.

[0045] When the ASC mode determination circuit 63 determines that the normal mode is being executed and the abnormality detection protection operation circuit 64 detects an abnormality in the semiconductor element, the logic circuit 65 outputs a signal (Low) for stopping the operation of the semiconductor element to the OUT terminal regardless of the first transmission control signal.

[0046] <ASC Mode>

[0047] In the ASC mode, a transition signal of a valid signal is input to the ASC_EN terminal. When the transition signal is a valid signal, the modulation circuit 15 generates a modulation signal including burst-shaped pulses by OOK (On-Off-Keying). The modulation signal is transmitted to the demodulation circuit 55 via the signal transmission circuit 3, and the demodulation circuit 55 outputs a transmission transition signal corresponding to the modulation signal to the ASC mode determination circuit 63. In addition, the transmission transition signal has a waveform substantially the same as the modulation signal of the modulation circuit 15.

[0048] Figure 3 1 is a timing chart showing the operation of the ASC mode determination circuit 63 according to the first embodiment. In the ASC mode determination circuit 63, a count reset trigger for resetting the count of pulses of the transmission transition signal to 0 and a determination trigger for the ASC mode determination circuit 63 to perform determination are generated. The determination cycle is the period between the count reset trigger and the determination trigger.

[0049] The ASC mode determination circuit 63 determines that the ASC mode is being executed when the pulse of the transmission transition signal is counted a predetermined N times (N≥2) within a predetermined period, i.e., within a determination cycle. In this case, the ASC mode determination circuit 63 outputs a determination signal of a valid signal indicating the determination result that the ASC mode is being executed to the logic circuit 65. On the other hand, even if the transition signal of the ASC_EN terminal is instantaneously a valid signal, if the number of times obtained from the pulse count of the transmission transition signal within the determination cycle does not reach N times, the ASC mode determination circuit 63 will not determine that the ASC mode is being executed. In this case, the ASC mode determination circuit 63 outputs a determination signal of an invalid signal indicating the determination result that the normal mode is being executed to the logic circuit 65. According to such a structure, it is possible to suppress the erroneous determination of the ASC mode determination circuit 63 caused by noise.

[0050] When the ASC mode determination circuit 63 determines that the ASC mode is being executed, the logic circuit 65 discards the first transfer control signal corresponding to the first control signal and outputs a drive signal to the OUT terminal based on the second transfer control signal corresponding to the second control signal.

[0051] <ASC mode when abnormality is detected>

[0052] When an abnormality occurs in a semiconductor element or the like in the ASC mode, a valid signal is input to the ErrIN terminal of the secondary circuit 5. When a valid signal is input to the ErrIN terminal, the abnormality detection protection operation circuit 64 detects the abnormality of the semiconductor element and outputs an abnormality detection signal of the valid signal to the logic circuit 65.

[0053] The logic circuit 65 outputs a drive signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal when the ASC mode determination circuit 63 determines that the ASC mode is being executed and the abnormality of the semiconductor element is detected by the abnormality detection protection action circuit 64. According to such a structure, in the ASC mode, the operation of the ASC mode can be continued regardless of the detection result of the abnormality detection protection action circuit 64.

[0054] <Summary of Implementation Method 1>

[0055] According to the semiconductor element driving device involved in the present embodiment 1, the ASC mode determination circuit 63 of the secondary side circuit 5 determines whether the normal mode or the ASC mode is being executed based on the transmission transition signal corresponding to the transition signal. According to such a structure, the secondary side circuit 5 can distinguish the operation of the ASC mode when an abnormality is detected from the operation of the normal mode when an abnormality is detected based on the determination result of the ASC mode determination circuit 63.

[0056] <Implementation method 2>

[0057] Figure 4 This is a circuit diagram showing the structure of a semiconductor element driving device according to the second embodiment. Figure 4 The structure of the primary side circuit 1 is relative to Figure 1 The structure of the primary side circuit 1 is the same as that after adding a demodulation circuit 16, an input priority determination circuit 18, a FO output circuit 17 as an output circuit, and a FO terminal as a terminal and deleting the modulation circuits 13 and 14. Figure 4 The structure of the secondary side circuit 5 is similar to that of the Figure 1 The structure of the secondary side circuit 5 is the same as that of the secondary side circuit 5 except that the modulation circuit 56 is added and the demodulation circuits 53 and 54 and the pulse restoration circuit 62 are deleted.

[0058] The modulation circuit 56 of the secondary side circuit 5 generates a modulation signal including burst-shaped pulses based on the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection protection operation circuit 64 .

[0059] The demodulation circuit 16 of the primary side circuit 1 generates a burst signal including burst-shaped pulses based on the modulation signal transmitted from the secondary side circuit 5 via the signal transmission circuit 3. The FO output circuit 17 smoothes the burst signal generated by the demodulation circuit 16 and generates a transmission result signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection protection action circuit 64. In addition, in the present embodiment 2, the transmission result signal corresponds to the logical OR signal of the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection protection action circuit 64, but may correspond to either the determination signal or the abnormality detection signal.

[0060] The input priority determination circuit 18 selects the first control signal of the IN terminal and the second control signal of the ASC_IN terminal based on the transmission result signal of the FO output circuit 17 and the transition signal of the ASC_EN terminal, and outputs them to the signal transmission circuit 3 via the modulation circuits 11 and 12. The FO terminal is a terminal for outputting the transmission result signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection protection action circuit 64 to the outside.

[0061] Figure 5 1 is a timing diagram showing the operation of the semiconductor element driving device according to the second embodiment. The following describes the normal mode, the normal mode when an abnormality is detected, the ASC mode, and the ASC mode when an abnormality is detected. In the following description of each mode, repeated contents are appropriately omitted.

[0062] <Normal Mode>

[0063] In the normal mode, a transition signal of an invalid signal is input to the ASC_EN terminal. When the transition signal is an invalid signal, the input priority determination circuit 18 determines that the normal mode is being executed regardless of the output signal of the FO output circuit 17. In this case, the input priority determination circuit 18 abandons the second control signal of the ASC_IN terminal and outputs the first control signal of the IN terminal to the modulation circuits 11 and 12.

[0064] The modulation circuits 11 and 12 generate modulation signals by edge-triggered modulation of the first control signal. The modulation signals generated by the modulation circuits 11 and 12 are supplied to the demodulation circuits 51 and 52 respectively via the signal transmission circuit 3.

[0065] The demodulation circuits 51 and 52 output edge trigger signals equivalent to the modulation signals generated by the modulation circuits 11 and 12 to the S terminal and the R terminal of the pulse restoration circuit 61. The pulse restoration circuit 61 generates a first transmission control signal having substantially the same waveform as the first control signal input to the primary side circuit 1 based on the edge trigger signals output from the demodulation circuits 51 and 52, and outputs the first transmission control signal from the Q terminal to the logic circuit 65.

[0066] If the modulation circuit 15 receives the invalid signal transition signal, it outputs the invalid signal, and the invalid signal is transmitted to the demodulation circuit 55 via the signal transmission circuit 3. The demodulation circuit 55 outputs the invalid signal transmission transition signal to the ASC mode determination circuit 63. The ASC mode determination circuit 63 determines that the normal mode is being executed based on the invalid signal transmission transition signal, and outputs the invalid signal determination signal indicating the determination result to the logic circuit 65.

[0067] When the ASC mode determination circuit 63 determines that the normal mode is being executed, the logic circuit 65 outputs a drive signal to the OUT terminal based on the first transfer control signal corresponding to the first control signal of the IN terminal.

[0068] <Normal mode when an abnormality is detected>

[0069] When an abnormality occurs in a semiconductor element or the like in the normal mode, a valid signal is input to the ErrIN terminal of the secondary circuit 5. When a valid signal is input to the ErrIN terminal, the abnormality detection protection operation circuit 64 detects the abnormality of the semiconductor element and outputs an abnormality detection signal of the valid signal to the logic circuit 65 and the modulation circuit 56.

[0070] When the ASC mode determination circuit 63 determines that the normal mode is being executed and the abnormality detection protection operation circuit 64 detects an abnormality in the semiconductor element, the logic circuit 65 outputs a signal for stopping the operation of the semiconductor element to the OUT terminal regardless of the first transfer control signal.

[0071] When the abnormality detection signal of the abnormality detection protection action circuit 64 is a valid signal, the modulation circuit 56 generates a modulation signal including burst-shaped pulses by OOK. The modulation signal is transmitted to the demodulation circuit 16 via the signal transmission circuit 3, and the demodulation circuit 16 outputs a burst signal corresponding to the modulation signal to the FO output circuit 17. In addition, the burst signal has a waveform substantially the same as the modulation signal of the modulation circuit 56.

[0072] The FO output circuit 17 smoothes the burst signal of the demodulation circuit 16 , and generates a transmission result signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection protection operation circuit 64 .

[0073] The transmission result signal is output to the FO terminal, and an external device on the primary side circuit 1 side can confirm the abnormality of the semiconductor element based on the transmission result signal of the FO terminal. In addition, the transmission result signal can be transmitted by a pair of insulating elements (here, a pair of transformers).

[0074] Furthermore, the transmission result signal is also output to the input priority determination circuit 18 , but since the transition signal of the ASC_EN terminal is an invalid signal, the input priority determination circuit 18 determines that the normal mode is being executed and outputs the first control signal of the IN terminal to the modulation circuits 11 , 12 .

[0075] <ASC Mode>

[0076] In the ASC mode, a transition signal of a valid signal is input to the ASC_EN terminal. When the transition signal is a valid signal, the modulation circuit 15 generates a modulation signal including a burst-shaped pulse by OOK. The modulation signal is transmitted to the demodulation circuit 55 via the signal transmission circuit 3, and the demodulation circuit 55 outputs a transmission transition signal corresponding to the modulation signal to the ASC mode determination circuit 63. In addition, the transmission transition signal has a waveform substantially the same as the modulation signal of the modulation circuit 15.

[0077] The ASC mode determination circuit 63 determines that the ASC mode is being executed when the pulse of the transmission transition signal is counted N times within the determination cycle. When the ASC mode determination circuit 63 determines that the ASC mode is being executed, it outputs a determination signal indicating a valid signal of the determination result not only to the logic circuit 65 but also to the modulation circuit 56. On the other hand, when the ASC mode determination circuit 63 determines that the normal mode is being executed, it outputs a determination signal indicating an invalid signal of the determination result not only to the logic circuit 65 but also to the modulation circuit 56.

[0078] The modulation circuit 56, the signal transmission circuit 3, the demodulation circuit 16, and the FO output circuit 17 perform the same operation as the normal mode operation when an abnormality is detected. As a result, a transmission result signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection protection operation circuit 64 is output to the FO terminal and the input priority determination circuit 18. Since the determination signal of the ASC mode determination circuit 63 is a valid signal, the transmission result signal also becomes a valid signal.

[0079] The input priority determination circuit 18 determines that the secondary side circuit 5 accepts the ASC mode when the transition signal of the ASC_EN terminal is a valid signal and the transfer result signal of the FO output circuit 17 is a valid signal. In this case, the input priority determination circuit 18 discards the first control signal of the IN terminal and outputs the second control signal of the ASC_IN terminal to the modulation circuits 11 and 12.

[0080] The modulation circuits 11 and 12, the signal transmission circuit 3, the demodulation circuits 51 and 52, and the pulse restoration circuit 61 perform the same operation as that in the normal mode on the second control signal. As a result, the second transmission control signal corresponding to the second control signal of the ASC_IN terminal is output to the logic circuit 65. When the ASC mode determination circuit 63 determines that the ASC mode is being executed, the logic circuit 65 outputs a drive signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal of the ASC_IN terminal.

[0081] <ASC mode when abnormality is detected>

[0082] When an abnormality occurs in a semiconductor element or the like in the ASC mode, a valid signal is input to the ErrIN terminal of the secondary circuit 5. When a valid signal is input to the ErrIN terminal, the abnormality detection protection operation circuit 64 detects the abnormality of the semiconductor element and outputs an abnormality detection signal of the valid signal to the logic circuit 65 and the modulation circuit 56.

[0083] The logic circuit 65 outputs a drive signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal when the ASC mode determination circuit 63 determines that the ASC mode is being executed and the abnormality of the semiconductor element is detected by the abnormality detection protection action circuit 64. According to such a structure, in the ASC mode, the operation of the ASC mode can be continued regardless of the detection result of the abnormality detection protection action circuit 64.

[0084] The modulation circuit 56, the signal transmission circuit 3, the demodulation circuit 16, and the FO output circuit 17 perform the same operation as the normal mode operation when an abnormality is detected. As a result, the transmission result signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection protection action circuit 64 is output to the FO terminal and the input priority determination circuit 18. Since the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection protection action circuit 64 are both valid signals, the transmission result signal also becomes a valid signal.

[0085] <Summary of Implementation Method 2>

[0086] According to the second embodiment, the input priority determination circuit 18 of the primary side circuit 1 selectively outputs the first control signal of the IN terminal and the second control signal of the ASC_IN terminal to the signal transmission circuit 3 based on the transition signal of the ASC_EN terminal. According to such a structure, the number of modulation circuits and demodulation circuits can be reduced compared with the structure of the first embodiment, so the area and the number of components of the semiconductor element driving device can be reduced.

[0087] In addition, the input priority determination circuit 18 of the primary side circuit 1 selectively outputs the first control signal of the IN terminal and the second control signal of the ASC_IN terminal to the signal transmission circuit 3 based on the transmission result signal of the FO output circuit 17 and the transition signal of the ASC_EN terminal. According to such a structure, the input priority determination circuit 18 can also take into account the transmission result signal reflecting the determination result of the ASC mode determination circuit 63 and control the switching of the first control signal and the second control signal.

[0088] <Implementation method 3>

[0089] Figure 6 This is a circuit diagram showing the structure of a semiconductor element driving device according to the third embodiment. Figure 6 The structure of the primary side circuit 1 is similar to that in Figure 4 The configuration of the primary side circuit 1 is the same as that in which the transition signal of the ASC_EN terminal is input to the modulation circuits 11 and 12 and the modulation circuit 15 is deleted. Figure 6 The structure of the secondary side circuit 5 is similar to that of the Figure 4 The structure of the secondary side circuit 5 is the same as that of the secondary side circuit 5 except that the OR circuit 70 is added and the demodulation circuit 55 is deleted.

[0090] When the transition signal of the ASC_EN terminal is an invalid signal, the modulation circuits 11 and 12 of the primary side circuit 1 perform edge-triggered modulation on the output signal of the input priority determination circuit 18 in the same operation as the modulation circuits 11 and 12 of Embodiment 2. On the other hand, when the transition signal of the ASC_EN terminal is a valid signal, the modulation circuits 11 and 12 perform OOK on the output signal of the input priority determination circuit 18 to generate a modulation signal including burst-shaped pulses.

[0091] The OR circuit 70 of the secondary side circuit 5 outputs a logical OR signal of the output signals of the demodulation circuits 51 and 52 to the ASC mode determination circuit 63 .

[0092] Figure 71 is a timing diagram showing the operation of the semiconductor element driving device according to the third embodiment. The following describes the normal mode, the normal mode when an abnormality is detected, the ASC mode, and the ASC mode when an abnormality is detected. In the following description of each mode, repeated contents are appropriately omitted.

[0093] <Normal Mode>

[0094] In the third embodiment, the logical OR signal from the OR circuit 70 is input to the ASC mode determination circuit 63. However, the interval between pulses of the logical OR signal in the normal mode is long, and therefore, the ASC mode determination circuit 63 does not count the pulses of the transmission transition signal N times within the determination cycle, and determines that the normal mode is being executed.

[0095] The normal mode of the present embodiment 3 is the same as the normal mode of the embodiment 2. That is, the input priority determination circuit 18 outputs the first control signal to the IN terminal, and the logic circuit 65 outputs the drive signal to the OUT terminal based on the first transmission control signal corresponding to the first control signal.

[0096] <Normal mode when an abnormality is detected>

[0097] The normal mode when an abnormality is detected in the third embodiment is the same as the normal mode when an abnormality is detected in the second embodiment. That is, the abnormality detection protection action circuit 64 outputs the abnormality detection signal of the valid signal to the logic circuit 65, and the logic circuit 65 outputs the signal for stopping the operation of the semiconductor element to the OUT terminal regardless of the first transmission control signal. In addition, the transmission result signal of the valid signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection protection action circuit 64 is output to the FO terminal of the primary side circuit 1.

[0098] <ASC Mode>

[0099] In the ASC mode, a transition signal of a valid signal is input to the ASC_EN terminal. In this case, the modulation circuits 11 and 12 do not perform edge-triggered modulation, but perform OOK on the output signal of the input priority determination circuit 18 to generate a modulation signal including burst-shaped pulses corresponding to the period of the output signal.

[0100] The modulated signal is transmitted to the demodulation circuits 51 and 52 via the signal transmission circuit 3. The demodulation circuits 51 and 52 respectively output signals corresponding to the modulated signal to the S terminal and the R terminal of the pulse restoration circuit 61. In addition, the demodulation circuits 51 and 52 output signals corresponding to the modulated signal to the OR circuit 70.

[0101] The OR circuit 70 outputs a logical OR signal of the output signals of the demodulation circuits 51 and 52 as a transmission transition signal to the ASC mode determination circuit 63. Similar to the transmission transition signal of the second embodiment, the ASC mode determination circuit 63 counts the pulses of the transmission transition signal including the burst-shaped pulse a predetermined N times within the determination cycle, and thus determines that the ASC mode is being executed.

[0102] The ASC mode involved in the present embodiment 3 is the same as the ASC mode involved in the embodiment 2. That is, the input priority determination circuit 18 outputs the second control signal of the ASC_IN terminal, and the logic circuit 65 outputs the drive signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal. In addition, the transmission result signal of the valid signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection protection action circuit 64 is output to the FO terminal of the primary side circuit 1.

[0103] <ASC mode when abnormality is detected>

[0104] As described in the ASC mode, the ASC mode when abnormality is detected according to the present embodiment 3 is the same as the ASC mode when abnormality is detected according to the embodiment 2, except that the generation process of the transmission transition signal is different from that of the embodiment 2. That is, the abnormality detection protection action circuit 64 outputs the abnormality detection signal of the valid signal to the logic circuit 65, and the logic circuit 65 outputs the drive signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal. In addition, the transmission result signal of the valid signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection protection action circuit 64 is output to the FO terminal of the primary side circuit 1.

[0105] <Summary of Implementation Method 3>

[0106] According to the third embodiment, the number of modulation circuits and demodulation circuits can be reduced compared to the structure of the second embodiment, so the area and the number of components of the semiconductor element driving device can be reduced. In addition, as long as it does not affect the determination of the ASC mode determination circuit 63, in the normal mode, the modulation circuits 11 and 12 can also generate and output modulation signals through OOK. According to such a structure, the secondary side circuit 5 can confirm the start-up of the primary side power supply of the primary side circuit 1.

[0107] <Implementation method 4>

[0108] Figure 8 This is a circuit diagram showing the structure of a semiconductor element driving device according to the fourth embodiment. Figure 8 The structure of the primary side circuit 1 is similar to that in Figure 6The structure of the primary side circuit 1 is the same as that after deleting the ASC_IN terminal, the ASC_EN terminal and the input priority determination circuit 18. Figure 8 The structure of the secondary side circuit 5 is similar to that in Figure 6 The structure of the secondary side circuit 5 is the same as that of the secondary side circuit 5 except that a waveform shaping circuit 72 is added.

[0109] In the fourth embodiment, a plurality of signals are selectively input to the IN terminal of the primary side circuit 1. The plurality of signals include a first control signal and a control transition signal. The control transition signal corresponds to the second control signal and the transition signal described above, and includes a burst-shaped pulse having a shorter pulse width than the first control signal.

[0110] The ASC mode determination circuit 63 determines whether the normal mode or the ASC mode is being executed based on the transmission transition signal corresponding to the control transition signal.

[0111] The modulation circuits 11 and 12, the demodulation circuits 51 and 52, and the pulse restoration circuit 61 generate a signal including a burst-shaped pulse corresponding to the control transition signal. In the fourth embodiment, the waveform of the signal output from the pulse restoration circuit 61 is substantially the same as the control transition signal. The waveform shaping circuit 72 generates a second transmission control signal as a square wave signal based on the signal output from the pulse restoration circuit 61. When the ASC mode determination circuit 63 determines that the ASC mode is being executed, the logic circuit 65 drives the semiconductor element based on the second transmission control signal as a square wave signal generated by the waveform shaping circuit 72.

[0112] Fig. 9 1 is a timing diagram showing the operation of the semiconductor element driving device according to the fourth embodiment. The following describes the normal mode, the normal mode when an abnormality is detected, the ASC mode, and the ASC mode when an abnormality is detected. In the following description of each mode, repeated contents are appropriately omitted.

[0113] <Normal Mode>

[0114] In normal mode, the first control signal is input to the IN terminal. The modulation circuits 11 and 12 generate modulation signals by edge-triggered modulation of the first control signal. The modulation signals generated by the modulation circuits 11 and 12 are provided to the demodulation circuits 51 and 52 via the signal transmission circuit 3, respectively.

[0115] The demodulation circuits 51 and 52 output edge trigger signals equivalent to the modulation signals generated by the modulation circuits 11 and 12 to the S terminal and the R terminal of the pulse restoration circuit 61, respectively. The pulse restoration circuit 61 generates a first transmission control signal having a waveform substantially the same as the first control signal input to the primary side circuit 1 based on the edge trigger signals output from the demodulation circuits 51 and 52, and outputs it from the Q terminal to the waveform shaping circuit 72. The first transmission control signal has a frequency less than the threshold value, and therefore, the waveform shaping circuit 72 outputs the first transmission control signal to the logic circuit 65.

[0116] The ASC mode determination circuit 63 does not count the pulse of the transmission transition signal N times within the determination cycle, and therefore determines that the normal mode is being executed. In addition, the ASC mode determination circuit 63 according to the fourth embodiment is different from the ASC mode determination circuit 63 according to the first to third embodiments, and determines whether each signal provided to the IN terminal is the first control signal of the normal mode or the control transition signal of the ASC mode.

[0117] As a result of the above operation, the logic circuit 65 outputs a drive signal to the OUT terminal based on the first transfer control signal corresponding to the first control signal.

[0118] <Normal mode when an abnormality is detected>

[0119] The normal mode when an abnormality is detected in the present embodiment 4 is the same as the normal mode when an abnormality is detected in the embodiment 3. That is, the abnormality detection protection action circuit 64 outputs the abnormality detection signal of the valid signal to the logic circuit 65, and the logic circuit 65 outputs the signal for stopping the operation of the semiconductor element to the OUT terminal regardless of the first transmission control signal. In addition, the transmission result signal of the valid signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection protection action circuit 64 is output to the FO terminal of the primary side circuit 1.

[0120] <ASC Mode>

[0121] In the ASC mode, the control transition signal is input to the IN terminal. The modulation circuits 11 and 12 generate modulation signals including burst-shaped pulses by edge-triggering the control transition signal. The modulation signals generated by the modulation circuits 11 and 12 are provided to the demodulation circuits 51 and 52 respectively via the signal transmission circuit 3.

[0122] The demodulation circuits 51 and 52 output edge trigger signals equivalent to the modulation signals generated by the modulation circuits 11 and 12 to the S terminal and the R terminal of the pulse restoration circuit 61. In addition, the demodulation circuits 51 and 52 output edge trigger signals equivalent to the modulation signals generated by the modulation circuits 11 and 12 to the OR circuit 70.

[0123] The pulse restoration circuit 62 generates a signal having a waveform substantially the same as the control transition signal input to the primary side circuit 1 based on the edge trigger signal output from the demodulation circuits 51 and 52, and outputs the signal from the Q terminal to the waveform shaping circuit 72. The signal output from the pulse restoration circuit 62 has a frequency greater than or equal to the threshold value, so the waveform shaping circuit 72 generates a second transmission control signal as a square wave signal based on the signal, and outputs the second transmission control signal to the logic circuit 65.

[0124] The OR circuit 70 outputs a logical OR signal of the edge-triggered signals output from the demodulation circuits 51 and 52 to the ASC mode determination circuit 63. Similar to the transmission transition signal of the third embodiment, the ASC mode determination circuit 63 counts the pulses of the logical OR signal including the burst-shaped pulses a predetermined N times within the determination cycle, and thus determines that the ASC mode is being executed.

[0125] The ASC mode involved in the present embodiment 3 hereafter is the same as the ASC mode involved in the embodiment 3. That is, the logic circuit 65 outputs the drive signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal. In addition, the transmission result signal of the valid signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection protection operation circuit 64 is output to the FO terminal of the primary side circuit 1.

[0126] <ASC mode when abnormality is detected>

[0127] The logic circuit 65 outputs a drive signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal when the ASC mode determination circuit 63 determines that the ASC mode is being executed and the abnormality of the semiconductor element is detected by the abnormality detection protection action circuit 64. In addition, a transmission result signal of a valid signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection protection action circuit 64 is output to the FO terminal of the primary side circuit 1.

[0128] <Summary of Implementation Method 4>

[0129] According to the semiconductor element driving device involved in the present embodiment 4, similarly to the embodiments 1 to 3, the ASC mode determination circuit 63 of the secondary side circuit 5 determines whether the normal mode or the ASC mode is being executed based on the transmission transition signal corresponding to the transition signal. According to such a structure, the secondary side circuit 5 can distinguish the operation of the ASC mode when an abnormality is detected from the operation of the normal mode when an abnormality is detected based on the determination result of the ASC mode determination circuit 63.

[0130] Furthermore, according to the fourth embodiment, the ASC_IN terminal, the ASC_EN terminal, and the input priority determination circuit 18 can be eliminated from the configuration of the third embodiment, and therefore, it is expected that the area and the number of components of the semiconductor element driving device can be reduced.

[0131] In addition, the embodiments and the modifications can be freely combined, or the embodiments and the modifications can be appropriately modified or omitted.

[0132] Hereinafter, each aspect of the present invention will be described collectively as supplementary notes.

[0133] (Note 1)

[0134] A semiconductor element driving device, comprising:

[0135] a primary-side circuit to which a plurality of signals are input, the plurality of signals including a first control signal for controlling the driving of a semiconductor element in a normal mode, a second control signal for controlling the driving of the semiconductor element in an ASC mode, and a transition signal for transitioning from the normal mode to the ASC mode, or including the first control signal and a control transition signal corresponding to the second control signal and the transition signal;

[0136] a signal transmission circuit comprising an insulating element capable of realizing signal transmission; and

[0137] a secondary side circuit that drives the semiconductor element based on a plurality of transmission signals corresponding to the plurality of signals transmitted from the primary side circuit via the signal transmission circuit,

[0138] The secondary side circuit comprises:

[0139] An ASC mode determination circuit that determines whether the normal mode or the ASC mode is being executed based on a transmission transition signal corresponding to the transition signal or the control transition signal among the plurality of transmission signals; and

[0140] A logic circuit that drives the semiconductor element based on a first transmission control signal corresponding to the first control signal among the multiple transmission signals when the ASC mode determination circuit determines that the normal mode is being executed, and drives the semiconductor element based on a second transmission control signal corresponding to the second control signal or the control transition signal among the multiple transmission signals when the ASC mode determination circuit determines that the ASC mode is being executed.

[0141] (Note 2)

[0142] The semiconductor element driving device according to Supplementary Note 1, wherein:

[0143] The transmission transition signal comprises a burst-shaped pulse,

[0144] The ASC mode determination circuit determines that the ASC mode is being executed when the pulse of the transmission transition signal is counted a predetermined number of times within a predetermined period.

[0145] (Note 3)

[0146] The semiconductor element driving device according to Supplement 1 or 2, wherein:

[0147] The secondary side circuit further includes an abnormality detection circuit for detecting an abnormality of the semiconductor element.

[0148] When the ASC mode determination circuit determines that the normal mode is being executed and the abnormality detection circuit detects an abnormality in the semiconductor element, the logic circuit performs an operation to protect the semiconductor element regardless of the first transmission control signal.

[0149] The logic circuit drives the semiconductor element based on the second transfer control signal when the ASC mode determination circuit determines that the ASC mode is being executed and the abnormality detection circuit detects an abnormality in the semiconductor element.

[0150] (Note 4)

[0151] The semiconductor element driving device according to any one of Supplementary Notes 1 to 3, wherein:

[0152] The primary side circuit includes a modulation circuit, the modulation circuit generating a modulation signal based on the rising edge and the falling edge of the first control signal, respectively.

[0153] The secondary-side circuit further includes a demodulation circuit that generates an edge trigger signal used for generating the first transmission control signal based on the modulation signal transmitted from the primary-side circuit via the signal transmission circuit.

[0154] (Note 5)

[0155] The semiconductor element driving device according to Supplementary Note 4, wherein:

[0156] The secondary-side circuit further includes a pulse restoration circuit that generates the first transmission control signal based on the edge trigger signal.

[0157] (Note 6)

[0158] The semiconductor element driving device according to Supplement 1 or 2, wherein:

[0159] The secondary side circuit further includes an abnormality detection circuit that outputs an abnormality detection signal indicating a detection result of an abnormality of the semiconductor element.

[0160] The primary side circuit includes a terminal for outputting a transmission result signal corresponding to the abnormality detection signal transmitted from the secondary side circuit via the signal transmission circuit to the outside.

[0161] (Note 7)

[0162] The semiconductor element driving device according to Supplement 1 or 2, wherein:

[0163] The secondary side circuit further comprises:

[0164] an abnormality detection circuit that outputs an abnormality detection signal indicating a result of detecting an abnormality of the semiconductor element; and

[0165] a modulation circuit that generates a modulation signal including burst-shaped pulses based on the abnormality detection signal,

[0166] The primary side circuit comprises:

[0167] a demodulation circuit that generates a burst signal including burst-shaped pulses based on the modulation signal transmitted from the secondary side circuit via the signal transmission circuit; and

[0168] An output circuit smoothes the burst signal to generate a transmission result signal corresponding to the abnormality detection signal.

[0169] (Note 8)

[0170] The semiconductor element driving device according to any one of Supplementary Notes 1 to 7, wherein:

[0171] The plurality of signals include the first control signal, the second control signal, and the transition signal.

[0172] The primary side circuit includes an input priority determination circuit that selectively outputs the first control signal and the second control signal to the signal transmission circuit based on the transition signal.

[0173] (Note 9)

[0174] A semiconductor element driving device according to Supplementary Note 8, wherein:

[0175] The secondary side circuit further includes an abnormality detection circuit for detecting an abnormality of the semiconductor element.

[0176] The input priority determination circuit selectively outputs the first control signal and the second control signal to the signal transmission circuit based on the transition signal, the determination result of the ASC mode determination circuit transmitted from the secondary side circuit via the signal transmission circuit, and the transmission result signal corresponding to the detection result of the abnormality detection circuit.

[0177] (Note 10)

[0178] The semiconductor element driving device according to any one of Supplementary Notes 1 to 7, wherein:

[0179] The plurality of signals include the first control signal and the control transition signal,

[0180] The secondary side circuit further includes a waveform shaping circuit that generates the second transmission control signal as a square wave signal based on a signal including a burst-shaped pulse corresponding to the control transition signal transmitted from the primary side circuit via the signal transmission circuit.

[0181] (Note 11)

[0182] The semiconductor element driving device according to any one of Supplementary Notes 1 to 10, wherein:

[0183] The isolation elements include transformers that are magnetically coupled to each other.

[0184] (Note 12)

[0185] The semiconductor element driving device according to any one of Supplementary Notes 1 to 10, wherein:

[0186] The insulating elements include capacitors that are capacitively coupled to each other.

[0187] (Note 13)

[0188] The semiconductor element driving device according to any one of Supplementary Notes 1 to 10, wherein:

[0189] The insulating elements include optical couplers that are optically coupled to each other.

[0190] Description of the label

[0191] 1 primary side circuit, 3 signal transmission circuit, 5 secondary side circuit, 11~15, 56 modulation circuit, 16, 51~55 demodulation circuit, 17FO output circuit, 18 input priority judgment circuit, 61, 62 pulse recovery circuit, 63ASC mode judgment circuit, 64 abnormal detection protection action circuit, 65 logic circuit, 70OR circuit, 72 waveform shaping circuit.

Claims

1. A semiconductor element driving device, comprising: a primary-side circuit to which a plurality of signals are input, the plurality of signals including a first control signal for controlling the driving of a semiconductor element in a normal mode, a second control signal for controlling the driving of the semiconductor element in an ASC mode, and a transition signal for transitioning from the normal mode to the ASC mode, or including the first control signal and a control transition signal corresponding to the second control signal and the transition signal; A signal transmission circuit comprising an insulating element capable of realizing signal transmission; as well as a secondary side circuit that drives the semiconductor element based on a plurality of transmission signals corresponding to the plurality of signals transmitted from the primary side circuit via the signal transmission circuit, The secondary side circuit comprises: an ASC mode determination circuit for determining whether the normal mode or the ASC mode is being executed based on a transmission transition signal corresponding to the transition signal or the control transition signal among the plurality of transmission signals; as well as A logic circuit that drives the semiconductor element based on a first transmission control signal corresponding to the first control signal among the multiple transmission signals when the ASC mode determination circuit determines that the normal mode is being executed, and drives the semiconductor element based on a second transmission control signal corresponding to the second control signal or the control transition signal among the multiple transmission signals when the ASC mode determination circuit determines that the ASC mode is being executed.

2. The semiconductor element driving device according to claim 1, wherein: The transmission transition signal comprises a burst-shaped pulse, The ASC mode determination circuit determines that the ASC mode is being executed when the pulse of the transmission transition signal is counted a predetermined number of times within a predetermined period.

3. The semiconductor element driving device according to claim 1 or 2, wherein: The secondary side circuit further includes an abnormality detection circuit for detecting an abnormality of the semiconductor element. When the ASC mode determination circuit determines that the normal mode is being executed and the abnormality detection circuit detects an abnormality in the semiconductor element, the logic circuit performs an action to protect the semiconductor element regardless of the first transmission control signal. The logic circuit drives the semiconductor element based on the second transfer control signal when the ASC mode determination circuit determines that the ASC mode is being executed and the abnormality detection circuit detects an abnormality in the semiconductor element.

4. The semiconductor element driving device according to any one of claims 1 to 3, wherein: The primary side circuit includes a modulation circuit, the modulation circuit generating a modulation signal based on the rising edge and the falling edge of the first control signal, respectively. The secondary-side circuit further includes a demodulation circuit that generates an edge trigger signal used for generating the first transmission control signal based on the modulation signal transmitted from the primary-side circuit via the signal transmission circuit.

5. The semiconductor element driving device according to claim 4, wherein: The secondary-side circuit further includes a pulse restoration circuit that generates the first transmission control signal based on the edge trigger signal.

6. The semiconductor element driving device according to claim 1 or 2, wherein: The secondary side circuit further includes an abnormality detection circuit that outputs an abnormality detection signal indicating a detection result of an abnormality of the semiconductor element. The primary side circuit includes a terminal for outputting a transmission result signal corresponding to the abnormality detection signal transmitted from the secondary side circuit via the signal transmission circuit to the outside.

7. The semiconductor element driving device according to claim 1 or 2, wherein: The secondary side circuit further comprises: an abnormality detection circuit that outputs an abnormality detection signal indicating a result of detecting an abnormality of the semiconductor element; and a modulation circuit that generates a modulation signal including burst-shaped pulses based on the abnormality detection signal, The primary side circuit comprises: a demodulation circuit that generates a burst signal including burst-shaped pulses based on the modulation signal transmitted from the secondary side circuit via the signal transmission circuit; and An output circuit smoothes the burst signal to generate a transmission result signal corresponding to the abnormality detection signal.

8. The semiconductor element driving device according to any one of claims 1 to 7, wherein: The plurality of signals include the first control signal, the second control signal, and the transition signal. The primary side circuit includes an input priority determination circuit that selectively outputs the first control signal and the second control signal to the signal transmission circuit based on the transition signal.

9. The semiconductor element driving device according to claim 8, wherein: The secondary side circuit further includes an abnormality detection circuit for detecting an abnormality of the semiconductor element. The input priority determination circuit selectively outputs the first control signal and the second control signal to the signal transmission circuit based on the transition signal, the determination result of the ASC mode determination circuit transmitted from the secondary side circuit via the signal transmission circuit, and the transmission result signal corresponding to the detection result of the abnormality detection circuit.

10. The semiconductor element driving device according to any one of claims 1 to 7, wherein: The plurality of signals include the first control signal and the control transition signal, The secondary side circuit further includes a waveform shaping circuit that generates the second transmission control signal as a square wave signal based on a signal including a burst-shaped pulse corresponding to the control transition signal transmitted from the primary side circuit via the signal transmission circuit.

11. The semiconductor element driving device according to any one of claims 1 to 10, wherein: The isolation elements include transformers that are magnetically coupled to each other.

12. The semiconductor element driving device according to any one of claims 1 to 10, wherein: The insulating elements include capacitors that are capacitively coupled to each other.

13. The semiconductor element driving device according to any one of claims 1 to 10, wherein: The insulating elements include optical couplers that are optically coupled to each other.

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