Double-closed-loop control circuit of two-phase interleaving synchronous rectification Buck power converter

Abstract

The invention discloses a double-closed-loop control circuit of a two-phase interleaving synchronous rectification Buck power converter, and belongs to the technical field of power converter control. Wherein the first phase synchronous rectification Buck current control circuit and the second phase synchronous rectification Buck current control circuit are connected in parallel in a staggered manner to form a current control loop part of a main loop, and two-phase current output control of the current control loop part of the main loop is used as inner loop current control of the double-closed-loop control circuit; the voltage closed-loop compensation control circuit is connected with the first phase synchronous rectification Buck current control circuit and the second phase synchronous rectification Buck current control circuit, and output voltage closed-loop regulation control serves as outer loop voltage control of the double closed-loop control circuit. The invention provides a double-closed-loop control circuit of a two-phase interleaving parallel synchronous rectification Buck power converter, which solves the problems of phase interleaving and balancing and system stability, and improves the overall energy efficiency of a system.

Description

Technical Field

[0001] The present application belongs to the technical field of power converter control, and in particular relates to a dual closed-loop control circuit of a two-phase staggered parallel synchronous rectification Buck power converter. Background Art

[0002] In the field of power converter technology, Buck circuit, as an efficient DC-DC converter, is widely used in voltage regulation and power management. As the requirements of electronic equipment for power performance continue to increase, the traditional single-phase Buck circuit can no longer meet the market demand for high power, high efficiency and low ripple output. Therefore, the two-phase Buck circuit has become the first choice for high-performance power applications because it can provide higher power handling capabilities and lower output ripple.

[0003] However, the design and implementation of existing two-phase Buck circuits face several technical challenges that limit their full performance:

[0004] 1. Accuracy and balance of phase difference control: In a two-phase Buck circuit, in order to achieve uniform load distribution and reduce output ripple, the current and voltage phase difference of each phase must be accurately controlled to achieve effective phase interleaving. This requirement is particularly critical in high-frequency operating environments, but it is quite challenging to achieve because any phase control error may significantly affect the overall performance of the circuit.

[0005] 2. Complexity and stability of control systems: The design complexity of control systems has a direct impact on the stability of the system. Although complex control loops can provide more sophisticated control, they also increase the risk of system instability. Therefore, designers must find a balance between control accuracy and system stability to ensure that the circuit can operate stably under various working conditions. Summary of the invention

[0006] In order to solve the problems in the related technology, the present application provides a two-phase interleaved parallel synchronous rectification Buck power converter dual closed-loop control circuit, which aims to solve the problems of phase interleaving and balance and system stability through innovative control strategies, thereby improving the overall energy efficiency of the system.

[0007] The technical solution is as follows:

[0008] A two-phase staggered parallel synchronous rectification Buck power converter double closed-loop control circuit, comprising: a first-phase synchronous rectification Buck current control circuit, a second-phase synchronous rectification Buck current control circuit and a voltage closed-loop compensation control circuit;

[0009] The first-phase synchronous rectification Buck current control circuit and the second-phase synchronous rectification Buck current control circuit are connected in parallel and staggered to form the current control loop part of the main loop. The two-phase current output control of the current control loop part of the main loop serves as the inner loop current control of the double closed-loop control circuit, which is used for two-way current signal feedback conditioning and current closed-loop PID control adjustment;

[0010] The voltage closed-loop compensation control circuit is connected to the first-phase synchronous rectification Buck current control circuit and the second-phase synchronous rectification Buck current control circuit respectively. The output voltage closed-loop regulation control serves as the outer-loop voltage control of the dual closed-loop control circuit and is used for voltage signal feedback conditioning and voltage closed-loop PID regulation control.

[0011] According to a further technical solution, a phase difference between a first-phase control driving signal of a first-phase synchronous rectification Buck current control circuit and a second-phase control driving signal of a second-phase synchronous rectification Buck current control circuit is 180°.

[0012] A further technical solution is that the first-phase synchronous rectification Buck current control circuit includes an operational amplifier chip unit U5A, the positive input end of the operational amplifier chip unit U5A is respectively connected to the sixteenth resistor R16, the seventeenth resistor R17, and the fifteenth resistor C15 and is grounded to receive the output signal of the voltage closed-loop compensation control circuit as the input given signal of the first-phase synchronous rectification Buck current control circuit, the negative input end of the operational amplifier chip unit U5A is connected to the first-phase main loop current output sensor feedback signal Vcfb1 through the fifteenth resistor R15, the output end of the operational amplifier chip unit U5A and the negative input end of the operational amplifier chip unit U5A are respectively connected to the second-order compensation network composed of the ninth capacitor C9, the tenth capacitor C10, and the fourteenth resistor R14, and the output end of the operational amplifier chip unit U5A is connected to the pulse width modulation generation circuit.

[0013] A further technical solution is that the voltage closed-loop compensation control circuit includes an operational amplifier chip unit U9A, the positive input end of the operational amplifier chip unit U9A is respectively connected to the seventeenth capacitor C17, the twenty-fourth resistor R24, and the twenty-third resistor R23 to receive the set voltage reference signal, and the negative output end of the operational amplifier chip unit U9A is connected to the fifteenth resistor R25 to input the voltage output sensor feedback signal Vfb1. After the two signals enter the operational amplifier chip unit U9A, a phase difference operation is performed, and then a PID compensation operation is performed after entering the second-order compensation network composed of the operational amplifier chip unit U9A and the thirteenth capacitor C13, the twenty-second resistor R22, and the fourteenth capacitor C14. The output end of the operational amplifier chip unit U9A obtains the output signal of the voltage closed-loop PID regulation control.

[0014] A further technical solution is that the dual closed-loop control circuit also includes a clock source generating circuit, a control signal distribution circuit connected to the clock source generating circuit, a trigger pulse control signal circuit connected to the control signal distribution circuit, a triangular sawtooth wave generating circuit connected to the trigger pulse control signal circuit, and a power supply circuit. The clock source generating circuit generates a square wave signal with an adjustable frequency. After the square wave signal passes through the two-channel control signal distribution circuit, two staggered synchronous control signals with a phase difference of 180° are generated to the two-channel staggered phase trigger pulse control signal circuit. The two short pulse trigger signals generated by the two-channel staggered phase trigger pulse signal control circuit serve as the start and end signals of the two-channel triangular sawtooth wave generating circuit.

[0015] According to a further technical solution, the power supply circuit is constructed by a power voltage regulator chip and discrete resistor and capacitor components.

[0016] According to a further technical solution, the power supply of the two-channel triangular sawtooth wave circuit is provided by two constant current source generating circuits, so as to generate a constant charging current for the two-channel circuit.

[0017] In a further technical solution, the triangular sawtooth wave circuits of the two channels are connected to the pulse width modulation generating circuit, the pulse width modulation generating circuit is connected to the signal driving circuit, the negative input terminal of the comparator U6A of the pulse width modulation generating circuit (6) is connected to the drain of the third MOSFET tube Q3 of the triangular sawtooth wave circuit 8, the positive input terminal of the comparator U6A is connected to the output terminal of the operational amplifier chip unit U5A of the first phase synchronous rectification Buck current control circuit 9, and the output terminal of the comparator U6A is connected to the signal driving circuit;

[0018] The negative input terminal of the comparator U6B of the pulse width modulation generating circuit 6 is connected to the drain of the fourth MOSFET tube Q4 of the triangular sawtooth wave circuit 8, the positive input terminal of the comparator U6B is connected to the output terminal of the operational amplifier chip unit U5B of the second phase synchronous rectification Buck current control circuit 10, and the output terminal of the comparator U6B is connected to the signal driving circuit.

[0019] A further technical solution is that the signal driving circuit of the two channels is used for the upper bridge arm and the lower bridge arm of the two power switch tubes in each main power loop circuit with dead zone signal interlocking, and the two driving signals of each channel are transmitted to the control electrodes of the upper bridge arm and the lower bridge arm of the power switch tube to be controlled, respectively, to provide control gate drive signals for the four switch power tubes in the main loop of the main power loop circuit.

[0020] A further technical solution is that the signal driving circuit of the two channels includes two NAND gate unit modules, the input ends of the two NAND gate unit modules respectively receive the two-phase duty cycle PWM signals of the pulse width modulation generating circuit 6, and then generate two-phase signals with opposite logical directions corresponding to the two phases, thereby obtaining two groups of signals used for two-phase staggered parallel control, that is, four signals.

[0021] The technical solution includes at least the following technical effects:

[0022] The first-phase synchronous rectification Buck current control circuit and the second-phase synchronous rectification Buck current control circuit are connected in parallel in an alternating manner to form the current control loop part of the main loop. The two-phase current output control of the current control loop part of the main loop serves as the inner-loop current control of the dual closed-loop control circuit; the voltage closed-loop compensation control circuit is respectively connected to the first-phase synchronous rectification Buck current control circuit and the second-phase synchronous rectification Buck current control circuit, and the output voltage closed-loop regulation control serves as the outer-loop voltage control of the dual closed-loop control circuit. The dual closed-loop control strategy of the voltage outer loop and the current inner loop adopted in this application can effectively realize the precise control of current and voltage, and improve the performance and stability of the power converter.

[0023] It should be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0025] Figure 1 It is a circuit principle block diagram of a single-phase synchronous rectification Buck power converter in the prior art;

[0026] Figure 2 A circuit diagram of a two-phase interleaved parallel synchronous rectifier Buck power converter provided in an embodiment of the present application;

[0027] Figure 3 A dual closed-loop control circuit for a two-phase interleaved parallel synchronous rectification Buck power converter provided in an embodiment of the present application;

[0028] 1. Clock source generation circuit; 2. Power supply circuit; 3. Control signal distribution circuit; 4. Trigger pulse control signal circuit; 5. Constant current source generation circuit; 6. Pulse width modulation generation circuit; 7. Signal drive circuit; 8. Triangle sawtooth wave generation circuit; 9. First phase synchronous rectification Buck current control circuit; 10. Second phase synchronous rectification Buck current control circuit; 11. Voltage closed-loop compensation control circuit. DETAILED DESCRIPTION

[0029] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0030] Figure 1 The figure shows a circuit diagram of a single-phase synchronous rectification Buck power converter in the prior art.

[0031] like Figure 1 As shown, a one-phase synchronous rectification Buck power converter circuit includes an input power supply Vin, an input side capacitor C1, an upper bridge arm switch tube Q1, a lower bridge arm switch tube Q2, a voltage conversion power inductor L1, an output side capacitor C2, an output voltage sensor VS1, a main circuit current sensor CS1, a synchronous rectification Buck control circuit PCB1, a PWM drive circuit DB1, an output voltage Vout, etc., wherein the resistor R1 is a load, the upper bridge arm switch tube Q1 and the lower bridge arm switch tube Q2 are N-type MOS field effect tubes, and the output side capacitor C2 is a filter capacitor.

[0032] The upper arm switch tube Q1 is turned on and enters the on state under the action of the synchronous rectification Buck control circuit PCB1 and the PWM drive circuit DB1. One end of the inductor L1 is connected to the positive electrode of the input power supply Vin through the upper arm switch tube Q1, and the other end of the inductor L1 is connected to the positive electrode of the output voltage Vout. Therefore, the difference between the input voltage Vin and the output voltage Vout will cause the current of the inductor L1 to increase. At the same time, during the on time of the upper arm switch tube Q1, the lower arm switch tube Q2 is in the off state, and the output filter capacitor C2 and the inductor L1 simultaneously provide electrical energy to the load R1.

[0033] When the upper-arm switch tube Q1 is turned off by the signal driving circuit DB1, the lower-arm switch tube Q2 is turned on, and the current of the inductor L1 cannot change suddenly. The energy stored in the inductor L1 during the conduction time of the upper-arm switch tube Q1 is supplied to the load R1 through the lower-arm switch tube Q2; in the balance between the inductor power supply and the load power consumption, the output filter capacitor C2 maintains the output voltage basically constant.

[0034] The on-time and off-time of the upper-arm switch tube Q1 and the lower-arm switch tube Q2 are jointly determined by the synchronous rectification Buck control circuit PCB1 and the drive control circuit DB1 to ensure that the output voltage is a certain set voltage value.

[0035] The synchronous rectification Buck control circuit PCB1 performs PID control adjustment of the current closed loop according to the current signal fed back by the current sensor CS1;

[0036] When the current exceeds the required regulation current, the PWM duty cycle of the control signal is reduced to the upper bridge arm switch tube Q1;

[0037] When the current is less than the required regulated current, the duty cycle of the control signal PWM is increased to the upper bridge arm switch tube Q1, thereby maintaining the required current basically constant at a current stable value within a very small controllable fluctuation range.

[0038] The synchronous rectification Buck control circuit PCB1 performs PID control adjustment of the voltage closed loop according to the voltage signal fed back by the voltage sensor VS1;

[0039] When the output voltage exceeds the set regulated output voltage, the control circuit PCB1 reduces the PWM duty cycle of the control signal to the upper bridge arm switch tube Q1;

[0040] When the output voltage is less than the required set regulation voltage, the control signal PWM duty cycle is increased to the upper bridge arm switch tube Q1, so as to maintain the required voltage basically constant at a voltage stability value within a very small controllable fluctuation range accuracy.

[0041] Figure 2 The figure shows the principle block diagram of the two-phase interleaved parallel synchronous rectification Buck power converter circuit. Figure 1 Developed on the basis of.

[0042] like Figure 2 As shown, the main power loop circuit part is formed by connecting the main power loops of two basic synchronous rectification Buck circuits in parallel. The first power switch tube Q1 and the second power switch tube Q2 of the first phase main loop and the third power switch tube Q3 and the fourth power switch tube Q4 of the second phase main loop are driven and controlled by a phase shift of 180°. The first power switch tube Q1, the second power switch tube Q2, the third power switch tube Q3 and the fourth power switch tube are N-type MOS field effect tubes.

[0043] The first inductor L1 is the power conversion power inductor of the first phase main circuit, the second inductor L2 is the power conversion power inductor of the second phase main circuit, the first current feedback sensor CS1 is the current feedback sensor of the first phase main circuit, the second current feedback sensor CS2 is the current feedback sensor of the second phase main circuit, the sensor VS1 is the output power supply voltage sensor shared by the two-phase main circuits, the first capacitor C1 is the input side capacitor, and the second capacitor C2 is the output side capacitor.

[0044] The synchronous rectification BUCk control circuit PCB1 and the PWM drive circuit DB1 share a circuit respectively. The input side capacitor C1 is shared by the two-phase main circuit as an input to provide a transient energy source. The output side capacitor C2 is also shared by the two-phase main circuit as an output to provide a transient energy source. The current signals fed back by the two current sensors and the voltage signals fed back by the one voltage sensor enter the synchronous rectification Buck control circuit PCB1 together. The synchronous rectification Buck control circuit PCB1 adjusts and controls the duty ratio of the output two groups of PWM pulse drive signals with a phase difference of 180° according to the feedback current signal and voltage signal to respectively give the upper bridge arm power switch tube and the lower bridge arm power switch tube of the two-phase main circuit, thereby realizing the double closed-loop control adjustment of the output voltage and the two-channel main circuit current, achieving the effect of stable output voltage and fast response speed. The circuit improves the EMC characteristics, reduces the stress of the power tube, reduces the switching loss, and improves the heat dissipation.

[0045] Figure 3 A dual closed-loop control circuit for a two-phase interleaved parallel synchronous rectification Buck power converter is provided in an embodiment of the present application.

[0046] like Figure 3 As shown, this embodiment provides a two-phase staggered parallel synchronous rectification Buck power converter dual closed-loop control circuit, including a clock source generating circuit 1, a control signal distribution circuit 3, a trigger pulse control signal circuit 4, a two-channel triangular sawtooth wave generating circuit 8, a power supply circuit 2, a two-channel constant current source generating circuit 5, a pulse width modulation generating circuit 6, a four-channel signal driving circuit 7, a first-phase synchronous rectification Buck current control circuit 9, a second-phase synchronous rectification Buck current control circuit 10, and a voltage closed-loop compensation control circuit 11.

[0047] The first-phase synchronous rectification Buck current control circuit 9 and the second-phase synchronous rectification Buck current control circuit 10 are staggered and connected in parallel to form the current control loop part of the main loop. The two-phase current output control of the current control loop part of the main loop serves as the inner-loop current control of the dual closed-loop control circuit, which is used for two-way current signal feedback conditioning and current closed-loop PID control adjustment; the phase difference between the first-phase control drive signal of the first-phase synchronous rectification Buck current control circuit 9 and the second-phase control drive signal of the second-phase synchronous rectification Buck current control circuit 10 is 180°. The inner-loop current control of the dual closed-loop control circuit is to achieve a stable output of current through two-way staggered synchronous parallel two-phase current closed-loop regulation control, and the output current acts on the two-way current compensation network and the control regulation loop circuit according to the output given signal of the voltage loop and the two-way actual current feedback signal.

[0048] The voltage closed-loop compensation control circuit 11 is connected to the first-phase synchronous rectification Buck current control circuit 9 and the second-phase synchronous rectification Buck current control circuit 10 respectively, and the output voltage closed-loop regulation control is used as the outer-loop voltage control of the dual closed-loop control circuit for voltage signal feedback conditioning and voltage closed-loop PID regulation control. The outer loop of the controller circuit is to achieve stable output of the output voltage through the output voltage closed-loop regulation control, and the output voltage can be set according to the set reference signal value. The set reference value signal and the actual value signal of the feedback act together on the voltage compensation network and the control regulation loop circuit, so as to achieve the effect of stable output voltage.

[0049] The staggered clock source synchronous generating circuit generates a square wave signal with adjustable frequency. After passing through the two-channel control signal distribution circuit, the square wave signal generates two staggered synchronous control signals with a phase difference of 180° to the two-channel staggered phase trigger pulse control signal circuit. The two short pulse trigger signals generated by the two-channel staggered phase trigger pulse signal control circuit serve as the start and end signals of the triangular sawtooth wave generating circuit of the two channels.

[0050] The power supply of the two-channel triangular sawtooth wave circuit is provided by the two-channel constant current source generating circuit, which is used to generate a constant charging current of the two-channel circuit, thereby controlling the charge and discharge cycle and the voltage signal amplitude reached by charging.

[0051] The negative input terminal of the comparator U6A of the pulse width modulation generating circuit 6 is connected to the drain of the third MOSFET tube Q3 of the triangular sawtooth wave circuit 8, the positive input terminal of the comparator U6A is connected to the output terminal of the operational amplifier chip unit U5A of the first phase synchronous rectification Buck current control circuit 9, and the output terminal of the comparator U6A is connected to the signal driving circuit; the negative input terminal of the comparator U6B of the pulse width modulation generating circuit 6 is connected to the drain of the fourth MOSFET tube Q4 of the triangular sawtooth wave circuit 8, the positive input terminal of the comparator U6B is connected to the output terminal of the operational amplifier chip unit U5B of the second phase synchronous rectification Buck current control circuit 10, and the output terminal of the comparator U6B is connected to the signal driving circuit.

[0052] The current feedback conditioning and control output signals of the second-phase synchronous rectification Buck current control circuit 10 and the first-phase synchronous rectification Buck current control circuit 9 and the sawtooth wave ramp signals generated by the triangular sawtooth wave circuit 8 of the two channels are respectively sent to the positive and negative ends of the two comparators of the pulse width modulation generation circuit 6 for comparison. The two comparators compare the two signals of each channel respectively and generate their own pulse width modulation PWM duty cycle signals for the two channels. The modulated PWM signals of the two channels respectively enter the signal driving circuit 7 of each channel.

[0053] The two-channel drive control circuit is used for the current control of each main circuit. The upper and lower bridge arms of the two power switch tubes in the main circuit have dead zone signal interlocking. Finally, the two drive signals of each channel are sent to the control electrodes of the upper and lower bridge arms of the power switch tube to be controlled, thereby providing control gate drive signals for the four switch power tubes in the two staggered parallel synchronous rectification main power circuits.

[0054] The second-order feedback compensation network circuit of the first-phase synchronous rectification Buck current control circuit 9 and the second-phase synchronous rectification Buck current control circuit 10 which are staggered in parallel with each other completes the feedback conditioning of two-way current signals and the current closed-loop PID control and adjustment functions.

[0055] The second-order feedback compensation network circuit of the voltage closed-loop compensation control circuit completes the voltage signal feedback conditioning and voltage closed-loop PID regulation control functions.

[0056] The voltage closed-loop compensation control circuit controls the adjustment output signal as the input given reference signal of the current closed-loop adjustment of the two staggered parallel first-phase synchronous rectification Buck current control circuits 9 and the second-phase synchronous rectification Buck current control circuits 10. The two staggered parallel current feedback conditioning signals and the power supply voltage feedback adjustment function output signal enter the current loop adjustment control loop circuit together to interact with each other to perform PID control to complete the current closed-loop adjustment function. The power supply voltage signal feedback signal and the adjustable given reference voltage signal enter the voltage closed-loop compensation control circuit together to form the voltage closed-loop PID adjustment control circuit function.

[0057] The power supply circuit constructed by the power voltage regulator chip and the discrete resistor and capacitor devices provides the required power supply voltage for control and signal conditioning to all other functional circuit parts.

[0058] In this embodiment, the power supply circuit 2 realizes the function of providing a stable power supply voltage for the entire dual closed-loop control circuit, which is implemented by the voltage stabilizer U10. The input Vin power supply voltage enters the input port of the voltage stabilizer U10 after filtering by the nineteenth capacitor C19 and the twentieth capacitor C20. The output port of the voltage stabilizer U10 is output to VDD after filtering and stabilization by the twenty-first capacitor C21 and the twenty-second capacitor C22. VDD provides a signal port input for the stable voltage of all other functional part circuits. The twenty-sixth resistor R26 and the twenty-seventh resistor R27 mainly realize the adjustment and setting function of the required stable output voltage, and the output voltage VDD is adjusted by the resistance parameters of the two resistors. Preferably, the voltage stabilizer U10 is a domestic three-terminal voltage stabilizer, model LM117.

[0059] In this embodiment, the clock source generating circuit 1 realizes the signal clock generating function of two-phase staggered synchronous parallel control, and the time base generator chip U1 is built with discrete resistor and capacitor components to complete the oscillation clock function, which serves as the time base of the entire double closed-loop control circuit. Preferably, the time base generator chip U1 is a domestic chip, model LM555. The three comparators inside the time base generator chip U1 are matched with the external discrete components of the first resistor R1, the second resistor R2, the first capacitor C1, and the second capacitor C2 to complete the clock signal generation function, and the frequency of the generated signal is set by adjusting the resistance of the first resistor R1 and the second resistor R2, and the capacitance parameter of the first capacitor C1. The 3-pin output signal of the time base generator chip U1 is the frequency signal generator waveform output generated by this part of the circuit, which is output to the control signal distribution circuit 3 of the later stage as the signal input of this control signal distribution circuit. The clock source generating circuit 1 in this embodiment is set to 200kHz.

[0060] In this embodiment, the control signal distribution circuit 3 realizes the function of the two-phase staggered parallel control synchronization signal distribution generation circuit. It is realized by using the trigger U2. Preferably, in this embodiment, only the A logic part of this chip is used, and the trigger U2 is a domestic simple sequential logic gate circuit integrated chip D trigger, model 74HC74D. The clock of the trigger U2 enters the trigger terminal 3 pin, and the state logic reverse output terminal 6 pin of the trigger returns to the state signal input terminal 2 pin of the trigger. When the signal of the clock edge trigger terminal 3 pin changes logically, the state of this trigger is logically reversed from the previous state, and the two state terminals 5 pin (positive logic state) and 6 pin (negative logic state) of the output are square wave signals with a phase difference of 180°, respectively. The frequency of these two signals is half of the output signal frequency of the input clock source generation circuit 1 part (this circuit is temporarily set to 100kHz). The two phases of this part of the functional circuit differ by 180°, and the frequency, duty cycle, high and low level amplitude of the waveform signal output are the same, but the phase difference is 180°. These two signals provide input signals to the trigger pulse control signal circuit 4 of the subsequent stage.

[0061] In this embodiment, the trigger pulse control signal circuit 4 realizes the two-phase staggered parallel control synchronization signal with a phase difference of 180° and the pulse generation and waveform shaping of the synchronous control signal. The combinational logic gate circuit NOT gate chip U3 is built in conjunction with the resistor, capacitor and diode discrete components to realize this circuit function. Preferably, the NOT gate chip U3 is a domestic chip with a model of 74HC04D. The NOT gate chip U3 uses four unit gates (U3A, U3B, U3C, U3D), U3A and U3B are used for the first phase pulse control signal, and U3C and U3D are used for the second phase pulse control signal.

[0062] The two interlaced parallel synchronous control signals from the control signal distribution circuit 3 enter the third capacitor C3 and the fourth capacitor C4 of the input capacitor elements of the trigger pulse control signal circuit 4 respectively. The components of the third capacitor C3, the first diode D1, the third resistor R3, U3A, and U3B constitute a first-phase synchronous trigger signal generating circuit, and the components of the fourth capacitor C4, the second diode D2, the fourth resistor R4, U3C, and U3D constitute a second-phase synchronous trigger signal generating circuit. The third capacitor C3 and the fourth capacitor C4 mainly function to process the input square wave signal to generate a sharp pulse signal. The first-phase square wave signal passing through the third capacitor C3 generates a first sharp pulse signal, and the second-phase square wave signal passing through the fourth capacitor C4 generates a second sharp pulse signal. After the two signals pass through the first diode D1, the third resistor R3, the second diode D2, and the fourth resistor R4, the voltage of the signal is limited and the anti-reverse processing function is performed, and then they enter the waveform shaping and level logic operation function circuit composed of two groups (U3A, U3B, U3C, and U3D) of logic gates of the NOT gate chip U3. After the two-way staggered synchronous trigger control signal passes through the two groups of logic gates, the output signal is a pulse signal with a very small duty cycle and a very narrow pulse signal with the frequency of the input signal remaining unchanged. The frequency of the two narrow pulse signals is the same as the frequency of the signals input to the third capacitor C3 and the fourth capacitor C4, and the signal phase remains unchanged. The phases of the two pulse signals are also 180° apart from each other. The output two narrow pulse signals are used as input signals of the two-phase triangular sawtooth wave generating circuit 8 of the subsequent stage.

[0063] In this embodiment, the constant current source generating circuit 5 realizes the function of providing a settable constant current charging current by the triangular sawtooth wave generating circuit 8 controlled by two-phase interleaved parallel connection. This is achieved by using a voltage reference source chip U4, an operational amplifier chip U5, and discrete resistors, capacitors, and transistor components. Preferably, the voltage reference source chip U4 is a domestic chip model TL431, and the operational amplifier chip U5 is a domestic chip model LM324.

[0064] The voltage reference source chip U4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the fifth capacitor C5, and the sixth capacitor C6 form an adjustable high-precision voltage reference signal generating circuit. The amplitude of the generated reference voltage signal is set by matching the resistance parameters of the sixth resistor R6 and the seventh resistor R7. The fifth capacitor C5 is used for filtering the input power supply voltage of the reference function circuit, and the sixth capacitor C6 is used for filtering the output voltage signal of the reference function circuit, thereby obtaining a more stable high-precision voltage signal. This high-precision voltage reference signal enters the positive input terminal of the two units (U5C, U5D) of the operational amplifier chip U5 as an input given reference signal. The outputs of U5C and U5D of the operational amplifier chip U5 act on the bases of the first transistor Q1 and the second transistor Q2, and then the emitters of the transistors act on the eighth resistor R8 and the ninth resistor R9, and the two constant current source generating circuits 5 are jointly formed. The emitter signals of the first transistor Q1 and the second transistor Q2 are simultaneously connected to the negative input terminals of the fifth C operational amplifier unit U5C and the fifth D operational amplifier unit U5D of the two unit circuits of the operational amplifier chip U5 as feedback signals, forming a negative feedback control regulation principle circuit to generate a constant current output from the collectors of the first transistor Q1 and the second transistor Q2. One of the two outputs is used for waveform generation by the triangular sawtooth wave generating circuit of the first phase of the staggered parallel synchronous control, and the other is used for the triangular sawtooth wave generating circuit of the second phase. By setting the voltage of the reference voltage circuit to the two-way constant current source generating circuit, the maximum allowable working voltage amplitude of the two-way constant current source generating circuit can be set, and by adjusting the resistance values ​​of the eighth resistor R8 and the ninth resistor R9, the constant charging current provided by the two-way channel constant current source generating circuit 5 to the two-way triangular sawtooth wave generating circuit 8 can be set. The output two-way constant current source current signal is output to the subsequent triangular sawtooth wave generating circuit 8 as an input current source, and is supplied to the circuit during the cross-current charging period inside the triangular sawtooth wave generating circuit 8.

[0065] The triangular sawtooth wave generating circuit 8 is implemented by the charging and discharging circuit principle. Preferably, it is constructed by using domestic MOSFET tubes and discrete components. When the two-way synchronous trigger narrow pulse signal output by the trigger pulse control signal circuit 4 is sent to the tenth resistor R10 and the eleventh resistor R11 of the triangular sawtooth wave generating circuit for current limiting processing, it enters the gates of the two MOSFET tubes, the third MOSFET tube Q3 and the fourth MOSFET tube Q4; when the two-way signal is a valid high-level pulse, the two MOSFET tubes, the third MOSFET tube Q3 and the fourth MOSFET tube Q4 are opened respectively; when the two-way signal is an invalid low level, the two tubes are closed, because the phase difference of the two-way synchronous trigger narrow pulse signal entering is 180°, so the time phase of the opening and closing of the two tubes will also differ by 180° phase shift. When the two tubes are turned on successively, the corresponding seventh capacitor C7 and eighth capacitor C8 will be discharged quickly. When the two tubes are turned off successively, the constant current set by the constant current source output by the collector of the first triode Q1 and the second triode Q2 of the constant current source generating circuit 5 will charge the corresponding two charging and discharging capacitors C7 and C8 at a constant rate. At this time, the voltage signal outputted at both ends of the two capacitors is the rising phase waveform of the two ramp sawtooth triangle waves with a constant slope. When the two MOSFET tubes, the third MOSFET tube Q3 and the fourth MOSFET tube Q4 are turned off successively, the corresponding seventh capacitor C7 and eighth capacitor C8 will be discharged quickly, thereby generating the falling phase waveform of the two sawtooth triangle waves. Through this principle, the two staggered parallel synchronous trigger signals continuously control the charging and discharging circuit to work, and will generate two continuous triangular waveforms with a phase difference of 180° for the subsequent modulation circuit. The high-frequency carrier signal used. The frequency generated by the two waveforms is the same as the input signal frequency, the highest voltage amplitude is the same, and the phase difference is 180°. The waveform signals generated by the two signals provide two carrier signals to the pulse width modulation generation circuit 6 at the subsequent stage.

[0066] The pulse width modulation generating circuit 6 realizes the two-channel pulse width modulation PWM signal function of the two-phase interleaved parallel control circuit. It is realized by using a comparator chip plus a pull-up resistor. Preferably, a domestic comparator chip of model LM319 is used. The reverse input ports of the two functional units of the comparator chip U6, the sixth A comparator unit U6A and the sixth B comparator unit U6B, are respectively connected to the two-phase triangular wave output voltage signals of the triangular sawtooth wave generating circuit 8. The forward input ports of the sixth A comparator unit U6A and the sixth B comparator unit U6B are respectively connected to the two-way adjustment control output voltage signal of the first phase synchronous rectification Buck current control circuit 9 and the second phase synchronous rectification Buck current control circuit 10. The sixth A comparator unit U6A and the sixth B comparator unit U6B respectively compare the two groups (4 signals, two in each group) of comparison signals input to the positive and negative ends, and modulate two output signals according to the PWM modulation principle. These two signals are PWM signals whose duty cycles change with the output voltage signals of the first phase synchronous rectification Buck current control circuit 9 and the second phase synchronous rectification Buck current control circuit 10. If the two duty cycles are the same, the output signals generated by the output ends of the sixth A comparator unit U6A and the sixth B comparator unit U6B are also two output signals with the same frequency, the same high level voltage, and a phase difference of 180°. These two signals are pulled up by the twelfth resistor R12 and the thirteenth resistor R13, and then output and sent to the signal driving circuit 7 of the next stage for use.

[0067] The signal driving circuit 7 realizes the function of driving the power tube switch signal of the driving main circuit of the double closed-loop control circuit. The two-phase driving signal is the upper and lower bridge arm power tube control signal, the upper and lower bridge arm interlocking function, and the dead zone generation function to prevent direct fault. Preferably, a domestic gate circuit chip is used, the non-gate chip model is 74HC04, and the non-and gate logic function circuit chip is 74HC00. The signal driving circuit 7 includes two non-and gate unit modules, and the input ends of the two non-and gate unit modules respectively receive the two-phase duty cycle PWM signal of the pulse width modulation generation circuit 6, and then generate two-phase signals with opposite logic directions corresponding to the two phases, and obtain two groups of signals used for two-phase interleaved parallel control, that is, 4 signals.

[0068] The two units U3E and U3F of chip U3 receive the two-phase duty cycle PWM signal of pulse width modulation generating circuit 6 at their input ends, and then generate two-phase signals with opposite logic directions corresponding to the two phases, so that two groups (4 signals) of signals used for two-phase staggered parallel control can be obtained. The two signals of the first phase are logically opposite, and the two signals of the second phase are also logically opposite. The two signals of each phase are respectively used as the logic control signals of the upper and lower bridge arm power tubes of the control main circuit. These two control signals pass through the following NAND gates (the first phase uses U7A, U7B, U7C, and U7D, and the second phase uses U8A, U8B, U8C, and U8D) to generate two groups of action signals with dead zones used for the corresponding two-phase staggered parallel control. The interlocking signals with dead zones output by the first phase are PH1 and PL1, and the interlocking signals with dead zones output by the second phase are PH2 and PL2. The two sets of signals of the two phases are output to the corresponding main circuit power tube gate drive circuit outside this circuit. The gate drive circuit decides the switching state of the subsequent power switch tube according to the input signal level logic.

[0069] In this embodiment, the voltage closed-loop compensation control circuit 11 realizes the voltage closed-loop feedback control PID adjustment circuit function of the two-phase staggered parallel control circuit. It adopts the second-order circuit compensation network principle to realize this function and is built using commonly used domestic operational amplifier chips and discrete components.

[0070] The positive input end of the operational amplifier chip unit U9A is connected to the seventeenth capacitor C17, the twenty-fourth resistor R24, and the twenty-third resistor R23 to receive the set voltage reference signal. The output voltage setting signal Vset is filtered by the eighteenth capacitor C18 and then divided by the twenty-third resistor R23 and the twenty-fourth resistor R24 ​​to obtain the set input given reference signal of the voltage closed-loop control PID principle circuit function. The negative input end of the operational amplifier chip unit U9A inputs the feedback signal Vfb1 of the voltage closed-loop control PID principle circuit function through the connected twenty-fifth resistor R25. After the two signals enter the operational amplifier chip unit U9A, a phase difference operation is performed, and then after entering the second-order compensation network composed of the operational amplifier chip unit U9A and the thirteenth capacitor C13, the twenty-second resistor R22, and the fourteenth capacitor C14, a PID compensation operation is performed. Finally, the output end of the operational amplifier chip unit U9A obtains the output signal of the voltage closed-loop PID regulation control. The ratio of the PID regulator can be set by adjusting the resistance of several related resistors (the 25th resistor R25, the 22nd resistor R22), and other links can be set by matching several resistors and capacitors (the 25th resistor R25, the 22nd resistor R22, the 13th capacitor C13, the 14th capacitor C14) parameters. The signal output from the voltage closed-loop compensation control circuit 11 is input to the two current closed-loop control PID adjustment module functional circuits of the two-phase staggered parallel connection at the subsequent stage, as a reference given signal for the PID circuit principle function of the two current closed-loop control PID adjustment module functional circuits.

[0071] Optionally, the model of the operational amplifier chip unit U9A is LM324, the seventeenth capacitor C17 is a matching capacitor, the twenty-third resistor R23 and the twenty-fourth resistor R24 ​​are set resistors, and the feedback signal Vfb1 is obtained by a main loop output voltage sensor outside the controller control circuit system.

[0072] In this embodiment, the first phase synchronous rectification Buck current control circuit 9 and the second phase synchronous rectification Buck current control circuit 10 mainly realize the two current closed-loop feedback control PID adjustment circuit functions of the two-phase staggered parallel control circuit. These two parts of the circuit are built using domestic commonly used operational amplifier chips and discrete components. Because the first phase synchronous rectification Buck current control circuit 9 and the second phase synchronous rectification Buck current control circuit 10 have the same function, one of them, the first phase synchronous rectification Buck current control circuit 9, is used for illustration.

[0073] The first-phase synchronous rectification Buck current control circuit 9 includes an operational amplifier chip unit U5A. The positive input end of the operational amplifier chip unit U5A is respectively connected to the sixteenth resistor R16, the seventeenth resistor R17, and the fifteenth resistor C15 and is grounded to receive the output signal of the voltage closed-loop compensation control circuit 11 as the input given signal of the first-phase synchronous rectification Buck current control circuit 9. This signal is a reference given signal for the current closed-loop control adjustment PID principle circuit function.

[0074] The negative input terminal of the operational amplifier chip unit U5A is connected to the first phase main loop current output sensor feedback signal Vcfb1 from the outside of the dual closed-loop control circuit through the fifteenth resistor R15. The output terminal of the operational amplifier chip unit U5A and the negative input terminal of the operational amplifier chip unit U5A are respectively connected to the second-order compensation network composed of the ninth capacitor C9, the tenth capacitor C10, and the fourteenth resistor R14, and the output terminal of the operational amplifier chip unit U5A is connected to the pulse width modulation generation circuit. A current given reference signal input to the positive terminal of the operational amplifier chip unit U5A and a current feedback signal input to the negative terminal of the operational amplifier chip unit U5A are processed by PID operation through the second-order compensation network composed of the operational amplifier chip unit U5A and the discrete components, the ninth capacitor C9, the tenth capacitor C10, and the fourteenth resistor R14 to obtain the output signal of the closed-loop control regulator, which is output from the output terminal of the operational amplifier chip unit U5A and then sent to the pulse width modulation generation circuit 6 of the subsequent stage to modulate and generate a PWM duty cycle signal. The second-order compensation network PID control controller composed of the operational amplifier chip unit U5A and discrete components can set the PID parameters of the control controller by adjusting the parameters of the resistor and capacitor components to achieve the desired optimal control effect, providing an optimal debugging method for the dual closed-loop current inner loop control.

[0075] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions that can be implemented in this application, so they have no substantial technical significance. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that can be produced by this application and the purposes that can be achieved, should still fall within the scope of the technical content disclosed in this application. At the same time, the terms such as "upper", "lower", "left", "right", "middle", "first", "second", etc. cited in this specification are only for the convenience of narration, and are not used to limit the scope of the implementation of this application. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of this application without substantial change in the technical content.

[0076] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention invented herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that the present application has not invented. The specification and embodiments are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the appended claims.

[0077] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A two-phase staggered parallel synchronous rectification Buck power converter double closed-loop control circuit, characterized in that: include: A first-phase synchronous rectification Buck current control circuit (9), a second-phase synchronous rectification Buck current control circuit (10) and a voltage closed-loop compensation control circuit (11); The first-phase synchronous rectification Buck current control circuit (9) and the second-phase synchronous rectification Buck current control circuit (10) are connected in parallel and staggered to form a current control loop part of the main loop. The two-phase current output control of the current control loop part of the main loop serves as the inner loop current control of the double closed-loop control circuit and is used for two-way current signal feedback conditioning and current closed-loop PID control adjustment; The voltage closed-loop compensation control circuit (11) is respectively connected to the first-phase synchronous rectification Buck current control circuit (9) and the second-phase synchronous rectification Buck current control circuit (10), and outputs voltage closed-loop regulation control, serving as an outer-loop voltage control of a dual closed-loop control circuit, and is used for voltage signal feedback conditioning and voltage closed-loop PID regulation control.

2. The double closed-loop control circuit according to claim 1, characterized in that: The phase difference between the first phase control driving signal of the first phase synchronous rectification Buck current control circuit (9) and the second phase control driving signal of the second phase synchronous rectification Buck current control circuit (10) is 180°.

3. The double closed-loop control circuit according to claim 1, characterized in that: The first-phase synchronous rectification Buck current control circuit (9) comprises an operational amplifier chip unit U5A, wherein the positive input terminal of the operational amplifier chip unit U5A is respectively connected to a sixteenth resistor R16, a seventeenth resistor R17, and a fifteenth resistor C15 and is grounded to receive an output signal of a voltage closed-loop compensation control circuit (11) as an input given signal of the first-phase synchronous rectification Buck current control circuit (9), the negative input terminal of the operational amplifier chip unit U5A is connected to a first-phase main loop current output sensor feedback signal Vcfb1 via the fifteenth resistor R15, the output terminal of the operational amplifier chip unit U5A and the negative input terminal of the operational amplifier chip unit U5A are respectively connected to a second-order compensation network composed of a ninth capacitor C9, a tenth capacitor C10, and a fourteenth resistor R14, and the output terminal of the operational amplifier chip unit U5A is connected to a pulse width modulation generation circuit.

4. The double closed-loop control circuit according to claim 1, characterized in that: The voltage closed-loop compensation control circuit (11) comprises an operational amplifier chip unit U9A, wherein the positive input end of the operational amplifier chip unit U9A is respectively connected to the seventeenth capacitor C17, the twenty-fourth resistor R24, and the twenty-third resistor R23 for receiving a set voltage reference signal, and the negative output end of the operational amplifier chip unit U9A is connected to the fifteenth resistor R25 to input a voltage output sensor feedback signal Vfb1, and the two signals enter the operational amplifier chip unit U9A for phase difference calculation, and then enter the second-order compensation network composed of the operational amplifier chip unit U9A, the thirteenth capacitor C13, the twenty-second resistor R22, and the fourteenth capacitor C14 for PID compensation calculation, and the output end of the operational amplifier chip unit U9A obtains the output signal of the voltage closed-loop PID regulation control.

5. The double closed-loop control circuit according to claim 1, characterized in that: The dual closed-loop control circuit further comprises a clock source generating circuit (1), a control signal distribution circuit (3) connected to the clock source generating circuit (1), a trigger pulse control signal circuit (4) connected to the control signal distribution circuit (3), a triangular sawtooth wave generating circuit (8) connected to the trigger pulse control signal circuit (4), and a power supply circuit (2). The clock source generating circuit (1) generates a square wave signal with an adjustable frequency. After the square wave signal passes through the two-channel control signal distribution circuit (3), two staggered synchronous control signals with a phase difference of 180° are generated and given to the two-channel staggered phase trigger pulse control signal circuit (4). The two short pulse trigger signals generated by the two-channel staggered phase trigger pulse signal control circuit serve as start and end signals of the two-channel triangular sawtooth wave generating circuit (8).

6. The double closed-loop control circuit according to claim 5, characterized in that: The power supply circuit (2) is constructed by using a power voltage stabilizing chip and discrete resistor and capacitor components.

7. The double closed-loop control circuit according to claim 5, characterized in that: The power supply of the two-channel triangular sawtooth wave circuit (8) is provided by a two-channel constant current source generating circuit (5) for generating a constant two-channel circuit charging current.

8. The double closed-loop control circuit according to claim 7, characterized in that: The two-channel triangular sawtooth wave circuit (8) is connected to the pulse width modulation generation circuit (6), and the pulse width modulation generation circuit (6) is connected to the signal driving circuit (7). The negative input terminal of the comparator U6A of the pulse width modulation generation circuit (6) is connected to the drain of the third MOSFET tube Q3 of the triangular sawtooth wave circuit (8), the positive input terminal of the comparator U6A is connected to the output terminal of the operational amplifier chip unit U5A of the first phase synchronous rectification Buck current control circuit (9), and the output terminal of the comparator U6A is connected to the signal driving circuit; The negative input terminal of the comparator U6B of the pulse width modulation generation circuit (6) is connected to the drain of the fourth MOSFET tube Q4 of the triangular sawtooth wave circuit (8), the positive input terminal of the comparator U6B is connected to the output terminal of the operational amplifier chip unit U5B of the second phase synchronous rectification Buck current control circuit (10), and the output terminal of the comparator U6B is connected to the signal driving circuit.

9. The double closed-loop control circuit according to claim 8, characterized in that: The signal driving circuit (7) of two channels is used for signal interlocking with dead zone of the upper bridge arm and the lower bridge arm of the two power switch tubes of each main circuit. The two driving signals of each channel are transmitted to the control electrodes of the upper bridge arm and the lower bridge arm of the power switch tube to be controlled, respectively, to provide control gate driving signals for the four switch power tubes of the main circuit of the main power circuit.

10. The double closed-loop control circuit according to claim 9, characterized in that: The signal driving circuit (7) comprises two NAND gate unit modules, the input ends of the two NAND gate unit modules respectively receive the two-phase duty cycle PWM signals of the pulse width modulation generating circuit (6), and then generate two-phase signals with opposite logic directions corresponding to the two phases, thereby obtaining two groups of signals used for two-phase staggered parallel control, that is, four signals.

Images