Two-phase interleaved parallel synchronous rectification buck power converter double closed loop control circuit

Abstract

The application discloses a two-phase staggered parallel synchronous rectification Buck power converter double-loop control circuit and belongs to the technical field of power converter control; wherein, the first-phase synchronous rectification Buck current control circuit and the second-phase synchronous rectification Buck current control circuit are connected in a staggered parallel mode to form a current control loop part of a main loop, and the two-phase current output control of the current control loop part of the main loop serves as inner loop current control of the double-loop control circuit; a voltage closed-loop compensation control circuit is connected with the first-phase synchronous rectification Buck current control circuit and the second-phase synchronous rectification Buck current control circuit respectively, and output voltage closed-loop adjustment control serves as outer loop voltage control of the double-loop control circuit. The application provides a two-phase staggered parallel synchronous rectification Buck power converter double-loop control circuit, solves the problems of phase staggering and balance and system stability, and improves the overall energy efficiency of the system.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power converter control, and particularly relates to a two-phase interleaved parallel synchronous rectification Buck power converter double-loop control circuit. BACKGROUND

[0002] In the field of power converter technology, Buck circuit, as a kind of efficient DC-DC converter, is widely used in voltage regulation and power management. With the continuous improvement of the performance requirements of electronic devices on power supply, the traditional single-phase Buck circuit has been unable to meet the market demand for high power, high efficiency and low ripple output. Therefore, two-phase Buck circuit has become the first choice for high-performance power supply applications because it can provide higher power handling capacity and lower output ripple.

[0003] However, the design and implementation of existing two-phase Buck circuit face several technical challenges that limit its full performance:

[0004] 1. Accuracy and balance of phase difference control: In two-phase Buck circuit, in order to achieve uniform distribution of load and reduce output ripple, the phase difference of current and voltage of each phase must be accurately controlled to achieve effective phase interleaving. This requirement is particularly critical in high-frequency operating environments, but it is quite challenging to achieve because any phase control error can significantly affect the overall performance of the circuit.

[0005] 2. Complexity and stability of control system: The complexity of the control system design has a direct impact on the stability of the system. Although a complex control loop can provide more precise control, it also increases the risk of system instability. Therefore, designers must find a balance between control accuracy and system stability to ensure that the circuit can operate stably under various working conditions. SUMMARY

[0006] To solve the problems in the related art, the application provides a two-phase interleaved parallel synchronous rectification Buck power converter double-loop control circuit, which aims to solve the problems of phase interleaving and balance and system stability through innovative control strategies, and improve the overall energy efficiency of the system.

[0007] The technical scheme is as follows:

[0008] A two-phase interleaved parallel synchronous rectification Buck power converter double-loop control circuit, comprising: a first-phase synchronous rectification Buck current control circuit, a second-phase synchronous rectification Buck current control circuit, and a voltage closed-loop compensation control circuit.

[0009] The first phase synchronous rectification Buck current control circuit and the second phase synchronous rectification Buck current control circuit are connected in parallel to form a current control loop part of a main loop, and the two-phase current output control of the current control loop part of the main loop is used as inner loop current control of a double closed loop control circuit for current signal feedback conditioning and current closed loop PID control adjustment.

[0010] The voltage closed loop compensation control circuit is connected with the first phase synchronous rectification Buck current control circuit and the second phase synchronous rectification Buck current control circuit, and outputs voltage closed loop adjustment control as outer loop voltage control of the double closed loop control circuit for voltage signal feedback conditioning and voltage closed loop PID adjustment control.

[0011] In a further technical solution, the phase difference between the first phase control driving signal of the first phase synchronous rectification Buck current control circuit and the second phase control driving signal of the second phase synchronous rectification Buck current control circuit is 180°.

[0012] In a further technical solution, the first phase synchronous rectification Buck current control circuit comprises an operational amplifier chip unit U5A, the positive input end of the operational amplifier chip unit U5A is connected with the sixteenth resistor R16, the seventeenth resistor R17 and the fifteenth resistor C15 and grounded to receive the output signal of the voltage closed loop compensation control circuit as the input given signal of the first phase synchronous rectification Buck current control circuit, the negative input end of the operational amplifier chip unit U5A is connected with the first phase main loop current output sensor feedback signal Vcfb1 through the fifteenth resistor R15, the output end of the operational amplifier chip unit U5A and the negative input end of the operational amplifier chip unit U5A are connected with the second-order compensation network composed of the ninth capacitor C9, the tenth capacitor C10 and the fourteenth resistor R14, and the output end of the operational amplifier chip unit U5A is connected with a pulse width modulation generating circuit.

[0013] In a further technical solution, the voltage closed loop compensation control circuit comprises an operational amplifier chip unit U9A, the positive input end of the operational amplifier chip unit U9A is connected with the seventeenth capacitor C17, the twenty-fourth resistor R24 and the twenty-third resistor to receive a set voltage reference signal, the negative output end of the operational amplifier chip unit U9A is connected with the voltage output sensor feedback signal Vfb1 through the fifteenth resistor R25, two signals are input into the operational amplifier chip unit U9A to perform phase difference operation, and then are input into the second-order compensation network composed of the operational amplifier chip unit U9A, the thirteenth capacitor C13, the twenty-second resistor R22 and the fourteenth capacitor C14 to perform PID compensation operation, and the output end of the operational amplifier chip unit U9A obtains the output signal of the voltage closed loop PID adjustment control.

[0014] Further technical solutions, the double closed loop control circuit further comprises a clock source generating circuit, a control signal distribution circuit connected with the clock source generating circuit, a trigger pulse control signal circuit connected with the control signal distribution circuit, a triangular sawtooth wave generating circuit connected with the trigger pulse control signal circuit, and a power supply circuit, the clock source generating circuit generates a square wave signal with adjustable frequency, the square wave signal passes through two paths of the control signal distribution circuit, and two paths of staggered phase trigger pulse control signal circuits are generated to generate two paths of staggered phase trigger pulse signals as start and end signals of the triangular sawtooth wave generating circuit of the two paths.

[0015] Further technical solutions, the power supply circuit is built by a power stabilizing chip and discrete resistance-capacitance devices.

[0016] Further technical solutions, the power supply of the triangular sawtooth wave circuit of the two paths is provided by two constant current source generating circuits to generate constant charging currents of the two paths of the circuit.

[0017] Further technical solutions, the triangular sawtooth wave circuit of the two paths is connected with a pulse width modulation generating circuit, the pulse width modulation generating circuit is connected with a signal driving circuit, a negative input end of a comparator U6A of the pulse width modulation generating circuit 6 is connected with a drain electrode of a third MOSFET tube Q3 of the triangular sawtooth wave circuit 8, a positive input end of the comparator U6A is connected with an output end of a U5A unit of a first synchronous rectification Buck current control circuit 9, and an output end of the comparator U6A is connected with the signal driving circuit.

[0018] A negative input end of a comparator U6B of the pulse width modulation generating circuit 6 is connected with a drain electrode of a fourth MOSFET tube Q4 of the triangular sawtooth wave circuit 8, a positive input end of the comparator U6B is connected with an output end of a U5B unit of a second synchronous rectification Buck current control circuit 10, and an output end of the comparator U6B is connected with the signal driving circuit.

[0019] Further technical solutions, the signal driving circuit of the two paths is used for the upper bridge arm and the lower bridge arm of the two power switch tubes of each main power loop circuit and is provided with a dead zone signal interlock, two driving signals of each path are transmitted to the control electrodes of the upper bridge arm and the lower bridge arm of the power switch tubes to be controlled, and the control gate driving signals of the four switch power tubes of the main loop of the main power loop circuit are provided.

[0020] Further technical solutions, the signal drive circuit of the two channels includes two NAND gate unit modules, the input ends of the two NAND gate unit modules respectively receive two-phase duty cycle PWM signals generated by the pulse width modulation generating circuit 6, then generate two-phase two-path logic direction opposite two-phase signals corresponding to the two phases, obtain two groups of signals used for two-phase interleaved parallel control, that is, four signals.

[0021] The technical solutions at least have the following technical effects:

[0022] The first phase synchronous rectification Buck current control circuit and the second phase synchronous rectification Buck current control circuit are connected in an interleaved parallel mode to form a current control loop part of a main loop, two-phase current outputs of the current control loop part of the main loop control an inner loop current control of a double closed loop control circuit; the voltage closed loop compensation control circuit is connected with the first phase synchronous rectification Buck current control circuit and the second phase synchronous rectification Buck current control circuit, and outputs a voltage closed loop adjustment control as an outer loop voltage control of the double closed loop control circuit. The double closed loop control strategy of the voltage outer loop and the current inner loop adopted by the application can effectively realize accurate control of the current and the voltage, and improve the performance and stability of the power converter.

[0023] It should be understood that the above general description and the following detailed description are only exemplary and cannot limit the application. BRIEF DESCRIPTION OF DRAWINGS

[0024] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the application and, together with the description, serve to explain the principles of the application.

[0025] Figure 1 It is a one-phase synchronous rectification Buck power converter circuit principle diagram of the prior art;

[0026] Figure 2 It is a two-phase interleaved parallel synchronous rectification Buck power converter circuit principle diagram provided by the embodiment of the application;

[0027] Figure 3 It is a double closed loop control circuit of a two-phase interleaved parallel synchronous rectification Buck power converter provided by the embodiment of the application;

[0028] 1, clock source generating circuit; 2, power supply circuit; 3, control signal distribution circuit; 4, trigger pulse control signal circuit; 5, constant current source generating circuit; 6, pulse width modulation generating circuit; 7, signal drive circuit; 8, triangular sawtooth wave generating circuit; 9, first phase synchronous rectification Buck current control circuit; 10, second phase synchronous rectification Buck current control circuit; 11, voltage closed loop compensation control circuit. DETAILED DESCRIPTION

[0029] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0030] Figure 1 The diagram shown is a block diagram of a conventional one-phase synchronous rectifier Buck power converter circuit.

[0031] like Figure 1 As shown, a synchronous rectified Buck power converter circuit includes an input power supply Vin, an input-side capacitor C1, an upper-side switch Q1, a lower-side switch Q2, a voltage conversion power inductor L1, an output-side capacitor C2, an output voltage sensor VS1, a main circuit current sensor CS1, a synchronous rectified Buck control circuit PCB1, a PWM drive circuit DB1, and an output voltage Vout. Among these components, resistor R1 is the load, upper-side switch Q1 and lower-side switch Q2 are N-type MOSFETs, and output-side capacitor C2 is a filter capacitor.

[0032] Under the action of the synchronous rectification Buck control circuit PCB1 and the PWM drive circuit DB1, the upper bridge arm switch Q1 is turned on and enters the conduction state. One end of the inductor L1 is connected to the positive terminal of the input power supply Vin through the upper bridge arm switch Q1, and the other end of the inductor L1 is connected to the positive terminal of the output voltage Vout. Therefore, the difference between the input voltage Vin and the output voltage Vout will cause the current of the inductor L1 to rise. At the same time, during the conduction time of the upper bridge arm switch Q1, the lower bridge arm switch Q2 is in the off state, and the output filter capacitor C2 and the inductor L1 simultaneously provide power to the load R1.

[0033] When the upper bridge arm switch Q1 is turned off by the signal drive circuit DB1, the lower bridge arm switch Q2 is turned on. The current of inductor L1 cannot change abruptly. During the conduction time of the upper bridge arm switch Q1, the energy stored in inductor L1 is supplied to the load R1 current through the lower bridge arm switch Q2. In the balance between the power supply of the inductor and the power consumption of the load, the output filter capacitor C2 maintains the output voltage at a basically constant value.

[0034] The turn-on and turn-off times of the upper bridge arm switch Q1 and the lower bridge arm switch Q2 are jointly determined by the synchronous rectification Buck control circuit PCB1 and the drive control circuit DB1 to ensure that the output voltage is a certain set voltage value.

[0035] The synchronous rectification Buck control circuit PCB1 performs closed-loop PID control adjustment of the current based on the current signal fed back by the current sensor CS1.

[0036] When the current is more than the required regulated current, decrease the PWM duty cycle of the control signal to the upper bridge arm switch Q1;

[0037] When the current is less than the required regulated current, increase the PWM duty cycle of the control signal to the upper bridge arm switch Q1, so as to maintain the required current basically constant within a small controllable fluctuation range.

[0038] The synchronous rectification Buck control circuit PCB1 carries out PID control regulation according to the voltage signal fed back by the voltage sensor VS1 in voltage closed loop;

[0039] When the output voltage is more than the set regulated output voltage, the control circuit PCB1 decreases the PWM duty cycle of the control signal to the upper bridge arm switch Q1;

[0040] When the output voltage is less than the required set regulated voltage, increase the PWM duty cycle of the control signal to the upper bridge arm switch Q1, so as to maintain the required voltage basically constant within a small controllable fluctuation range.

[0041] Figure 2 The two-phase interleaved parallel synchronous rectification Buck power converter circuit principle block diagram shown is developed on the basis of Figure 1 .

[0042] As shown in Figure 2 , the main power loop circuit part is composed of two basic synchronous rectification Buck circuits in parallel, the first power switch Q1, the second power switch Q2 of the first phase main loop and the third power switch Q3, the fourth power switch Q4 of the second phase main loop adopt phase shift 180° phase drive control, the first power switch Q1, the second power switch Q2, the third power switch Q3, the fourth power switch are N type MOS field effect tube.

[0043] The first inductor L1 is the power conversion power inductor of the first phase main loop, the second inductor L2 is the power conversion power inductor of the second phase main loop, the first current feedback sensor CS1 is the current feedback sensor of the first phase main loop, the second current feedback sensor CS2 is the current feedback sensor of the second phase main loop, the sensor VS1 is the output power voltage sensor shared by the two-phase main loop, the first capacitor C1 is the input side capacitor, and the second capacitor C2 is the output side capacitor.

[0044] The synchronous rectification Buck control circuit PCB1 and the PWM drive circuit DB1 share one circuit respectively, the input side capacitor C1 is shared by two-phase main circuits as an input to provide a transient energy source, the output side capacitor C2 is also shared by two-phase main circuits as an output to provide a transient energy source, the current signals fed back by two current sensors and the voltage signal fed back by one voltage sensor enter the synchronous rectification Buck control circuit PCB1, the synchronous rectification Buck control circuit PCB1 adjusts and controls the duty ratio of two sets of PWM pulse drive signals with a phase difference of 180° to the upper bridge arm power switch tube and the lower bridge arm power switch tube of the two-phase main circuit respectively according to the current signal and the voltage signal, so that the double closed-loop control and adjustment of the output voltage and the current of the two-channel main circuit are realized, and the effects of stable output voltage and fast response speed are achieved. The circuit improves the EMC characteristics, reduces the stress of the power tube, reduces the switching loss, and improves the heat dissipation.

[0045] Figure 3 The two-phase interleaved parallel synchronous rectification Buck power converter double closed-loop control circuit is provided for the embodiments of the application.

[0046] As shown in Figure 3 The two-phase interleaved parallel synchronous rectification Buck power converter double closed-loop control circuit provided by the embodiments of the application includes a clock source generation circuit 1, a control signal distribution circuit 3, a trigger pulse control signal circuit 4, a two-channel triangular sawtooth wave generation circuit 8, a power supply circuit 2, a two-channel constant current source generation circuit 5, a pulse width modulation generation circuit 6, a four-channel signal drive circuit 7, a first-phase synchronous rectification Buck current control circuit 9, a second-phase synchronous rectification Buck current control circuit 10, and a voltage closed-loop compensation control circuit 11.

[0047] The first-phase synchronous rectification Buck current control circuit 9 and the second-phase synchronous rectification Buck current control circuit 10 are connected in an interleaved parallel mode to constitute a current control loop part of a main circuit, the two-phase current output control of the current control loop part of the main circuit is used as the inner loop current control of the double closed-loop control circuit, and is used for current signal feedback conditioning and current closed-loop PID control adjustment; the phase difference between the first-phase control drive signal of the first-phase synchronous rectification Buck current control circuit 9 and the second-phase control drive signal of the second-phase synchronous rectification Buck current control circuit 10 is 180°. The inner loop current control of the double closed-loop control circuit is realized by two-phase current closed-loop adjustment and control in an interleaved synchronous parallel mode, and the output current is jointly used in the two-channel current compensation network and the control adjustment loop circuit according to the output given signal of the voltage loop and the two actual current feedback signals.

[0048] The voltage closed-loop compensation control circuit 11 is connected with the first-phase synchronous rectification Buck current control circuit 9 and the second-phase synchronous rectification Buck current control circuit 10 respectively, and outputs a voltage closed-loop adjustment control as an outer loop voltage control of a double closed-loop control circuit, which is used for voltage signal feedback conditioning and voltage closed-loop PID adjustment control. The outer loop of the controller circuit realizes stable output of the output voltage through the output voltage closed-loop adjustment control, and the output voltage can be set according to a set reference signal value. The set reference signal and the feedback actual value signal jointly act on the voltage compensation network and the control adjustment loop circuit, so that the effect of stable output voltage is achieved.

[0049] The staggered clock source synchronous generation circuit generates a square wave signal with adjustable frequency. After passing through two channel control signal distribution circuits, the square wave signal generates two staggered synchronous control signals with a phase difference of 180° to the two-channel staggered phase trigger pulse control signal circuit. The two-channel staggered phase trigger pulse signal control circuit generates two short pulse trigger signals as the start and end signals of the two-channel triangular sawtooth wave generation circuit.

[0050] The power supply of the two-channel triangular sawtooth wave circuit is provided by the two-channel constant current source generation circuit, which is used to generate constant charging currents of the two-channel circuit, thereby controlling the charging and discharging period and the voltage signal amplitude reached by charging.

[0051] The negative input end of the comparator U6A of the pulse width modulation generation circuit 6 is connected with the drain of the third MOSFET tube Q3 of the triangular sawtooth wave circuit 8, the positive input end of the comparator U6A is connected with the output end of the operational amplifier chip unit U5A of the first-phase synchronous rectification Buck current control circuit 9, and the output end of the comparator U6A is connected with the signal driving circuit. The negative input end of the comparator U6B of the pulse width modulation generation circuit 6 is connected with the drain of the fourth MOSFET tube Q4 of the triangular sawtooth wave circuit 8, the positive input end of the comparator U6B is connected with the output end of the operational amplifier chip unit U5B of the second-phase synchronous rectification Buck current control circuit 10, and the output end of the comparator U6B is connected with the signal driving circuit.

[0052] The signals output by the current feedback conditioning adjustment control of the second-phase synchronous rectification Buck current control circuit 10 and the first-phase synchronous rectification Buck current control circuit 9 and the sawtooth wave ramp signal generated by the two-channel triangular sawtooth wave circuit 8 are respectively sent to the positive and negative ends of the two comparators of the pulse width modulation generation circuit 6 for comparison. After the two comparators compare the two signals of each channel respectively, two-channel pulse width modulation PWM duty cycle signals are generated respectively. The completed PWM signals of the two channels are respectively input into the signal driving circuit 7 of each channel.

[0053] The drive control circuit of the two channels is used for current control of the upper bridge arm and the lower bridge arm of the two power switch tubes of each main loop circuit, and the signals of the two channels are interlocked with a dead zone, and finally the two drive signals of each channel are sent to the control poles of the upper bridge arm and the lower bridge arm of the power switch tube to be controlled, so as to provide control gate drive signals for the four switch power tubes of the two interleaved parallel synchronous rectification main power loop circuit.

[0054] The two-order feedback compensation network circuit of the first-phase synchronous rectification Buck current control circuit 9 and the second-phase synchronous rectification Buck current control circuit 10 completes the current signal feedback conditioning and current closed-loop PID control adjustment functions.

[0055] The two-order feedback compensation network circuit of the voltage closed-loop compensation control circuit completes the voltage signal feedback conditioning and voltage closed-loop PID adjustment control functions.

[0056] The output signal of the voltage closed-loop compensation control circuit is used as the input given reference signal of the current closed-loop adjustment of the first-phase synchronous rectification Buck current control circuit 9 and the second-phase synchronous rectification Buck current control circuit 10, and the current feedback conditioning signal and the power voltage feedback adjustment function output signal are jointly input into the current loop adjustment control loop circuit to interact with each other to complete the current closed-loop adjustment function. The power voltage signal feedback signal and the given reference voltage signal that can be adjusted are jointly input into the voltage closed-loop compensation control circuit to constitute the voltage closed-loop PID adjustment control circuit function.

[0057] The power supply circuit built by the power supply stabilizing chip and the discrete resistor-capacitor device provides the power voltage required by all the functional circuit parts for control and signal conditioning.

[0058] In the embodiment, the power supply circuit 2 realizes the power supply voltage stabilization function of the entire double closed-loop control circuit, which is built and realized by the stabilizer U10. The input Vin power voltage is filtered by the nineteenth capacitor C19 and the twentieth capacitor C20, and then input into the input port of the stabilizer U10. The output port of the stabilizer U10 is filtered and stabilized by the twenty-first capacitor C21 and the twenty-second capacitor C22, and then outputs VDD. VDD is the stable voltage signal port input of all the functional circuit parts. The twenty-sixth resistor R26 and the twenty-seventh resistor R27 mainly realize the adjustment setting function of setting the required stable output voltage, and the output voltage VDD is adjusted by the resistance parameters of the two resistors. Preferably, the stabilizer U10 is a domestic three-terminal stabilizer with the model number LM117.

[0059] In this embodiment, the clock source generation circuit 1 realizes the function of two-phase staggered parallel control signal clock generation. The time base generator chip U1 and the resistance-capacitance discrete components are used to complete the oscillation clock function, which is the time base of the entire double closed-loop control circuit. Preferably, the time base generator chip U1 is a domestic chip, and the model is LM555. The three comparators inside the time base generator chip U1 are matched with the external discrete components, the first resistor R1, the second resistor R2, the first capacitor C1, and the second capacitor C2 to complete the clock signal generation function. The signal frequency is set by adjusting the resistance value of the first resistor R1 and the second resistor R2, and the capacitance parameter of the first capacitor C1. The 3-pin output signal of the time base generator chip U1 is the frequency signal generator waveform output generated by this part of the circuit, which is input to the control signal distribution circuit 3 in the next stage as the signal input of the control signal distribution circuit. The clock source generation circuit 1 in this embodiment is set to 200 kHz.

[0060] In this embodiment, the control signal distribution circuit 3 realizes the function of two-phase staggered parallel control synchronous signal distribution generation circuit. A flip-flop U2 is used to realize it. Preferably, only the A logic part of this chip is used in this embodiment. The flip-flop U2 is a domestic simple sequential logic gate integrated chip D flip-flop, and the model is 74HC74D. The clock edge trigger end 3 pin of the flip-flop U2 enters, and the state logic inverting output end 6 pin of the flip-flop returns to the state signal input end 2 pin of the flip-flop. When the signal of the clock edge trigger end 3 pin changes logically, the state of the flip-flop is logically inverted from the previous state, and the output of the two state ends 5 pin (positive logic state) and 6 pin (negative logic state) are square wave signals with a phase difference of 180°. The frequency of the two signals is half of the output signal frequency of the input clock source generation circuit 1 part (this circuit is temporarily set to 100 kHz). The frequency, duty cycle, and high-low level amplitude of the two-phase phase difference 180° output waveform signals of this part of the functional circuit are the same, except that the phase difference is 180°. The two signals provide input signals for the trigger pulse control signal circuit 4 in the next stage.

[0061] In this embodiment, the trigger pulse control signal circuit 4 realizes the function of two-phase staggered parallel control synchronous signal two-phase staggered phase difference 180° synchronous control signal pulse generation and waveform shaping. A combination of logic gate NOT chip U3 and resistance-capacitance, diode discrete components is used to realize this circuit function. Preferably, the NOT chip U3 is a domestic chip, and the model is 74HC04D. The NOT chip U3 uses four single units (U3A, U3B, U3C, U3D). U3A and U3B are used for the first phase pulse control signal, and U3C and U3D are used for the second phase pulse control signal.

[0062] The two staggered parallel synchronous control signals from the control signal distribution circuit 3 enter the input capacitive elements third capacitor C3 and fourth capacitor C4 of the trigger pulse control signal circuit 4 respectively. The elements third capacitor C3, first diode D1, third resistor R3, U3A, U3B form a first phase synchronous trigger signal generating circuit, the elements fourth capacitor C4, second diode D2, fourth resistor R4, U3C, U3D form a second phase synchronous trigger signal generating circuit, and the third capacitor C3 and the fourth capacitor C4 mainly function to process the input square wave signal to generate a sharp pulse signal. The first phase square wave signal entering through the third capacitor C3 generates a first path sharp pulse signal, and the second phase square wave signal entering through the fourth capacitor C4 generates a second path sharp pulse signal. After the two signals pass through the first diode D1, the third resistor R3, the second diode D2, and the fourth resistor R4 for voltage limiting and anti-reverse processing functions, they enter the waveform shaping and level logic operation function circuit composed of two groups (U3A, U3B, U3C, U3D) of logic gates of the NAND gate chip U3. After the two staggered synchronous trigger control signals pass through the two groups of logic gates, the output signal is a pulse signal with a very small duty cycle and a frequency that remains unchanged. The frequency of the two narrow pulse signals is the same as the frequency of the signal input to the third capacitor C3 and the fourth capacitor C4, and the signal phase remains unchanged. The phases of the two pulse signals are also 180° apart. The two narrow pulse signals are output to the input signals of the two-phase triangular sawtooth wave generating circuit 8 in the next stage.

[0063] In this embodiment, the constant current source generating circuit 5 realizes the function of providing a settable constant current charging current for the two-phase staggered parallel control triangular sawtooth wave generating circuit 8. It is implemented by using a voltage reference source chip U4, an operational amplifier chip U5, and discrete resistors, capacitors, and transistor elements. Preferably, the voltage reference source chip U4 is a domestic chip model TL431, and the operational amplifier chip U5 is a domestic chip model LM324.

[0064] The voltage reference source chip U4 and the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the fifth capacitor C5, the sixth capacitor C6 constitute an adjustable high-precision voltage reference signal generating circuit, the amplitude of the generated reference voltage signal is set by the resistance value parameters of the sixth resistor R6 and the seventh resistor R7, the fifth capacitor C5 is the input power voltage filtering function of the reference circuit, and the sixth capacitor C6 is the output voltage signal filtering function of the reference circuit, so that a more stable high-precision voltage signal is obtained. This high-precision voltage reference signal enters the positive input terminals of the two units (U5C, U5D) of the operational amplifier chip U5 as the input given reference signal. The U5C and U5D of the operational amplifier chip U5 output to the bases of the first transistor Q1 and the second transistor Q2, and then the emitters of the transistors act on the eighth resistor R8 and the ninth resistor R9, and together act to constitute a two-way constant current source generating circuit 5. The emitter signals of the first transistor Q1 and the second transistor Q2 are connected to the negative input terminals of the fifth C operational amplifier unit U5C and the fifth D operational amplifier unit U5D of the two unit circuits of the operational amplifier chip U5 as feedback signals, and a negative feedback control adjustment principle circuit is constructed to generate a constant current output from the collectors of the first transistor Q1 and the second transistor Q2. One of the two-way outputs is used for the waveform generation of the first-phase triangle sawtooth wave generating circuit controlled by staggered parallel synchronization, and the other is used for the second-phase triangle sawtooth wave generating circuit. The highest allowable working voltage amplitude of the two-way constant current source generating circuit can be set by setting the voltage of the reference voltage circuit, and the constant charging current provided by the two-way constant current source generating circuit 5 to the two-way triangle sawtooth wave generating circuit 8 can be set by adjusting the resistance values of the eighth resistor R8 and the ninth resistor R9. The output two-way constant current source current signal is output to the later-stage triangle sawtooth wave generating circuit 8 as an input current source, which is used for the circuit during the cross-current charging period in the triangle sawtooth wave generating circuit 8.

[0065] The triangle sawtooth wave generating circuit 8 is realized by using the principle of charging and discharging circuit. Preferably, it is built by using domestic MOSFET tubes and discrete components. When the two-way synchronous trigger narrow pulse signals output by the trigger pulse control signal circuit 4 are sent into the tenth resistor R10 and the eleventh resistor R11 of the triangle sawtooth wave generating circuit after being limited current, they enter the gates of the third MOSFET tube Q3 and the fourth MOSFET tube Q4. When the two-way signals are effective high-level pulses, the third MOSFET tube Q3 and the fourth MOSFET tube Q4 are opened respectively. When the two-way signals are invalid low-level, the two tubes are closed. Because the two-way synchronous trigger narrow pulse signals are 180° out of phase, the time phases of the opening and closing of the two tubes are also 180° out of phase. When the two tubes are opened in turn, the corresponding seventh capacitor C7 and eighth capacitor C8 are rapidly discharged. When the two tubes are closed in turn, the constant current source set by the first transistor Q1 and the second transistor Q2 of the constant current source generating circuit 5 outputs a constant current, which charges the corresponding two-way charging and discharging capacitors C7 and C8 at a constant rate. At this time, the voltage signals output by the two capacitors are the rising stage waveforms of two-way sawtooth triangle waves with constant slope. When the third MOSFET tube Q3 and the fourth MOSFET tube Q4 are closed in turn, the corresponding seventh capacitor C7 and eighth capacitor C8 are rapidly discharged, thereby generating the falling stage waveforms of two-way sawtooth triangle waves. Through such a principle, the two-way staggered parallel synchronous trigger signals continuously control the charging and discharging circuit to work, thereby generating two-way high-frequency carrier signals with a triangle waveform and a phase difference of 180° for subsequent modulation circuit use. The frequency and voltage amplitude of the two-way waveforms generated are the same as the input signal frequency and voltage amplitude, and the phase difference is 180°. The waveform signals generated by the two-way signals provide two-way carrier signals for the pulse width modulation generating circuit 6 in the subsequent stage.

[0066] The pulse width modulation generating circuit 6 realizes the function of two-channel pulse width modulation PWM signals of the two-phase interleaving parallel control circuit. The function is realized by using a comparator chip and a pull-up resistor. Preferably, a domestic comparator chip model LM319 is used. The reverse input ports of the two functional units of the comparator chip U6, the sixth A comparator unit U6A and the sixth B comparator unit U6B, are connected to the two-phase triangular wave output voltage signals of the triangular sawtooth wave generating circuit 8. The positive input ports of the sixth A comparator unit U6A and the sixth B comparator unit U6B are connected to the two-way regulation control output voltage signals of the first-phase synchronous rectification Buck current control circuit 9 and the second-phase synchronous rectification Buck current control circuit 10. The sixth A comparator unit U6A and the sixth B comparator unit U6B compare the two groups (4-way signals, two in each group) of comparison signals input to the positive and negative terminals, respectively, and modulate two-way output signals according to the PWM modulation principle. The two-way signals are PWM signals with a duty cycle that changes with the output voltage signals of the first-phase synchronous rectification Buck current control circuit 9 and the second-phase synchronous rectification Buck current control circuit 10. If the duty cycles of the two ways are the same, the output signals generated by the output ends of the sixth A comparator unit U6A and the sixth B comparator unit U6B are also two-way output signals with the same frequency, the same high-level voltage, and a phase difference of 180°. After the two-way signals are pulled up by the twelfth resistor R12 and the thirteenth resistor R13, they are output to the signal driving circuit 7 in the next stage for use.

[0067] The signal driving circuit 7 realizes the function of driving the main loop power tube driving switch signal of the double closed-loop control circuit. The two-phase driving signals are the upper and lower bridge arm power tube control signals, which realize the upper and lower bridge arm interlocking function and the dead zone generation function to prevent straight-through failure. Preferably, a domestic gate circuit chip is used, and the NOT gate chip model is 74HC04. The NOT gate logic function circuit chip is 74HC00. The signal driving circuit 7 includes two NOT gate unit modules, and the input ends of the two NOT gate unit modules receive the two-phase duty cycle PWM signals of the pulse width modulation generating circuit 6, then generate two-way logic signals with opposite directions corresponding to the two phases, and obtain two groups of signals, i.e., four signals, for two-phase interleaving parallel control.

[0068] The two units U3E, U3F of the chip U3 receive the two-phase duty cycle PWM signals of the pulse width modulation generating circuit 6, and then generate two-phase two-way logic direction opposite two-phase signals, so that two groups (4 signals) of signals used for two-phase interleaved parallel control can be obtained. The two signals of the first phase are logic opposite, and the two signals of the second phase are also logic opposite. The two signals of each phase are used as the logic control signals of the upper and lower bridge arm power tubes of the main circuit, respectively. The two control signals pass through the following NAND gates (U7A, U7B, U7C, U7D for the first phase, and U8A, U8B, U8C, U8D for the second phase), and two groups of two-phase interleaved parallel control signals with dead zones are generated. The two-phase interleaved parallel control signals with dead zones output by the first phase are PH1 and PL1, and the two-phase interleaved parallel control signals with dead zones output by the second phase are PH2 and PL2. The two groups of signals of the two phases are output to the gate drive circuit of the corresponding main circuit power tube outside the circuit. The gate drive circuit determines the switching state of the following power switch tube according to the logic of the input signal level.

[0069] In the embodiment, the voltage closed-loop compensation control circuit 11 is a voltage closed-loop feedback control PID adjustment circuit function of the two-phase interleaved parallel control circuit. The function is realized by using a second-order circuit compensation network principle and commonly used domestic operational amplifier chips and discrete components.

[0070] The positive input end of the operational amplifier chip unit U9A is connected with the seventeenth capacitor C17, the twenty-fourth resistor R24 and the twenty-third resistor R23 for receiving a set voltage reference signal. The output voltage set signal Vset is filtered by the eighteenth capacitor C18, then is divided by the twenty-third resistor R23 and the twenty-fourth resistor R24, and then an input given reference signal of the set voltage closed-loop control PID principle circuit function is obtained. The negative input end of the operational amplifier chip unit U9A inputs a feedback signal Vfb1 of the voltage closed-loop control PID principle circuit function through the connected twenty-fifth resistor R25. After the two signals enter the operational amplifier chip unit U9A, a difference operation is performed. Then, after entering a second-order compensation network composed of the operational amplifier chip unit U9A, the twelfth capacitor C13, the twenty-second resistor R22 and the thirteenth capacitor C14, a PID compensation operation is performed. Finally, the output end of the operational amplifier chip unit U9A obtains an output signal of the voltage closed-loop PID adjustment control. The proportion of the PID regulator can be set by adjusting the resistance values of several related electric components (the twenty-fifth resistor R25 and the twenty-second resistor R22), and other links can be set by matching several resistance-capacitance (the twenty-fifth resistor R25, the twenty-second resistor R22, the thirteenth capacitor C13 and the fourteenth capacitor C14) parameters. The signal output from the voltage closed-loop compensation control circuit 11 is input to the two-phase interleaved parallel two current closed-loop control PID adjustment module function circuits in the rear stage as a reference given signal of the PID circuit principle function of the two current closed-loop control PID adjustment module function circuits.

[0071] Optionally, the model of the operational amplifier chip unit U9A is LM324, the seventeenth capacitor C17 is a matching capacitor, the twenty-third resistor R23 and the twenty-fourth resistor R24 are set resistors, and the feedback signal Vfb1 is obtained by a main loop output voltage sensor outside the controller control circuit system.

[0072] In the embodiment, the first-phase synchronous rectification Buck current control circuit 9 and the second-phase synchronous rectification Buck current control circuit 10 mainly realize the two current closed-loop feedback control PID adjustment circuit functions of the two-phase interleaved parallel control circuit. The two circuits are completed by using a domestic commonly used operational amplifier chip and discrete components. Because the first-phase synchronous rectification Buck current control circuit 9 and the second-phase synchronous rectification Buck current control circuit 10 have the same functions, the first-phase synchronous rectification Buck current control circuit 9 is taken as an example for description.

[0073] The first phase synchronous rectification Buck current control circuit 9 comprises an operational amplifier chip unit U5A, the positive input end of the operational amplifier chip unit U5A is connected with the sixteenth resistor R16, the seventeenth resistor R17 and the fifteenth resistor C15 and grounded to receive the output signal of the voltage closed loop compensation control circuit 11 as the input given signal of the first phase synchronous rectification Buck current control circuit 9, which is the reference given signal of the current closed loop control adjustment PID principle circuit function.

[0074] The negative input end of the operational amplifier chip unit U5A is connected with the first phase main loop current output sensor feedback signal Vcfb1 from the double closed loop control circuit outside through the fifteenth resistor R15. The output end of the operational amplifier chip unit U5A and the negative input end of the operational amplifier chip unit U5A are connected with the second-order compensation network composed of the ninth capacitor C9, the tenth capacitor C10 and the fourteenth resistor R14, and the output end of the operational amplifier chip unit U5A is connected with the pulse width modulation generation circuit. The current given reference signal input to the positive end of the operational amplifier chip unit U5A and the current feedback signal input to the negative end of the operational amplifier chip unit U5A are processed by the PID operation of the second-order compensation network composed of the operational amplifier chip unit U5A and the discrete elements ninth capacitor C9, tenth capacitor C10 and fourteenth resistor R14, and then the output signal of the closed loop control regulator is obtained, which is output from the output end of the operational amplifier chip unit U5A and then sent to the pulse width modulation generation circuit 6 in the rear stage to generate the PWM duty cycle signal. The PID adjustment controller of the second-order compensation network composed of the operational amplifier chip unit U5A and the discrete elements can set the PID parameters of the adjustment controller by adjusting the parameters of the resistance and capacitance elements to achieve the desired optimal control effect, which provides an optimal debugging method for the current inner loop control of the double closed loop.

[0075] The structures, proportions, sizes and the like shown in the drawings attached to the specification are only used to cooperate with the content disclosed in the specification for understanding and reading by those skilled in the art, and do not define the limiting conditions for the implementation of the application, so they do not have technical significance. Any modification of the structure, change of the proportional relationship or adjustment of the size, without affecting the effect and purpose that can be achieved by the application, should still fall within the scope of the disclosed technical content. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "first", "second" and the like in the specification are only for the convenience of clear description, and are not used to limit the scope of the application. The change or adjustment of the relative relationship without substantially changing the technical content is also considered as the scope of the application.

[0076] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

[0077] It is to be understood that the application is not limited to the precise construction herein disclosed and shown in the drawings, and that various changes in shape, size and arrangements of parts can be made without departing from the scope of the application. The scope of the application is limited only by the claims that follow.

Claims

1. A dual closed-loop control circuit for a two-phase interleaved parallel synchronous rectifier Buck power converter, characterized in that, include: The first phase synchronous rectification Buck current control circuit (9), the second phase synchronous rectification Buck current control circuit (10), and the voltage closed-loop compensation control circuit (11); The first phase synchronous rectification Buck current control circuit (9) and the second phase synchronous rectification Buck current control circuit (10) are connected in parallel to form the current control circuit of the main circuit. The two-phase current output control of the current control circuit of the main circuit is used as the inner loop current control of the double closed loop control circuit for two-way current signal feedback conditioning and current closed loop PID control regulation. The voltage closed-loop compensation control circuit (11) is connected to the first phase synchronous rectification Buck current control circuit (9) and the second phase synchronous rectification Buck current control circuit (10) respectively, and outputs voltage closed-loop regulation control as the outer loop voltage control of the dual closed-loop control circuit, which is used for voltage signal feedback conditioning and voltage closed-loop PID regulation control. The dual closed-loop control circuit also includes a clock source generating circuit (1), a control signal distribution circuit (3) connected to the clock source generating circuit (1), a trigger pulse control signal circuit (4) connected to the control signal distribution circuit (3), a triangular sawtooth wave generating circuit (8) connected to the trigger pulse control signal circuit (4), and a power supply circuit (2). The clock source generating circuit (1) generates a square wave signal with an adjustable frequency. After the square wave signal passes through the two-channel control signal distribution circuit (3), it generates two staggered synchronous control signals with a phase difference of 180° to the two-channel staggered phase trigger pulse control signal circuit (4). The two short pulse trigger signals generated by the two-channel staggered phase trigger pulse signal control circuit serve as the start and end signals of the two-channel triangular sawtooth wave generating circuit (8).

2. The dual closed-loop control circuit according to claim 1, characterized in that, The phase difference between the first phase control drive signal of the first phase synchronous rectification Buck current control circuit (9) and the second phase control drive signal of the second phase synchronous rectification Buck current control circuit (10) is 180°.

3. The dual closed-loop control circuit according to claim 1, characterized in that, The first phase synchronous rectification Buck current control circuit (9) includes an operational amplifier chip unit U5A. The positive input terminal of the operational amplifier chip unit U5A is connected to the sixteenth resistor R16, the seventeenth resistor R17, and the fifteenth capacitor C15 and grounded to receive the output signal of the voltage closed-loop compensation control circuit (11) as the input given signal of the first phase synchronous rectification Buck current control circuit (9). The negative input terminal of the operational amplifier chip unit U5A is connected to the feedback signal Vcfb1 of the first phase main circuit current output sensor through the fifteenth resistor R15. The output terminal and the negative input terminal of the operational amplifier chip unit U5A are connected to the second-order compensation network composed of the ninth capacitor C9, the tenth capacitor C10, and the fourteenth resistor R14. The output terminal of the operational amplifier chip unit U5A is connected to the pulse width modulation generation circuit.

4. The dual closed-loop control circuit according to claim 1, characterized in that, The voltage closed-loop compensation control circuit (11) includes an operational amplifier chip unit U9A. The positive input terminal of the operational amplifier chip unit U9A is connected to the seventeenth capacitor C17, the twenty-fourth resistor R24, and the twenty-third resistor R23 to receive the set voltage reference signal. The negative output terminal of the operational amplifier chip unit U9A is connected to the twenty-fifth resistor R25 to input the voltage output sensor feedback signal Vfb1. After the two signals enter the operational amplifier chip unit U9A, they are subjected to phase difference calculation, and then enter the second-order compensation network composed of the operational amplifier chip unit U9A, the thirteenth capacitor C13, the twenty-second resistor R22, and the fourteenth capacitor C14 for PID compensation calculation. The output terminal of the operational amplifier chip unit U9A obtains the output signal of the voltage closed-loop PID regulation control.

5. The dual closed-loop control circuit according to claim 1, characterized in that, The power supply circuit (2) is constructed using a power regulator chip and discrete resistor-capacitor components.

6. The dual closed-loop control circuit according to claim 1, characterized in that, The power supply for the triangular sawtooth wave circuit (8) of the two channels is provided by the constant current source generation circuit (5) of the two channels, which is used to generate a constant charging current for the two channels.

7. The dual closed-loop control circuit according to claim 6, characterized in that, The triangular sawtooth wave circuit (8) of the two channels is connected to the pulse width modulation generation circuit (6), and the pulse width modulation generation circuit (6) is connected to the signal driving circuit (7). The negative input terminal of comparator U6A in the pulse width modulation generation circuit (6) is connected to the drain of the third MOSFET Q3 in the triangular sawtooth wave circuit (8), the positive input terminal of comparator U6A is connected to the output terminal of the operational amplifier chip unit U5A in the first phase synchronous rectification Buck current control circuit (9), and the output terminal of comparator U6A is connected to the signal driving circuit. The negative input terminal of comparator U6B in the pulse width modulation generation circuit (6) is connected to the drain of the fourth MOSFET Q4 in the triangular sawtooth wave circuit (8), the positive input terminal of comparator U6B is connected to the output terminal of the operational amplifier chip unit U5B in the second phase synchronous rectification Buck current control circuit (10), and the output terminal of comparator U6B is connected to the signal driving circuit.

8. The dual closed-loop control circuit according to claim 7, characterized in that, The two-channel signal drive circuit (7) is used for signal interlocking with dead time on the upper and lower bridge arms of the two power switching transistors in each main circuit. The two drive signals of each channel are transmitted to the control poles of the upper and lower bridge arms of the power switching transistors that need to be controlled, so as to provide control gate drive signals for the four main circuit power switching transistors of the main power circuit.

9. The dual closed-loop control circuit according to claim 8, characterized in that, The signal driving circuit (7) includes two NAND gate unit modules. The input terminals of the two NAND gate unit modules respectively receive the two-phase duty cycle PWM signals of the pulse width modulation generation circuit (6), and then generate two-phase signals with opposite logic directions corresponding to the two phases, thus obtaining two sets of signals used for two-phase interleaved parallel control, namely 4 signals.

Images