Amplifier circuit

Abstract

An amplifier circuit is disclosed. The Doherty amplifier circuit has an adjustable impedance and phase ("TIP") circuit to provide an adjustable alpha factor that allows selection of a power added efficiency (PAE) curve that is useful for applications with different modulations or for meeting other criteria. Embodiments include a Doherty amplifier having a TIP circuit that provides adjustability to impedance ZINV (producing an adjustable alpha factor) while maintaining the phase of the output of the carrier amplifier at a phase change of 90 DEG (for a selected polarity) + / -low. Embodiments of a TIP circuit include one or more TIP cells connected in series, the TIP cells including at least one TIP circuit in combination with an adjustable phase adjustment circuit. In operation, when adjusting the impedance of the TIP cell, adjustments within the cell are also made to provide phase shift correction back to 90 DEG (at a selected polarity).

Description

[0001] This application is a divisional application of the invention patent application with application number 201910184705.6 and invention name “Doherty amplifier with adjustable alpha factor” submitted by the applicant to the China Patent Office on March 12, 2019. Technical Field

[0002] The present invention relates to electronic circuits and, more particularly, to radio frequency amplifier circuits. Background Art

[0003] Many modern electronic systems include radio frequency (RF) transceivers, examples include personal computers, tablet computers, wireless network components, televisions, cable system "set-top" boxes, radar systems, and cellular phones. Many RF transceivers are fairly complex two-way radios that transmit and receive RF signals on multiple frequencies in multiple frequency bands using one or more signaling protocols. For example, a modern "smart phone" may include RF transceiver circuitry that is capable of operating on different cellular communication systems (e.g., GSM and CDMA), different wireless network frequencies and protocols (e.g., IEEE 802.1bg at 2.4 GHz, IEEE 802.1n at 2.4 GHz and 5 GHz), and "personal" local area networks (e.g., Bluetooth-based systems).

[0004] In portable battery-operated devices such as cellular phones, the RF power amplifier (PA) in the RF transceiver consumes a significant portion of the total device current, thus affecting battery life. Therefore, reducing the average PA current will extend battery life and increase "talk time," which is defined as the time it takes to discharge the device battery while on a phone call or transmitting or receiving data.

[0005] Cellular telephone systems require the handset PA to output a range of power levels, depending on the distance to the base station and signal path conditions. The efficiency of such a system can be expressed as a percentage: power added efficiency (PAE), defined as (RF power out - RF power in) ÷ DC power supplied; higher percentages are desirable. Efforts have been made to maximize PAE at full power levels, and in some systems (e.g., GSM cellular systems), PAE has reached 50-60% at full power. It is argued that it would also be beneficial to improve PAE at lower power levels, thereby increasing the average PAE at multiple power levels; see, e.g., Darren W. Ferwalt, "A Base Control Doherty Power Amplifier Design for Improved Efficiency in GSM Handsets," §1.1 and §1.2, B.S. Thesis, Oregon State University, December 10, 2003.

[0006] A method for achieving improved PAE at lower power levels was first developed by William Doherty as described in U.S. Patent No. 2,210,028, issued on August 6, 1940. Figure 1A 1 is a simplified schematic diagram of a prior art Doherty amplifier 100. The Doherty amplifier 100 consists of a carrier amplifier 102 coupled in parallel with a peak amplifier 104; for example, the amplifiers 102, 104 may be MOSFET-based circuits. The RF input signal RF IN is directly applied to the carrier amplifier 102, and the RF input signal RF is transmitted through the quarter-wavelength transmission line L1. IN The quarter-wavelength transmission line L1 directly applies RF IN The output of the carrier amplifier 102 is phase-shifted by -90° by the quarter-wavelength transmission line L2 and combined in phase with the output of the peak amplifier 104 to generate a phase shift of -90° at the load resistor R L Provides an amplified RF output signal RF OUT The quarter-wavelength transmission line L2 is also called an impedance inverter and has Z INV Characteristic impedance (Z0).

[0007] In operation, both amplifiers 102, 104 are turned on at full power, while the peak amplifier 104 is turned off at a low power level. The two amplifiers 102, 104 are configured so that as the power output of the peak amplifier 104 decreases, the load impedance of the carrier amplifier 102 increases to allow the load amplifier 102 to operate at high efficiency at a low power level. Therefore, the combined efficiency at reduced power is improved over the efficiency of a single amplifier.

[0008] The problem with conventional Doherty amplifiers 100 is that, although their outputs can be applied to an adjustable impedance matching network to provide impedance matching for different RF frequency bands, they have a constant alpha factor, α = R L / Z INV .For example, Figure 1B 150 is a graph of amplifier efficiency as a function of output power Pout for a prior art Doherty amplifier with a constant alpha factor of 0.25 (curve 152) and a prior art Doherty amplifier with a constant alpha factor of 0.5 (curve 154); dashed curve graph 156 shows the characteristics of an ideal class B amplifier. For some applications, an alpha factor of 0.25 may be preferred, while for other applications, an alpha factor of 0.5 may be preferred (of course, other alpha factors may be used).

[0009] The constant α is not beneficial in different modulation schemes, such as those used in cellular telephone systems (e.g., Long Term Evolution (LTE), 5G NR, WDCMA, CDMA, GSM, etc.), WiFi LANS, and other wireless transmission systems, especially those using battery-powered transceivers. These modulation schemes have different peak-to-average power ratios. The amplifier must be able to handle the peak power, but more frequently operates at lower average powers. These peak-to-average ratios currently range from 0 dB to about 7 dB. A single fixed Doherty amplifier used for all of these modulation schemes will suffer from lower PAE at high peak-to-average ratios.

[0010] Therefore, there is a need for a Doherty amplifier circuit with an adjustable alpha factor. The present invention satisfies this need. Summary of the invention

[0011] Embodiments of the present invention include a Doherty amplifier circuit with adjustable impedance and phase circuits to provide an adjustable alpha factor. The adjustable alpha factor allows selection of a power added efficiency (PAE) curve that is useful for applications with different modulation schemes or to meet other criteria. In particular, the adjustable alpha factor allows adjustment of the secondary PAE peak so that the overall PAE can be optimized for different modulations (peak-to-average ratio) and also for average power levels. Embodiments maintain good PAE over a wide range of power levels.

[0012] Embodiments include a Doherty amplifier in which a conventional distributed quarter-wavelength transmission line impedance inverter is replaced by a tunable impedance and phase ("TIP") circuit. A characteristic of the TIP circuit is that it provides an impedance Z INV Adjustability (thus obtaining adjustable α = R L / Z INV ), while maintaining the output phase of the carrier amplifier at 90° (for the selected polarity) ± acceptably low phase variation.

[0013] Various embodiments of the TIP circuit include one or more series-connected adjustable phase impedance units, the adjustable phase impedance unit including at least one adjustable impedance circuit combined with at least one adjustable phase adjustment circuit. In operation, when the impedance of the adjustable impedance and phase unit is adjusted, adjustments are also made within the unit to provide phase shift correction back to 90° (at a selected polarity).

[0014] The details of one or more embodiments of the invention are set forth in the following drawings and description. Other features, objects, and advantages of the invention will be apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A is a simplified schematic diagram of a prior art Doherty amplifier.

[0016] Figure 1B For the following amplifier, as output power P out Graph of amplifier efficiency as a function of: a prior art Doherty amplifier with a constant alpha factor of 0.25, and a prior art Doherty amplifier with a constant alpha factor of 0.5; the dashed line graph shows the characteristics of an ideal class B amplifier.

[0017] Figure 2 is a simplified schematic diagram of a Doherty amplifier providing an adjustable alpha factor with low phase shift.

[0018] Figure 3A is a schematic diagram of a first embodiment of an adjustable impedance and phase circuit.

[0019] Figure 3B is a schematic diagram of a second embodiment of an adjustable impedance and phase circuit.

[0020] Figure 4 is a schematic diagram of a third embodiment of an adjustable impedance and phase circuit.

[0021] Figure 5A yes Figure 2 Schematic diagram of a Doherty amplifier, where the block symbols representing the adjustable impedance and phase circuits have been Figure 3A An adjustable impedance and phase unit of the type shown in FIG.

[0022] Figure 5B yes Figure 2 Schematic diagram of a modified version of the Doherty amplifier, in which the block symbols representing the adjustable impedance and phase circuits have been replaced by Figure 4 An adjustable impedance and phase unit of the type shown is substituted.

[0023] Figure 6 The values ​​shown in Table 1 are used to show the Figure 3A Modeled adjustable impedance and phase units of the type shown, for Z INV Plot of PAE as a function of power input (Pin) for different values ​​of .

[0024] Figure 7 is a flow chart illustrating a first method of manufacturing a Doherty amplifier.

[0025] Figure 8 is a flow chart illustrating a second method of manufacturing a Doherty amplifier.

[0026] Fig. 9 is a flow chart illustrating a third method of manufacturing a Doherty amplifier.

[0027] The same reference numerals and names refer to the same elements in different drawings. DETAILED DESCRIPTION

[0028] Embodiments of the invention include a Doherty amplifier with adjustable impedance and phase circuits to provide an adjustable alpha factor. The adjustable alpha factor allows selection of a power added efficiency (PAE) curve that is useful for applications with different modulation schemes or to meet other criteria. In particular, the adjustable alpha factor allows adjustment of the secondary PAE so that the overall PAE can be optimized for different modulations (peak-to-average ratio) and also for average power levels. Embodiments maintain good PAE over a wide range of power levels.

[0029] The transmission lines L1, L2 of a conventional Doherty amplifier can be approximated by a lumped element circuit, and in some applications, the lumped element circuit may be adjustable. However, simply replacing the conventional impedance inverter L2 with an adjustable lumped element equivalent circuit (e.g., an adjustable LC low-pass filter) results in a circuit in which the alpha factor can be adjusted (by adjusting the value of L or C to change Z INV , thereby changing the characteristic impedance Z0—for an adjustable lumped element), but wherein the phase of the output of inverter L3 is substantially deviated from the optimal 90° value (for the selected polarity), thereby changing the impedance transformation for the carrier amplifier 102 and also changing the phase alignment when the outputs of amplifiers 102, 104 are combined. This will result in a power loss due to combining two signals of different phases.

[0030] Figure 2 is a simplified schematic diagram of a Doherty amplifier 200 that provides an adjustable alpha factor with low phase shift. The amplifier circuit is similar to that of FIG. 1 except that the conventional distributed quarter-wavelength transmission line impedance inverter L2 is replaced by an adjustable impedance and phase (“TIP”) circuit 202. Figure 1A The characteristic of TIP circuit 202 is that it provides an impedance Z INV Adjustability (thus obtaining adjustable α = R L / Z INV ) while maintaining the phase of the output of carrier amplifier 102 at 90° (for the selected polarity, positive or negative) ± an acceptably low phase variation; for many applications, the low phase variation is approximately ±10°, but as described below, a lower phase variation range is achievable.

[0031] Various embodiments of the TIP circuit 202 include one or more stages of adjustable circuitry that provide a 90° phase shift (of a selected polarity) to the input signal, as well as providing adjustable impedance. This can allow for tighter control of phase variations with frequency. For example, Figure 3A FIG. 1 is a schematic diagram of a first embodiment of an adjustable impedance and phase circuit 300a. In the illustrated embodiment, an RF input signal (eg, from a carrier amplifier 102) RF IN is coupled to the RF OUT In this example, each TIP cell 302 includes a "pi" type CLC circuit including a series inductor L1 and two comparable adjustable parallel capacitors C1, which typically have the same value range. In addition, an adjustable capacitor C11 is coupled in parallel with the series inductor L1 to form an adjustable inductor circuit 304 (shown within the dashed oval).

[0032] More specifically, Figure 3A The TIP cells 302 in the embodiment can be viewed as a lumped element approximation of a transmission line. Multiple TIP cells 302 can be cascaded to increase the bandwidth of the lumped element transmission line; typically, each successive TIP cell 302 is a smaller step in phase. Making the lumped element tunable allows for adjustment or tuning of the characteristic impedance and phase shift of the network. While one or both of an adjustable inductor and an adjustable capacitor can be used for such a lumped element, the adjustable inductor tends to consume a large amount of integrated circuit area. However, as Figure 3A As shown in the exemplary adjustable inductor circuit 304 of FIG. 3 , an adjustable inductor may be implemented by placing an adjustable capacitor (eg, C11 ) in parallel with a fixed inductor (eg, L1 ).

[0033] In operation, the impedance and phase of the TIP unit 302 can be adjusted by changing the size and / or ratio of the adjustable impedance and adjustable capacitance lumped elements. Figure 3A In the specific example of the TIP unit 302, the impedance and phase can be adjusted by adjusting the capacitors C1 and C11. Therefore, the Z can be adjusted for the coupled carrier amplifier 102 as needed. INV , to achieve the selected α factor while making a phase shift correction back to 90° (of the selected polarity) for the appropriate amplifier function. Since each of C1 and C11 affects the impedance and phase of the TIP unit 302, the adjustment of C1 and C11 can be a simultaneous or iterative process. In practice, a calibration process can be performed to map the adjustment states of C1 and C11 so that the required impedance and phase shift are obtained by adjusting C1 and C11 to specific values ​​simultaneously without using an iterative process. Alternatively, such mapping can be accomplished by design and / or simulation. The mapped values ​​can be stored in a lookup table. Such a lookup table may include, for example, the following functions: input a required mode (e.g., a specific transmission configuration, such as for an LTE cellular system), map the mode to the required component values ​​for the required α factor, and output adjustment values ​​to adjust C11 and / or C11. Alternatively, the adjustment states of C1 and C11 may be dynamically adjusted in a closed-loop manner to achieve the required impedance and phase shift by measuring the phase and impedance of the output of the TIP unit 302 and readjusting the adjustment values ​​of C1 and / or C11 as needed.

[0034] in other words, Figure 3AEach exemplary TIP unit 302 in can be viewed as two coupled circuits, one primarily for adjusting impedance and the other primarily for adjusting phase, but is best viewed as a single adjustable circuit capable of adjusting both impedance and phase simultaneously. Regardless of the characteristics, embodiments of the present invention are capable of adjusting the alpha factor, thereby allowing the secondary PAE peak to be adjusted, so that the overall PAE can be optimized for different modulations (peak-to-average ratio) and also for average power levels.

[0035] Figure 3B FIG. 1 is a schematic diagram of a second embodiment of an adjustable impedance and phase circuit 300 b. Figure 3A The circuits are essentially the same (some reference numerals are omitted to avoid confusion), except for the following differences: Figure 3A The pair of parallel capacitors C1 in the circuit are replaced by a single "shared" capacitor C1', thereby saving components and integrated circuit die area. Generally, the value of capacitor C1' should be approximately the sum of the capacitance of the pair of capacitors C1 replaced by capacitor C1' (thus, if the pair of capacitors C1 replaced are of equal value, the capacitance of capacitor C1' should generally be about twice the capacitance of capacitor C1).

[0036] Figure 4 4 is a schematic diagram of a third embodiment of an adjustable impedance and phase circuit. In this example, an adjustable impedance and phase ("TIP") cell 400 includes a "pi" type LCL circuit including a series resistor C1 and two parallel shunt inductors L1. In addition, a pair of adjustable capacitors C11, typically having the same value range, are coupled in parallel with the shunt inductor L1 to form an adjustable inductor circuit 402 (shown within the dashed oval). It is worth noting that the illustrated TIP cell 400 acts as a high pass network that will provide a +90° base phase shift and therefore requires a +90° shifted input to operate correctly (see below). Figure 5B example).

[0037] Therefore, the TIP unit 400 is Figure 3A The "CLC" TIP cell 302 of the embodiment of the present invention is the "LCL" counterpart of the TIP cell 302 and is adjustable in a similar manner. As described above, since each of C1 and C11 affects the impedance and phase of the TIP cell 302, the adjustment of C1 and C11 can be a simultaneous or iterative process. Similarly, the adjustment of Figure 3A The TIP unit 302 described above may be used to apply calibration, mapping and / or closed-loop adjustment processing.

[0038] It is worth noting that in other embodiments, the polarity of the phase shift of a particular subcircuit may be changed. The key is that the phase shifts are aligned so that the outputs of the carrier amplifier 102 and the peaking amplifier 104 combine in phase. For example, some embodiments may use a -90° phase shift before the carrier amplifier 102, or a -90° phase shift before the peaking amplifier (as described above for the embodiment of FIG. 1 ), as long as the outputs of the amplifiers 102, 104 are appropriately phase shifted to combine in phase. Figure 1A Transmission lines can also be used to produce various phase shifts as required.

[0039] In full context, Figure 5A yes Figure 2 FIG. 5 is a schematic diagram of a Doherty amplifier, wherein the block symbol representing the adjustable impedance and phase circuit 202 is Figure 3A An adjustable impedance and phase unit 302 of the type shown is substituted.

[0040] Similarly, Figure 5B yes Figure 2 A schematic diagram 520 of a modified version of a Doherty amplifier is shown in which the block symbol representing the adjustable impedance and phase circuit 202 is replaced by Figure 4 An adjustable impedance and phase unit 400 of the type shown is substituted. In this example, because the TIP unit 400 is a high pass network, the input to the carrier amplifier 102 is phase shifted by -90° relative to the direct input to the peaking amplifier 104.

[0041] As will be appreciated by those skilled in the art, there are many other ways to implement the following adjustable impedance and phase circuit: The circuit provides an impedance Z INV , while maintaining the phase of the output of the carrier amplifier 102 at 90° (of the selected polarity) ± an acceptably low phase variation. For example, embodiments of the present invention may be implemented using a tee-type (also referred to as a “T-type”) adjustment network, which is respectively Figure 3A and 4 As additional examples, other types of regulating networks may be utilized to implement embodiments of the present invention, including but not limited to LC, CL, low-pass, high-pass, etc., as well as circuits of various topologies, such as pi, tee, bridged-T, L-pad, etc.

[0042] The adjustable capacitors C1 and C11 need not have the same value range, and the value range may vary within the TIP unit 302. One or more of the adjustable capacitors C1, C11 may include a digitally adjustable capacitor of the type described, for example, in U.S. Patent No. 9,024,700, entitled "Method and Apparatus for Digitally Adjusting a Resistor in an Integrated Circuit Device," issued on May 5, 2015, or U.S. Patent No. 9,197,194, entitled "Method and Apparatus for Adjusting Reactance in a Circuit Device," issued on November 24, 2015, the contents of both patents being incorporated herein by reference. Inductor L1 may be fixed (e.g., Figure 3A , 3B and 4), or may be variable, such as a digitally tunable inductor (DTL) of the type described in U.S. Patent No. 9,197,194.

[0043] Although it is advantageous to manufacture all components of TIP cell 302 on the integrated circuit (IC) die, some components may be off-die. Figure 3A , 3B Since IC inductors often consume a large amount of die area in the examples shown in FIG. 4 , it may be useful to use an off-die inductor for L1.

[0044] like Figure 3A As shown, multiple TIP units 302 connected in series better approximate the characteristics of the transmission line, increase the bandwidth of the circuit, and improve the tolerance of the phase shift capability ( Figure 3A Some modeled examples of circuits may maintain the phase of the output of the carrier amplifier 102 at 90°±5° or better for a selected polarity). However, in some implementations, it may be useful to connect multiple TIP cells 302 in parallel or in a configuration where some TIP cells 302 are connected in parallel and some TIP cells 302 are connected in series (e.g., a parallel-series configuration or a grid configuration).

[0045] Specific examples

[0046] exist Figure 3A In a modeled example of a TIP cell 302 of the type shown, capacitors C1, C11 are implemented using DTCs, with the DTCs for the C1 capacitor having the same range and settings; a fixed value (13.9 nH) inductor L1 is used for the model. By setting the values ​​of the DTCs to the values ​​shown in Table 1 below, the characteristic impedance Z0 (=Z INV ) can be varied over a range of about 70Ω to about 190Ω while maintaining a phase shift of -90°±10° over a frequency range of 825-925 MHz.

[0047]

[0048] Note that with these exemplary circuit values, a -14× adjustment ratio for C11 is required to fully cover the Z0 range of about 70Ω to about 190Ω, but only a 2× adjustment ratio for C11 is required to cover the Z0 range of about 100Ω to about 190Ω.

[0049] Figure 6 The values ​​shown in Table 1 are used to show the Figure 3A A modeled TIP unit 302 of the type shown, for Z INV PAE is plotted as a function of power input (Pin) for different values ​​of (i.e., represented as “xΩ”). It can be seen that for a specific input power level, by adjusting the characteristic impedance Z0 (=Z INV ) can change the PAE curve, thereby adjusting α(=R L / Z INV ).

[0050] calibration

[0051] The TIP circuit 202 can be calibrated to obtain a set of component values ​​similar to those shown in Table 1, with the same, more, or fewer different Z0 settings. One calibration method is to step through possible combinations of values ​​for the DTCs including capacitors C1 and C11, and measure the resulting characteristic impedance Z0 for the circuit. If each DTC has 5 control bits, this means that each DTC can be selected to have 2 5 = 32 states, then Figure 3A The number of combinations of values ​​of C1 and C11 in a single TIP cell 302 of the type shown is 1024 (2 5 ×2 5 , assuming that for each combination, the two C1 capacitors are set to the same value). Utilizing multiple TIP cells 302 increases the total number of available combinations.

[0052] A subset of such DTC combinations can be conveniently selected that produces a Z0 value that closely matches the desired characteristic impedance. In any case, the combination of settings for the DTCs can be stored in a lookup table that maps DTC states to specific Z0 values. The lookup table can be implemented as a read-only memory device (e.g., ROM, PROM, EAROM, EPROM, etc.) that can be used in conjunction with conventional control circuitry.

[0053] method

[0054] Another aspect of the invention includes a method for making a Doherty amplifier having an adjustable impedance and phase circuit, wherein the adjustable impedance and phase circuit provides an adjustable alpha factor. For example, Figure 7 702. The present invention is a flow chart illustrating a first method of manufacturing a Doherty amplifier, the method comprising providing a Doherty amplifier having an impedance inverter, the impedance inverter comprising an adjustable impedance and phase circuit, the adjustable impedance and phase circuit providing adjustability to the characteristic impedance of the impedance inverter while maintaining an insertion phase of a signal passing through the impedance inverter at approximately 90° (e.g., -90° or +90°) with a selected polarity.

[0055] As another example, Figure 8 is a flow chart illustrating a second method of making a Doherty amplifier, the method comprising providing a Doherty amplifier with circuitry for providing an adjustable alpha factor (step 802).

[0056] As another example, Fig. 9 is a flow chart illustrating a third method of manufacturing a Doherty amplifier, the method comprising providing a Doherty amplifier having an impedance inverter, the impedance inverter comprising at least one digitally adjustable circuit configured to provide (1) adjustability of a characteristic impedance of the Doherty amplifier, and (2) adjustability of a phase of a signal input to the impedance inverter to maintain the phase of the signal at approximately 90° with a selected polarity.

[0057] Other embodiments of the above method may include one or more of the following aspects: wherein the phase of the signal passing through the impedance inverter is maintained at 90°±about 10° at a selected polarity; wherein the phase of the signal passing through the impedance inverter is maintained at 90°±about 5° at a selected polarity; wherein the adjustable impedance and phase circuit includes one or more adjustable impedance and phase units connected in series and / or in parallel; wherein at least one adjustable impedance and phase unit provides adjustability using at least one digitally adjustable capacitor; wherein at least one adjustable impedance and phase circuit includes one of an LCL circuit or a CLC circuit or an LC circuit or a CL circuit; wherein the adjustable impedance and phase circuit is configured in one of a pi-type or a tee-type configuration; wherein the circuit system for providing an adjustable alpha factor provides adjustability to the characteristic impedance of the Doherty amplifier; wherein the circuit system for providing an adjustable alpha factor provides adjustability of the phase of a signal input so as to maintain the phase of the signal at approximately 90° at a selected polarity; wherein the circuit system for providing an adjustable alpha factor comprises at least one adjustable circuit comprising one of an LCL circuit or a CLC circuit or an LC circuit or a CL circuit; wherein the circuit system for providing an adjustable alpha factor comprises at least one adjustable circuit configured in one of a pi-type or a tee-type configuration; wherein the phase of the signal is maintained at 90°±approximately 10° at a selected polarity; wherein the phase of the signal is maintained at 90°±approximately 5° at a selected polarity; further comprising adjusting the adjustable alpha factor for different modulations of the input signal; and further comprising adjusting the adjustable alpha factor for different power levels of the input signal.

[0058] application

[0059] Circuits and devices according to the present invention may be used alone or in combination with other components, circuits or devices. Embodiments of the present invention may be manufactured as integrated circuits (ICs), which may be packaged in IC packages and / or modules to facilitate handling, manufacturing and / or performance enhancement.

[0060] Circuits according to the present invention are useful in a wide range of larger radio frequency (RF) circuits for performing a range of functions. Such functions are useful in a variety of applications, such as radar systems (including phased array and automotive radar systems), radio systems, and test equipment. Such circuits can be used in systems operating over some or all of the radio frequency range (e.g., from about 20 kHz to about 300 GHz).

[0061] Radio system uses include cellular radio systems (including base stations, relay stations, and handheld transceivers) that utilize such technology standards as various types of Orthogonal Frequency Division Multiplexing (“ODFM”), various types of Quadrature Amplitude Modulation (“QAM”), Code Division Multiple Access (“CDMA”), Wideband Code Division Multiple Access (“WCDMA”), Global System for Mobile Communications (“GSM”), Enhanced Data Rates for GSM Evolution (EDGE), Long Term Evolution (“LTE”), 5G New Radio (“5G NR”), and other radio communication standards and protocols.

[0062] In particular, the present invention is useful in portable battery operated devices such as cellular telephones which would benefit from utilizing a Doherty amplifier circuit having an adjustable impedance and phase circuit providing an adjustable alpha factor. The adjustable alpha factor allows the PAE curve to be selected over a wide range of power levels, so that current consumption in such devices can be better controlled, thereby enabling improved battery life.

[0063] Manufacturing technology and selection

[0064] The term "MOSFET" as used in this disclosure means any field effect transistor (FET) having an insulated gate and including metal or metalloid, insulator, and semiconductor structures. The term "metal" or "metalloid" includes at least one conductive material (e.g., aluminum, copper or other metals, or highly doped polysilicon, graphene or other electrical conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric materials), and "semiconductor" includes at least one semiconductor material.

[0065] It is readily apparent to those skilled in the art that various embodiments of the present invention can be implemented to meet a wide range of specifications. Unless otherwise noted above, the selection of appropriate component values ​​is a matter of design choice, and various embodiments of the present invention can be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit form. Integrated circuit implementations can be manufactured using any suitable substrate and process, including but not limited to standard bulk silicon, silicon-on-insulator (SOI) and silicon-on-sapphire (SOS). Unless otherwise noted above, the present invention can be implemented with other transistor technologies, such as bipolar, GaAs HBT, GaN HEMT, GaAs pHEMT and MESFET technology. However, the above-mentioned inventive concepts are particularly useful for SOI-based manufacturing processes (including SOS) and manufacturing processes with similar characteristics. Manufacturing in CMOS processes on SOI or SOS realizes the following circuits: the circuit has low power consumption, the ability to withstand high power signals during operation generated by FET stacking, good linearity and high-frequency operation (i.e., up to and exceeding 50GHz radio frequencies). Monolithic IC implementations are particularly useful because parasitic capacitances can usually be kept low (or at least kept consistent across all cells, allowing them to be compensated) by careful design.

[0066] Depending on the particular specifications and / or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices), voltage levels may be adjusted, or voltage and / or logic signal polarity may be inverted. For example, component voltage, current, and power handling capabilities may be adjusted as needed by adjusting device size, "stacking" components (particularly FETs) in series to withstand higher voltages, and / or utilizing multiple components in parallel to handle higher currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or provide additional functionality without significantly changing the functionality of the disclosed circuits.

[0067] in conclusion

[0068] Some embodiments of the present invention have been described. It will be appreciated that various modifications may be made without departing from the spirit and scope of the present invention. For example, some of the steps described above may be order-independent and thus may be performed in an order different from that described. Furthermore, some of the steps described above may be optional. The various activities described with respect to the above-described methods may be performed in a repetitive, serial, or parallel manner.

[0069] In addition, the present invention also includes the following embodiments.

[0070] Embodiment 1. A Doherty amplifier comprising an impedance inverter, the impedance inverter comprising an adjustable impedance and phase circuit, the adjustable impedance and phase circuit providing adjustability of the characteristic impedance of the impedance inverter while maintaining the insertion phase of a signal passing through the impedance inverter at approximately 90° with a selected polarity.

[0071] Embodiment 2. The Doherty amplifier of embodiment 1, wherein the phase of the signal passing through the impedance inverter is maintained at 90°±about 10° with the selected polarity.

[0072] Embodiment 3. The Doherty amplifier of Embodiment 1, wherein the phase of the signal passing through the impedance inverter is maintained at 90°±about 5° with the selected polarity.

[0073] Embodiment 4: The Doherty amplifier according to embodiment 1, wherein the adjustable impedance and phase circuit comprises one or more adjustable impedance and phase units connected in series and / or in parallel.

[0074] Embodiment 5. The Doherty amplifier of embodiment 4, wherein the at least one adjustable impedance and phase unit utilizes at least one digitally adjustable capacitor to provide adjustability.

[0075] Embodiment 6. The Doherty amplifier according to embodiment 4, wherein the at least one adjustable impedance and phase circuit comprises one of an LCL circuit or a CLC circuit or an LC circuit or a CL circuit.

[0076] Embodiment 7. The Doherty amplifier of embodiment 1, wherein the adjustable impedance and phase circuit is configured as one of a pi-type configuration or a tee-type configuration.

[0077] Embodiment 8. A Doherty amplifier including circuitry for providing an adjustable alpha factor.

[0078] Embodiment 9. The Doherty amplifier of Embodiment 8, wherein the circuit system for providing an adjustable alpha factor provides adjustability of a characteristic impedance of the Doherty amplifier.

[0079] Embodiment 10. The Doherty amplifier of Embodiment 8, wherein the circuit system for providing an adjustable alpha factor provides adjustability of the phase of the signal input to maintain the phase of the signal at approximately 90° with a selected polarity.

[0080] Embodiment 11. The Doherty amplifier of Embodiment 10, wherein the phase of the signal is maintained at 90°±about 10° with the selected polarity.

[0081] Embodiment 12. The Doherty amplifier of Embodiment 10, wherein the phase of the signal is maintained at 90°±about 5° with the selected polarity.

[0082] Embodiment 13. The Doherty amplifier of Embodiment 8, wherein the circuit system for providing an adjustable alpha factor comprises at least one adjustable circuit, the adjustable circuit comprising one of an LCL circuit or a CLC circuit or an LC circuit or a CL circuit.

[0083] Embodiment 14. The Doherty amplifier of Embodiment 8, wherein the circuit system for providing an adjustable alpha factor comprises at least one adjustable circuit configured in one of a pi-type configuration or a tee-type configuration.

[0084] Embodiment 15. The Doherty amplifier of Embodiment 8, wherein the adjustable alpha factor is adjusted for different modulations of the input signal.

[0085] Embodiment 16. The Doherty amplifier of Embodiment 8, wherein the adjustable alpha coefficient is adjusted for different power levels of an input signal.

[0086] Embodiment 17. A Doherty amplifier comprising an impedance inverter, the impedance inverter comprising at least one digitally adjustable circuit, the digitally adjustable circuit being configured to provide adjustability of the characteristic impedance of the Doherty amplifier and to provide adjustability of the phase of a signal input to the impedance inverter, thereby maintaining the phase of the signal at approximately 90° with the selected polarity.

[0087] Embodiment 18. The Doherty amplifier of Embodiment 17, wherein the phase of the signal is maintained at 90°±about 10° with the selected polarity.

[0088] Embodiment 19. The Doherty amplifier of Embodiment 17, wherein the phase of the signal is maintained at 90°±about 5° with the selected polarity.

[0089] Embodiment 20. A method of manufacturing a Doherty amplifier, the method comprising providing a Doherty amplifier having an impedance inverter, the impedance inverter comprising an adjustable impedance and phase circuit, the adjustable impedance and phase circuit providing adjustability of the characteristic impedance of the impedance inverter while maintaining an insertion phase of a signal passing through the impedance inverter at approximately 90° with a selected polarity.

[0090] Embodiment 21. The method of Embodiment 20, wherein the phase of the signal passing through the impedance inverter is maintained at 90°±approximately 10° with the selected polarity.

[0091] Embodiment 22. The method of Embodiment 20, wherein the phase of the signal passing through the impedance inverter is maintained at 90° ± approximately 5° with the selected polarity.

[0092] Embodiment 23. The method according to embodiment 20, wherein the adjustable inverter and phase circuit includes one or more adjustable impedance and phase units connected in series and / or in parallel.

[0093] Embodiment 24. The method of Embodiment 23, wherein the at least one adjustable impedance and phase unit utilizes at least one digitally adjustable capacitor to provide adjustability.

[0094] Embodiment 25. The method according to embodiment 23, wherein the at least one adjustable impedance and phase circuit comprises one of an LCL circuit or a CLC circuit or an LC circuit or a CL circuit.

[0095] Embodiment 26. The method of embodiment 20, wherein the adjustable impedance and phase circuit is configured as one of a pi-type configuration or a tee-type configuration.

[0096] Embodiment 27. A method of manufacturing a Doherty amplifier, the method comprising providing the Doherty amplifier with circuitry for providing an adjustable alpha coefficient.

[0097] Embodiment 28. The method of Embodiment 27, wherein the circuitry for providing an adjustable alpha factor provides adjustability of a characteristic impedance of the Doherty amplifier.

[0098] Embodiment 29. The method of Embodiment 27, wherein the circuit system for providing an adjustable alpha coefficient provides adjustability of the phase of the signal input to maintain the phase of the signal at approximately 90° with a selected polarity.

[0099] Embodiment 30. The method of Embodiment 29, wherein the phase of the signal is maintained at 90° ± approximately 10° with the selected polarity.

[0100] Embodiment 31. A method according to Embodiment 29, wherein the phase of the signal is maintained at 90°±approximately 5° with the selected polarity.

[0101] Embodiment 32. The method of embodiment 27, wherein the circuit system for providing an adjustable alpha factor includes at least one adjustable circuit, the adjustable circuit including one of an LCL circuit or a CLC circuit or an LC circuit or a CL circuit.

[0102] Embodiment 33. The method of Embodiment 27, wherein the circuit system for providing an adjustable alpha factor includes at least one adjustable circuit configured in one of a pi-type configuration or a tee-type configuration.

[0103] Embodiment 34. The method of embodiment 27, further comprising: adjusting the adjustable alpha factor for different modulations of the input signal.

[0104] Embodiment 35. The method of embodiment 27, further comprising: adjusting the adjustable alpha factor for different power levels of the input signal.

[0105] Embodiment 36. A method for manufacturing a Doherty amplifier, the method comprising providing a Doherty amplifier having an impedance inverter, the impedance inverter comprising at least one digitally adjustable circuit, the digitally adjustable circuit being configured to provide adjustability of the characteristic impedance of the Doherty amplifier, and to provide adjustability of the phase of a signal input to the impedance inverter, thereby maintaining the phase of the signal at approximately 90° with the selected polarity.

[0106] Embodiment 37. A method according to Embodiment 36, wherein the phase of the signal is maintained at 90°±approximately 10° with the selected polarity.

[0107] Embodiment 38. A method according to Embodiment 36, wherein the phase of the signal is maintained at 90°±approximately 5° with the selected polarity.

[0108] It will be appreciated that the above description is intended to illustrate, but not to limit, the scope of the invention, which is defined by the scope of the claims, and other implementations are within the scope of the claims. (It is worth noting that parenthetical markings used for claim elements are for ease of reference to such elements, and do not in themselves indicate a specific required order or enumeration of the elements; furthermore, such markings may be reused in dependent claims as references to additional elements without being deemed to initiate a conflicting marking sequence).

Claims

1. An amplifier circuit comprising a carrier amplifier coupled in parallel with a peaking amplifier, and further comprising a digitally adjustable impedance and phase circuit coupled to the carrier amplifier and the peaking amplifier, the digitally adjustable impedance and phase circuit being configured to select a power added efficiency (PAE) curve of the amplifier circuit as a function of output power.

2. The amplifier circuit according to claim 1, wherein: The digitally adjustable impedance and phase circuit is configured to provide an adjustable alpha factor.

3. The amplifier circuit according to claim 2, wherein: The adjustable alpha factor allows the secondary PAE peak to be adjusted according to the selected modulation scheme.

4. The amplifier circuit according to claim 2, wherein: The adjustable alpha factor allows the secondary PAE peak to be adjusted to optimize the average power level.

5. The amplifier circuit according to claim 2, wherein: The peak efficiency of the amplifier circuit relative to output power can be selected based on the adjustable alpha factor.

6. The amplifier circuit according to claim 2, wherein: The adjustable alpha factor is adjustable for different modulations of the input signal.

7. The amplifier circuit according to claim 2, wherein: The adjustable alpha factor is adjustable for different power levels of the input signal.

8. The amplifier circuit according to claim 1, wherein: The digitally adjustable impedance and phase circuit provides adjustability of both the impedance level and the amount of phase shift of the applied signal.

9. The amplifier circuit according to claim 1, wherein: The digitally adjustable impedance and phase circuit maintains an insertion phase of an applied signal through the adjustable impedance and phase circuit at approximately 90° over an impedance range.

10. The amplifier circuit according to claim 1, wherein: The digitally adjustable impedance and phase circuit comprises a lumped element digitally adjustable impedance and phase circuit.

11. The amplifier circuit according to claim 1, wherein: The digitally adjustable impedance and phase circuit provides adjustability of both the impedance level and the amount of phase shift of an applied signal, and maintains an insertion phase of an applied signal passing through the adjustable impedance and phase circuit at approximately 90° over an impedance range.

12. The amplifier circuit according to claim 11, wherein: The digitally adjustable impedance and phase circuit comprises a lumped element digitally adjustable impedance and phase circuit.

13. An amplifier circuit comprising a carrier amplifier coupled in parallel with a peaking amplifier, and further comprising a digitally adjustable impedance and phase circuit coupled to the carrier amplifier and the peaking amplifier, the digitally adjustable impedance and phase circuit being configured to provide an adjustable alpha factor of the amplifier circuit, wherein: Different power added efficiency (PAE) curves can be selected based on the adjustable alpha factor.

14. The amplifier circuit according to claim 13, wherein: Each PAE curve includes a peak value.

15. The amplifier circuit according to claim 13, wherein: The adjustable alpha factor allows the secondary power added efficiency (PAE) peak to be adjusted according to the selected modulation scheme.

16. The amplifier circuit according to claim 13, wherein: The adjustable alpha factor allows the secondary power added efficiency PAE peak to be adjusted to optimize the average power level.

17. The amplifier circuit according to claim 13, wherein: The peak efficiency of the amplifier circuit relative to output power can be selected based on the adjustable alpha factor.

18. The amplifier circuit according to claim 13, wherein: The adjustable alpha factor is adjustable for different modulations of the input signal.

19. The amplifier circuit according to claim 13, wherein: The adjustable alpha factor is adjustable for different power levels of the input signal.

20. The amplifier circuit of claim 13, wherein: The digitally adjustable impedance and phase circuit provides adjustability of both the impedance level and the amount of phase shift of the applied signal.

21. The amplifier circuit of claim 13, wherein: The digitally adjustable impedance and phase circuit maintains an insertion phase of an applied signal through the adjustable impedance and phase circuit at approximately 90° over an impedance range.

22. The amplifier circuit of claim 13, wherein: The digitally adjustable impedance and phase circuit comprises a lumped element digitally adjustable impedance and phase circuit.

23. The amplifier circuit of claim 13, wherein: The digitally adjustable impedance and phase circuit provides adjustability of both the impedance level and the amount of phase shift of an applied signal, and maintains an insertion phase of an applied signal passing through the adjustable impedance and phase circuit at approximately 90° over an impedance range.

24. The amplifier circuit of claim 23, wherein: The digitally adjustable impedance and phase circuit comprises a lumped element digitally adjustable impedance and phase circuit.

25. An amplifier circuit comprising a carrier amplifier coupled in parallel with a peak amplifier, and further comprising a digitally adjustable impedance and phase circuit coupled to the carrier amplifier and the peak amplifier, wherein: The digitally adjustable impedance and phase circuit is configured to (1) provide an adjustable alpha factor, and (2) select a power added efficiency (PAE) curve of the amplifier based on the adjustable alpha factor.

26. The amplifier circuit of claim 25, wherein: Each PAE curve includes a peak value.

27. The amplifier circuit of claim 26, wherein: The adjustable alpha factor allows the secondary PAE peak to be adjusted according to the selected modulation scheme.

28. The amplifier circuit of claim 26, wherein: The adjustable alpha factor allows the secondary PAE peak to be adjusted to optimize the average power level.

29. The amplifier circuit of claim 25, wherein: The peak efficiency of the amplifier circuit relative to output power can be selected based on the adjustable alpha factor.

30. The amplifier circuit of claim 25, wherein: The adjustable alpha factor is adjustable for different modulations of the input signal.

31. The amplifier circuit of claim 25, wherein: The adjustable alpha factor is adjustable for different power levels of the input signal.

32. The amplifier circuit of claim 25, wherein: The digitally adjustable impedance and phase circuit provides adjustability of both the impedance level and the amount of phase shift of the applied signal.

33. The amplifier circuit of claim 25, wherein: The digitally adjustable impedance and phase circuit maintains an insertion phase of an applied signal through the adjustable impedance and phase circuit at approximately 90° over an impedance range.

34. The amplifier circuit of claim 25, wherein: The digitally adjustable impedance and phase circuit comprises a lumped element digitally adjustable impedance and phase circuit.

35. The amplifier circuit of claim 25, wherein: The digitally adjustable impedance and phase circuit provides adjustability of both the impedance level and the amount of phase shift of an applied signal, and maintains an insertion phase of an applied signal passing through the adjustable impedance and phase circuit at approximately 90° over an impedance range.

36. The amplifier circuit of claim 25, wherein: The digitally adjustable impedance and phase circuit comprises a lumped element digitally adjustable impedance and phase circuit.

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