High-power and high-efficiency millimeter wave power amplifier based on CMOS (Complementary Metal Oxide Semiconductor) process
By designing a high-power, high-efficiency millimeter-wave power amplifier based on CMOS process including input barron module, drive amplifier module, stacked power amplifier module, harmonic control module and power synthesis module, the challenges of millimeter-wave power amplifier based on CMOS process in achieving high power output and high power additional efficiency are solved, and a high-efficiency and low-loss power amplification effect is achieved.
Patent Information
- Application Number
- CN202421955736.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-13
- Publication Date
- 2025-06-13
- Estimated Expiration
- 2034-08-13
AI Technical Summary
Millimeter-wave power amplifiers based on CMOS processes have challenges in achieving high power output and high power additional efficiency, including low supply voltage, low quality factor substrate parasitics and passive devices, and loss problems in traditional power synthesis techniques.
A high-power, high-efficiency millimeter-wave power amplifier based on CMOS process, including an input barron module, a drive amplifier module, a stacked power amplifier module, a harmonic control module and a power synthesis module, is designed. Increase the power supply voltage by stacking power amplifier modules, shaping the drain voltage and current waveform using the harmonic control module, and reducing power synthesis loss through the spatial power synthesis antenna structure.
This achieves the improvement of output power and power additional efficiency of silicon-based millimeter-wave power amplifiers, saves chip area, and reduces losses in traditional transformer power synthesizers.
Smart Images
Figure CN222981512U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of power amplifiers, and specifically relates to a high-power and high-efficiency millimeter-wave power amplifier based on CMOS technology. Background Art
[0002] Power amplifiers are key components in radio frequency communication systems and radar systems. How to effectively transfer power to the antenna has been a huge challenge for a long time. With the increasing demand for power in communication systems, there are more and more applications with high-power output. Currently, most mainstream power amplifiers use compound semiconductor processes. Although they have high saturated output power and power-added efficiency, compound semiconductors are costly, not convenient for large-scale digital circuit integration, and occupy a large area. With the continuous increase in the cut-off frequency of silicon-based processes, millimeter-wave power amplifiers based on CMOS technology have gradually become a research hotspot. However, there are also many problems in designing power amplifiers based on CMOS technology. First, the power supply voltage of silicon-based processes is low, making it difficult to achieve high-power output. Second, the substrate parasitics of silicon-based processes and the quality factors of passive devices are low, resulting in difficulty in achieving high power-added efficiency for power amplifiers. Finally, traditional power combining technologies all have their own losses, which increase with the increase in the number of combining branches. Therefore, it is of great significance to study high-power and high-efficiency millimeter-wave power amplifiers based on CMOS technology. Summary of the Utility Model
[0003] The purpose of the utility model is to provide a high-power and high-efficiency millimeter-wave power amplifier based on CMOS technology to improve the output power and power-added efficiency of silicon-based millimeter-wave power amplifiers.
[0004] The technical method adopted by the utility model to achieve the above purpose is as follows:
[0005] A high-power and high-efficiency millimeter-wave power amplifier based on CMOS technology includes an input balun module, a driver amplifier module, a stacked power amplifier module, a harmonic control module, and a power combining module. The signal output end of the input balun is connected to the signal input end of the driver amplifier, the signal output end of the driver amplifier is connected to the signal input end of the stacked power amplifier, the signal output end of the stacked power amplifier is connected to the signal input end of the harmonic control module, and the signal output end of the harmonic control module is connected to the signal input end of the power combiner.
[0006] As defined: The input balun module includes a first input balun and a second input balun with the same structure. Each input balun includes an input coil and an output coil. An open-circuit transmission line is provided in the input coil. The input coil includes two signal input terminals, one for inputting an external single-ended signal and the other open-circuited; the output coil includes two signal output terminals for outputting differential signals, and the signal output terminals of the output coil are connected to the signal input terminals of the driver amplifier module.
[0007] As defined: The driver amplifier module includes a first driver amplifier and a second driver amplifier with the same structure. Each driver amplifier includes a first-stage amplifier and a second-stage amplifier. The first-stage amplifier is a common-source structure amplifier, and the second-stage amplifier is a cascode structure amplifier. Inter-stage matching is achieved between the first-stage amplifier and the second-stage amplifier through a connecting first transformer; the signal input terminal of the first-stage amplifier is connected to the signal output terminal of the input balun module, and the signal output terminal of the second-stage amplifier is connected to the signal input terminal of the stacked power amplifier module.
[0008] As a further limitation: The first-stage amplifier includes a first capacitor, a second capacitor, a first resistor, a second resistor, a first transistor, a second transistor, a third capacitor, and a fourth capacitor; the second-stage amplifier includes a third transistor, a fourth transistor, a fifth capacitor, a sixth capacitor, a fifth transistor, a sixth transistor, a third resistor, a fourth resistor, a second transformer, a seventh capacitor, and an eighth capacitor; one end of the first capacitor and one end of the second capacitor are both connected to the signal output terminal of the input balun module, the other end of the first capacitor is respectively connected to one end of the first resistor, the gate of the first transistor, and one end of the third capacitor, the other end of the second capacitor is respectively connected to one end of the second resistor, the gate of the second transistor, and one end of the fourth capacitor, the other ends of the first resistor and the second resistor are commonly connected to the first gate bias voltage, the sources of the first transistor and the second transistor are commonly grounded, the drain of the first transistor is respectively connected to the other end of the fourth capacitor and one end of the primary coil of the first transformer, the drain of the second transistor is respectively connected to the other end of the third capacitor and the other end of the primary coil of the first transformer, the center tap of the primary coil of the first transformer is connected to the first DC bias voltage; one end of the secondary coil of the first transformer is respectively connected to one end of the fifth capacitor and the gate of the third transistor, the other end of the secondary coil of the first transformer is respectively connected to one end of the sixth capacitor and the gate of the fourth transistor, the center tap of the secondary coil of the first transformer is connected to the second gate bias voltage, the sources of the third transistor and the fourth transistor are commonly grounded, the drain of the third transistor is respectively connected to the other end of the sixth capacitor and the source of the fifth transistor, the drain of the fourth transistor is respectively connected to the other end of the fifth capacitor and the source of the sixth transistor, the gate of the fifth transistor is connected to one end of the third resistor, the gate of the sixth transistor is connected to one end of the fourth resistor, the other ends of the third resistor and the fourth resistor are commonly connected to the third gate bias voltage, the drain of the fifth transistor is connected to one end of the primary coil of the second transformer, the drain of the sixth transistor is connected to the other end of the primary coil of the second transformer, the center tap of the primary coil of the second transformer is connected to the second DC bias voltage, one end of the secondary coil of the second transformer is connected to one end of the seventh capacitor, the other end of the secondary coil of the second transformer is connected to one end of the eighth capacitor, and the other ends of the seventh capacitor and the eighth capacitor are both connected to the signal input terminal of the stacked power amplifier module.
[0009] As a limitation: The stacked power amplifier module includes a first stacked power amplifier and a second stacked power amplifier with the same structure. Each stacked power amplifier includes a plurality of stacked transistor units connected in series. An inductor is connected between adjacent stacked transistor units. The signal input terminal of the first-layer stacked transistor unit is connected to the signal output terminal of the drive amplifier module. An output matching circuit is connected to the last-layer stacked transistor unit. The signal output terminal of the output matching circuit is connected to the signal input terminal of the harmonic control module. A feedback network is introduced between the first-layer stacked transistor unit and the output matching circuit.
[0010] As a further limitation: Each stacked power amplifier includes four layers of stacked transistor units. The first layer of stacked transistor units includes a ninth capacitor, a tenth capacitor, a seventh transistor, an eighth transistor, a fifth resistor, a sixth resistor, an eleventh capacitor, and a twelfth capacitor; the second layer of stacked transistor units includes a thirteenth capacitor, a fourteenth capacitor, a ninth transistor, a tenth transistor, a seventh resistor, an eighth resistor, a fifteenth capacitor, and a sixteenth capacitor; the third layer of stacked transistor units includes a seventeenth capacitor, an eighteenth capacitor, an eleventh transistor, a twelfth transistor, a ninth resistor, a tenth resistor, a nineteenth capacitor, and a twentieth capacitor; the fourth layer of stacked transistor units includes a twenty-first capacitor, a twenty-second capacitor, a thirteenth transistor, a fourteenth transistor, an eleventh resistor, a twelfth resistor, a twenty-third capacitor, and a twenty-fourth capacitor; the output matching circuit includes a seventh inductor, an eighth inductor, a twenty-fifth capacitor, and a twenty-sixth capacitor; the feedback network includes a thirteenth resistor, a fourteenth resistor, a twenty-seventh capacitor, and a twenty-eighth capacitor; the stacked power amplifier further includes a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor, a sixth inductor, a seventh inductor, an eighth inductor, and a ninth inductor; the sources of the seventh transistor and the eighth transistor are commonly connected to one end of the ninth inductor, the other end of the ninth inductor is grounded, the gate of the seventh transistor is respectively connected to one end of the ninth capacitor, one end of the fifth resistor, and one end of the eleventh capacitor, the gate of the eighth transistor is respectively connected to one end of the tenth capacitor, one end of the sixth resistor, and one end of the twelfth capacitor, the other ends of the ninth capacitor and the tenth capacitor are both connected to the signal output end of the drive amplifier module, the other ends of the fifth resistor and the sixth resistor are both connected to the fourth gate bias voltage, the drain of the seventh transistor is respectively connected to the other end of the twelfth capacitor and one end of the first inductor, the drain of the eighth transistor is respectively connected to the other end of the eleventh capacitor and one end of the second inductor, the other end of the first inductor is connected to the source of the ninth transistor, the other end of the second inductor is connected to the source of the tenth transistor; the gate of the ninth transistor is respectively connected to one end of the thirteenth capacitor, one end of the seventh resistor, and one end of the fifteenth capacitor, the gate of the tenth transistor is respectively connected to one end of the fourteenth capacitor, one end of the eighth resistor, and one end of the sixteenth capacitor, the other ends of the thirteenth capacitor and the fourteenth capacitor are both grounded, the other ends of the seventh resistor and the eighth resistor are both connected to the fifth gate bias voltage, the drain of the ninth transistor is respectively connected to the other end of the sixteenth capacitor and one end of the third inductor, the drain of the tenth transistor is respectively connected to the other end of the fifteenth capacitor and one end of the fourth inductor, the other end of the third inductor is connected to the source of the eleventh transistor, the other end of the fourth inductor is connected to the source of the twelfth transistor;The gate of the eleventh transistor is respectively connected to one end of the seventeenth capacitor, one end of the ninth resistor, and one end of the nineteenth capacitor. The gate of the twelfth transistor is respectively connected to one end of the eighteenth capacitor, one end of the tenth resistor, and one end of the twentieth capacitor. The other ends of the seventeenth capacitor and the eighteenth capacitor are both grounded. The other ends of the ninth resistor and the tenth resistor are both connected to the sixth gate bias voltage. The drain of the eleventh transistor is respectively connected to the other end of the twentieth capacitor and one end of the fifth inductor. The drain of the twelfth transistor is respectively connected to the other end of the nineteenth capacitor and one end of the sixth inductor. The other end of the fifth inductor is connected to the source of the thirteenth transistor. The other end of the sixth inductor is connected to the source of the fourteenth transistor. The gate of the thirteenth transistor is respectively connected to one end of the twenty-first capacitor, one end of the eleventh resistor, and one end of the twenty-third capacitor. The gate of the fourteenth transistor is respectively connected to one end of the twenty-second capacitor, one end of the twelfth resistor, and one end of the twenty-fourth capacitor. The other ends of the twenty-first capacitor and the twenty-second capacitor are both grounded. The other ends of the eleventh resistor and the twelfth resistor are both connected to the seventh gate bias voltage. The drain of the thirteenth transistor is respectively connected to the other end of the twenty-fourth capacitor, one end of the twenty-fifth capacitor, one end of the seventh inductor, and one end of the thirteenth resistor. The drain of the fourteenth transistor is respectively connected to the other end of the twenty-third capacitor, one end of the twenty-sixth capacitor, one end of the eighth inductor, and one end of the fourteenth resistor. The other ends of the twenty-fifth capacitor and the twenty-sixth capacitor are both connected to the signal input terminal of the harmonic control module. The other ends of the seventh inductor and the eighth inductor are both connected to the power supply voltage. The other end of the thirteenth resistor is connected to one end of the twenty-seventh capacitor. The other end of the twenty-seventh capacitor is connected to the gate of the seventh transistor. The other end of the fourteenth resistor is connected to one end of the twenty-eighth capacitor. The other end of the twenty-eighth capacitor is connected to the other end of the tenth capacitor.;
[0011] As a definition: The harmonic control module includes a first harmonic control circuit and a second harmonic control circuit. Each harmonic control circuit includes a twenty-ninth capacitor, a thirtieth capacitor, a thirty-first capacitor, a thirty-second capacitor, a thirty-third capacitor, a thirty-fourth capacitor, a thirty-fifth capacitor, a thirty-sixth capacitor, a tenth inductor, an eleventh inductor, a twelfth inductor, and a thirteenth inductor. One end of the twenty-ninth capacitor and one end of the thirtieth capacitor are both connected to the signal output end of the stacked power amplifier module. The other end of the twenty-ninth capacitor is respectively connected to one end of the tenth inductor, one end of the thirty-third capacitor, and one end of the twelfth inductor. The other end of the tenth inductor is connected to one end of the thirty-first capacitor. The other end of the thirty-first capacitor is grounded. The other end of the thirty-third capacitor is respectively connected to the other end of the twelfth inductor and one end of the thirty-fifth capacitor. The other end of the thirty-fifth capacitor is connected to the signal input end of the power combining module. The other end of the thirtieth capacitor is respectively connected to one end of the eleventh inductor, one end of the thirty-fourth capacitor, and one end of the thirteenth inductor. The other end of the eleventh inductor is connected to one end of the thirty-second capacitor. The other end of the thirty-second capacitor is grounded. The other end of the thirty-fourth capacitor is respectively connected to the other end of the thirteenth inductor and one end of the thirty-sixth capacitor. The other end of the thirty-sixth capacitor is connected to the signal input end of the power combining module.
[0012] As a further definition: The power combining module is a spatial power combining antenna structure, which includes a first transmission line, a fifth transmission line, a seventh transmission line, a ninth transmission line, an eleventh transmission line, and a third transmission line connected in sequence, and a second transmission line, a sixth transmission line, an eighth transmission line, a tenth transmission line, a twelfth transmission line, and a fourth transmission line connected in sequence, jointly forming a differential antenna structure. The ports of the first transmission line, the second transmission line, the third transmission line, and the fourth transmission line serve as the signal input ends of the power combining module to receive the signals output from the signal output end of the harmonic control module. The first transmission line, the second transmission line, the third transmission line, and the fourth transmission line are impedance-matched with the output impedance of the harmonic control module. The sum of the lengths of the fifth transmission line and the seventh transmission line is a half wavelength. The sum of the lengths of the ninth transmission line and the eleventh transmission line is a half wavelength. The sum of the lengths of the sixth transmission line and the eighth transmission line is a half wavelength. The sum of the lengths of the fourth transmission line and the twelfth transmission line is a half wavelength.
[0013] Due to the adoption of the above solution, the beneficial effects obtained by the present utility model compared with the prior art are as follows:
[0014] A high-power and high-efficiency millimeter-wave power amplifier based on CMOS technology provided by the present utility model, by setting an input balun module, a driver amplifier module, a stacked power amplifier module, a harmonic control module and a power combining module connected in sequence. The input balun module converts two-way signals into four-way differential signals, and realizes signal amplification and isolation between the front and rear stages through the driver amplifier module. The amplified signal increases the power supply voltage through the stacked power amplifier module, thereby increasing the saturated output power of the power amplifier. Compared with the traditional transformer power combining method, it saves a certain chip area, and a feedback network is introduced at the input and output ends of the stacked power amplifier to improve the problem of poor output standing wave of the stacked power amplifier. Then, the harmonic control module shapes the drain voltage and current waveforms of the stacked power amplifier module, thereby increasing the power added efficiency of the power amplifier. The four-way differential signals after passing through the harmonic control module are combined in power through the power combining module. By adopting a spatial power combining antenna structure for power combination, the power signals are combined in space and radiated and transmitted in space, avoiding the loss introduced by the traditional transformer power combiner during combination, and capable of increasing the saturated output power and power added efficiency of the power amplifier.
[0015] The present utility model is applicable to millimeter-wave power amplification. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The present utility model will be further described in detail below with reference to the drawings and specific embodiments.
[0017] Figure 1 is a schematic block diagram of a high-power and high-efficiency millimeter-wave power amplifier based on CMOS technology according to an embodiment of the present utility model;
[0018] Figure 2 is the layout of the input balun according to an embodiment of the present utility model;
[0019] Figure 3 is the circuit diagram of the driver amplifier according to an embodiment of the present utility model;
[0020] Figure 4 is the circuit diagram of the stacked power amplifier according to an embodiment of the present utility model;
[0021] Figure 5 is the circuit diagram of the harmonic control circuit according to an embodiment of the present utility model;
[0022] Figure 6 is a schematic diagram of the spatial power combining antenna structure according to an embodiment of the present utility model;
[0023] In the figure: 1. Input balun module; 2. Driver amplifier module; 3. Stacked power amplifier module; 4. Harmonic control module; 5. Power combining module. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0024] The present utility model will be further described below in conjunction with embodiments. However, those skilled in the art should understand that the present utility model is not limited to the following embodiments. Any improvements and equivalent changes made on the basis of the specific embodiments of the present utility model are within the scope of protection of the claims of the present utility model.
[0025] Embodiment: A high-power and high-efficiency millimeter-wave power amplifier based on CMOS process
[0026] A high-power and high-efficiency millimeter-wave power amplifier based on CMOS process, the principle block diagram of which is as Figure 1 shown, includes an input balun module 1, a driver amplifier module 2, a stacked power amplifier module 3, a harmonic control module 4 and a power combining module 5. The signal output end of the input balun is connected to the signal input end of the driver amplifier, the signal output end of the driver amplifier is connected to the signal input end of the stacked power amplifier, the signal output end of the stacked power amplifier is connected to the signal input end of the harmonic control module 4, and the signal output end of the harmonic control module 4 is connected to the signal input end of the power combiner. The two-way signal is converted into a four-way differential signal by the input balun module 1, and the signal is amplified and isolated between the front and rear stages through the driver amplifier module 2. The amplified signal passes through the stacked power amplifier module 3 and the harmonic control module 4, and the four-way differential signal after passing through the harmonic control module 4 realizes the power combination of the signal through the power combining module 5.
[0027] The input balun module 1 includes a first input balun and a second input balun with the same structure. Each input balun includes an input coil and an output coil. The layout of the first input balun in this embodiment is as Figure 2 shown. An open-circuit transmission line Lopen is provided in the input coil to improve the amplitude imbalance and phase imbalance of the balun; the input coil includes two signal input ends, one signal input end INN is used to input an external single-ended signal, and the other signal input end INP is open-circuited. The output coil includes two signal output ends OUTP and OUTN for outputting differential signals; the OUTP signal output end and the OUTN signal output end of the first input balun, and the OUTP signal output end and the OUTN signal output end of the second input balun are respectively connected to the four signal input ends of the driver amplifier module 2.
[0028] The driver amplifier module 2 includes a first driver amplifier and a second driver amplifier with the same structure. Each driver amplifier includes a first-stage amplifier and a second-stage amplifier. The first-stage amplifier is a common-source structure amplifier. The first-stage amplifier includes a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, a first transistor M1, a second transistor M2, a third capacitor C dr1 and a fourth capacitor C dr2; The second-stage amplifier is a cascode amplifier, and the second-stage amplifier includes a third transistor M3, a fourth transistor M4, a fifth capacitor C dr3 , a sixth capacitor C dr4 , a fifth transistor M5, a sixth transistor M6, a third resistor R3, a fourth resistor R4, a second transformer TF2, a seventh capacitor C3, and an eighth capacitor C4; The inter-stage matching between the first-stage amplifier and the second-stage amplifier is completed by connecting the first transformer TF1. The circuit diagram of the first driving amplifier in this embodiment is as shown in Figure 3 . One end of the first capacitor C1 is the INP1 signal input terminal of the first driving amplifier, and one end of the second capacitor C2 is the INN1 signal input terminal of the first driving amplifier. Both the first capacitor C1 and the second capacitor C2 are DC-blocking capacitors. The other end of the first capacitor C1 is respectively connected to one end of the first resistor R1, the gate of the first transistor M1, and one end of the third capacitor C dr1 . The other end of the second capacitor C2 is respectively connected to one end of the second resistor R2, the gate of the second transistor M2, and one end of the fourth capacitor C dr2 . The other ends of the first resistor R1 and the second resistor R2 are commonly connected to the first gate bias voltage VG1. The sources of the first transistor M1 and the second transistor M2 are commonly grounded. The drain of the first transistor M1 is respectively connected to the other end of the fourth capacitor C dr2 and one end of the primary coil of the first transformer TF1. The drain of the second transistor M2 is respectively connected to the other end of the third capacitor C dr1 and the other end of the primary coil of the first transformer TF1. The center tap of the primary coil of the first transformer TF1 is connected to the first DC bias voltage VDD1. Both the third capacitor C dr1 and the fourth capacitor C dr2 are neutralizing capacitors, which are used to improve the stability and gain of the first-stage amplifier; One end of the secondary coil of the first transformer TF1 is respectively connected to one end of the fifth capacitor C dr3 and the gate of the third transistor M3. The other end of the secondary coil of the first transformer TF1 is respectively connected to one end of the sixth capacitor C dr4 and the gate of the fourth transistor M4. The center tap of the secondary coil of the first transformer TF1 is connected to the second gate bias voltage VG2. The sources of the third transistor M3 and the fourth transistor M4 are commonly grounded. The drain of the third transistor M3 is respectively connected to the other end of the sixth capacitor C dr4 and the source of the fifth transistor M5. The drain of the fourth transistor M4 is respectively connected to the other end of the fifth capacitor C dr3 and the source of the sixth transistor M6. The fifth capacitor C dr3 and the sixth capacitor C dr4The neutralizing capacitor for improving the stability of the second-stage amplifier, the gate of the fifth transistor M5 is connected to one end of the third resistor R3, the gate of the sixth transistor M6 is connected to one end of the fourth resistor R4, the other ends of the third resistor R3 and the fourth resistor R4 are commonly connected to the third gate bias voltage VG3, the drain of the fifth transistor M5 is connected to one end of the primary coil of the second transformer TF2, the drain of the sixth transistor M6 is connected to the other end of the primary coil of the second transformer TF2, the center tap of the primary coil of the second transformer TF2 is connected to the second DC bias voltage VDD2, one end of the secondary coil of the second transformer TF2 is connected to one end of the seventh capacitor C3, the other end of the secondary coil of the second transformer TF2 is connected to one end of the eighth capacitor C4, the second transformer TF2 is used to complete the inter-stage matching between the front and rear stages in the circuit, the other end of the seventh capacitor C3 is the OUTP1 signal output terminal of the first driver amplifier, the other end of the eighth capacitor C4 is the OUTN1 signal output terminal of the first driver amplifier, and both the seventh capacitor C3 and the eighth capacitor C4 are DC-blocking capacitors. The INP1 signal input terminal and the INN1 signal input terminal of the first driver amplifier, and the INP1 signal input terminal and the INN1 signal input terminal of the second driver amplifier are respectively connected to the four signal output terminals of the input balun module 1, and the OUTP1 signal output terminal and the OUTN1 signal output terminal of the first driver amplifier, and the OUTP1 signal output terminal and the OUTN1 signal output terminal of the second driver amplifier are respectively connected to the four signal input terminals of the stacked power amplifier module 3.
[0029] The stacked power amplifier module 3 includes a first stacked power amplifier and a second stacked power amplifier with the same structure. Each stacked power amplifier includes a plurality of stacked transistor units connected in series. Inductors are connected between adjacent stacked transistor units. The signal input end of the first-layer stacked transistor unit is connected to the signal output end of the drive amplifier module 2. The last-layer stacked transistor unit is connected with an output matching circuit. The signal output end of the output matching circuit is connected to the signal input end of the harmonic control module 4. A feedback network is introduced between the first-layer stacked transistor unit and the output matching circuit, which improves the problem of poor output standing wave of the stacked power amplifier. Each stacked power amplifier includes four layers of stacked transistor units. The first-layer stacked transistor unit includes a ninth capacitor C5, a tenth capacitor C6, a seventh transistor M7, an eighth transistor M8, a fifth resistor R5, a sixth resistor R6, an eleventh capacitor CP1, and a twelfth capacitor CP2; the second-layer stacked transistor unit includes a thirteenth capacitor C7, a fourteenth capacitor C8, a ninth transistor M9, a tenth transistor M10, a seventh resistor R7, an eighth resistor R8, a fifteenth capacitor CP3, and a sixteenth capacitor CP4; the third-layer stacked transistor unit includes a seventeenth capacitor C9, an eighteenth capacitor C10, an eleventh transistor M11, a twelfth transistor M12, a ninth resistor R9, a tenth resistor R10, a nineteenth capacitor CP5, and a twentieth capacitor CP6; the fourth-layer stacked transistor unit includes a twenty-first capacitor C11, a twenty-second capacitor C12, a thirteenth transistor M13, a fourteenth transistor M14, an eleventh resistor R11, a twelfth resistor R12, a twenty-third capacitor CP7, and a twenty-fourth capacitor CP8; the output matching circuit includes a seventh inductor L7, an eighth inductor L8, a twenty-fifth capacitor C13, and a twenty-sixth capacitor C14; the feedback network includes a thirteenth resistor R F1 , a fourteenth resistor R F2 , a twenty-seventh capacitor C F1 and a twenty-eighth capacitor C F2 ; the stacked power amplifier further includes a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a fifth inductor L5, a sixth inductor L6, a seventh inductor L7, an eighth inductor L8, and a ninth inductor Ls. The circuit diagram of the first stacked power amplifier in this embodiment is as shown in Figure 4As shown, the sources of the seventh transistor M7 and the eighth transistor M8 are commonly connected to one end of the ninth inductor Ls, the other end of the ninth inductor Ls is grounded, and the ninth inductor Ls is used to improve the stability of the stacked power amplifier and improve the input standing wave. The gate of the seventh transistor M7 is respectively connected to one end of the ninth capacitor C5, one end of the fifth resistor R5, and one end of the eleventh capacitor CP1. The gate of the eighth transistor M8 is respectively connected to one end of the tenth capacitor C6, one end of the sixth resistor R6, and one end of the twelfth capacitor CP2. The other end of the ninth capacitor C5 is the INC1 signal input terminal of the first stacked power amplifier, and the other end of the tenth capacitor C6 is the IND1 signal input terminal of the first stacked power amplifier. Both the ninth capacitor C5 and the tenth capacitor C6 are DC-blocking capacitors. The other ends of the fifth resistor R5 and the sixth resistor R6 are both connected to the fourth gate bias voltage VG4. The drain of the seventh transistor M7 is respectively connected to the other end of the twelfth capacitor CP2 and one end of the first inductor L1. The drain of the eighth transistor M8 is respectively connected to the other end of the eleventh capacitor CP1 and one end of the second inductor L2. The eleventh capacitor CP1 and the twelfth capacitor CP2 are used to improve the stability and gain of the first-layer stacked transistor unit. The other end of the first inductor L1 is connected to the source of the ninth transistor M9, and the other end of the second inductor L2 is connected to the source of the tenth transistor M10. The first inductor L1 and the second inductor L2 complete the inter-stage matching between the first-layer stacked transistor unit and the second-layer stacked transistor unit; The gate of the ninth transistor M9 is respectively connected to one end of the thirteenth capacitor C7, one end of the seventh resistor R7, and one end of the fifteenth capacitor CP3. The gate of the tenth transistor M10 is respectively connected to one end of the fourteenth capacitor C8, one end of the eighth resistor R8, and one end of the sixteenth capacitor CP4. The other ends of the thirteenth capacitor C7 and the fourteenth capacitor C8 are both grounded. The thirteenth capacitor C7 and the fourteenth capacitor C8 are bypass capacitors of the second-layer stacked transistor unit. The other ends of the seventh resistor R7 and the eighth resistor R8 are both connected to the fifth gate bias voltage VG5. The drain of the ninth transistor M9 is respectively connected to the other end of the sixteenth capacitor CP4 and one end of the third inductor L3. The drain of the tenth transistor M10 is respectively connected to the other end of the fifteenth capacitor CP3 and one end of the fourth inductor L4. The fifteenth capacitor CP3 and the sixteenth capacitor CP4 are used to improve the stability and gain of the second-layer stacked transistor unit. The other end of the third inductor L3 is connected to the source of the eleventh transistor M11, and the other end of the fourth inductor L4 is connected to the source of the twelfth transistor M12. The third inductor L3 and the fourth inductor L4 complete the inter-stage matching between the second-layer stacked transistor unit and the third-layer stacked transistor unit;The gate of the eleventh transistor M11 is connected to one end of the seventeenth capacitor C9, one end of the ninth resistor R9, and one end of the nineteenth capacitor CP5 respectively. The gate of the twelfth transistor M12 is connected to one end of the eighteenth capacitor C10, one end of the tenth resistor R10, and one end of the twentieth capacitor CP6 respectively. The other ends of the seventeenth capacitor C9 and the eighteenth capacitor C10 are both grounded. The seventeenth capacitor C9 and the eighteenth capacitor C10 are bypass capacitors of the third-layer stacked transistor unit. The other ends of the ninth resistor R9 and the tenth resistor R10 are both connected to the sixth gate bias voltage VG6. The drain of the eleventh transistor M11 is connected to the other end of the twentieth capacitor CP6 and one end of the fifth inductor L5 respectively. The drain of the twelfth transistor M12 is connected to the other end of the nineteenth capacitor CP5 and one end of the sixth inductor L6 respectively. The nineteenth capacitor CP5 and the twentieth capacitor CP6 are used to improve the stability and gain of the third-layer stacked transistor unit. The other end of the fifth inductor L5 is connected to the source of the thirteenth transistor M13. The other end of the sixth inductor L6 is connected to the source of the fourteenth transistor M14. The fifth inductor L5 and the sixth inductor L6 complete the inter-stage matching between the third-layer stacked transistor unit and the fourth-layer stacked transistor unit. The gate of the thirteenth transistor M13 is connected to one end of the twenty-first capacitor C11, one end of the eleventh resistor R11, and one end of the twenty-third capacitor CP7 respectively. The gate of the fourteenth transistor M14 is connected to one end of the twenty-second capacitor C12, one end of the twelfth resistor R12, and one end of the twenty-fourth capacitor CP8 respectively. The other ends of the twenty-first capacitor C11 and the twenty-second capacitor C12 are both grounded. The twenty-first capacitor C11 and the twenty-second capacitor C12 are bypass capacitors of the fourth-layer stacked transistor unit. The other ends of the eleventh resistor R11 and the twelfth resistor R12 are both connected to the seventh gate bias voltage VG7. The drain of the thirteenth transistor M13 is connected to the other end of the twenty-fourth capacitor CP8, one end of the twenty-fifth capacitor C13, one end of the seventh inductor L7, and one end of the thirteenth resistor R; F1 The other end of the fourteenth transistor M14 is connected to the other end of the twenty-third capacitor CP7, one end of the twenty-sixth capacitor C14, one end of the eighth inductor L8, and one end of the fourteenth resistor R F2 respectively. The twenty-third capacitor CP7 and the twenty-fourth capacitor CP8 are used to improve the stability and gain of the fourth-layer stacked transistor unit. The other end of the twenty-fifth capacitor C13 is the OUTC1 signal output terminal of the first stacked power amplifier. The other end of the twenty-sixth capacitor C14 is the OUTD1 signal output terminal of the first stacked power amplifier. The other ends of the seventh inductor L7 and the eighth inductor L8 are both connected to the power supply voltage VDD. The seventh inductor L7, the eighth inductor L8, the twenty-fifth capacitor C13, and the twenty-sixth capacitor C14 complete the output matching. The other end of the thirteenth resistor R F1 is connected to the twenty-seventh capacitor CF1 is connected to one end, and the twenty-seventh capacitor C F1 The other end is connected to the gate of the seventh transistor M7, and the fourteenth resistor R F2 The other end is connected to one end of the twenty-eighth capacitor C F2 is connected to one end, and the twenty-eighth capacitor C F2 The other end is connected to the other end of the tenth capacitor C6. The INC1 signal input terminal and the IND1 signal input terminal of the first stacked power amplifier, and the INC1 signal input terminal and the IND1 signal input terminal of the second stacked power amplifier are respectively connected to the four signal output terminals of the drive amplifier module 2; the OUTC1 signal output terminal and the OUTD1 signal output terminal of the first stacked power amplifier, and the OUTC1 signal output terminal and the OUTD1 signal output terminal of the second stacked power amplifier are respectively connected to the four signal input terminals of the harmonic control module 4. The stacked power amplifier improves the power supply voltage by stacking transistors, increases the saturation output power of the power amplifier, and compared with the power synthesis method of transformers, the transistors can save a certain amount of chip area; a feedback network is introduced at the input and output ends of the stacked power amplifier to improve the problem of poor output standing wave of the stacked power amplifier.
[0030] The harmonic control module 4 includes a first harmonic control circuit and a second harmonic control circuit. Each harmonic control circuit includes a twenty-ninth capacitor C15, a thirtieth capacitor C16, a thirty-first capacitor C17, a thirty-second capacitor C18, a thirty-third capacitor C19, a thirty-fourth capacitor C20, a thirty-fifth capacitor C21, a thirty-sixth capacitor C22, a tenth inductor L9, an eleventh inductor L10, a twelfth inductor L11, and a thirteenth inductor L12. The circuit diagram of the first harmonic control circuit in this embodiment is as Figure 5As shown, one end of the twenty-ninth capacitor C15 is the input terminal of the INE1 signal of the first harmonic control circuit, and one end of the thirtieth capacitor C16 is the input terminal of the INF1 signal of the first harmonic control circuit. The other end of the twenty-ninth capacitor C15 is connected to one end of the tenth inductor L9, one end of the thirty-third capacitor C19, and one end of the twelfth inductor L11 respectively. The other end of the tenth inductor L9 is connected to one end of the thirty-first capacitor C17, and the other end of the thirty-first capacitor C17 is grounded. The other end of the thirty-third capacitor C19 is connected to the other end of the twelfth inductor L11 and one end of the thirty-fifth capacitor C21 respectively, and the other end of the thirty-fifth capacitor C21 is the output terminal of the OUTE1 signal of the first harmonic control circuit. The other end of the thirtieth capacitor C16 is connected to one end of the eleventh inductor L10, one end of the thirty-fourth capacitor C20, and one end of the thirteenth inductor L12 respectively. The other end of the eleventh inductor L10 is connected to one end of the thirty-second capacitor C18, and the other end of the thirty-second capacitor C18 is grounded. The other end of the thirty-fourth capacitor C20 is connected to the other end of the thirteenth inductor L12 and one end of the thirty-sixth capacitor C22 respectively, and the other end of the thirty-sixth capacitor C22 is the output terminal of the OUTF1 signal of the first harmonic control circuit. The input terminals of the INE1 signal and INF1 signal of the first harmonic control circuit, and the input terminals of the INE1 signal and INF1 signal of the second harmonic control circuit are respectively connected to the four signal output terminals of the stacked power amplifier module 3; the output terminals of the OUTE1 signal and OUTF1 signal of the first harmonic control circuit, and the output terminals of the OUTE1 signal and OUTF1 signal of the second harmonic control circuit are respectively connected to the four signal input terminals of the power combining module 5. The tenth inductor L9 and the thirty-first capacitor C17 are short-circuited at the second harmonic, the eleventh inductor L10 and the thirty-second capacitor C18 are short-circuited at the second harmonic, the twelfth inductor L11 and the thirty-third capacitor C19 have an infinite impedance at the third harmonic, and the thirteenth inductor L12 and the thirty-fourth inductor have an infinite impedance at the third harmonic; the functions of the twenty-ninth capacitor C15, the thirtieth capacitor C16, the thirty-fifth capacitor C21, and the thirty-sixth capacitor C22 are on the one hand to block DC and pass AC, and on the other hand to adjust the harmonic impedance of the harmonic control circuit. The harmonic control circuit, as a part of the output matching of the stacked power amplifier, is used to shape the drain terminal voltage and current waveforms of the stacked power amplifier, thereby improving the power added efficiency. By optimizing the harmonic network parameters, the optimal load impedance can be obtained at the fundamental frequency, short-circuited at the second harmonic, and the impedance is infinite at the third harmonic, so as to realize the shaping of the drain voltage and drain current waveforms of the stacked power amplifier, and thus improve the power added efficiency of the power amplifier.
[0031] The power combining module 5 is a spatial power combining antenna structure, including a first transmission line TL1, a fifth transmission line TL5, a seventh transmission line TL7, a ninth transmission line TL9, an eleventh transmission line TL11, and a third transmission line TL3 connected in sequence, and a second transmission line TL2, a sixth transmission line TL6, an eighth transmission line TL8, a tenth transmission line TL10, a twelfth transmission line TL12, and a fourth transmission line TL4 connected in sequence, jointly constituting a differential antenna structure. The spatial power combining antenna structure of this embodiment is as Figure 6 shown. The OUT1 port of the first transmission line TL1, the OUT2 port of the second transmission line TL2, the OUT3 port of the third transmission line TL3, and the OUT4 port of the fourth transmission line TL4 are used as the four signal input ends of the power combining module 5, respectively receiving the signals output from the four signal output ends of the harmonic control module 4. The first transmission line TL1, the second transmission line TL2, the third transmission line TL3, and the fourth transmission line TL4 are impedance-matched with the output impedance of the harmonic control module 4. The sum of the lengths of the fifth transmission line TL5 and the seventh transmission line TL7 is half a wavelength, the sum of the lengths of the ninth transmission line TL9 and the eleventh transmission line TL11 is half a wavelength, the sum of the lengths of the sixth transmission line TL6 and the eighth transmission line TL8 is half a wavelength, and the sum of the lengths of the fourth transmission line TL4 and the twelfth transmission line TL12 is half a wavelength. Through the spatial power combining antenna structure for power combining, the power signals are combined in space and radiated and transmitted in space, avoiding the losses introduced in the combination by the traditional transformer power combiner, and capable of improving the saturated output power and power added efficiency of the power amplifier.
Claims
1. A high-power and high-efficiency millimeter-wave power amplifier based on CMOS technology, characterized in that: It includes an input balun module, a driving amplifier module, a stacked power amplifier module, a harmonic control module and a power synthesis module. The signal output end of the input balun is connected to the signal input end of the driving amplifier, the signal output end of the driving amplifier is connected to the signal input end of the stacked power amplifier, the signal output end of the stacked power amplifier is connected to the signal input end of the harmonic control module, and the signal output end of the harmonic control module is connected to the signal input end of the power synthesizer.
2. The high-power and high-efficiency millimeter-wave power amplifier based on CMOS technology according to claim 1, characterized in that: The input balun module includes a first input balun and a second input balun with the same structure. Each input balun includes an input coil and an output coil. An open transmission line is provided in the input coil. The input coil includes two signal input terminals, one signal input terminal is used to input an external single-ended signal, and the other signal input terminal is open; the output coil includes two signal output terminals for outputting differential signals, and the signal output terminal of the output coil is connected to the signal input terminal of the driving amplifier module.
3. A high-power and high-efficiency millimeter-wave power amplifier based on CMOS technology according to claim 1 or 2, characterized in that: The driving amplifier module includes a first driving amplifier and a second driving amplifier with the same structure. Each driving amplifier includes a first-stage amplifier and a second-stage amplifier. The first-stage amplifier is a common-source structure amplifier, and the second-stage amplifier is a common-source and common-gate structure amplifier. The first-stage amplifier and the second-stage amplifier are connected by connecting a first transformer to achieve inter-stage matching; the signal input end of the first-stage amplifier is connected to the signal output end of the input balun module, and the signal output end of the second-stage amplifier is connected to the signal input end of the stacked power amplifier module.
4. The high-power and high-efficiency millimeter-wave power amplifier based on CMOS technology according to claim 3, characterized in that: The first-stage amplifier includes a first capacitor, a second capacitor, a first resistor, a second resistor, a first transistor, a second transistor, a third capacitor and a fourth capacitor; the second-stage amplifier includes a third transistor, a fourth transistor, a fifth capacitor, a sixth capacitor, a fifth transistor, a sixth transistor, a third resistor, a fourth resistor, a second transformer, a seventh capacitor and an eighth capacitor; one end of the first capacitor and one end of the second capacitor are both connected to the signal output end of the input balun module, the other end of the first capacitor is respectively connected to one end of the first resistor, the gate of the first transistor and one end of the third capacitor, the other end of the second capacitor is respectively connected to one end of the second resistor, the gate of the second transistor and one end of the fourth capacitor, the other end of the first resistor and the other end of the second resistor are commonly connected to the first gate bias voltage, the source of the first transistor and the source of the second transistor are commonly grounded, the drain of the first transistor is respectively connected to the other end of the fourth capacitor and one end of the primary coil of the first transformer, the drain of the second transistor is respectively connected to the other end of the third capacitor and the other end of the primary coil of the first transformer, and the center tap of the primary coil of the first transformer is connected to the first DC bias voltage; one end of the secondary coil of the first transformer is respectively The first transformer is connected to one end of the fifth capacitor and the gate of the third transistor, the other end of the first transformer secondary coil is respectively connected to one end of the sixth capacitor and the gate of the fourth transistor, the center tap of the first transformer secondary coil is connected to the second gate bias voltage, the source of the third transistor and the source of the fourth transistor are commonly grounded, the drain of the third transistor is respectively connected to the other end of the sixth capacitor and the source of the fifth transistor, the drain of the fourth transistor is respectively connected to the other end of the fifth capacitor and the source of the sixth transistor, the gate of the fifth transistor is connected to one end of the third resistor, the gate of the sixth transistor is connected to one end of the fourth resistor, the other end of the third resistor and the other end of the fourth resistor are commonly connected to the third gate bias voltage, the drain of the fifth transistor is connected to one end of the second transformer primary coil, the drain of the sixth transistor is connected to the other end of the second transformer primary coil, the center tap of the second transformer primary coil is connected to the second DC bias voltage, one end of the second transformer secondary coil is connected to one end of the seventh capacitor, the other end of the second transformer secondary coil is connected to one end of the eighth capacitor, and the other end of the seventh capacitor and the other end of the eighth capacitor are both connected to the signal input end of the stacked power amplifier module.
5. A high-power and high-efficiency millimeter-wave power amplifier based on CMOS technology according to any one of claims 1, 2 and 4, characterized in that: The stacked power amplifier module includes a first stacked power amplifier and a second stacked power amplifier with the same structure. Each stacked power amplifier includes multiple layers of stacked transistor units connected in series. An inductor is connected between adjacent layers of stacked transistor units. The signal input end of the first layer of stacked transistor units is connected to the signal output end of the driving amplifier module. The last layer of stacked transistor units is connected to an output matching circuit. The signal output end of the output matching circuit is connected to the signal input end of the harmonic control module. A feedback network is introduced between the first layer of stacked transistor units and the output matching circuit.
6. The high-power and high-efficiency millimeter-wave power amplifier based on CMOS technology according to claim 5, characterized in that: Each stacked power amplifier includes four layers of stacked transistor units, the first layer of stacked transistor units includes a ninth capacitor, a tenth capacitor, a seventh transistor, an eighth transistor, a fifth resistor, a sixth resistor, an eleventh capacitor and a twelfth capacitor; the second layer of stacked transistor units includes a thirteenth capacitor, a fourteenth capacitor, a ninth transistor, a tenth transistor, a seventh resistor, an eighth resistor, a fifteenth capacitor and a sixteenth capacitor; the third layer of stacked transistor units includes a seventeenth capacitor, an eighteenth capacitor, an eleventh transistor, a twelfth transistor, a ninth resistor, a tenth resistor, a nineteenth capacitor and a twentieth capacitor; the fourth layer of stacked transistor units includes a twenty-first capacitor, a twenty-second capacitor , a thirteenth transistor, a fourteenth transistor, an eleventh resistor, a twelfth resistor, a twenty-third capacitor and a twenty-fourth capacitor; the output matching circuit includes a seventh inductor, an eighth inductor, a twenty-fifth capacitor and a twenty-sixth capacitor; the feedback network includes a thirteenth resistor, a fourteenth resistor, a twenty-seventh capacitor and a twenty-eighth capacitor; the stacked power amplifier also includes a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor, a sixth inductor, a seventh inductor, an eighth inductor and a ninth inductor; the sources of the seventh transistor and the eighth transistor are commonly connected to one end of the ninth inductor, the other end of the ninth inductor is grounded, and the gate of the seventh transistor is respectively connected to one end of the ninth capacitor, the fifth resistor and the sixth inductor. One end of the transistor is connected to one end of the eleventh capacitor, the gate of the eighth transistor is respectively connected to one end of the tenth capacitor, one end of the sixth resistor and one end of the twelfth capacitor, the other end of the ninth capacitor and the other end of the tenth capacitor are both connected to the signal output end of the driving amplifier module, the other ends of the fifth resistor and the sixth resistor are both connected to the fourth gate bias voltage, the drain of the seventh transistor is respectively connected to the other end of the twelfth capacitor and one end of the first inductor, the drain of the eighth transistor is respectively connected to the other end of the eleventh capacitor and one end of the second inductor, the other end of the first inductor is connected to the source of the ninth transistor, and the other end of the second inductor is connected to the source of the tenth transistor; the gate of the ninth transistor are respectively connected to one end of a thirteenth capacitor, one end of a seventh resistor and one end of a fifteenth capacitor, the gate of the tenth transistor is respectively connected to one end of a fourteenth capacitor, one end of an eighth resistor and one end of a sixteenth capacitor, the other end of the thirteenth capacitor and the other end of the fourteenth capacitor are both grounded, the other ends of the seventh resistor and the eighth resistor are both connected to a fifth gate bias voltage, the drain of the ninth transistor is respectively connected to the other end of the sixteenth capacitor and one end of the third inductor, the drain of the tenth transistor is respectively connected to the other end of the fifteenth capacitor and one end of the fourth inductor, the other end of the third inductor is connected to the source of the eleventh transistor, and the other end of the fourth inductor is connected to the source of the twelfth transistor;The gate of the eleventh transistor is connected to one end of the seventeenth capacitor, one end of the ninth resistor and one end of the nineteenth capacitor respectively, the gate of the twelfth transistor is connected to one end of the eighteenth capacitor, one end of the tenth resistor and one end of the twentieth capacitor respectively, the other end of the seventeenth capacitor and the other end of the eighteenth capacitor are grounded, the other ends of the ninth resistor and the tenth resistor are connected to the sixth gate bias voltage, the drain of the eleventh transistor is connected to the other end of the twentieth capacitor and one end of the fifth inductor respectively, the drain of the twelfth transistor is connected to the other end of the nineteenth capacitor and one end of the sixth inductor respectively, the other end of the fifth inductor is connected to the source of the thirteenth transistor, and the other end of the sixth inductor is connected to the source of the fourteenth transistor; the gate of the thirteenth transistor is connected to one end of the twenty-first capacitor, one end of the eleventh resistor and one end of the twenty-third capacitor respectively, the gate of the fourteenth transistor is connected to one end of the twenty-second capacitor, one end of the twelfth resistor and the twenty-fourth transistor respectively. The other end of the 21st capacitor and the other end of the 22nd capacitor are both grounded, the other ends of the 11th resistor and the 12th resistor are both connected to the seventh gate bias voltage, the drain of the 13th transistor is respectively connected to the other end of the 24th capacitor, one end of the 25th capacitor, one end of the seventh inductor and one end of the 13th resistor, the drain of the 14th transistor is respectively connected to the other end of the 23rd capacitor, one end of the 26th capacitor, one end of the eighth inductor and one end of the 14th resistor, the other end of the 25th capacitor and the other end of the 26th capacitor are both connected to the signal input end of the harmonic control module, the other end of the seventh inductor and the other end of the eighth inductor are both connected to the power supply voltage, the other end of the 13th resistor is connected to one end of the 27th capacitor, the other end of the 27th capacitor is connected to the gate of the seventh transistor, the other end of the 14th resistor is connected to one end of the 28th capacitor, and the other end of the 28th capacitor is connected to the other end of the tenth capacitor. ; 7. A high-power and high-efficiency millimeter-wave power amplifier based on CMOS technology according to any one of claims 1, 2, 4, and 6, characterized in that: The harmonic control module includes a first harmonic control circuit and a second harmonic control circuit, each of which includes a twenty-ninth capacitor, a thirtieth capacitor, a thirty-first capacitor, a thirty-second capacitor, a thirty-third capacitor, a thirty-fourth capacitor, a thirty-fifth capacitor, a thirty-sixth capacitor, a tenth inductor, an eleventh inductor, a twelfth inductor and a thirteenth inductor; one end of the twenty-ninth capacitor and one end of the thirtieth capacitor are both connected to the signal output end of the stacked power amplifier module, the other end of the twenty-ninth capacitor is respectively connected to one end of the tenth inductor, one end of the thirty-third capacitor and one end of the twelfth inductor, and the other end of the tenth inductor is connected to one end of the thirty-first capacitor. The other end of the thirty-first capacitor is connected to ground, the other end of the thirty-third capacitor is respectively connected to the other end of the twelfth inductor and one end of the thirty-fifth capacitor, and the other end of the thirty-fifth capacitor is connected to the signal input end of the power synthesis module; the other end of the thirtieth capacitor is respectively connected to one end of the eleventh inductor, one end of the thirty-fourth capacitor and one end of the thirteenth inductor, the other end of the eleventh inductor is connected to one end of the thirty-second capacitor, the other end of the thirty-second capacitor is grounded, the other end of the thirty-fourth capacitor is respectively connected to the other end of the thirteenth inductor and one end of the thirty-sixth capacitor, and the other end of the thirty-sixth capacitor is connected to the signal input end of the power synthesis module.
8. The high-power and high-efficiency millimeter-wave power amplifier based on CMOS technology according to claim 7, characterized in that: The power synthesis module is a spatial power synthesis antenna structure, including a first transmission line, a fifth transmission line, a seventh transmission line, a ninth transmission line, an eleventh transmission line and a third transmission line connected in sequence, and a second transmission line, a sixth transmission line, an eighth transmission line, a tenth transmission line, a twelfth transmission line and a fourth transmission line connected in sequence, which together constitute a differential antenna structure; the ports of the first transmission line, the second transmission line, the third transmission line and the fourth transmission line serve as signal input ends of the power synthesis module to receive signals output by a signal output end of the harmonic control module, the first transmission line, the second transmission line, the third transmission line and the fourth transmission line are matched with the output impedance of the harmonic control module, the sum of the lengths of the fifth transmission line and the seventh transmission line is one-half wavelength, the sum of the lengths of the ninth transmission line and the eleventh transmission line is one-half wavelength, the sum of the lengths of the sixth transmission line and the eighth transmission line is one-half wavelength, and the sum of the lengths of the fourth transmission line and the twelfth transmission line is one-half wavelength.