All-digital memory operation CMOS circuit based on ferroelectric transistor

Abstract

The invention designs and provides a plurality of all-digital in-memory computing circuits based on ferroelectric transistors, and belongs to the field of integrated circuits. According to the invention, a plurality of all-digital in-memory computing circuits based on ferroelectric transistors are designed, weight data can be stored in the computing circuits to carry out all Boolean logic operations based on FEFET logic gate structures, and the all-digital in-memory computing circuit has important significance for breaking through a memory wall and a power consumption wall of a Von. Noiemann architecture. According to the FEFET in-memory calculation unit provided by the invention, relatively fixed weight data can be stored in a calculation circuit, so that the repeated transmission of the weight data is reduced, and the power consumption can be greatly reduced; meanwhile, due to full-digital calculation, multi-bit calculation precision cannot be sacrificed, the accuracy can be effectively improved, and the method is a potential technology applied to an artificial intelligence chip and an AI neural network.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of integrated circuits, and relates to a full-digital in-memory computing CMOS circuit based on ferroelectric transistors. BACKGROUND

[0002] Traditional computing architectures are built on the 75-year-old von Neumann model, which includes physically separate processing units (CPUs / GPUs) and memory units (DRAM / SRAM). This separation forces data to constantly shuttle between processing and memory units, creating the “memory wall,” where data movement consumes 60-70% of system energy in AI workloads, and data access latency can be 100x higher than computation itself. This bottleneck further diminishes the efficiency of data-intensive tasks as artificial intelligence model sizes increase.

[0003] In-memory computing is a new type of computing architecture that can perform computations directly on the memory array where the data resides instead of moving the data to an external processor for computation, which eliminates data migration. This is achieved by reconfiguring the memory unit to perform logical operations or analog computations. However, analog in-memory computing architectures are susceptible to precision degradation caused by noise or variations in memristor devices. This precision degradation is particularly evident when performing multi-bit computations. Moreover, current mainstream analog in-memory computing systems contain a large number of digital-to-analog converters (DACs) and analog-to-digital converters (ADCs), which will occupy a large amount of power consumption and chip area of the in-memory computing system.

[0004] To solve the problem of analog in-memory computing systems, various CMOS ferroelectric field effect transistor (FEFET) digital logic circuits are designed in this paper. FEFET digital logic circuits do not require any ADC and DAC, simplifying the in-memory computing system architecture and reducing system power consumption. FEFET has ultra-low read-write power consumption and unique read-write separation characteristics of three-terminal devices, making it a promising emerging technology that can be applied to the next generation of in-memory computing architectures. Unlike traditional charge-based memory devices, FEFET utilizes the inherent polarization switch of ferroelectric material integrated into the transistor gate stack to achieve non-volatile data storage. The core of the FEFET in-memory computing circuit lies in the ability to modulate transistor channel conductivity through the residual polarization state of the ferroelectric layer. Binary data (“0” / “1”) is stored in a stable up / down polarization direction, which is converted into different FEFET threshold voltages. Therefore, FEFET can also be used as a non-volatile digital switch in digital circuits. SUMMARY

[0005] The application designs and proposes a full-digital memory computing unit architecture based on a ferroelectric transistor (FEFET), and gives a design and a design method of a FEFET-based NAND, NOR, AND and OR logic gate, and simulates and verifies functions and timing of the logic gate.

[0006] In order to realize high-precision in-memory operation, the application designs a full-digital in-memory computing unit based on a FEFET, wherein a structure diagram of a FEFET-based NOR gate is as shown in Figure 1 The NOR gate includes two ferroelectric transistors, one PMOS and one NMOS. The pull-up network is composed of a PMOS and a ferroelectric transistor in series, and the ferroelectric transistor stores weight data B. The pull-down network is composed of an NMOS and a ferroelectric transistor in parallel, and the ferroelectric transistor stores weight data The FEFET NOR gate CMOS digital circuit has two modes of weight loading mode and calculation mode. In the weight loading mode, the weight vector B is written into the two ferroelectric transistors through the Vb1 and Vb2 ports, wherein when writing data "1", the Vb1 voltage is Vw and the Vb2 voltage is -Vw; when writing data "0", the Vb1 voltage is -Vw and the Vb2 voltage is Vw, and the range of Vw is greater than the coercive voltage (Vc) of the ferroelectric capacitor and less than the breakdown voltage Vbr of the ferroelectric capacitor, that is, Vc < Vw < Vbr. In the calculation mode, the input value A is input through the port A, and then the readout voltage Vr is configured at the Vb1 and Vb2 ports for calculation, and the range of Vr is 0mV-VDD.

[0007] In order to realize high-precision in-memory operation, the application designs a full-digital in-memory computing unit based on a FEFET, wherein a structure diagram of a FEFET-based AND gate is as shown in Figure 2 The AND gate includes two ferroelectric transistors, one PMOS and one NMOS. The pull-up network is composed of a PMOS and a ferroelectric transistor in parallel, and the ferroelectric transistor stores weight data B. The pull-down network is composed of an NMOS and a ferroelectric transistor in series, and the ferroelectric transistor stores weight data The FEFET AND gate CMOS digital circuit has two modes of weight loading mode and calculation mode. In the weight loading mode, the weight vector B is written into the two ferroelectric transistors through the Vb1 and Vb2 ports, wherein when writing data "1", the Vb1 voltage is Vw and the Vb2 voltage is -Vw; when writing data "0", the Vb1 voltage is -Vw and the Vb2 voltage is Vw, and the range of Vw is greater than the coercive voltage (Vc) of the ferroelectric capacitor and less than the breakdown voltage Vbr of the ferroelectric capacitor, that is, Vc < Vw < Vbr. In the calculation mode, the input value A is input through the port A, and then the readout voltage Vr is configured at the Vb1 and Vb2 ports for calculation, and the range of Vr is 0mV-VDD.

[0008] To achieve high-precision in-memory computing, the present invention designs a fully digital in-memory computing unit based on FEFET. The schematic diagram of the OR gate structure based on FEFET is as Figure 3 shown. This OR gate consists of a FEFET NOR gate in series with a CMOS inverter at the output node. Therefore, its pull-up network and pull-down network are the same as those of the FEFET NOR gate. The FEFET OR gate CMOS digital circuit has two modes: weight loading mode and computing mode. In the weight loading mode, the weight vector B is written into two ferroelectric transistors through the Vb1 and Vb2 ports respectively. When writing data "1", the voltage of Vb1 is Vw and the voltage of Vb2 is -Vw; when writing data "0", the voltage of Vb1 is -Vw and the voltage of Vb2 is Vw. The range of Vw is greater than the coercive voltage (Vc) of the ferroelectric capacitor and less than the breakdown voltage Vbr of the ferroelectric capacitor, that is, Vc < Vw < Vbr. In the computing mode, the input value A is input through port A, and then the read voltage Vr is configured at the Vb1 and Vb2 ports for computing. The range of Vr is 0mV - VDD.

[0009] To achieve high-precision in-memory computing, the present invention designs a fully digital in-memory computing unit based on FEFET. The schematic diagram of the AND gate structure based on FEFET is as Figure 4 shown. This AND gate consists of a FEFET NAND gate in series with a CMOS inverter at the output node. Therefore, its pull-up network and pull-down network are the same as those of the FEFET NAND gate. The FEFET AND gate CMOS digital circuit has two modes: weight loading mode and computing mode. In the weight loading mode, the weight vector B is written into two ferroelectric transistors through the Vb1 and Vb2 ports respectively. When writing data "1", the voltage of Vb1 is Vw and the voltage of Vb2 is -Vw; when writing data "0", the voltage of Vb1 is -Vw and the voltage of Vb2 is Vw. The range of Vw is greater than the coercive voltage (Vc) of the ferroelectric capacitor and less than the breakdown voltage Vbr of the ferroelectric capacitor, that is, Vc < Vw < Vbr. In the computing mode, the input value A is input through port A, and then the read voltage Vr is configured at the Vb1 and Vb2 ports for computing. The range of Vr is 0mV - VDD.

[0010] To achieve multi-bit high-precision in-memory computing, the present invention designs a multi-bit fully digital in-memory computing unit based on FEFET. The schematic diagram of the 3-bit NOR gate structure based on FEFET is as Figure 5 shown. This NOR gate contains four ferroelectric transistors, one PMOS and one NMOS. Among them, the pull-up network consists of one PMOS and two ferroelectric transistors in series. These two ferroelectric transistors store the weight data B and the weight data C respectively. The pull-down network consists of one NMOS and two ferroelectric transistors in parallel. These two ferroelectric transistors store the weight data and the weight data The FEFET 3-bit NOR gate CMOS digital circuit has two modes of weight loading mode and calculation mode. In the weight loading mode, the weight vector B is written into two ferroelectric transistors through the Vb1 and Vb2 ports respectively, wherein when writing data "1", the Vb1 voltage is Vw and the Vb2 voltage is -Vw; when writing data "0", the Vb1 voltage is -Vw and the Vb2 voltage is Vw, and the range of Vw is greater than the coercive voltage (Vc) of the ferroelectric capacitor and less than the breakdown voltage Vbr of the ferroelectric capacitor, that is, Vc < Vw < Vbr. The weight vector C is written into two ferroelectric transistors through the Vc1 and Vc2 ports respectively, wherein when writing data "1", the Vc1 voltage is Vw and the Vc2 voltage is -Vw; when writing data "0", the Vc1 voltage is -Vw and the Vc2 voltage is Vw, and the range of Vw is greater than the coercive voltage (Vc) of the ferroelectric capacitor and less than the breakdown voltage Vbr of the ferroelectric capacitor, that is, Vc < Vw < Vbr. In the calculation mode, the input value A is input through the port A, and then the readout voltage Vr of the Vb1, Vb2, Vc1 and Vc2 ports is configured for calculation, and the range of Vr is 0mV-VDD.

[0011] In order to realize the in-memory operation of multiple bits with high precision, the application designs a multi-bit all-digital in-memory calculation unit based on FEFET, wherein the structure diagram of the 3-bit NOR gate based on FEFET is as shown in the figure. Figure 6 The NOR gate includes four ferroelectric transistors, one PMOS and one NMOS. Among them, the pull-up network is composed of one PMOS and two ferroelectric transistors in parallel, and the two ferroelectric transistors store weight data B and weight data C respectively. The pull-down network is composed of one NMOS and two ferroelectric transistors in series, and the two ferroelectric transistors store weight data and weight data The FEFET 3-bit NAND CMOS digital circuit has two modes of weight loading mode and calculation mode. In the weight loading mode, the weight vector B is written into the two ferroelectric transistors through the Vb1 and Vb2 ports respectively, wherein when writing data "1", the Vb1 voltage is Vw and the Vb2 voltage is -Vw; when writing data "0", the Vb1 voltage is -Vw and the Vb2 voltage is Vw, and the range of Vw is greater than the coercive voltage (Vc) of the ferroelectric capacitor and less than the breakdown voltage Vbr of the ferroelectric capacitor, that is, Vc < Vw < Vbr. The weight vector C is written into the two ferroelectric transistors through the Vc1 and Vc2 ports respectively, wherein when writing data "1", the Vc1 voltage is Vw and the Vc2 voltage is -Vw; when writing data "0", the Vc1 voltage is -Vw and the Vc2 voltage is Vw, and the range of Vw is greater than the coercive voltage (Vc) of the ferroelectric capacitor and less than the breakdown voltage Vbr of the ferroelectric capacitor, that is, Vc < Vw < Vbr. In the calculation mode, the input value A is input through the port A, and then the readout voltage Vr of the Vb1, Vb2, Vc1 and Vc2 ports is configured for calculation, and the range of Vr is 0mV-VDD.

[0012] The above structure can realize three basic operations of AND, OR and NOT, and on this basis, all Boolean logic operations including AND, OR, XNOR and XOR can be realized.

[0013] The present application has the following beneficial effects:

[0014] The present application designs and proposes a full-digital in-memory computing unit based on FEFET, which can realize all Boolean logic operations. The FEFET full-digital in-memory computing unit proposed by the present application can store relatively fixed weight data in the calculation circuit, reducing the repeated transmission of weight data and saving a large amount of power consumption; at the same time, since it is a full-digital calculation, the multi-bit calculation accuracy is not sacrificed, and the correctness can be effectively improved, which is a very potential technology applied to artificial intelligence chips and AI neural networks. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a structure schematic diagram of realizing FEFET NAND gate.

[0016] Figure 2 is a structure schematic diagram of realizing FEFET NAND gate.

[0017] Figure 3 is a structure schematic diagram of realizing FEFET OR gate.

[0018] Figure 4 is a structure schematic diagram of realizing FEFET AND gate.

[0019] Figure 5 is a structure schematic diagram of realizing 3-bit FEFET NAND gate.

[0020] Figure 6 is a structure diagram of implementing 3-bit FEFET NOR gate.

[0021] Figure 7 is a simulation result waveform diagram of embodiment one.

[0022] Figure 8 is a simulation result waveform diagram of embodiment two.

[0023] Figure 9 is a simulation result waveform diagram of embodiment three.

[0024] Figure 10 is a simulation result waveform diagram of embodiment four.

[0025] Figure 11 is a simulation result waveform diagram of embodiment five.

[0026] Figure 12 is a simulation result waveform diagram of embodiment six. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical scheme and advantages of the present application more clear, the beneficial effects of the present application will be further described by six specific embodiments:

[0028] Embodiment one:

[0029] The logic operation of full input is carried out in the FEFET NOR gate. The operation result simulation waveform is as shown in Figure 7 .

[0030] The specific operation process is as follows: first, in the weight loading mode, the data "0" is written into the two ferroelectric transistors by applying-2.5V and 2.5V voltages to the ports Vb1 and Vb2 respectively. In the weight loading mode, the A port maintains VDD to close the PMOS. Then enter the calculation mode, the A port inputs data "0" (GND) and data "1" (VDD) respectively, the Vb1 and Vb2 set the bias voltage 600mV, and the calculation of "0" NOR "0" and "1" NOR "0" is carried out, and the calculation results "0" NOR "0" = 1 and "1" NOR "0" = 0 are obtained. After the calculation is completed, the circuit enters the weight loading mode. The input voltages of the Vb1 and Vb2 ports are 2.5V and-2.5V respectively, and the weight data "1" is written into the two ferroelectric transistors. Then enter the calculation mode, the A port inputs data "0" (GND) and data "1" (VDD) respectively, the Vb1 and Vb2 set the bias voltage 600mV, and the calculation of "0" NOR "1" and "1" NOR "1" is carried out, and the calculation results "0" NOR "1" = 0 and "1" NOR "1" = 0 are obtained.

[0031] Embodiment two:

[0032] The logic operation of all inputs is performed in the FEFET and the NOR gate. The simulation waveform of the operation result is shown in Figure 8

[0033] The specific operation process is as follows: first, in the weight loading mode, the data "0" is written into the two ferroelectric transistors by applying -2.5V and 2.5V voltages to the ports Vb1 and Vb2 respectively. In the weight loading mode, the A port maintains VDD to close the PMOS. Then enter the calculation mode, the A port inputs data "0" (GND) and data "1" (VDD) respectively, the bias voltage of Vb1 is set to 50mV, and the bias voltage of Vb2 is set to 200mV, to perform the calculation of "0" NAND "0" and "1" NAND "0", and the calculation results are "0" NAND "0" = 1 and "1" NAND "0" = 1. After the calculation is completed, the circuit enters the weight loading mode. The input voltages of the ports Vb1 and Vb2 are 2.5V and -2.5V respectively, and the weight data "1" is written into the two ferroelectric transistors. Then enter the calculation mode, the A port inputs data "0" (GND) and data "1" (VDD) respectively, the bias voltage of Vb1 is set to 50mV, and the bias voltage of Vb2 is set to 200mV, to perform the calculation of "0" NAND "1" and "1" NAND "1", and the calculation results are "0" NAND "1" = 1 and "1" NAND "1" = 0.

[0034] Example Three

[0035] The logic operation of all inputs is performed in the FEFET and the NOR gate. The simulation waveform of the operation result is shown in Figure 9

[0036] The specific operation process is as follows: first, in the weight loading mode, the data "0" is written into the two ferroelectric transistors by applying -2.5V and 2.5V voltages to the ports Vb1 and Vb2 respectively. In the weight loading mode, the A port maintains VDD to close the PMOS. Then enter the calculation mode, the A port inputs data "0" (GND) and data "1" (VDD) respectively, the bias voltage of Vb1 is set to 50mV, and the bias voltage of Vb2 is set to 200mV, to perform the calculation of "0" NAND "0" and "1" NAND "0", and the calculation results are "0" NAND "0" = 1 and "1" NAND "0" = 1. After the calculation is completed, the circuit enters the weight loading mode. The input voltages of the ports Vb1 and Vb2 are 2.5V and -2.5V respectively, and the weight data "1" is written into the two ferroelectric transistors. Then enter the calculation mode, the A port inputs data "0" (GND) and data "1" (VDD) respectively, the bias voltage of Vb1 is set to 50mV, and the bias voltage of Vb2 is set to 200mV, to perform the calculation of "0" NAND "1" and "1" NAND "1", and the calculation results are "0" NAND "1" = 1 and "1" NAND "1" = 0.​​

[0037] Example Four:

[0038] Full input logic operation is performed in the FEFET AND gate. The operation result simulation waveform is shown in Figure 10

[0039] The specific operation process is as follows: first, in the weight loading mode, data "0" is written into the two ferroelectric transistors by applying -2.5V and 2.5V voltages to the ports Vb1 and Vb2 respectively. In the weight loading mode, the A port maintains VDD to close the PMOS. Then enter the calculation mode, the A port inputs data "0" (GND) and data "1" (VDD) respectively, the Vb1 bias voltage is set to 50mV, and the Vb2 bias voltage is set to 200mV, to perform "0" AND "0" and "1" AND "0" calculation, and get the calculation results "0" AND "0" = 0 and "1" AND "0" = 0. After calculation, the circuit enters the weight loading mode. The input voltages of the Vb1 and Vb2 ports are 2.5V and -2.5V respectively, and the weight data "1" is written into the two ferroelectric transistors. Then enter the calculation mode, the A port inputs data "0" (GND) and data "1" (VDD) respectively, the Vb1 bias voltage is set to 50mV, and the Vb2 bias voltage is set to 200mV, to calculate "0" AND "1" and "1" AND "1", and get the calculation results "0" AND "1" = 0 and "1" AND "1" = 0.

[0040] Example Five:

[0041] Full input logic operation is performed in the 3-bit FEFET NOR gate. The operation result simulation waveform is shown in Figure 11

[0042] The specific operation process is as follows: first, update the data B and C stored in the four ferroelectric transistors in the weight loading mode, and then input the vector A in the calculation mode (in the calculation mode, the Vb1, Vb2, Vc1 and Vc2 ports are configured with a bias voltage of 600mV). All eight different logic input conditions are simulated. Only when the input is A = 0, B = 0, C = 0, the output is "1". In all other input conditions, the output is "0".

[0043] Example Six:

[0044] Full input logic operation is performed in the 3-bit FEFET NOR gate. The operation result simulation waveform is shown in Figure 12

[0045] ​​​The specific operation process is: first, update the data B and C stored in the four ferroelectric transistors in the weight loading mode, and then input the vector A in the calculation mode (in the calculation mode, 50mV voltage is configured at the Vb1 and Vc1 ports, and 200mV bias voltage is configured at the Vb2 and Vc2 ports). All eight different logic input conditions are simulated. Only when the input is A=1, B=1, C=1, the output is "0". In all other input conditions, the output is "1".

[0046] The above-described embodiments only express the implementation manners of the present application, but cannot be understood as the limitation to the scope of the patent of the present application. It should be noted that, for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which all belong to the protection scope of the present application.

Claims

1. A ferroelectric transistor (FEFET) based NOR gate CMOS circuit, characterized in that, Comprise two ferroelectric transistors, one PMOS and one NMOS. Among them, the pull-up network is composed of a PMOS and a ferroelectric transistor in series, and the ferroelectric transistor stores weight data B. The pull-down network is composed of an NMOS and a ferroelectric transistor in parallel, and the ferroelectric transistor stores weight data 2. A ferroelectric transistor (FEFET) based NAND CMOS circuit according to claim 1, wherein, Weight loading mode, the range of write voltage Vw is greater than the coercive voltage (Vc) of ferroelectric capacitor and less than the breakdown voltage Vbr of ferroelectric capacitor, i.e. Vc < Vw < Vbr. The bias voltage range of Vb1 and Vb2 in the calculation mode is 0mV-VDD.

3. A ferroelectric transistor (FEFET) based NAND CMOS circuit, comprising: The ferroelectric transistor contains two ferroelectric transistors, one PMOS and one NMOS. Among them, the pull-up network is composed of a PMOS and a ferroelectric transistor in parallel, and the ferroelectric transistor stores weight data B. The pull-down network is composed of an NMOS and a ferroelectric transistor in series, and the ferroelectric transistor stores weight data B 4. A ferroelectric transistor (FEFET) based NAND gate CMOS circuit according to claim 3, wherein, Weight loading mode, the range of write voltage Vw is greater than the coercive voltage (Vc) of ferroelectric capacitor and less than the breakdown voltage Vbr of ferroelectric capacitor, i.e. Vc < Vw < Vbr. The bias voltage range of Vb1 and Vb2 in the calculation mode is 0mV-VDD.

5. A ferroelectric transistor (FEFET) based OR gate CMOS circuit, characterized in that, The output node is composed of a FEFET NOR gate in series with a CMOS inverter, whose pull-up network and pull-down network are the same as the FEFET NOR gate.

6. A ferroelectric transistor (FEFET) based OR CMOS circuit as claimed in claim 5, wherein, Weight loading mode, the range of write voltage Vw is greater than the coercive voltage (Vc) of ferroelectric capacitor and less than the breakdown voltage Vbr of ferroelectric capacitor, i.e. Vc < Vw < Vbr. The bias voltage range of Vb1 and Vb2 in the calculation mode is 0mV-VDD.

7. A ferroelectric transistor (FEFET) based AND CMOS circuit, characterized in that, The output node is composed of a FEFET NOR gate in series with a CMOS inverter, whose pull-up network and pull-down network are the same as the FEFET NOR gate.

8. A ferroelectric transistor (FEFET) based AND CMOS circuit according to claim 7, wherein, Weight loading mode, the range of write voltage Vw is greater than the coercive voltage (Vc) of ferroelectric capacitor and less than the breakdown voltage Vbr of ferroelectric capacitor, i.e. Vc < Vw < Vbr. The bias voltage range of Vb1 and Vb2 in the calculation mode is 0mV-VDD.

9. A 3-bit NOR gate CMOS circuit based on ferroelectric transistor (FEFET), characterized in that, Comprise four ferroelectric transistors, a PMOS and an NMOS. Among them, the pull-up network is composed of a PMOS and two ferroelectric transistors in series, and the two ferroelectric transistors store weight data B and weight data C respectively. The pull-down network is composed of an NMOS and two ferroelectric transistors in parallel, and the two ferroelectric transistors store weight data and weight data 10. A 3-bit NOR gate CMOS circuit based on ferroelectric transistor (FEFET) as claimed in claim 9, wherein, Weight loading mode, the range of write voltage Vw is greater than the coercive voltage (Vc) of ferroelectric capacitor and less than the breakdown voltage Vbr of ferroelectric capacitor, i.e. Vc < Vw < Vbr. The bias voltage range of Vb1, Vb2, Vc1 and Vc2 ports in the calculation mode is 0mV-VDD.

11. A ferroelectric transistor (FEFET) based 3-bit NAND CMOS circuit, comprising: Comprise four ferroelectric transistors, a PMOS and an NMOS. Among them, the pull-up network is composed of a PMOS and two ferroelectric transistors in parallel, and the two ferroelectric transistors store weight data B and weight data C respectively. The pull-down network is composed of an NMOS and two ferroelectric transistors in series, and the two ferroelectric transistors store weight data and weight data 12. A 3-bit NAND gate CMOS circuit based on ferroelectric transistor (FEFET) as claimed in claim 11, wherein, Weight loading mode, the range of write voltage Vw is greater than the coercive voltage (Vc) of ferroelectric capacitor and less than the breakdown voltage Vbr of ferroelectric capacitor, i.e. Vc < Vw < Vbr. The bias voltage range of Vb1, Vb2, Vc1 and Vc2 ports in the calculation mode is 0mV-VDD. Weight loading mode, the range of write voltage Vw is greater than the coercive voltage (Vc) of ferroelectric capacitor and less than the breakdown voltage Vbr of ferroelectric capacitor, i.e. Vc < Vw < Vbr. The bias voltage range of Vb1, Vb2, Vc1 and Vc2 ports in the calculation mode is 0mV-VDD.

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