Linear gain adjusting circuit for CMOS image sensor chip

Abstract

The invention provides a linear gain adjusting circuit for a CMOS image sensor chip. The linear gain adjusting circuit is provided with a current source array, a signal output end, a gain resistor array and a trimming resistor array. The signal output end is connected with the current source array circuit; the gain resistor array is connected with the current source array circuit, the gain resistor array is connected with the signal output end in parallel, the trimming resistor array is connected with the current source array circuit, and the trimming resistor array is connected with the gain resistor array in parallel; wherein the gain resistor array is used for carrying out amplitude gain on the voltage of the signal output end according to the total resistance value and the variable total current of the gain resistor array, so that the signal output end outputs a voltage signal with a slope change property; the trimming resistor array is used for simulating the resistance value linear variation degree of the gain resistor array and carrying out nonlinear offset adjustment on the total resistance value according to the resistance value linear variation degree, so that the nonlinear influence of the gain resistor array can be counteracted in the actual gain process, and the gain precision is improved.

Description

Technical Field

[0001] This application relates to the field of CMOS image sensor chip design, and particularly to a linear gain adjustment circuit for a CMOS image sensor chip. Background Art

[0002] Single slope type column ADC (SS-ADC) is widely used in high-speed CMOS image sensors. The SS-ADC structure is suitable for column ADC integration, has low power consumption and is easy to implement correlated double sampling (CDS), and can achieve a balance between chip performance and area cost. The basic principle of SS-ADC is to connect the reference ramp voltage and the pixel photosensitive voltage of the CMOS image chip to the two input terminals of the comparator respectively. The ramp changes monotonically under the control of a high-speed clock, gradually approaching the pixel photosensitive voltage until the comparator flips, and outputs a 1-bit decision result. This decision result is used to control the counter to count: at the beginning of the comparison (when the reference ramp starts to change monotonically), the counter starts to count; when the comparator decision flips, the counter stops counting. At this time, the count value stored in the counter is the quantization result of the corresponding pixel photosensitive voltage.

[0003] In fact, the gain adjustment circuit is necessary in the practical application of CMOS image sensors: in a low-light environment, the difference in pixel photosensitive voltage is small. Using a gain adjustment circuit that outputs a large-slope ramp voltage will cause the comparator to finish the decision quickly. On the one hand, this will result in too small a count result for each column ADC. On the other hand, it will result in little or no difference in the count values between different regions. Eventually, the image has low brightness, low contrast, and lacks details. When using a gain adjustment circuit that outputs a small-slope ramp voltage, since the ramp changes slowly, the comparator decision result is delayed, and the counter can count more data. The image brightness is increased, and the subtle differences between different columns can also be reflected in the count values.

[0004] In the prior art, to improve the gain accuracy of the gain adjustment circuit, the number of control bits needs to be increased. For any gain adjustment array, a larger area and multiple resistor units are required, which increases the mismatch between resistor units and exacerbates the array gradient difference. In the actual gain process, there are slight differences in each resistor unit, resulting in inconsistent changes in the slope of the overall output ramp. DNL and INL are not 0, which further introduces non-linearity into the ramp gain of the gain adjustment circuit and reduces the gain accuracy. Summary of the Invention

[0005] The main purpose of the embodiments of the present application is to propose a linear gain adjustment circuit for a CMOS image sensor chip, which can offset the influence of non-linearity between resistance units during the actual gain process, thereby improving the gain accuracy of the gain adjustment circuit.

[0006] To achieve the above object, a first aspect of the embodiments of the present application proposes a linear gain adjustment circuit for a CMOS image sensor chip, including: A current source array, the current source array includes a plurality of bit-by-bit controllable current source units, and the current source units are connected in parallel with each other. The current source array is used to output a variable total current; A signal output terminal, the signal output terminal is connected to the current source array circuit; A gain resistor array, the gain resistor array is connected to the current source array circuit, and the gain resistor array is connected in parallel with the signal output terminal. The gain resistor array includes a plurality of resistor units, and the resistor units are connected in parallel with each other; A trimming resistor array, the trimming resistor array is connected to the current source array circuit, and the trimming resistor array is connected in parallel with the gain resistor array; Among them, the gain resistor array is used to perform amplitude gain on the voltage of the signal output terminal according to the total resistance value and the variable total current collected by each resistor unit in the conducting state, so that the signal output terminal outputs a voltage signal with a ramp change property; The trimming resistor array is used to simulate the linear change degree of the resistance value of the gain resistor array, and perform non-linear offset trimming on the total resistance value according to the linear change degree of the resistance value, so that the voltage gain of the gain resistor array for the signal output terminal is stably in the linear region.

[0007] Further, in some embodiments, the linear gain adjustment circuit further includes: A gain resistor decoding controller, the gain resistor decoding controller is connected to the gain resistor array circuit; A trimming resistor decoding controller, the trimming resistor decoding controller is connected to the trimming resistor array circuit; Among them, the gain resistor decoding controller is used to receive a resistor array control signal, and output a constant voltage high level to each resistor unit according to the resistor array control signal, so that the resistor unit is in the conducting state; The trimming resistor decoding controller is used to receive a resistor array control signal, and dynamically simulate the linear change degree of the resistance value of the gain resistor array according to the resistor array control signal.

[0008] Further, in some embodiments, the linear gain adjustment circuit further includes: Gain signal input terminal, the gain signal input terminal is connected to the gain resistor decoding controller circuit, the gain signal input terminal is connected to the trimming resistor decoding controller circuit, and the gain resistor decoding controller is connected in parallel with the trimming resistor decoding controller; Current source signal input terminal, the current source signal input terminal is connected to the current source array circuit; Among them, the gain signal input terminal is used to transmit resistor array control signals to the gain resistor decoding controller and the trimming resistor decoding controller respectively; The current source signal input terminal is used to input a current source array control signal to the current source array, so that the current source array controls the opening and closing of each current source unit bit by bit according to the current source array control signal to output a variable total current.

[0009] Furthermore, in some embodiments, the resistor array control signal includes a resistor set / reset control signal, a resistor strobe enable signal, and a clock control signal; The current source array control signal includes a current source set / reset control signal, a current source strobe enable signal, and a clock control signal.

[0010] Furthermore, in some embodiments, the first input terminal of the resistor unit is connected to the current source array circuit, the second input terminal of the resistor unit is connected to the gain resistor decoding controller circuit, and the output terminal of the resistor unit is grounded; Among them, the resistor unit is internally provided with a resistor and a MOS switch. The first pole of the MOS switch is connected to one end of the resistor in circuit. The other end of the resistor is used as the first input terminal of the resistor unit. The second pole of the MOS switch is used as the output terminal of the resistor unit. The third pole of the MOS switch is used as the second input terminal of the resistor unit, and the third pole of the MOS switch is the gate.

[0011] Furthermore, in some embodiments, the linear gain adjustment circuit further includes a current source global bias generator, the current source global bias generator is connected to the current source array circuit, and the current source global bias generator is used to transmit a global bias signal to the current source array, so that the current source array controls each current source unit to output the same current according to the global bias signal.

[0012] The embodiments of the first aspect of the present application have the following beneficial effects: Through the collaborative design of the gain resistor array and the trimming resistor array, the present application realizes the generation of a ramp voltage signal with high linearity and high stability at the signal output end. Among them, the parallel structure of the gain resistor array is used to dynamically adjust the total resistance value, and the variable total current of the current source array is combined to flexibly control the amplitude gain; at the same time, the trimming resistor array actively compensates for the non-linear offset by real-time simulating the linear change degree of the resistance value of the gain resistor, effectively suppressing the gain non-linearity problem caused by the discreteness of resistor units, temperature drift or process deviation; moreover, the dual-array parallel architecture not only retains the programmable characteristics of the resistor network, but also significantly improves the overall linearity of the system through the closed-loop trimming mechanism, which is particularly suitable for fields with strict requirements for the linearity of ramp signals, such as high-precision digital-to-analog conversion and power management chips. This structure improves the signal quality while reducing the calibration complexity and increasing the gain accuracy of the gain adjustment circuit.

[0013] To achieve the above object, a second aspect of the embodiments of the present application proposes a linear gain adjustment circuit for a CMOS image sensor chip, including: A current source array, which includes a plurality of bit-by-bit controllable current source units, and the current source units are connected in parallel with each other. The current source array is used to output a variable total current; A signal output end, which is circuit-connected to the current source array; A gain resistor array, which is circuit-connected to the current source array, and is connected in parallel between the gain resistor array and the signal output end. The gain resistor array includes a plurality of resistor units, and the resistor units are connected in parallel with each other; A gain resistor decoding controller, which is circuit-connected to the gain resistor array; A DAC converter, which is circuit-connected to the gain resistor decoding controller; Among them, the gain resistor array is used to perform amplitude gain on the voltage of the signal output end according to the total resistance value and the variable total current collected by each resistor unit in the conducting state, so that the signal output end outputs a voltage signal with a ramp change property; The gain resistor decoding controller is used to receive the resistor array control signal and output a constant high level to each resistor unit according to the resistor array control signal, so that the resistor unit is in the conducting state; The DAC converter is used to adjust the voltage value of the high level output by the gain resistor decoding controller according to the resistor array control signal, so as to adjust the number of conducting states of the resistor units in the case of non-linear resistance offset, so that the voltage gain of the gain resistor array to the signal output end is stably in the linear region.

[0014] Further, in some embodiments, the linear gain adjustment circuit further includes: Gain signal input terminal, the gain signal input terminal is respectively connected to a gain resistor decoding controller and a DAC converter circuit; Current source signal input terminal, the current source signal input terminal is connected to a current source array circuit; The gain signal input terminal is used to transmit resistor array control signals to the gain resistor decoding controller and the DAC converter respectively; The current source signal input terminal is used to input a current source array control signal to the current source array, so that the current source array controls the on / off of each current source unit bit by bit according to the current source array control signal to output a variable total current; Among them, the resistor array control signal includes a resistor set / reset control signal, a resistor strobe enable signal, and a clock control signal; the current source array control signal includes a current source set / reset control signal, a current source strobe enable signal, and a clock control signal.

[0015] Further, in some embodiments, the linear gain adjustment circuit further includes a current source global bias generator, the current source global bias generator is connected to the current source array circuit, and the current source global bias generator is used to transmit a global bias signal to the current source array, so that the current source array controls each current source unit to output the same current according to the global bias signal.

[0016] Further, in some embodiments, the first input terminal of the resistor unit is connected to the current source array circuit, the second input terminal of the resistor unit is connected to the gain resistor decoding controller circuit, and the output terminal of the resistor unit is grounded; Among them, the resistor unit is internally provided with a resistor and a MOS switch. The first pole of the MOS switch is connected in series with one end of the resistor. The other end of the resistor is used as the first input terminal of the resistor unit. The second pole of the MOS switch is used as the output terminal of the resistor unit. The third pole of the MOS switch is used as the second input terminal of the resistor unit, and the third pole of the MOS switch is the gate.

[0017] In the embodiments of the second aspect of the present application, the following beneficial effects are achieved: Through the multi-level collaborative control of the gain resistor array, the decoding controller, and the DAC converter, high-precision non-linear compensation and dynamic linearization adjustment are realized in the linear gain adjustment circuit. Among them, the DAC converter actively adjusts the high-level voltage output by the decoding controller based on the gain control signal. By changing the conduction threshold of the resistor unit, it adaptively compensates for the non-linear offset of the resistor unit, significantly improving the overall linearity of the gain resistor array. Then, the gain resistor decoding controller realizes the full conduction control of the resistor unit through constant voltage driving. Combining with the voltage fine-tuning mechanism of the DAC converter, it can dynamically optimize the conduction resistance distribution without changing the physical layout, enhancing the robustness of the system to process deviations and environmental interference. Moreover, by integrating the traditional analog trimming function with the digital control logic, the calibration process is simplified through the digital interface of the DAC converter, reducing the complexity of the external compensation circuit, while improving the resolution and stability of the ramp signal. As a result, the linear gain adjustment circuit combines the advantages of high linearity output, low power consumption, and process compatibility, providing an efficient solution for the ramp precision signal generation of CMOS image sensor chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is the overall structure diagram of the linear gain adjustment circuit for a CMOS image sensor chip provided by some embodiments of the present application; Figure 2 is the overall structure diagram of the resistor unit provided by some other embodiments of the present application; Figure 3 is the overall structure diagram of the linear gain adjustment circuit for a CMOS image sensor chip provided by some other embodiments of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] In order to make the objectives, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0020] In the description of the present application, it should be understood that the orientation or positional relationship indicated by terms such as up, down, front, back, left, right, etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application.

[0021] It should also be noted that in the description of this application, the meaning of "several" is more than one, the meaning of "multiple" is more than two, "greater than", "less than", "exceeding", etc. are understood as not including the base number, and "above", "below", "within", etc. are understood as including the base number. If the first and second are described, it is only for the purpose of distinguishing technical features and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence of the indicated technical features.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0023] In the description of this application, the descriptions with reference to terms such as "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0024] Single slope type column ADC (SS-ADC) is widely used in high-speed CMOS image sensors. The SS-ADC structure is suitable for column ADC integration, has low power consumption and is easy to implement correlated double sampling (CDS), and can balance chip performance and area cost. The basic principle of SS-ADC is to connect the reference ramp voltage and the pixel photosensitive voltage of the CMOS image chip to the two input terminals of the comparator respectively. The ramp changes monotonically under the control of a high-speed clock, gradually approaching the pixel photosensitive voltage until the comparator flips and outputs a 1-bit decision result. This decision result is used to control the counter to count: at the start of the comparison (when the reference ramp starts to change monotonically), the counter starts to count; when the comparator decision flips, the counter stops counting. At this time, the count value stored in the counter is the quantization result of the corresponding pixel photosensitive voltage.

[0025] When reading out pixel information in a column SS-ADC, it follows row-by-row gating and column parallel reading: when row gating, all columns share a global reference ramp signal to compare and count the pixel signals. The speed of the monotonic change of the reference ramp signal, that is, the ramp slope, determines the time when the comparator flips. For the same pixel photosensitive voltage, different counting results will be obtained using reference ramps with different slopes. Defining the change in the slope of the ramp as gain adjustment, a large slope corresponds to low gain, and a low slope corresponds to high gain. In fact, a gain adjustment circuit is necessary in the practical application of a CMOS image sensor: in a low-light environment, the voltage difference of the pixel photosensitive voltage is small. Using a gain adjustment circuit that outputs a ramp voltage with a large slope will cause the comparator to finish the judgment quickly. On the one hand, this will result in too small counting results for each column ADC. On the other hand, it will result in little or no difference in the count values between different regions. Eventually, the image will have low brightness, low contrast, and missing details. When switching to a gain adjustment circuit that outputs a ramp voltage with a small slope, since the ramp changes slowly, the comparator judgment result is delayed, and the counter can record more data. The image brightness is increased, and the subtle differences between different columns can also be reflected in the count values. This is also the reason why a large slope corresponds to low gain and a small slope corresponds to high gain. A small slope increases the count value of the counter and the image brightness, which is equivalent to an increase in the amplification ability of the readout circuit for the photosensitive signal, that is, an increase in gain.

[0026] Since the photosensitive environment is changing, the gain needs to be flexibly adjustable and preferably linearly adjustable. A linearly varying gain is beneficial for multi-frame synthesis (such as HDR), denoising, or color restoration algorithms. A linear gain can ensure comparability between different frames, thus improving the image quality. It is also more convenient to perform white balance, exposure control, gamma correction, etc. in the image signal processing chain, facilitating the establishment of a lookup table (LUT) or using a linear model for dynamic range control and gain compensation in the ISP. Linear gain adjustment can also more precisely implement the combination strategy of "analog gain + digital gain", thereby improving the dynamic range without sacrificing the linearity of the image.

[0027] In the prior art, to improve the gain accuracy of the gain adjustment circuit, it is necessary to increase the number of control bits. For any gain adjustment array, a larger area and multiple resistor units are required, which increases the mismatch between resistor units and exacerbates the array gradient difference. The gain adjustment is achieved by controlling the number of resistor units actually connected to the ramp generation circuit in the gain adjustment array. Ideally, the resistor units are completely consistent, and the change amounts caused after being connected to the circuit are also completely consistent. Then, the change amounts of the ramp slopes are completely consistent. By statistically analyzing the change amounts of the ramp slopes within the gain adjustment range, the INL and DNL are theoretically 0, and the ramp gain adjustment is considered linear. However, in the actual gain process, there are slight differences in each resistor unit, resulting in inconsistent change amounts of the overall output ramp slopes, non-zero DNL and INL, and thus introducing non-linearity to the ramp gain of the gain adjustment circuit and reducing the gain accuracy.

[0028] Based on this, a linear gain adjustment circuit for a CMOS image sensor chip is proposed, which can cancel the influence of non-linearity between resistor units during the actual gain process, thereby improving the gain accuracy of the gain adjustment circuit.

[0029] A linear gain adjustment circuit for a CMOS image sensor chip provided by an embodiment of the present application will be specifically described through the following embodiments.

[0030] In a first aspect, referring to Figure 1 as shown, Figure 1 is an overall structural diagram of a linear gain adjustment circuit for a CMOS image sensor chip provided by some embodiments of the present application. The linear gain adjustment circuit for a CMOS image sensor chip includes a current source array 110, a signal output terminal 120, a gain resistor array 130, and a trimming resistor array 140. The signal output terminal 120 is electrically connected to the current source array 110. The gain resistor array 130 is electrically connected to the current source array 110, and the gain resistor array 130 is connected in parallel with the signal output terminal 120. The trimming resistor array 140 is electrically connected to the current source array 110, and the trimming resistor array 140 is connected in parallel with the gain resistor array 130. The current source array 110 includes multiple controllable current source units that are connected in parallel with each other. The current source array 110 is used to output a variable total current. The gain resistor array 130 includes multiple resistor units that are connected in parallel with each other.

[0031] Among them, the gain resistor array 130 is used to perform amplitude gain on the voltage of the signal output terminal 120 according to the total resistance value aggregated by each resistor unit in the conducting state and the variable total current, so that the signal output terminal 120 outputs a voltage signal with a ramp change property.

[0032] Moreover, the trimming resistor array 140 is used to simulate the resistance linear change degree of the gain resistor array 130, and non-linearly offset and trim the total resistance value according to the resistance linear change degree, so that the voltage gain of the gain resistor array 130 to the signal output terminal 120 is stably in the linear region.

[0033] It should be noted that each current source unit has the same output current. Each current source unit can be switched sequentially, or the current source units can be strobed row by row. Due to the parallel relationship, the output currents of the current source units in the on state are aggregated into a variable total current I out and then output to the gain resistor array 130 and the signal output terminal 120.

[0034] It should also be noted that each resistor unit has the same resistance value. Each resistor unit can be switched individually, that is, any number of resistor units can be selected in parallel, and then the total resistance value aggregated when the resistor units are in the conducting state is obtained.

[0035] By switching each current source unit one by one and sequentially, the variable total current I out will gradually change, and then the variable total current I out is multiplied by the total resistance value of the gain resistor array 130 according to the total resistance value aggregated when each resistor unit is in the conducting state, and a voltage signal Vramp with a ramp change property is obtained.

[0036] During a single ramp change process, the total resistance value of the gain resistor array 130 is set to a certain fixed value before the ramp starts to change, and this total resistance value can only be changed after the ramp change is completed. The variable total current I out when all current source units in the current source array 110 output simultaneously (that is, at this time I out is the maximum value) is multiplied by the total resistance value to obtain the voltage signal Vramp. The amplitude of this voltage signal Vramp is the maximum swing of the ramp under the current gain resistor; the voltage obtained by multiplying the current output by any one current source unit in the current source array 110 by the total resistance value of the gain resistor array 130 is the change step of the ramp under the current gain resistor, also called the LSB of the ramp change. Figure 1 The voltage Vramp1 and voltage Vramp2 in out are schematic diagrams of two ramps with different LSBs and swings. With the same number of current source units and variable total current I

[0037] Furthermore, from Figure 1It can be seen that the first input end of each resistor unit is circuit-connected to the current source array 110, the second input end of the resistor unit is circuit-connected to the gain resistor decoding controller 150, and the output end of the resistor unit is grounded.

[0038] Among them, with reference to Figure 2 as shown, Figure 2 is the overall structure diagram of the resistor unit provided by some other embodiments of the present application. The resistor unit is internally provided with a resistor r and a MOS switch. The first pole of the MOS switch is circuit-connected to one end of the resistor r. The other end of the resistor r is used as the first input end of the resistor unit. The second pole of the MOS switch is used as the output end of the resistor unit. The third pole of the MOS switch is used as the second input end of the resistor unit. The third pole of the MOS switch is the gate. In one embodiment, when the MOS switch is an NMOS transistor, the first pole of the MOS switch is the drain, and the second pole of the MOS switch is the source. In another embodiment, when the MOS switch is an NMOS transistor, the first pole of the MOS switch is the source, and the first pole of the MOS switch is the drain.

[0039] In one embodiment, R1 to R16 are connected in parallel in the gain resistor array 130, and then R1 to R4 are selected to be connected in parallel and made conductive. Ideally, the total resistance value of the gain resistor array 130 should be 1 / 4 of the maximum resistance value (i.e., when R1 to R16 are simultaneously conductive). However, due to the influence of resistor matching, line parasitics, gradient effects, etc., there are slight differences in the resistance values inside R1 to R4, resulting in the total resistance value of the gain resistor array 130 being higher than the theoretical value, making the step size of the gain change smaller, that is, the gain change of the gain resistor array 130 appears non-linear. In the present application, due to the relevant parallel relationship between the trimming resistor array 140 and the gain resistor array 130, the resistance values inside R1 to R4 in the gain resistor array 130 can be simulated by the trimming resistor array 140, and then the resistance value of the trimming resistor array 140 is adjusted to non-linearly compensate the resistance values of R1 to R4 in the gain resistor array 130, so that the total resistance value of the gain resistor array 130 is close to the theoretical value, making the output voltage with a ramp property reach the theoretical voltage value, and making the signal output end 120 output a voltage signal with a theoretical ramp LSB change amount.

[0040] Furthermore, the linear gain adjustment circuit further includes a gain resistor decoding controller 150, and the gain resistor decoding controller 150 is circuit-connected to the gain resistor array 130. Among them, the gain resistor decoding controller 150 is used to receive the resistor array control signal and output a constant high level to each resistor unit according to the resistor array control signal to make the resistor unit in a conductive state.

[0041] It should be noted that after the resistor array control signal is decoded by the gain resistor decoder controller 150, it can control the switch of each resistor unit. The high level output by the gain resistor decoder controller 150 is the power supply voltage of the current source array 110, and the low level output is the ground voltage. When the high level is output by the gain resistor decoder controller 150, since the second input terminal of the resistor unit is circuit-connected to the gain resistor decoder controller 150, the high level can be input to the third pole of the MOS switch of the resistor unit. At this time, when the third pole of the MOS switch receives the high level, the first pole and the second pole of the MOS switch are turned on, so that the resistor r of the resistor unit is in the working state.

[0042] Moreover, the linear gain adjustment circuit further includes a trimming resistor decoder controller 160, and the trimming resistor decoder controller 160 is circuit-connected to the trimming resistor array 140; the trimming resistor decoder controller 160 is used to receive the resistor array control signal and dynamically simulate the resistance linear change degree of the gain resistor array 130 according to the resistor array control signal.

[0043] Furthermore, the linear gain adjustment circuit further includes a gain signal input terminal 170, the gain signal input terminal 170 is circuit-connected to the gain resistor decoder controller 150, the gain signal input terminal 170 is circuit-connected to the trimming resistor decoder controller 160, and the gain resistor decoder controller 150 and the trimming resistor decoder controller 160 are connected in parallel with each other; the gain signal input terminal 170 is used to transmit the resistor array control signal to the gain resistor decoder controller 150 and the trimming resistor decoder controller 160 respectively.

[0044] Moreover, the linear gain adjustment circuit further includes a current source signal input terminal 180, and the current source signal input terminal 180 is circuit-connected to the current source array 110; the current source signal input terminal 180 is used to input the current source array 110 control signal to the current source array 110, so that the current source array 110 controls the opening and closing of each current source unit one by one according to the current source array 110 control signal to output a variable total current.

[0045] Among them, the resistor array control signal includes a resistor set / reset control signal, a resistor strobe enable signal, and a clock control signal; the resistor set / reset control signal is used to realize the row-by-row selection of the resistor units, and the resistor strobe enable signal is used to specify the interval in which a certain resistor unit can be switched one by one.

[0046] And the current source array 110 control signal includes a current source set / reset control signal, a current source strobe enable signal, and a clock control signal. The current source set / reset control signal is used to realize the row-by-row selection of the current source units, the current source strobe enable signal is used to specify the interval in which a certain current source unit can be switched one by one, and the clock control signal is used to determine at what equal time intervals the current source units or the resistor units are switched one by one.

[0047] Further, the linear gain adjustment circuit further includes a current source global bias generator 190. The current source global bias generator 190 is circuit-connected to the current source array 110. The current source global bias generator 190 is configured to transmit a global bias signal to the current source array 110, so that the current source array 110 controls each current source unit to output the same current according to the global bias signal.

[0048] In a second aspect, referring to Figure 3 as shown, Figure 3 FIG. is an overall structure diagram of a linear gain adjustment circuit for a CMOS image sensor chip provided by some other embodiments of the present application. The linear gain adjustment circuit includes a current source array 210, a signal output terminal 220, a gain resistor array 230, a gain resistor decoding controller 240, and a DAC converter 250. The signal output terminal 220 is circuit-connected to the current source array 210. The gain resistor array is circuit-connected to the current source array 210. The gain resistor array 230 is connected in parallel with the signal output terminal 220. The gain resistor decoding controller 240 is circuit-connected to the gain resistor array 230. The DAC converter 250 is circuit-connected to the gain resistor decoding controller 240.

[0049] Among them, the current source array 210 includes a plurality of bit-by-bit controllable current source units, and each current source unit is connected in parallel with each other. The current source array 210 is configured to output a variable total current. The gain resistor array 230 includes a plurality of resistor units, and each resistor unit is connected in parallel with each other.

[0050] Moreover, the gain resistor array 230 is configured to perform amplitude gain on the voltage of the signal output terminal 220 according to the total resistance value collected by each resistor unit in the conducting state and the variable total current, so that the signal output terminal 220 outputs a voltage signal with a ramp change property.

[0051] Further, the gain resistor decoding controller 240 is configured to receive a resistor array control signal and output a constant-voltage high level to each resistor unit according to the resistor array control signal, so that each resistor unit is in a conducting state.

[0052] Meanwhile, the DAC converter 250 is configured to adjust the voltage value of the high level output by the gain resistor decoding controller 240 according to the resistor array control signal, so as to adjust the number of conducting resistor units in the case of non-linear offset of the resistance value, so that the voltage gain of the gain resistor array 230 for the signal output terminal 220 is stably in the linear region.

[0053] It should be noted that the first input terminal of the resistor unit is circuit-connected to the current source array 210, the second input terminal of the resistor unit is circuit-connected to the gain resistor decoding controller 240, and the output terminal of the resistor unit is grounded; Among them, fromFigure 2 It can be known that the resistor unit internally includes a resistor and a MOS switch. The first pole of the MOS switch is connected in series with one end of the resistor. The other end of the resistor is used as the first input terminal of the resistor unit. The second pole of the MOS switch is used as the output terminal of the resistor unit. The third pole of the MOS switch is used as the second input terminal of the resistor unit, and the third pole of the MOS switch is the gate. In one embodiment, when the MOS switch is an NMOS transistor, the first pole of the MOS switch is the drain, and the second pole of the MOS switch is the source. In another embodiment, when the MOS switch is an NMOS transistor, the first pole of the MOS switch is the source, and the first pole of the MOS switch is the drain.

[0054] In one embodiment, R1 to R16 are connected in parallel in the gain resistor array 230, and then R1 to R4 are selected to be connected in parallel and made conductive. Ideally, the total resistance value of the gain resistor array 230 should be 1 / 4 of the maximum resistance value (i.e., when R1 to R16 are simultaneously conductive). However, due to factors such as resistor matching, line parasitics, and gradient effects, there are slight differences in the resistance values inside R1 to R4, resulting in the total resistance value of the gain resistor array 230 being higher than the theoretical value, causing the step size of the gain change to become smaller, that is, the gain change of the gain resistor array 230 appears non-linear. And in this application, due to the circuit connection between the DAC converter 250 and the gain resistor decoding controller 240, the voltage value of the high level output by the gain resistor decoding controller 240 can be adjusted through the DAC converter 250, so that the voltage value applied to the third pole of the MOS switch of the resistor unit changes, and then the conduction state between the first pole and the second pole of the MOS switch can be indirectly controlled, so as to re-control the switches of R1 to R4, and then indirectly adjust the total resistance value of the gain resistor array 230 to be close to the theoretical value, so that the output voltage with a ramp property reaches the theoretical voltage value, and the voltage signal with the theoretical ramp LSB change amount is output at the signal output terminal 220.

[0055] In one embodiment, the resistance values inside R1 to R4 are too high, resulting in the total resistance value of the gain resistor array 230 being too high. The voltage value corresponding to the high level input to R1 can be lowered through the DAC converter 250, so that the conduction state between the first pole and the second pole of the MOS switch changes from the conductive state to the non-conductive state, that is, R1 is in a non-operating state. At this time, the total resistance value of the gain resistor array 230 is obtained by summing up the resistance values inside R2 to R4, thereby reducing the total resistance value of the gain resistor array 230 and making the total resistance value of the gain resistor array 230 close to the theoretical value.

[0056] Further, the linear gain adjustment circuit further includes a gain signal input terminal 260, which is respectively connected to the gain resistor decoding controller 240 and the DAC converter 250. The gain signal input terminal 260 is used to transmit resistor array control signals to the gain resistor decoding controller 240 and the DAC converter 250 respectively.

[0057] Moreover, the linear gain adjustment circuit further includes a current source signal input terminal 270, which is connected to the current source array 210. The current source signal input terminal 270 is used to input a current source array 210 control signal to the current source array 210, so that the current source array 210 controls the opening and closing of each current source unit bit by bit according to the current source array 210 control signal to output a variable total current.

[0058] Among them, the resistor array control signal includes a resistor set / reset control signal, a resistor strobe enable signal, and a clock control signal; the current source array 210 control signal includes a current source set / reset control signal, a current source strobe enable signal, and a clock control signal.

[0059] Further, the linear gain adjustment circuit further includes a current source global bias generator 280, which is connected to the current source array 210. The current source global bias generator 280 is used to transmit a global bias signal to the current source array 210, so that the current source array 210 controls each current source unit to output the same current according to the global bias signal.

[0060] The embodiments described in the embodiments of the present application are for more clearly explaining the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0061] Those skilled in the art can understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or combine some steps, or different steps.

[0062] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0063] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices can be implemented as software, firmware, hardware and their appropriate combinations.

[0064] In the description of the present application and the above-mentioned accompanying drawings, terms such as "first", "second", "third", "fourth", etc. (if any) are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0065] It should be understood that in the present application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the association relationship of associated objects and indicates that there can be three relationships. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist at the same time. Among them, A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (one) of the following" or its similar expression refers to any combination of these items, including any combination of single items (ones) or plural items (ones). For example, at least one (one) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0066] In several embodiments provided by the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are only illustrative. For example, the above-mentioned division of units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces, and the indirect coupling or communication connection of devices or units can be in electrical, mechanical or other forms.

[0067] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0068] In addition, in each embodiment of the present application, each functional unit may be integrated into one processing unit, may exist physically alone for each unit, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of a software functional unit.

[0069] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a computer-accessible storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, may be embodied in the form of a software product. The computer software product is stored in a storage medium and includes multiple instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in each embodiment of the present application.

[0070] The preferred embodiments of the embodiments of the present application have been described above with reference to the accompanying drawings. However, this does not limit the scope of the rights of the embodiments of the present application. Any modification, equivalent replacement, and improvement made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall fall within the scope of the rights of the embodiments of the present application.

Claims

1. A linear gain adjustment circuit for a CMOS image sensor chip, characterized in that, Comprising: A current source array, the current source array including a plurality of bit-by-bit controllable current source units, each of the current source units being connected in parallel with each other, the current source array being used to output a variable total current; A signal output terminal, the signal output terminal being circuit-connected to the current source array; A gain resistor array, the gain resistor array being circuit-connected to the current source array, the gain resistor array being connected in parallel with the signal output terminal, the gain resistor array including a plurality of resistor units, each of the resistor units being connected in parallel with each other; A trimming resistor array, the trimming resistor array being circuit-connected to the current source array, the trimming resistor array being connected in parallel with the gain resistor array; Wherein, the gain resistor array is used to perform amplitude gain on the voltage of the signal output terminal according to the total resistance value aggregated by each of the resistor units in the conducting state and the variable total current, so that the signal output terminal outputs a voltage signal having a ramp change property; The trimming resistor array is used to simulate the resistance value linear change degree of the gain resistor array and perform non-linear offset trimming on the total resistance value according to the resistance value linear change degree, so that the voltage gain of the gain resistor array for the signal output terminal is stably in the linear region.

2. The linear gain adjustment circuit according to claim 1, wherein Further comprising: A gain resistor decoding controller, the gain resistor decoding controller being circuit-connected to the gain resistor array; A trimming resistor decoding controller, the trimming resistor decoding controller being circuit-connected to the trimming resistor array; Wherein, the gain resistor decoding controller is used to receive a resistor array control signal and output a constant voltage high level to each of the resistor units according to the resistor array control signal, so that the resistor units are in the conducting state; The trimming resistor decoding controller is used to receive the resistor array control signal and dynamically simulate the resistance value linear change degree of the gain resistor array according to the resistor array control signal.

3. The linear gain adjustment circuit according to claim 2, characterized in that Further comprising: A gain signal input terminal, the gain signal input terminal being circuit-connected to the gain resistor decoding controller, the gain signal input terminal being circuit-connected to the trimming resistor decoding controller, the gain resistor decoding controller and the trimming resistor decoding controller being connected in parallel with each other; A current source signal input terminal, the current source signal input terminal being circuit-connected to the current source array; Wherein, the gain signal input terminal is used to transmit the resistor array control signal to the gain resistor decoding controller and the trimming resistor decoding controller respectively; The current source signal input terminal is used to input a current source array control signal to the current source array, so that the current source array controls the opening and closing of each of the current source units bit by bit according to the current source array control signal to output the variable total current.

4. The linear gain adjustment circuit according to claim 3, characterized in that The resistor array control signal includes a resistor set / reset control signal, a resistor strobe enable signal and a clock control signal; The current source array control signal includes a current source set / reset control signal, a current source strobe enable signal and the clock control signal.

5. The linear gain adjustment circuit according to claim 2, wherein The first input terminal of the resistance unit is connected to the current source array circuit, the second input terminal of the resistance unit is connected to the gain resistance decoding controller circuit, and the output terminal of the resistance unit is grounded; Wherein, the resistance unit internally includes a resistor and a MOS switch. The first pole of the MOS switch is circuit-connected to one end of the resistor. The other end of the resistor is used as the first input terminal of the resistance unit. The second pole of the MOS switch is used as the output terminal of the resistance unit. The third pole of the MOS switch is used as the second input terminal of the resistance unit, and the third pole of the MOS switch is the gate.

6. The linear gain adjustment circuit according to claim 1, characterized in that It further includes: A current source global bias generator, which is connected to the current source array circuit. The current source global bias generator is used to transmit a global bias signal to the current source array, so that the current source array controls each current source unit to output the same current according to the global bias signal.

7. A linear gain adjustment circuit for a CMOS image sensor chip, characterized in that It includes: A current source array, which includes a plurality of bit-by-bit controllable current source units. Each of the current source units is connected in parallel with each other. The current source array is used to output a variable total current; A signal output terminal, which is connected to the current source array circuit; A gain resistance array, which is connected to the current source array circuit. The gain resistance array is connected in parallel with the signal output terminal. The gain resistance array includes a plurality of resistance units, and each of the resistance units is connected in parallel with each other; A gain resistance decoder controller, which is connected to the gain resistance array circuit; A DAC converter, which is connected to the gain resistance decoder controller circuit; Wherein, the gain resistance array is used to perform amplitude gain on the voltage of the signal output terminal according to the total resistance value collected by each resistance unit in the on state and the variable total current, so that the signal output terminal outputs a voltage signal with a ramp change property; The gain resistance decoder controller is used to receive a resistance array control signal and output a constant voltage high level to each resistance unit according to the resistance array control signal, so that the resistance unit is in the on state; The DAC converter is used to adjust the voltage value of the high level output by the gain resistance decoder controller according to the resistance array control signal, so as to adjust the conduction number of the resistance units in the case of non-linear offset of the resistance value, so that the voltage gain of the gain resistance array to the signal output terminal is stably in the linear region.

8. The linear gain adjustment circuit according to claim 7, wherein It further includes: A gain signal input terminal, which is respectively connected to the gain resistance decoder controller and the DAC converter circuit; A current source signal input terminal, which is connected to the current source array circuit; The gain signal input terminal is used to transmit the resistance array control signal to the gain resistance decoder controller and the DAC converter respectively; The current source signal input terminal is used to input a current source array control signal to the current source array, so that the current source array controls the on / off of each current source unit bit by bit according to the current source array control signal to output the variable total current; Among them, the resistor array control signal includes a resistor set / reset control signal, a resistor strobe enable signal, and a clock control signal; The current source array control signal includes a current source set / reset control signal, a current source strobe enable signal, and the clock control signal.

9. The linear gain adjustment circuit according to claim 7, wherein It further includes: A current source global bias generator, which is connected to the current source array circuit. The current source global bias generator is used to transmit a global bias signal to the current source array, so that the current source array controls each current source unit to output the same current according to the global bias signal.

10. The linear gain adjustment circuit according to claim 7, characterized in that, The first input terminal of the resistor unit is connected to the current source array circuit, the second input terminal of the resistor unit is connected to the gain resistor decoding controller circuit, and the output terminal of the resistor unit is grounded; Among them, the resistor unit is internally provided with a resistor and a MOS switch. The first pole of the MOS switch is connected in series with one end of the resistor. The other end of the resistor is used as the first input terminal of the resistor unit. The second pole of the MOS switch is used as the output terminal of the resistor unit. The third pole of the MOS switch is used as the second input terminal of the resistor unit. The third pole of the MOS switch is the gate.

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