Interconnection-line-free carrier synchronization method, device and equipment and storage medium

Abstract

The invention discloses an interconnection-line-free carrier synchronization method and device, equipment and a storage medium, and relates to the technical field of power systems. The method comprises the following steps: acquiring a voltage signal of a grid-connected point, and determining a first interruption triggering moment according to the state of the voltage signal by using a logic state capturing unit; determining a clock reference moment corresponding to a target phase in voltage phases by using phase-locked loop software, and determining an optimal time interval according to the first interrupt trigger moment and the clock reference moment; and determining the moment of the second interruption triggering moment after the optimal time interval as a carrier synchronization reference moment, and carrying out carrier synchronization at the carrier synchronization reference moment. According to the technical scheme provided by the embodiment of the invention, the high-precision determination of the reference moment is realized through the combination of software and hardware, the realization is simple, the problem that the reference time of the carrier synchronization without the interconnection line is inaccurate is solved, the carrier synchronization effect is improved, and the parallel circulating current is inhibited.

Description

Technical Field

[0001] The present invention relates to the technical field of power systems, and in particular to a carrier synchronization method, device, equipment and storage medium without interconnection lines. Background Art

[0002] With the goal of building a new power system, the proportion of renewable energy power generation will further increase, the application of string photovoltaic inverters and string energy storage converters will become more and more extensive, and there are more and more application scenarios where multiple photovoltaic inverters or energy storage converters are connected in parallel at the AC end and then connected to a step-up transformer. However, when multiple inverters are connected in parallel at the AC end, it is easy to cause current circulation at the switching frequency, which not only reduces the power quality of the output current, but also threatens the safe operation of the inverter.

[0003] At present, the core of the suppression measures for parallel circulation current is to achieve carrier synchronization between inverters. Carrier synchronization methods are mainly divided into carrier synchronization with interconnection lines and carrier synchronization without interconnection lines. The carrier synchronization method with interconnection lines usually requires a high-speed signal synchronization line or communication line to provide a reference time for the carriers of different inverters, and then perform carrier synchronization. When the number of inverters that need to be connected in parallel is too large or the distance is far, the effectiveness of carrier synchronization with interconnection lines will decrease and the cost will increase. Carrier synchronization without interconnection lines usually uses public information of the power grid, such as grid voltage, grid current, etc., to provide a time reference for carrier synchronization, which is suitable for large-scale inverter parallel scenarios.

[0004] However, the conventional carrier synchronization method without interconnection line has defects. For example, the parameter difference of hardware circuit will cause the deviation of reference time, thus affecting the carrier synchronization effect. This method is suitable for parallel connection of inverters with lower switching frequency. Summary of the invention

[0005] The present invention provides a carrier synchronization method, device, equipment and storage medium without an interconnection line, so as to solve the problem of inaccurate reference time of carrier synchronization without an interconnection line.

[0006] In a first aspect, the present invention provides a carrier synchronization method without an interconnection line, comprising:

[0007] Acquire a voltage signal of the grid connection point, and determine a first interrupt triggering moment according to a state of the voltage signal by using a logic state capture unit;

[0008] Determine a clock reference time corresponding to a target phase in a voltage phase by using phase-locked loop software, and determine an optimal time interval according to the first interrupt triggering time and the clock reference time;

[0009] The moment after the second interrupt trigger moment passes through the optimal time interval is determined as the carrier synchronization reference moment, and carrier synchronization is performed at the carrier synchronization reference moment, wherein the second interrupt trigger moment is an interrupt trigger moment determined by a logic state capture unit and is later than the first interrupt trigger moment.

[0010] In a second aspect, the present invention provides a carrier synchronization device without interconnection lines, comprising:

[0011] An interruption time determination module, used for acquiring a voltage signal of a grid connection point, and determining a first interruption triggering time according to a state of the voltage signal by using a logic state capture unit;

[0012] An optimal interval module, used to determine a clock reference time corresponding to a target phase in a voltage phase by using a phase-locked loop software, and determine an optimal time interval according to the first interrupt triggering time and the clock reference time;

[0013] A carrier synchronization module is used to determine the moment after the second interrupt trigger moment passes through the optimal time interval as the carrier synchronization reference moment, and perform carrier synchronization at the carrier synchronization reference moment, wherein the second interrupt trigger moment is an interrupt trigger moment determined by a logic state capture unit and is later than the first interrupt trigger moment.

[0014] In a third aspect, the present invention provides an electronic device, the electronic device comprising:

[0015] at least one processor;

[0016] and a memory communicatively coupled to the at least one processor;

[0017] The memory stores a computer program executable by at least one processor, and the computer program is executed by at least one processor so that the at least one processor can execute the carrier synchronization method without interconnection line of the first aspect.

[0018] In a fourth aspect, the present invention provides a computer-readable storage medium storing computer instructions, which are used to enable a processor to implement the carrier synchronization method without interconnection line of the first aspect when executed.

[0019] The carrier synchronization scheme without interconnection line provided by the present invention obtains the voltage signal of the grid connection point, and uses the logic state capture unit to determine the first interrupt triggering moment according to the state of the voltage signal, uses the phase-locked loop software to determine the clock reference moment corresponding to the target phase in the voltage phase, and determines the optimal time interval according to the first interrupt triggering moment and the clock reference moment, determines the moment after the second interrupt triggering moment passes through the optimal time interval as the carrier synchronization reference moment, and performs carrier synchronization at the carrier synchronization reference moment, wherein the second interrupt triggering moment is the interrupt triggering moment determined by the logic state capture unit later than the first interrupt triggering moment. By adopting the above technical scheme, the characteristic of relatively accurate determination of the voltage phase by the PLL (Phase Locked Loop, phase-locked loop) software is utilized to compensate for the time deviation of the hardware logic state capture unit capturing the key signal (such as the voltage zero crossing point) to trigger the interrupt, and the reference moment is determined with high precision through the combination of software and hardware, and the implementation is simple, which solves the problem of inaccurate reference time of carrier synchronization without interconnection line, improves the carrier synchronization effect, and suppresses the parallel circulation.

[0020] It should be understood that the content described in this section is not intended to identify the key or important features of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 This is a flow chart of a carrier synchronization method without interconnection line provided according to the first embodiment of the present invention;

[0023] Figure 2 A multi-inverter parallel grid-connected circuit diagram provided according to Embodiment 1 of the present invention;

[0024] Figure 3 This is a schematic diagram of a carrier gradual change method provided according to Embodiment 1 of the present invention;

[0025] Figure 4 This is a flow chart of a carrier synchronization method without interconnection line provided according to the second embodiment of the present invention;

[0026] Figure 5 This is a waveform diagram provided according to Embodiment 2 of the present invention;

[0027] Figure 6 is a three-phase output current waveform diagram of an inverter provided according to Embodiment 2 of the present invention;

[0028] Figure 7 This is a schematic diagram of the structure of a carrier synchronization device without interconnection lines provided according to Embodiment 3 of the present invention;

[0029] Figure 8 It is a schematic diagram of the structure of an electronic device provided according to Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0031] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In the description of the present invention, unless otherwise specified, "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0032] Embodiment 1

[0033] Figure 1A flowchart of a carrier synchronization method without an interconnection line is provided for Embodiment 1 of the present invention. This embodiment is applicable to the case of carrier synchronization. The method can be executed by a carrier synchronization device without an interconnection line. The carrier synchronization device without an interconnection line can be implemented in the form of hardware and / or software. The carrier synchronization device without an interconnection line can be configured in an electronic device. The electronic device can be composed of two or more physical entities or one physical entity.

[0034] like Figure 1 As shown, the carrier synchronization method without interconnection line provided in the first embodiment of the present invention specifically includes the following steps:

[0035] S101, acquiring a voltage signal of a grid connection point, and using a logic state capture unit to determine a first interrupt triggering moment according to a state of the voltage signal.

[0036] Specifically, the method described in this embodiment can be applied to various types of converters.

[0037] For example, Figure 2 This is a circuit diagram of multiple inverters connected in parallel and connected to the grid. Figure 2 As shown, the AC output end of the inverter is connected in parallel to the step-up transformer and then connected to the grid. The switching frequency circulation generated in parallel is caused by the asynchronous driving signal of the switch tube of the inverter. Further analysis shows that the deviation of the crystal oscillator of each inverter causes the deviation of the carrier frequency. The voltage signal of the grid connection point can be obtained by using the built-in voltage sensor in the inverter and the sampling and conditioning circuit on the control board. Then the logic state capture unit can trigger an interrupt according to the state of the voltage signal. The moment corresponding to the interrupt is the first interrupt triggering moment, which is recorded as teCAP. Among them, there is usually a relatively fixed deviation between teCAP and the actual occurrence time corresponding to the state of the grid voltage actually triggering the interrupt, which is recorded as ΔteCAP. This deviation is affected by the differences in the hardware circuit parameters of different inverters, but the specific deviation range is uncertain.

[0038] S102: Determine a clock reference time corresponding to a target phase in a voltage phase by using a phase-locked loop software, and determine an optimal time interval according to the first interrupt triggering time and the clock reference time.

[0039] In this embodiment, the PLL software (i.e., phase-locked loop software) can be used to determine the voltage phase according to the digital signal corresponding to the voltage signal, and determine the time corresponding to the phase (i.e., the target phase) pre-specified by the voltage phase as the clock reference time, such as determining the time corresponding to when the a-phase voltage reaches the trough or peak as the clock reference time, recorded as tPLL. Among them, the time difference between tPLL and the actual time corresponding to the target phase of the grid voltage is theoretically π / 2, but because the PLL is implemented by software, it is affected by the frequency deviation of the chip crystal oscillator and there are fluctuations, but the fluctuation range is clear, usually one switching cycle. Then, the time difference between the clock reference time and the first interrupt triggering time can be determined as the optimal time interval. The difference can also be preset and the operation result is determined as the optimal time interval. For example, the sum of the difference and the preset margin value is determined to determine the optimal time interval.

[0040] S103. Determine the moment after the optimal time interval of the second interrupt trigger moment as the carrier synchronization reference moment, and perform carrier synchronization at the carrier synchronization reference moment, wherein the second interrupt trigger moment is an interrupt trigger moment determined by a logic state capture unit and is later than the first interrupt trigger moment.

[0041] In this embodiment, after the optimal time interval is determined, when the interrupt is triggered again (i.e., after the second interrupt is triggered), the optimal time interval can be assigned to the period register of the timer, and the timer interrupt is turned on. The time when the timer interrupt occurs (i.e., the time after the second interrupt is triggered after the optimal time interval) is determined as the carrier synchronization reference time, and then the timer interrupt is turned off. Finally, carrier synchronization is started at the carrier synchronization reference time to achieve suppression of parallel circulating current.

[0042] The technical solution of the embodiment of the present invention utilizes the characteristics of PLL software determining the voltage phase relatively accurately and with a clear fluctuation range, to compensate for the characteristics of the hardware logic state capture unit capturing the hardware deviation of the interrupt trigger voltage and the uncertain specific deviation range. By combining the advantages of the two, the disadvantages of both are compensated, and the accurate determination of the carrier synchronization reference moment is achieved with simple implementation, which solves the problem of inaccurate reference time of carrier synchronization without interconnection line, improves the carrier synchronization effect, and suppresses parallel circulation current.

[0043] Optionally, the method of using a logic state capture unit to determine the first interrupt trigger moment according to the state of the voltage signal includes: using a built-in eCAP capture unit to determine the target moment when the voltage of the first target phase changes direction according to the state of the voltage signal, and determining the target moment as the first interrupt trigger moment.

[0044] Specifically, the embedded chip built into the converter, such as a DSP (digital signal processing chip), in the eCAP capture unit can determine the voltage change direction of the (second) target phase in the grid voltage according to the state of the voltage signal, thereby triggering an interruption, and the moment corresponding to the interruption is the first interruption triggering moment. The voltage change direction of the first target phase can be an upward zero crossing and / or a downward zero crossing, and the first target phase can be at least one of phase a, phase b, and phase c.

[0045] Exemplarily, when the voltage change direction of the first target phase is an upward zero crossing and a downward zero crossing, and the first target phase is one of the a phase, the b phase, and the c phase, two first interruption triggering moments can be determined in one power frequency cycle. When the voltage change direction of the first target phase is an upward zero crossing or a downward zero crossing, and the first target phase is the a phase, the b phase, and the c phase, three first interruption triggering moments can be determined in one power frequency cycle. When the voltage change direction of the first target phase is an upward zero crossing and a downward zero crossing, and the first target phase is the a phase, the b phase, and the c phase, six first interruption triggering moments can be determined in one power frequency cycle.

[0046] Among them, PLL software is a phase-locked loop technology that is fully implemented in the software of a digital signal processor (DSP), field programmable gate array (FPGA) or application-specific integrated circuit (ASIC). A phase-locked loop is a circuit used to synchronize and stabilize a clock signal. It generates a control signal to adjust the input of a variable oscillator by comparing the phase of a reference signal with the phase of a feedback signal, thereby locking the output frequency and phase to the reference frequency and phase. The eCAP capture unit of the DSP is a powerful functional module that is mainly used to capture the logic state changes of external input pins, such as the high and low levels, rising edges or falling edges.

[0047] Optionally, performing carrier synchronization at the carrier synchronization reference moment includes: determining the maximum value of the time base counter value within the analog-to-digital conversion interrupt period corresponding to the carrier synchronization reference moment as the original maximum value; updating the maximum value of the time base counter value to a target value using a preset value according to a change trend of the time base counter value of the built-in ePWM unit after the carrier synchronization reference moment, and updating the target value to the original maximum value after a preset period to complete carrier synchronization.

[0048] Specifically, the ePWM (Enhanced Pulse Width Modulation) unit is an enhanced pulse width modulation module, which is widely used in digital signal processors (DSP) to control power conversion, motor drive and other applications. The maximum value of the time base counter value can be changed by using a preset value according to the change trend of the time base counter value of the ePWM unit after the carrier synchronization reference moment. For example, when the change trend is rising, the maximum value of the time base counter value is updated to the first preset value, and when the change trend is falling, the maximum value of the time base counter value is updated to the second preset value. At this time, the first preset value can be greater than the original maximum value, and the second preset value can be less than the original maximum value. After continuing for a preset period, the target value is restored to the original maximum value to complete the carrier synchronization.

[0049] Further, according to the change trend of the time base counter value of the built-in ePWM unit after the carrier synchronization reference moment, the maximum value of the time base counter value is updated to a target value using a preset value, and the target value is updated to the original maximum value after a preset period to complete carrier synchronization, including: when the time base counter value of the built-in ePWM unit shows a downward trend at the carrier synchronization reference moment, the maximum value of the time base counter value is updated to a first target value in the next analog-to-digital conversion interrupt cycle, and the maximum value of the time base counter value is updated to the original maximum value after the first preset period, wherein the first target value is the difference between the original maximum value and the preset value, and the first preset period is the quotient of the original maximum value and a preset value of a preset multiple of analog-to-digital conversion interrupt cycles; when the time base counter value of the built-in ePWM unit shows an upward trend at the carrier synchronization reference moment, the maximum value of the time base counter value is updated to a second target value in the next analog-to-digital conversion interrupt cycle, and the maximum value of the time base counter value is updated to the original maximum value after the first preset period, wherein the second target value is the sum of the original maximum value and the preset value.

[0050] Exemplarily, after the carrier synchronization reference time is determined, the carrier can be synchronized by using a carrier slow change method. Figure 3 Schematic diagram of a carrier slow change method, such as Figure 3 As shown, at the carrier synchronization reference time (i.e. Figure 3The ePWM unit's time base count register value (i.e., time base counter value) TBCTR and the time base counter count direction are recorded at the time of the timer interrupt in the timer interruption. When the count direction is decreasing (i.e., the time base counter value is decreasing), in the next analog-to-digital conversion interruption cycle, the ePWM period register value TBPRD (i.e., the original maximum value) is updated to the value of the original TBPRD value minus Δ (Δ can be any positive integer less than the original TBPRD value), and after [TBCTR / (2Δ)] interruption cycles ([] indicates rounding operation), TBPRD is changed back to the original value. This process is equivalent to increasing the carrier frequency to achieve carrier synchronization. When the count direction is increasing, in the next analog-to-digital conversion interruption cycle, TBPRD is changed to the value of the original value plus Δ, and after [TBCTR / (2Δ)] interruption cycles, TBPRD is changed back to the original value. This process is equivalent to reducing the carrier frequency to achieve carrier synchronization.

[0051] Embodiment 2

[0052] Figure 4 This is a flow chart of a carrier synchronization method without interconnection line provided in the second embodiment of the present invention. The technical solution of the embodiment of the present invention is further optimized on the basis of the above-mentioned optional technical solutions, and a specific method of carrier synchronization is given.

[0053] Optionally, the use of phase-locked loop software to determine the clock reference moment corresponding to the target phase in the voltage phase includes: using the phase-locked loop software to determine the voltage phase of the grid voltage based on the digital signal of the voltage signal; after the first interrupt triggering moment, screening out the target phase corresponding to the preset phase from the voltage signal of the first target phase of the grid voltage; and determining the moment corresponding to the target phase as the clock reference moment.

[0054] Optionally, before the method of using the built-in eCAP capture unit to determine the target time when the voltage of the first target phase changes direction according to the state of the voltage signal, it also includes: converting the voltage signal into a square wave; wherein, the method of using the built-in eCAP capture unit to determine the target time when the voltage of the first target phase changes direction according to the state of the voltage signal includes: using the built-in eCAP capture unit to determine the falling edge or rising edge of the square wave of the first target phase, and determining the time when the falling edge or rising edge occurs as the target time. Optionally, the method of determining the optimal time interval according to the first interrupt trigger moment and the clock reference moment includes: for each first interrupt trigger moment, determining the time interval between the target clock reference moment and the current first interrupt trigger moment as the initial time interval, wherein the target clock reference moment is a clock reference moment that occurs after the current first interrupt trigger moment and before the next first interrupt trigger moment; and determining the optimal time interval using the initial time interval.

[0055] like Figure 4 As shown, a carrier synchronization method without interconnection line provided in the second embodiment of the present invention specifically includes the following steps:

[0056] S201, obtaining a voltage signal of a grid connection point, and converting the voltage signal into a square wave.

[0057] Specifically, Figure 5 The built-in filter circuit can be used to filter the sinusoidal voltage signal. Convert to Square wave, the corresponding waveform is as follows Figure 5 shown.

[0058] S202 , using the built-in eCAP capture unit, determine the falling edge or rising edge of the square wave of the first target phase, and determine the occurrence time of the falling edge or rising edge as the target time; determine the target time as the first interrupt triggering time.

[0059] Specifically, Figure 5 As shown, the falling edge of the square wave can generate an eCAP interrupt, and the time corresponding to this interrupt can be determined as the target time teCAP, and ΔteCAP is the fixed deviation between teCAP and the time when the actual zero crossing of the grid voltage occurs. Among them, the time when the falling edge or rising edge of the square wave occurs is the target time when the voltage changes direction.

[0060] S203: Determine the voltage phase of the grid voltage according to the digital signal of the voltage signal using phase-locked loop software.

[0061] Specifically, the voltage signal is processed by an analog-to-digital converter to obtain a digital signal of the voltage signal. The phase-locked loop software can output the voltage phase of the grid voltage according to the digital signal.

[0062] S204: After the first interruption triggering moment, select a target phase corresponding to a preset phase from the voltage signal of the first target phase of the grid voltage.

[0063] Specifically, the first target phase of the grid voltage may be one of phase a, phase b and phase c. Exemplarily, if the preset phase is the phase at the trough, the phase when the voltage of the first target phase in the voltage signal reaches the trough is the target phase.

[0064] S205: Determine the time corresponding to the target phase as the clock reference time.

[0065] For example, Figure 5 As shown, the clock reference time when the voltage passes through the valley can be recorded as tPLL, which is also the film phase determined by the PLL software. The moment of time.

[0066] S206. For each first interrupt triggering moment, determine the time interval between the target clock reference moment and the current first interrupt triggering moment as an initial time interval; and determine the optimal time interval using the initial time interval.

[0067] The target clock reference time is a clock reference time that occurs after the current first interrupt triggering time and before the next first interrupt triggering time.

[0068] For example, Figure 5 The Δtd shown in is the initial time interval, and Δtstd is the optimal time interval. If it is preset that N first interrupt triggering moments need to be determined, the process of determining the initial time interval can be:

[0069] Whenever the eCAP capture unit captures the grid voltage falling edge triggering the eCAP interrupt (teCAP moment), the timer starts counting until the tPLL moment (i.e., the clock reference moment). The timer count result Δtd is stored in the array, and the above counting process is repeated N-1 times in the next N-1 power frequency cycles. Among them, selecting an appropriate N value can reflect the frequency deviation of the chip crystal oscillator, such as the count value result of the timer changes evenly in one or more switching cycles.

[0070] Then, the counting results of the N counters can be subjected to a preset operation, such as maximum, minimum, average or other preset algorithms, to obtain the optimal time interval Δtstd. The above whole process can be defined as a self-learning process.

[0071] S207: Determine a time after the second interrupt triggering time has passed the optimal time interval as a carrier synchronization reference time.

[0072] Exemplarily, the timer may start counting at the second interrupt triggering moment and be turned off after an optimal time interval, and the turning off moment is the carrier synchronization reference moment. Figure 5 The rising edge time of the timer interrupt shown in is the time when the timer interrupt is turned off, and this time is also the carrier synchronization reference time.

[0073] S208: Determine the maximum value of the time base counter value within the analog-to-digital conversion interruption period corresponding to the carrier synchronization reference time as the original maximum value.

[0074] S209. When the time base counter value of the built-in ePWM unit shows a downward trend at the carrier synchronization reference time, the maximum value of the time base counter value is updated to the first target value in the next analog-to-digital conversion interruption cycle, and the maximum value of the time base counter value is updated to the original maximum value after a first preset cycle; when the time base counter value of the built-in ePWM unit shows an upward trend at the carrier synchronization reference time, the maximum value of the time base counter value is updated to the second target value in the next analog-to-digital conversion interruption cycle, and the maximum value of the time base counter value is updated to the original maximum value after the first preset cycle.

[0075] Among them, the first target value is the difference between the original maximum value and the preset value, the first preset period is the quotient of the original maximum value and the preset value of the preset multiple analog-to-digital conversion interruption period, and the second target value is the sum of the original maximum value and the preset value.

[0076] Specifically, the above steps can be executed repeatedly until the carrier synchronization is completed.

[0077] For example, take three energy storage inverters connected in parallel and connected to the grid as an example. The hardware topology relationship of the three inverters is as follows: Figure 2 As shown, the rated power of a single energy storage converter is 200kW, the rated voltage is 800V, the rated frequency is 50Hz, and the short-circuit ratio of the power grid is 10. Figure 6 This is a three-phase output current waveform of an inverter. Figure 6 Figure a in the figure is the three-phase output current waveform of the inverter after full load. Figure 6 Figure b in FIG. 1 is a three-phase output current waveform before the carrier synchronization algorithm is switched on (i.e., the carrier synchronization method without interconnection line provided in the embodiment of the present invention is applied). Figure 6 Figure c in the figure is after the carrier synchronization algorithm is switched on. Figure 6 As shown in the figure, before the carrier synchronization algorithm is switched on, the switching frequency harmonics of the three-phase current are large, the three-phase current envelope has obvious fluctuations, and the system contains obvious current circulation of switching frequency sub-currents. After the carrier synchronization algorithm is switched on, the three-phase current envelope becomes smooth, and the switching frequency sub-harmonic content of the three-phase current decreases sharply, which verifies the effectiveness of the method described in this embodiment, and after multiple rounds of experiments, it can be seen that the greater the load of this method, the higher the accuracy.

[0078] The carrier synchronization method without interconnection line provided by the embodiment of the present invention uses the built-in eCAP capture unit to capture the grid voltage zero-crossing time, uses the PLL software to calculate the reference time, and obtains the optimal time interval based on these two times. When the eCAP triggers the interrupt again, the timer interrupt is triggered after the optimal time interval has passed. At the time of the timer interrupt, the effective synchronization of the carrier without interconnection line is achieved through the preset carrier slow-changing synchronization method. This method is applicable to various types of converters with multiple machines running in parallel.

[0079] Embodiment 3

[0080] Figure 7 This is a schematic diagram of the structure of a carrier synchronization device without interconnection line provided in the third embodiment of the present invention. Figure 7 As shown, the device includes: an interruption time determination module 301, an optimal interval module 302 and a carrier synchronization module 303, wherein:

[0081] The interruption time determination module 301 is used to obtain the voltage signal of the grid connection point, and determine the first interruption triggering time according to the state of the voltage signal by using the logic state capture unit;

[0082] An optimal interval module 302, configured to determine a clock reference time corresponding to a target phase in a voltage phase by using a phase-locked loop software, and determine an optimal time interval according to the first interrupt triggering time and the clock reference time;

[0083] The carrier synchronization module 303 is used to determine the moment after the second interrupt trigger moment passes through the optimal time interval as the carrier synchronization reference moment, and perform carrier synchronization at the carrier synchronization reference moment, wherein the second interrupt trigger moment is an interrupt trigger moment determined by a logic state capture unit and is later than the first interrupt trigger moment.

[0084] The carrier synchronization device without interconnection line provided in the embodiment of the present invention utilizes the characteristic of relatively accurate determination of voltage phase by PLL software to compensate for the time deviation of the hardware logic state capture unit capturing the key signal (such as voltage zero crossing) triggering the interruption, and realizes high-precision determination of the reference time through the combination of software and hardware. The implementation is simple, solves the problem of inaccurate reference time of carrier synchronization without interconnection line, improves the carrier synchronization effect, and suppresses parallel circulation current.

[0085] Optionally, the optimal interval module 302 includes:

[0086] A voltage phase determination unit, used for determining a voltage phase of a grid voltage according to a digital signal of the voltage signal using a phase-locked loop software;

[0087] a target phase determination unit, configured to select a target phase corresponding to a preset phase from a voltage signal of a first target phase of a grid voltage after the first interruption triggering moment;

[0088] The clock reference time determination unit is used to determine the time corresponding to the target phase as the clock reference time.

[0089] Optionally, the interruption time determination module 301 includes:

[0090] The interruption time determination unit is used to determine the target time when the voltage of the first target phase changes direction according to the state of the voltage signal by using the built-in eCAP capture unit, and determine the target time as the first interruption triggering time.

[0091] Optionally, the device further comprises:

[0092] The signal conversion module is used to convert the voltage signal into a square wave before the target time when the voltage of the first target phase changes direction is determined according to the state of the voltage signal by using the built-in eCAP capture unit.

[0093] Furthermore, the use of the built-in eCAP capture unit to determine the target moment when the voltage of the first target phase changes direction according to the state of the voltage signal includes: using the built-in eCAP capture unit to determine the falling edge or rising edge of the square wave of the first target phase, and determining the occurrence moment of the falling edge or rising edge as the target moment.

[0094] Optionally, the optimal interval module 302 includes:

[0095] an initial interval determination unit, for determining, for each first interrupt triggering moment, a time interval between a target clock reference moment and a current first interrupt triggering moment as an initial time interval, wherein the target clock reference moment is a clock reference moment that occurs after the current first interrupt triggering moment and before the next first interrupt triggering moment;

[0096] The optimal interval determining unit is used to determine the optimal time interval using the initial time interval.

[0097] Optionally, the carrier synchronization module 303 includes:

[0098] an original maximum value determining unit, configured to determine the maximum value of the time base counter value within the analog-to-digital conversion interruption period corresponding to the carrier synchronization reference time as the original maximum value;

[0099] The carrier synchronization unit is used to update the maximum value of the time base counter value to the target value using a preset value according to the change trend of the time base counter value of the built-in ePWM unit after the carrier synchronization reference moment, and update the target value to the original maximum value after a preset period to complete carrier synchronization.

[0100] Further, according to the change trend of the time base counter value of the built-in ePWM unit after the carrier synchronization reference moment, the maximum value of the time base counter value is updated to a target value using a preset value, and the target value is updated to the original maximum value after a preset period to complete carrier synchronization, including: when the time base counter value of the built-in ePWM unit shows a downward trend at the carrier synchronization reference moment, the maximum value of the time base counter value is updated to a first target value in the next analog-to-digital conversion interrupt cycle, and the maximum value of the time base counter value is updated to the original maximum value after the first preset period, wherein the first target value is the difference between the original maximum value and the preset value, and the first preset period is the quotient of the original maximum value and a preset value of a preset multiple of analog-to-digital conversion interrupt cycles; when the time base counter value of the built-in ePWM unit shows an upward trend at the carrier synchronization reference moment, the maximum value of the time base counter value is updated to a second target value in the next analog-to-digital conversion interrupt cycle, and the maximum value of the time base counter value is updated to the original maximum value after the first preset period, wherein the second target value is the sum of the original maximum value and the preset value.

[0101] The carrier synchronization device without interconnection line provided in the embodiment of the present invention can execute the carrier synchronization method without interconnection line provided in any embodiment of the present invention, and has the functional modules and beneficial effects corresponding to the execution method.

[0102] Embodiment 4

[0103] Figure 8 The schematic diagram of the structure of the electronic device 40 that can be used to implement the embodiment of the present invention is shown. The electronic device can be various forms of digital computers and converters, etc. The components shown herein, their connections and relationships, and their functions are only examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0104] like Figure 8As shown, the electronic device 40 includes at least one processor 41, and a memory connected to the at least one processor 41, such as a read-only memory (ROM) 42, a random access memory (RAM) 43, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 41 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 42 or the computer program loaded from the storage unit 48 to the random access memory (RAM) 43. In the RAM 43, various programs and data required for the operation of the electronic device 40 can also be stored. The processor 41, the ROM 42, and the RAM 43 are connected to each other through a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44.

[0105] A number of components in the electronic device 40 are connected to the I / O interface 45, including: an input unit 46, such as a keyboard, a mouse, etc.; an output unit 47, such as various types of displays, speakers, etc.; a storage unit 48, such as a disk, an optical disk, etc.; and a communication unit 49, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 49 allows the electronic device 40 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0106] The processor 41 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 41 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 41 performs the various methods and processes described above, such as a carrier synchronization method without an interconnection line.

[0107] In some embodiments, the carrier synchronization method without an interconnection line can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 48. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 40 via the ROM 42 and / or the communication unit 49. When the computer program is loaded into the RAM 43 and executed by the processor 41, one or more steps of the carrier synchronization method without an interconnection line described above can be performed. Alternatively, in other embodiments, the processor 41 can be configured to perform the carrier synchronization method without an interconnection line by any other appropriate means (for example, by means of firmware).

[0108] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0109] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0110] The computer device provided above can be used to execute the carrier synchronization method without interconnection line provided in any of the above embodiments, and has corresponding functions and beneficial effects.

[0111] Embodiment 5

[0112] In the context of the present invention, a computer readable storage medium may be a tangible medium, wherein the computer executable instructions, when executed by a computer processor, are used to perform a carrier synchronization method without an interconnect line, the method comprising:

[0113] Acquire a voltage signal of the grid connection point, and determine a first interrupt triggering moment according to a state of the voltage signal by using a logic state capture unit;

[0114] Determine a clock reference time corresponding to a target phase in a voltage phase by using phase-locked loop software, and determine an optimal time interval according to the first interrupt triggering time and the clock reference time;

[0115] The moment after the second interrupt trigger moment passes through the optimal time interval is determined as the carrier synchronization reference moment, and carrier synchronization is performed at the carrier synchronization reference moment, wherein the second interrupt trigger moment is an interrupt trigger moment determined by a logic state capture unit and is later than the first interrupt trigger moment.

[0116] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or with an instruction execution system, device, or equipment or used in combination with an instruction execution system, device, or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0117] The computer device provided above can be used to execute the carrier synchronization method without interconnection line provided in any of the above embodiments, and has corresponding functions and beneficial effects.

[0118] It is worth noting that in the embodiment of the above-mentioned carrier synchronization device without interconnection lines, the various units and modules included are only divided according to functional logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be achieved; in addition, the specific names of the functional units are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention.

[0119] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A carrier synchronization method without interconnection line, characterized in that: include: Acquire a voltage signal of the grid connection point, and determine a first interrupt triggering moment according to a state of the voltage signal by using a logic state capture unit; Determine a clock reference time corresponding to a target phase in a voltage phase by using phase-locked loop software, and determine an optimal time interval according to the first interrupt triggering time and the clock reference time; The moment after the second interrupt trigger moment passes through the optimal time interval is determined as the carrier synchronization reference moment, and carrier synchronization is performed at the carrier synchronization reference moment, wherein the second interrupt trigger moment is an interrupt trigger moment determined by a logic state capture unit and is later than the first interrupt trigger moment.

2. The method according to claim 1, characterized in that: The method of using a logic state capture unit to determine the first interrupt triggering moment according to the state of the voltage signal includes: By using the built-in eCAP capture unit, a target time when the voltage of the first target phase changes direction is determined according to the state of the voltage signal, and the target time is determined as the first interrupt triggering time.

3. The method according to claim 1, characterized in that The method of using phase-locked loop software to determine the clock reference time corresponding to the target phase in the voltage phase includes: Determining the voltage phase of the grid voltage according to the digital signal of the voltage signal using phase-locked loop software; After the first interruption triggering moment, selecting a target phase corresponding to a preset phase from a voltage signal of a first target phase of a grid voltage; The time corresponding to the target phase is determined as the clock reference time.

4. The method according to claim 2, characterized in that: Before using the built-in eCAP capture unit to determine the target time when the voltage of the first target phase changes direction according to the state of the voltage signal, the method further includes: Converting the voltage signal into a square wave; The method of using the built-in eCAP capture unit to determine the target time when the voltage of the first target phase changes direction according to the state of the voltage signal includes: The built-in eCAP capture unit is used to determine the falling edge or rising edge of the square wave of the first target phase, and the occurrence time of the falling edge or rising edge is determined as the target time.

5. The method according to any one of claims 1 to 4, characterized in that The determining the optimal time interval according to the first interrupt triggering time and the clock reference time comprises: For each first interrupt triggering moment, determining the time interval between the target clock reference moment and the current first interrupt triggering moment as the initial time interval, wherein the target clock reference moment is a clock reference moment that occurs after the current first interrupt triggering moment and before the next first interrupt triggering moment; An optimal time interval is determined using the initial time interval.

6. The method according to claim 1, characterized in that The performing carrier synchronization at the carrier synchronization reference time comprises: Determine the maximum value of the time base counter value within the analog-to-digital conversion interruption period corresponding to the carrier synchronization reference time as the original maximum value; According to the change trend of the time base counter value of the built-in ePWM unit after the carrier synchronization reference moment, the maximum value of the time base counter value is updated to the target value using a preset value, and the target value is updated to the original maximum value after a preset period to complete carrier synchronization.

7. The method according to claim 6, characterized in that The method of updating the maximum value of the time base counter value to a target value using a preset value according to a change trend of the time base counter value of the built-in ePWM unit after the carrier synchronization reference time, and updating the target value to the original maximum value after a preset period to complete carrier synchronization, includes: When the time base counter value of the built-in ePWM unit shows a downward trend at the carrier synchronization reference time, the maximum value of the time base counter value is updated to a first target value in the next analog-to-digital conversion interruption cycle, and the maximum value of the time base counter value is updated to the original maximum value after a first preset cycle, wherein the first target value is the difference between the original maximum value and the preset value, and the first preset cycle is the quotient of the original maximum value and the preset value of the preset multiple analog-to-digital conversion interruption cycles; When the time base counter value of the built-in ePWM unit shows an upward trend at the carrier synchronization reference time, the maximum value of the time base counter value is updated to a second target value in the next analog-to-digital conversion interrupt cycle, and the maximum value of the time base counter value is updated to the original maximum value after the first preset cycle, wherein the second target value is the sum of the original maximum value and the preset value.

8. A carrier synchronization device without interconnection line, characterized in that: include: An interruption time determination module, used for acquiring a voltage signal of a grid connection point, and determining a first interruption triggering time according to a state of the voltage signal by using a logic state capture unit; An optimal interval module, used to determine a clock reference time corresponding to a target phase in a voltage phase by using a phase-locked loop software, and determine an optimal time interval according to the first interrupt triggering time and the clock reference time; A carrier synchronization module is used to determine the moment after the second interrupt trigger moment passes through the optimal time interval as the carrier synchronization reference moment, and perform carrier synchronization at the carrier synchronization reference moment, wherein the second interrupt trigger moment is an interrupt trigger moment determined by a logic state capture unit and is later than the first interrupt trigger moment.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the carrier synchronization method without interconnection line according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the carrier synchronization method without an interconnection line according to any one of claims 1 to 7 when executed.

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