Simple two-layer exchange method and system for communication base station management data based on FPGA (Field Programmable Gate Array)
By adopting a simple layer 2 switching method based on FPGA in the system for data management of communication base stations, the complex problem of existing system design is solved, and efficient, flexible and scalable data transmission is achieved.
Patent Information
- Application Number
- CN202510143602.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-10
- Publication Date
- 2025-05-13
AI Technical Summary
The existing communication base station management data layer 2 switching system is designed in complex and requires high professional knowledge and technical support, which increases the cost of system development and maintenance and limits the flexibility and scalability of the system.
The simple layer 2 switching method of communication base station management data based on FPGA is adopted. The data output by external devices is received through the FPGA, converted into Ethernet data in the AXI4-STREAM interface format, and the destination address matching is used by CAM memory to achieve efficient data forwarding.
It reduces the wiring complexity and system cost, improves the flexibility and scalability of the system, and realizes efficient transmission of managed data between BBU and RRU and between other communication devices.
Smart Images
Figure CN119996352A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of information technology, and in particular relates to a simple layer 2 switching method for communication base station management data based on FPGA and a system thereof. Background Art
[0002] In large communication networks, BBU (Baseband Unit) is usually used in conjunction with multiple RRUs (Remote Radio Units) to form a distributed base station architecture. In these scenarios, the BBU sends management messages to control the behavior of each RRU. Since management messages usually have a small flow, the Layer 2 switching network is widely used for data exchange and management between BBU and RRU. Through the Layer 2 switching network, the BBU can efficiently forward and process messages from different RRUs to ensure accurate data transmission and normal operation of services.
[0003] Usually, when network messages need to be forwarded, a network switch or switch chip is required. However, the protocol used between BBU and RRU in the market is not a standard Ethernet protocol, so there is no way to directly use a switch or switch chip to forward data.
[0004] Although there are some hardware-based Layer 2 switching systems currently used to exchange communication base station management data, these systems are often complex in design and require a high degree of expertise and technical support. This complexity not only increases the development and maintenance costs of the system, but also limits the flexibility and scalability of the system.
[0005] In order to solve the above technical problems, the present invention proposes a simple layer 2 switching method and system for communication base station management data based on FPGA with simple structure, easy maintenance and efficient transmission. Summary of the invention
[0006] In view of this, the purpose of the present invention is to provide a simple layer 2 switching method and system for communication base station management data based on FPGA, which can not only reduce wiring complexity and system cost, but also improve the flexibility and scalability of the system.
[0007] To achieve the above object, the present invention provides a simple layer 2 switching method for communication base station management data based on FPGA, wherein the method comprises:
[0008] FPGA receives data output by external devices;
[0009] Convert the received data into Ethernet data in AXI4-STREAM interface format;
[0010] The converted Ethernet data is stored in the FIFO, and the destination address in the Ethernet data frame in the FIFO is polled to see if it exists in the CAM memory. If so, the data is forwarded to the specified port, otherwise the data is forwarded to all ports except the polled port.
[0011] Preferably, the specific content of converting the received data into Ethernet data in the AXI4-STREAM interface format is:
[0012] Convert the data bit width to the same bit width inside the FPGA;
[0013] Encapsulate the received non-Ethernet data into an AXI4-STREAM interface format Ethernet frame;
[0014] After encapsulation is completed, the Ethernet data frame is stored in the FIFO and waits to be read.
[0015] Preferably, before forwarding the data to the designated port or to all ports except the polled port, the method further comprises: converting the Ethernet data in the AXI4-STREAM interface format into a corresponding interface format for output.
[0016] Further preferably, the forwarding method of converting the Ethernet data in the AXI4-STREAM interface format into the corresponding interface format output includes a forwarding method of broadcast data and a forwarding method of unicast data.
[0017] To achieve the above object, the present invention further provides a system using the above-mentioned FPGA-based communication base station management data simplified layer 2 switching method, wherein the system comprises:
[0018] FPGA interface, connected to external devices, used to transmit data between external devices;
[0019] An interface conversion module, connected to the FPGA interface, for converting data received by the FPGA interface into Ethernet protocol data in an AXI4-STREAM interface format;
[0020] FIFO, connected to the interface conversion module, for temporarily storing AXI4-STREAM interface format data to be exchanged;
[0021] A CAM memory, connected to the FIFO, used to use certain bits of the source MAC address in the received Ethernet data frame as the address of the memory and customize the stored data as the device interface number of the external device connected to the FPGA;
[0022] The data forwarding module is connected to the FIFO and the CAM memory respectively, and is used to take a specific bit in the MAC address of the Ethernet data header from the FIFO polled to have data as the read address of the CAM memory, and transfer the data in the FIFO to the device port according to the device port number corresponding to the obtained read address of the CAM memory.
[0023] Preferably, the FPGA interface includes an FPGA data receiving interface and an FPGA data sending interface.
[0024] Further preferably, the interface conversion module includes a receiving data encapsulation module and a sending data module, the receiving data encapsulation module is connected to the FPGA data receiving interface, and the sending data module is connected to the FPGA data sending interface.
[0025] Further preferably, the FIFO includes a receive data FIFO and a send data FIFO, the receive data FIFO is connected to the FPGA data receive interface, and the send data FIFO is connected to the FPGA data send interface.
[0026] Further preferably, the data forwarding module is connected to the receiving data FIFO and the sending data FIFO respectively.
[0027] Preferably, the FPGA interface is a UART, IIC, 1G / 10G Ethernet or PCIE interface.
[0028] The beneficial effects of the present invention are as follows: the method scheme described in the present invention includes: FPGA receives data output by an external device; converts the received data into Ethernet data in the format of an AXI4-STREAM interface; stores the converted Ethernet data in a FIFO, and polls to read whether the destination address in the Ethernet data frame in the FIFO exists in the CAM memory, and if so, forwards the data to a designated port, otherwise forwards the data to all ports except the polled port. Therefore, the present invention uses FPGA to receive data output by an external device through a specific interface, and converts it into Ethernet protocol data in the format of an AXI4-STREAM interface; FPGA is also used to implement a simple content addressable memory and to implement unicast or multicast forwarding of Ethernet data. Therefore, the technical scheme described in the embodiment of the present invention aims to utilize the high-speed parallel processing capability and programmability of FPGA to design a simple-structured, easy-to-maintain Layer 2 switching system to meet the requirements for efficient transmission of management data between BBU and RRU, and between other communication devices. In addition, the system technical solution described in the present invention not only eliminates the need for a standard RJ45 interface or optical port to be used as the interface between the external device and the FPGA, thereby only requiring data to be transmitted with the FPGA through a specific interface; it also eliminates the need to design additional Ethernet interfaces on the devices within the system for connecting to switches, thereby reducing wiring complexity and system costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to make the purpose, technical solution and beneficial effects of the present invention clearer, the present invention provides the following drawings for illustration:
[0030] Figure 1 A schematic diagram of the basic flow of a simplified layer 2 switching method for communication base station management data based on FPGA according to the first embodiment of the present invention;
[0031] Figure 2 for Figure 1 A schematic diagram of the specific process of step S20 described in;
[0032] Figure 3 A schematic diagram of a data forwarding method of a simple layer 2 switching method for communication base station management data based on FPGA according to the first embodiment of the present invention;
[0033] Figure 4 This is a schematic diagram of the structure of a simple layer-2 switching system for communication base station management data based on FPGA according to the second embodiment of the present invention. DETAILED DESCRIPTION
[0034] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0035] Terminology explanation:
[0036] BBU (Baseband Unit) is an important component in wireless communication systems. It is mainly used to process the baseband part of radio signals. In wireless communication, information is first modulated into a form suitable for transmission, that is, a radio frequency (RF) signal, and then transmitted through the antenna; the receiving end is the opposite, first receiving the RF signal through the antenna, and then demodulating it back to the original information. The unmodulated signal or low-frequency signal involved in this process is called the baseband signal.
[0037] RRU (Remote Radio Unit) is one of the key components in wireless communication systems, mainly responsible for processing high-frequency radio frequency signals. It is usually paired with the baseband processing unit (BBU) to complete the task of sending and receiving radio signals.
[0038] FPGA (Field-Programmable Gate Array) is a highly flexible integrated circuit that users can configure through programming after manufacturing. Its application in communication equipment also includes but is not limited to baseband processing units (BBU), radio remote units (RRU), and network infrastructure such as routers and switches.
[0039] CAM (Content-Addressable Memory) is a special type of memory in which data is searched for a match by providing the data itself or part of its content. In other words, CAM can search all its storage locations in parallel and return the addresses of all entries that match the provided data.
[0040] FIFO (First In First Out) is a special storage structure used to temporarily store data items until they are processed or transmitted. It follows the "first in, first out" principle, that is, the data items that enter the buffer earliest will be removed and processed first.
[0041] The AXI4-STREAM interface format is an efficient streaming data transmission interface. AXI4-STREAM is a member of the AMBA (Advanced Microcontroller Bus Architecture) protocol family proposed by ARM, and is specially designed for high-speed, low-latency streaming data transmission.
[0042] When transmitting data in a communication base station, it is usually necessary to forward network messages, which requires the use of a network switch or switch chip. However, the protocol used between the BBU and RRU on the market is not a standard Ethernet protocol, so there is no way to directly use a switch or switch chip to forward data. Although there are currently some hardware-based Layer 2 switching systems used for the exchange of communication base station management data, these systems are often complex in design and require a high degree of expertise and technical support. This complexity not only increases the development and maintenance costs of the system, but also limits the flexibility and scalability of the system. In view of this, the present invention proposes a simple Layer 2 switching method and system for communication base station management data based on FPGA, which has a simple structure, is easy to maintain, and has efficient transmission.
[0043] Implementation
[0044] like Figure 1 As shown, an embodiment of the present invention provides a simple layer 2 switching method for communication base station management data based on FPGA, wherein the method includes:
[0045] Step S10: FPGA receives data output by an external device.
[0046] It should be noted that FPGA receives data output by external devices through interfaces that match the external devices. Due to the programmable nature of FPGA, it can support a variety of interfaces, such as UART (Universal Asynchronous Receiver / Transmitter), IIC (Inter-Integrated Circuit), 1G / 10G Ethernet, PCIE (peripheral component interconnect express) and other interfaces. It is necessary to use the corresponding IP core or the corresponding code to describe the circuit behavior according to the actual situation to receive the data output by the external device.
[0047] Step S20: Convert the received data into Ethernet data in the AXI4-STREAM interface format.
[0048] It should be noted that, since the data bit width and data clock domain of multiple external device interfaces may be inconsistent, it is necessary to convert the data bit width to the same bit width inside the FPGA according to the actual situation, and encapsulate the received non-Ethernet data into an Ethernet frame in the AXI4-STREAM interface format. After encapsulation, the Ethernet data frame is stored in the FIFO and waits to be read. Figure 2 As shown, in the embodiment of the present invention, the specific content of converting the received data into Ethernet data in the AXI4-STREAM interface format is:
[0049] Step S21: Convert the data bit width into the same bit width inside the FPGA.
[0050] Specifically, in FPGA (Field-Programmable Gate Array) design, it is sometimes necessary to convert data streams of different bit widths to the same target bit width. This usually happens when data is transferred from one module to another, or when the bit width of the external interface does not match the bit width of the internal processing unit. In order to achieve this bit width conversion, a variety of methods and techniques can be used, and the common implementation methods are as follows:
[0051] 1) For the case of converting from a smaller bit width to a larger bit width, the data width can be increased by adding zero padding or sign extension. For example, if 8-bit data needs to be converted to 32 bits, 24 zeros can be filled in the high position or the most significant bit (MSB) can be copied to maintain the sign. Or when the source data bit width is smaller than the target bit width, multiple source data packets can be collected and merged into a wider data packet. This method is suitable for streaming data transmission, especially in the AXI4-STREAM protocol. Use handshake signals such as TVALID and TREADY to ensure that all parts are received correctly before being combined together.
[0052] 2) If the source data width is larger than the target data width, the large-width data can be segmented into multiple small-width data packets and sent in sequence. Similarly, handshake signals are used to ensure that each segment can be correctly received.
[0053] Step S22: encapsulate the received non-Ethernet data into an AXI4-STREAM interface format Ethernet frame.
[0054] It should be noted that the received non-Ethernet data is constructed according to the Ethernet protocol specification and encapsulated into data that can be sent through the AXI4-STREAM interface. Usually, a complete Ethernet frame usually contains the following seven parts: Preamble: 7 bytes, used to synchronize the receiving end clock; Start Frame Delimiter (SFD): 1 byte, indicating the start of the frame; Destination MAC Address: 6 bytes; Source MAC Address: 6 bytes; Type / Length Field (Type / Length): 2 bytes, used to identify the upper layer protocol or indicate the payload length; Data Payload: 46 to 1500 bytes, depending on the specific application; Frame Check Sequence (FCS): 4 bytes, used for error detection.
[0055] Step S23: After encapsulation is completed, the Ethernet data frame is stored in the FIFO to wait for being read.
[0056] Specifically, in order to process data streams of different rates or solve the problem of mismatched bit widths, the embodiment of the present invention adds a buffer FIFO before and after the conversion logic. FIFO can not only provide temporary storage space, but also play a synchronization role, which is particularly useful when transferring data between asynchronous clock domains.
[0057] Step S30, storing the converted Ethernet data in the FIFO, and polling to see whether the destination address in the Ethernet data frame in the FIFO exists in the CAM memory, if so, forwarding the data to the designated port, otherwise forwarding the data to all ports except the polled port.
[0058] Specifically, the FIFO storing the converted Ethernet data of each interface is polled, and when a FIFO with data is polled, the Ethernet data in the FIFO is taken out and the polling is stopped. When the Ethernet data is taken out, the source address of the converted Ethernet data header message is used as the address of the CAM memory, and the port receiving the data is written into the memory as the data of the CAM memory. The destination address of the Ethernet data header is used as the address of the CAM memory, and the data stored at the corresponding address is read from the CAM memory. If the stored value is 0, the data is broadcast to all ports except the polled port. If the stored value is not 0, the data is forwarded to the specified port. After the forwarding is completed, each FIFO is polled continuously, and the above process is repeated to realize data forwarding.
[0059] In the embodiment of the present invention, before forwarding the data to the designated port or to all ports except the polled port, the method further includes: converting the Ethernet data in the AXI4-STREAM interface format into a corresponding interface format for output.
[0060] Specifically, after each interface receives the forwarded data, it needs to extract the original data from the Ethernet data encapsulated in the AXI4-STREAM interface format and send the original data to the external device at the other end of the interface according to the data format required by the interface. Figure 3 As shown, in the implementation of the present invention, the forwarding method of converting the Ethernet data in the AXI4-STREAM interface format into the corresponding interface format output includes a forwarding method of broadcast data and a forwarding method of unicast data, which are specifically described as follows:
[0061] Inside the FPGA, external device 1 outputs data to the FPGA through the FPGA data receiving interface, and then passes the data through the receiving data encapsulation module and the receiving data FIFO in turn, and is unidirectionally connected to the data forwarding module, and is transmitted to the respective sending data FIFOs, sending data modules and the FPGA sending and receiving interface to external device 5, external device 6, external device 7 and external device 8 through the forwarding method of broadcast data. Inside the FPGA, external device 6 outputs data to the FPGA through the FPGA data receiving interface, and then passes the data through the receiving data encapsulation module and the receiving data FIFO in turn, and is unidirectionally connected to the data forwarding module, and is transmitted to the sending data FIFO, the sending data module and the FPGA sending and receiving interface to external device 3 through the forwarding method of unicast data.
[0062] Therefore, the technical solution described in the present invention includes: FPGA receives data output by an external device; converts the received data into Ethernet data in the format of an AXI4-STREAM interface; stores the converted Ethernet data in a FIFO, and polls to read whether the destination address in the Ethernet data frame in the FIFO exists in the CAM memory, and if so, forwards the data to a designated port, otherwise forwards the data to all ports except the polled port. Therefore, the present invention uses FPGA to receive data output by an external device through a specific interface, and converts it into Ethernet protocol data in the format of an AXI4-STREAM interface; FPGA is also used to implement a simple content addressable memory and to implement unicast or multicast forwarding of Ethernet data. Therefore, the technical solution described in the embodiment of the present invention aims to utilize the high-speed parallel processing capability and programmability of FPGA to design a simple-structured, easy-to-maintain Layer 2 switching system to meet the requirements for efficient transmission of management data between BBU and RRU, and between other communication devices.
[0063] Embodiment 2
[0064] like Figure 4 As shown, an embodiment of the present invention further provides a system using the above-mentioned FPGA-based communication base station management data simplified layer 2 switching method, wherein the system includes:
[0065] FPGA interface 100, connected to an external device, for transmitting data with the external device;
[0066] The interface conversion module 200 is connected to the FPGA interface 100 and is used to convert the data received by the FPGA interface 100 into Ethernet protocol data in the AXI4-STREAM interface format;
[0067] FIFO300, connected to the interface conversion module 200, for temporarily storing AXI4-STREAM interface format data to be exchanged;
[0068] A CAM memory 400, connected to the FIFO 300, is used to use certain bits of the source MAC address in the received Ethernet data frame as the address of the memory and customize the stored data as the device interface number of the external device connected to the FPGA;
[0069] The data forwarding module 500 is connected to the FIFO 300 and the CAM memory 400 respectively, and is used to take a specific bit in the MAC address of the Ethernet data header from the FIFO 300 polled to have data as the read address of the CAM memory 400, and transfer the data in the FIFO 300 to the device port according to the device port number corresponding to the read address of the CAM memory 400 obtained.
[0070] In an embodiment of the present invention, the FPGA interface 100 includes an FPGA data receiving interface and an FPGA data sending interface. The interface conversion module 200 includes a receiving data encapsulation module and a sending data module, the receiving data encapsulation module is connected to the FPGA data receiving interface, and the sending data module is connected to the FPGA data sending interface. The FIFO 300 includes a receiving data FIFO and a sending data FIFO, the receiving data FIFO is connected to the FPGA data receiving interface, and the sending data FIFO is connected to the FPGA data sending interface. The data forwarding module 500 is connected to the receiving data FIFO and the sending data FIFO respectively. The FPGA interface 100 is a UART, IIC, 1G / 10G Ethernet or PCIE interface.
[0071] In order to better understand the technical solution described in the embodiment of the present invention, the following is a detailed description:
[0072] The simple layer 2 Ethernet data exchange system provided by the present invention is composed of an external device interface, an interface conversion module, a storage module, a simple CAM (content addressable memory) and a data exchange module. The external device interface is a connection medium between FPGA and external devices, and FPGA can obtain data output by external devices through this interface, and the interface does not need to be a standard Ethernet interface; the interface conversion module will convert the data received by the external device interface into AXI4-STREAM interface format Ethernet protocol data, and will also convert the exchanged AXI4-STREAM interface format Ethernet protocol data into original data output, and the storage module is used to temporarily store the AXI4-STREAM interface format data to be exchanged; the address of the CAM is certain bits of the source MAC address in the received Ethernet data frame as the address of the memory, and the stored data is the device interface number of the self-defined external device connected to the FPGA; the data exchange module will forward data according to the data stored in the CAM and the destination MAC address of the Ethernet data in the storage module.
[0073] Therefore, the technical solution described in the present invention includes an FPGA interface 100 connected to an external device, an interface conversion module 200, a FIFO300, a CAM memory 400 and a data forwarding module 500, wherein the FPGA interface 100 is used to transmit data between external devices, and the interface conversion module 200 is connected to the FPGA interface 100, and is used to convert the data received by the FPGA interface 100 into Ethernet protocol data in the AXI4-STREAM interface format or convert; the FIFO300 is connected to the interface conversion module 200, and is used to temporarily store the AXI4-STREAM interface format data to be exchanged; the CAM memory 400 is connected to the FIFO300, and is used to use certain bits of the source MAC address in the received Ethernet data frame as the address of the memory and customize the stored data as the device interface number of the external device connected to the FPGA; the data forwarding module 500 is respectively connected to the FIFO300 and the CAM memory 400, and is used to forward the data stored in the CAM memory 400 and the destination MAC address of the Ethernet data in the FIFO300. Therefore, the present invention not only eliminates the need for a standard RJ45 interface or optical port to be used as the interface between the external device and the FPGA, thereby only requiring data to be transmitted with the FPGA through a specific interface; it also eliminates the need to design additional Ethernet interfaces on the devices within the system for connecting to switches, thereby reducing wiring complexity and system costs.
[0074] The above is a detailed introduction to a simple layer 2 switching method for communication base station management data based on FPGA and its system provided by the present application. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.
[0075] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or terminal including the element.
[0076] Finally, it should be noted that the above preferred embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail through the above preferred embodiments, those skilled in the art should understand that various changes can be made in form and details without departing from the scope defined by the claims of the present invention.
Claims
1. A simple layer 2 switching method for communication base station management data based on FPGA, characterized in that: The method includes: FPGA receives data output by external devices; Convert the received data into Ethernet data in AXI4-STREAM interface format; The converted Ethernet data is stored in the FIFO, and the destination address in the Ethernet data frame in the FIFO is polled to see if it exists in the CAM memory. If so, the data is forwarded to the specified port, otherwise the data is forwarded to all ports except the polled port.
2. According to claim 1, the method for simplified layer 2 switching of communication base station management data based on FPGA is characterized in that: The specific content of converting the received data into Ethernet data in AXI4-STREAM interface format is: Convert the data bit width to the same bit width inside the FPGA; Encapsulate the received non-Ethernet data into an AXI4-STREAM interface format Ethernet frame; After encapsulation is completed, the Ethernet data frame is stored in the FIFO and waits to be read.
3. According to claim 1, the method for simplified layer 2 switching of communication base station management data based on FPGA is characterized in that: Before forwarding the data to the designated port or to all ports except the polled port, the method further includes: converting the Ethernet data in the AXI4-STREAM interface format into a corresponding interface data format for output.
4. According to claim 3, the method for simplified layer 2 switching of communication base station management data based on FPGA is characterized in that: The forwarding method of converting Ethernet data in the AXI4-STREAM interface format into the corresponding interface format for output includes a forwarding method for broadcast data and a forwarding method for unicast data.
5. A system using the FPGA-based simplified layer 2 switching method for communication base station management data as claimed in any one of claims 1 to 4, characterized in that: The system includes: FPGA interface, connected to external devices, used to transmit data between external devices; An interface conversion module, connected to the FPGA interface, for converting data received by the FPGA interface into Ethernet protocol data in an AXI4-STREAM interface format; FIFO, connected to the interface conversion module, for temporarily storing AXI4-STREAM interface format data to be exchanged; A CAM memory, connected to the FIFO, used to use certain bits of the source MAC address in the received Ethernet data frame as the address of the memory and customize the stored data as the device interface number of the external device connected to the FPGA; The data forwarding module is connected to the FIFO and the CAM memory respectively, and is used to take a specific bit in the MAC address of the Ethernet data header from the FIFO polled to have data as the read address of the CAM memory, and transfer the data in the FIFO to the device port according to the device port number corresponding to the obtained read address of the CAM memory.
6. According to claim 5, the FPGA-based communication base station management data simple layer 2 switching system is characterized in that: The FPGA interface includes an FPGA data receiving interface and an FPGA data sending interface.
7. The FPGA-based simple layer 2 switching system for communication base station management data according to claim 6 is characterized in that: The interface conversion module includes a receiving data encapsulation module and a sending data module. The receiving data encapsulation module is connected to the FPGA data receiving interface, and the sending data module is connected to the FPGA data sending interface.
8. According to claim 6, the FPGA-based communication base station management data simple layer 2 switching system is characterized in that: The FIFO includes a receiving data FIFO and a sending data FIFO. The receiving data FIFO is connected to the FPGA data receiving interface, and the sending data FIFO is connected to the FPGA data sending interface.
9. The FPGA-based simple layer 2 switching system for communication base station management data according to claim 6 is characterized in that: The data forwarding module is connected to the receiving data FIFO and the sending data FIFO respectively.
10. The FPGA-based simple layer 2 switching system for communication base station management data according to claim 5 is characterized in that: The FPGA interface is a UART, IIC, 1G / 10G Ethernet or PCIE interface.