Data transmission method and device and electronic equipment

Abstract

The invention provides a data transmission method and device and electronic equipment, and relates to the technical field of data transmission, and the data transmission method comprises the steps: obtaining to-be-sent data, and sequentially writing the to-be-sent data into a cache region which comprises at least one layer of cache unit; receiving space indication information of the cache region, wherein the space indication information is used for indicating the residual storage space of the cache region; and in response to the situation that the space indication information indicates that the residual storage space of the cache region is empty, the cache data in each layer of cache unit in the cache region is sent layer by layer, so that efficient data transmission is realized.

Description

Technical Field

[0001] The present application relates to the technical field of data transmission, and in particular to a data transmission method, device and electronic equipment. Background Art

[0002] In the development and debugging of industrial real-time control systems such as power electronics and motor control, researchers need to know the real-time data of various key parameters in order to analyze the characteristics of the system or locate the cause of the fault. Generally, the data variables in the main control chip are transmitted to the host computer through the industrial protocol, and a visual waveform is drawn.

[0003] Industrial real-time control systems generally use interrupt control. In high-switching-frequency digital power supplies and motor control systems, the interrupt frequency can reach 300kHz or even above 1MHz. At such a high frequency, the effective execution time of the interrupt is only a few microseconds, and the chip CPU load is high, requiring a high variable upload speed. General industrial communication protocols cannot meet the needs of high-speed upload, and the data transmission effect is poor. Summary of the invention

[0004] The present application aims to solve one of the technical problems in the related art at least to some extent.

[0005] To this end, the first objective of the present application is to propose a data transmission method to achieve efficient and secure data transmission.

[0006] The second objective of the present application is to provide a data transmission device.

[0007] The third objective of the present application is to provide an electronic device.

[0008] A fourth objective of the present application is to provide a computer-readable storage medium.

[0009] A fifth object of the present application is to provide a computer program product.

[0010] To achieve the above-mentioned purpose, the first aspect of the present application proposes a data transmission method, which is executed by a chip and includes:

[0011] Acquire data to be sent, and write the data to be sent into a cache area in sequence, wherein the cache area includes at least one layer of cache units;

[0012] Receiving space indication information of the cache area, where the space indication information is used to indicate remaining storage space of the cache area;

[0013] In response to the space indication information indicating that the remaining storage space of the cache area is empty, the cache data in the cache units of each layer in the cache area are sent layer by layer.

[0014] To achieve the above-mentioned purpose, the second aspect of the present application proposes another data transmission method, which is executed by a host computer and includes:

[0015] receiving at least two cache data of each layer of cache units sent by the chip;

[0016] The at least two cached data are compared and verified, and in response to the at least two cached data being completely consistent, any cached data of the cache unit is selected for display.

[0017] To achieve the above-mentioned purpose, the third aspect of the present application provides a data transmission device, which is executed by a chip and includes:

[0018] A cache module, used to obtain data to be sent, and write the data to be sent into a cache area in sequence, wherein the cache area includes at least one layer of cache units;

[0019] A receiving module, used for receiving space indication information of the buffer area, where the space indication information is used for indicating the remaining storage space of the buffer area;

[0020] The sending module is used for sending the cache data in the cache units of each layer in the cache area layer by layer in response to the space indication information indicating that the remaining storage space of the cache area is empty.

[0021] To achieve the above-mentioned purpose, the fourth aspect of the present application proposes another data transmission device, which is executed by a host computer and includes:

[0022] A receiving module, used for receiving at least two cache data of each layer of cache unit sent by the chip;

[0023] The display module is used to compare and verify the at least two cached data, and in response to the at least two cached data being completely consistent, select any cached data of the cache unit for display.

[0024] To achieve the above-mentioned purpose, a fifth aspect of the present application provides an electronic device, including: a processor, and a memory communicatively connected to the processor;

[0025] The memory stores computer-executable instructions;

[0026] The processor executes the computer-executable instructions stored in the memory to implement the method described in any one of the first aspect or the second aspect.

[0027] To achieve the above-mentioned purpose, the sixth aspect embodiment of the present application proposes a computer-readable storage medium, in which computer execution instructions are stored. When the computer execution instructions are executed by a processor, they are used to implement the method described in any one of the first aspect or the second aspect.

[0028] To achieve the above-mentioned purpose, the seventh aspect of the present application proposes a computer program product, including a computer program, which implements the method described in any one of the first aspect or the second aspect when executed by a processor.

[0029] The data transmission method, device and electronic device provided in the present application cache the data to be sent through the cache area in the chip, cache the data to be sent based on the multi-layer cache units in the cache area, and send the cached data in the order of the cache units when the cache area is full, thereby improving the speed and efficiency of data transmission.

[0030] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0032] Figure 1 A flowchart of a data transmission method provided in an embodiment of the present application;

[0033] Figure 2 A flowchart of another data transmission method provided in an embodiment of the present application;

[0034] Figure 3 An interactive schematic diagram of a data transmission method provided in an embodiment of the present application;

[0035] Figure 4 A schematic diagram of the structure of a data transmission device provided in an embodiment of the present application;

[0036] Figure 5 A schematic diagram of the structure of a data transmission device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0038] The data transmission method, device and electronic device according to the embodiments of the present application are described below with reference to the accompanying drawings.

[0039] Figure 1 The following is a flow chart of a data transmission method provided in an embodiment of the present application. Figure 1As shown, the data transmission method is executed by the chip and includes the following steps:

[0040] S101, obtaining data to be sent, and writing the data to be sent into a buffer area in sequence.

[0041] In some implementations, the chip may be an integrated circuit with a central processing unit (CPU) or equivalent functions, such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), a microcontroller unit (MCU), a field programmable gate array (FPGA), etc.

[0042] Optionally, the data to be sent in the chip can be data collected by analog peripherals, for example, by sampling the external circuit voltage through an analog-to-digital converter (ADC) through analog input / output (I / O) to obtain a digital value of the corresponding number of bits, and the data is stored in a register inside the chip.

[0043] Optionally, the data to be sent in the chip can be data received by a communication peripheral, such as a Universal Synchronous Asynchronous Receiver Transmitter (USART), a Serial Peripheral Interface (SPI) or other communication peripherals, and the received data is stored in a register inside the chip.

[0044] Optionally, the data to be sent in the chip can also be a value calculated by a user program, and its format includes integer, floating point and Boolean value, etc. The data is stored in a register inside the chip.

[0045] In some implementations, the chip can extract the data to be sent from the register during an interruption, and write the data to be sent into the cache area in sequence, and the data updated during subsequent interruptions are also written in sequence in sequence; an interruption refers to the process in which the CPU temporarily suspends the current processing when processing an event because another more urgent or more demanding event occurs, and switches to processing a new event. After the new event is processed, the CPU will return to the place where it was originally suspended to continue execution. This embodiment can also obtain the data to be sent by setting an interruption at a fixed time, that is, performing an interrupt at a fixed time, and reading data from the register during the interruption to increase the data processing speed.

[0046] In some implementations, the cache area can be located in a storage medium that supports real-time writing within the chip, and small areas can be written independently, and the refresh frequency domain is not much different from the main frequency of the chip, such as random access memory (RAM); the cache area includes at least one layer of cache units, and the size of each layer of cache units can be determined based on the display situation of the host computer. For example, if the host computer can display 100 data at a time, the maximum storage capacity of a single-layer cache unit is the bit length (bit length) of storing 100 data, so as to ensure that each layer of cache units can be displayed smoothly after being sent to the host computer.

[0047] In some implementations, each data type corresponds to an independent cache area. For example, different data types such as temperature, humidity, and pressure correspond to independent cache areas. In some implementations, different position data of the same type, such as the first pressure and the second pressure corresponding to the top and bottom of the device, respectively, also correspond to independent cache areas to avoid data confusion and achieve better data caching and analysis effects.

[0048] It can be understood that when the data to be sent is written into the cache area, it is written starting from the first-layer cache unit of the cache area, that is, the data to be sent is first stored in the first-layer cache unit. After there is no free storage space in the first-layer cache unit, the subsequent data to be sent is stored in the second-layer cache unit in sequence until the storage space of the second-layer cache unit is zero, and so on. The data to be sent is stored in sequence from top to bottom in the cache units until the data to be sent is completely stored in the cache area, or the remaining storage space of all cache units in the cache area is zero.

[0049] S102, receiving space indication information of the buffer area.

[0050] In some implementations, each layer of cache unit can send a corresponding full storage signal when the storage space is zero, and the full storage signal is used to indicate that the storage space of the corresponding cache unit is zero; optionally, the cache area can send space indication information in real time, and the space indication information is used to indicate the remaining storage space of the cache area, that is, according to the space indication information, it can be determined whether the cache units in each layer of the cache area are full.

[0051] In some implementations, the storage information of each layer of cache units can also be displayed in a register. For example, if the cache area includes n layers of cache units, the register includes indication information of n positions. When the cache unit sends a full storage signal, the indication information at the corresponding position in the register is modified to full storage information. For example, the indication information in the register is 0 or 1, 0 indicates not full, and 1 indicates full. After determining that the cache unit sends a full storage signal, the indication information at the corresponding position in the register changes from 0 to 1, so as to more intuitively monitor the storage status in the cache area.

[0052] S103 , in response to the space indication information indicating that the remaining storage space of the cache area is empty, sending the cache data in the cache units of each layer in the cache area layer by layer.

[0053] It can be understood that when the space indication information indicates that the remaining storage space of the cache area is empty, it means that all cache units in the cache area are full, and the data to be sent will no longer be written into the buffer, and the chip starts to send a signal to indicate that data can be sent; optionally, data can be sent through communication peripherals or communication protocols to send the data in the buffer to the host computer.

[0054] In some implementations, data sending can start from the first layer of cache units in the cache area, and after all the data of the first layer of cache units are sent, the second layer of cache units are sent, and so on until all the data of the nth layer of cache units are sent; optionally, after the data of each layer of cache units are sent, the indication of the corresponding position of the cache unit in the register can be changed from 1 to 0, indicating that the current cache unit is empty.

[0055] In some implementations, the response signals of cache units at each layer can be monitored, and the response signals are used to indicate whether the cache data of the corresponding cache unit has been sent. In response to monitoring the response signals of all cache units in the cache area, the response signals of the cache units at each layer in the cache area are reset. That is, after determining that the data of all cache units in the cache area have been sent successfully, the response signals are reset so that the response signals can be sent again in subsequent transmissions. The response signal can be an indication signal of a corresponding position in a register, and resetting the response signal means changing the indication signal of the corresponding cache unit in the register.

[0056] In some implementations, after listening to the response signal of each layer of cache unit, the remaining data to be sent can be written into the cache unit that has been sent in sequence until all the data to be sent is written, or the space indication information of the cache area is received again to indicate that the remaining storage space is empty; for example, assuming that after listening to the response signal of the first layer of cache unit, indicating that the data of the first layer of cache unit has been sent, the data of the second layer of cache unit will continue to be sent, and while sending the data of the second layer of cache unit, the remaining data to be sent will continue to be written into the first layer of cache unit that has been sent. After the data of the second layer of cache unit is sent, the data of the third layer of cache unit will continue to be sent and the remaining data to be sent will be written into the second layer of cache unit that has been sent in sequence, and so on. While sending layer by layer, the remaining data to be sent will be written into the cache unit that has been sent layer by layer to improve data sending efficiency.

[0057] Optionally, in response to monitoring a response signal from the bottom-level cache unit in the cache area, identify whether there is cache data in the first-level cache unit of the cache area; in response to the presence of cache data in the first-level cache unit, send the cache data in each level of cache unit layer by layer and monitor the response signals of each level of cache units.

[0058] That is to say, after determining that the cache data of the nth layer cache unit in the cache area has been sent, it is again identified whether there is cache data in the first layer cache unit. If there is newly written cache data in the first layer cache unit, the cache data will continue to be sent from the first layer, and the response signals of the cache units of each layer will be listened to in turn to determine the data sending status of the cache unit.

[0059] In some implementations, the cached data of the cache units to be sent layer by layer can also be backed up to obtain at least two copies of the cached data; for example, two universal synchronous / asynchronous serial receiver / transmitters (USART) peripherals are used simultaneously for data transmission to achieve dual backup redundant communication of the cached data, and at least two copies of the cached data are sent simultaneously. The effective levels of the two USART peripherals are defined in opposite ways to improve the anti-interference ability during data transmission.

[0060] In this embodiment, data to be sent is obtained and written into a cache area in sequence. The cache area includes one or more layers of cache units to improve the caching speed of the data to be sent. Space indication information of the cache area is received in real time. When the space indication information indicates that the remaining storage space of the cache area is zero, the cached data in the cache area is sent, starting from the first layer of cache units in the cache area. After one layer of cache units is sent, new data to be sent is written to improve data transmission efficiency. The cached data can also be backed up to realize dual backup redundant communication of the cached data, improve the anti-interference ability during data transmission, and realize efficient and accurate data transmission.

[0061] Based on the above embodiments, Figure 2 A flow chart of another data transmission method provided in an embodiment of the present application. Figure 2 As shown, the method is executed by the host computer and includes the following steps:

[0062] S201, receiving at least two cache data of each layer of cache unit sent by a chip.

[0063] Optionally, the host computer is a computer device with strong data processing capabilities and control functions, and can at least perform the functions of data reception, verification and display.

[0064] It is understandable that the cache data in the cache unit can be backed up before sending, thereby obtaining at least two copies of the cache data, and sending the cache data to the host computer according to their respective communication peripherals, thereby achieving the reception of at least two copies of the cache data for each layer of cache unit.

[0065] S202, comparing and verifying at least two cached data, and in response to at least two cached data being completely consistent, selecting any cached data of the cache unit for display.

[0066] In some implementations, data frames or data units of at least two cached data can be verified, that is, the same data frames in the two cached data can be compared and verified, for example, using a cyclic redundancy check (CRC) to verify the data frames to ensure that the received cached data is correct and without interference. When it is determined that at least two cached data are completely consistent, it means that the current cached data is received correctly, and the cached data of the cache unit is displayed.

[0067] Optionally, the cached data can be sampled for display, for example, 5 seconds of cached data can be randomly sampled for display refresh to observe changes in the data, thereby achieving continuous visualization of high switching frequency real-time control system variables, facilitating performance parameter debugging and fault analysis by technical personnel, and supporting data refresh at a maximum of MHz level, with no requirements for the communication protocol rate.

[0068] In response to at least two cached data being not completely consistent, at least two cached data of the next layer of cache units are judged, and the completely consistent cached data are displayed; that is, when there is inconsistency or error in data verification, the cached data of this layer is discarded to avoid resource occupation by erroneous data, the upper computer does not refresh the data, keeps the data display of the previous layer of cache units, receives the cached data of the next layer of cache units and verifies the cached data until all the cached data are received and refreshed and displayed in turn.

[0069] Optionally, the data refresh interval is maintained at least for several seconds to ensure that the human eye can distinguish the specific data waveform.

[0070] In this embodiment, the host computer can receive the cache data of each layer of cache units, and perform data frame verification and comparison based on at least two cache data to ensure the correctness of the received cache data, which greatly improves the communication reliability and data accuracy of the industrial host computer. The received cache data of each layer is displayed to facilitate observation of data changes. When it is identified that there are errors in the received cache data, the cache data of the next layer of cache units is received and displayed, which maximizes the data transmission efficiency without affecting data analysis and greatly improves the refresh rate of the host computer interface.

[0071] Figure 3 The following is an interactive diagram of a data transmission method provided in an embodiment of the present application. Figure 3 Said method comprises:

[0072] S301, the chip obtains the data to be sent, and writes the data to be sent into the buffer area in sequence.

[0073] In the embodiment of the present application, the implementation method of step S301 can be implemented by any of the methods in the embodiments of the present disclosure, which is not limited here and will not be repeated.

[0074] S302, receiving space indication information of the buffer area.

[0075] In the embodiment of the present application, the implementation method of step S302 can be implemented by any of the methods in the embodiments of the present disclosure, which is not limited here and will not be repeated.

[0076] S303 , in response to the space indication information indicating that the remaining storage space of the cache area is empty, sending the cache data in the cache units of each layer in the cache area layer by layer.

[0077] In the embodiment of the present application, the implementation method of step S303 can be implemented by any of the methods in the embodiments of the present disclosure, which is not limited here and will not be repeated.

[0078] S304, the host computer receives at least two cache data of each layer of cache unit sent by the chip.

[0079] In the embodiment of the present application, the implementation method of step S304 can be implemented by any of the methods in the embodiments of the present disclosure, which is not limited here and will not be repeated.

[0080] S305 , comparing and verifying at least two cached data, and in response to at least two cached data being completely consistent, selecting any cached data of the cache unit for display.

[0081] In the embodiment of the present application, the implementation method of step S305 can be implemented by any of the methods in the embodiments of the present disclosure, which is not limited here and will not be repeated.

[0082] In an embodiment of the present application, the chip obtains the data to be sent and writes the data to be sent into a cache area in sequence. The cache area includes one or more layers of cache units to improve the caching speed of the data to be sent, and receives the space indication information of the cache area in real time. When the space indication information indicates that the remaining storage space of the cache area is zero, the cached data in the cache area is sent, starting from the first layer of cache units in the cache area, and sending them to the host computer layer by layer, and writing new data to be sent after one layer of cache units is sent, thereby improving the data transmission efficiency. The cached data can also be backed up to achieve dual backup redundant communication of the cached data, thereby improving the anti-interference ability during data transmission. The host computer receives the cached data of each layer of cache units, and performs data frame verification and comparison based on at least two copies of the cached data to ensure the correctness of the reception of the cached data, and displays the received cached data of each layer to facilitate observation of data changes. When it is identified that there is an error in the received cached data, the cached data of the next layer of cache units is received and displayed, thereby maximizing the data transmission efficiency without affecting data analysis, and greatly improving the refresh rate of the host computer interface.

[0083] In order to implement the above embodiments, the present application also proposes a data transmission device.

[0084] Figure 4 A schematic diagram of a data transmission device provided in an embodiment of the present application is shown in FIG. Figure 4As shown, the data transmission device 400 is executed by a chip, and includes:

[0085] The cache module 401 is used to obtain the data to be sent and write the data to be sent into the cache area in sequence, and the cache area includes at least one layer of cache units;

[0086] A receiving module 402 is used to receive space indication information of a buffer area, where the space indication information is used to indicate the remaining storage space of the buffer area;

[0087] The sending module 403 is used to send the cache data in the cache units of each layer in the cache area layer by layer in response to the space indication information indicating that the remaining storage space of the cache area is empty.

[0088] Further, in a possible implementation of the embodiment of the present application, the sending module 403 includes:

[0089] Monitor the response signals of the cache units at each layer, where the response signals are used to indicate whether the cache data of the corresponding cache unit has been sent;

[0090] In response to monitoring the response signals of all cache units in the cache area, the response signals of the cache units at each layer in the cache area are reset.

[0091] Furthermore, in a possible implementation of the embodiment of the present application, the apparatus 400 further includes:

[0092] After monitoring the response signal of each layer of cache unit, the remaining data to be sent is written into the cache unit that has been sent in sequence until all the data to be sent is written, or the space indication information of the cache area is received again to indicate that the remaining storage space is empty.

[0093] Furthermore, in a possible implementation of the embodiment of the present application, the apparatus 400 further includes:

[0094] In response to monitoring a response signal of the lowest level cache unit in the cache area, identifying whether cache data exists in the first level cache unit of the cache area;

[0095] In response to the existence of cache data in the first-layer cache unit, the cache data in the cache units of each layer are sent layer by layer and the response signals of the cache units of each layer are monitored.

[0096] Furthermore, in a possible implementation of the embodiment of the present application, the apparatus 400 further includes:

[0097] Backing up the cache data of the cache units to be sent layer by layer to obtain at least two copies of the cache data;

[0098] At least two copies of cached data are sent simultaneously.

[0099] It should be noted that the above explanation of the data transmission method embodiment is also applicable to the data transmission device of this embodiment, and will not be repeated here.

[0100] In an embodiment of the present application, data to be sent is obtained and written into a cache area in sequence. The cache area includes one or more layers of cache units to improve the caching speed of the data to be sent. Space indication information of the cache area is received in real time. When the space indication information indicates that the remaining storage space of the cache area is zero, the cached data in the cache area is sent, starting from the first layer of cache units in the cache area. After one layer of cache units is sent, new data to be sent is written to improve data transmission efficiency. The cached data can also be backed up to realize dual backup redundant communication of the cached data, improve the anti-interference ability during data transmission, and realize efficient and accurate data transmission.

[0101] Figure 5 A schematic diagram of a data transmission device provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the data transmission device 500 is executed by a host computer and includes:

[0102] The receiving module 501 is used to receive at least two cache data of each layer of cache unit sent by the chip;

[0103] The display module 502 is used to compare and verify at least two cached data, and in response to at least two cached data being completely consistent, select any cached data of the cache unit for display.

[0104] Furthermore, in a possible implementation of the embodiment of the present application, the apparatus 500 further includes:

[0105] In response to at least two cached data being not completely consistent, at least two cached data of a next-level cache unit are judged, and cached data that are completely consistent are displayed.

[0106] In an embodiment of the present application, the upper computer can receive the cache data of each layer of cache units, and perform data frame verification and comparison based on at least two cache data to ensure the correctness of the reception of the cache data, and display the received cache data of each layer to facilitate observation of data changes. When it is identified that there are errors in the received cache data, the cache data of the next layer of cache units is received and displayed, thereby maximizing the data transmission efficiency without affecting data analysis, and greatly improving the refresh rate of the upper computer interface.

[0107] In order to implement the above embodiments, the present application also proposes an electronic device, comprising: a processor, and a memory communicatively connected to the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the method provided by the above embodiments.

[0108] In order to implement the above embodiments, the present application also proposes a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the methods provided by the above embodiments.

[0109] In order to implement the above embodiments, the present application also proposes a computer program product, including a computer program, which implements the methods provided by the above embodiments when executed by a processor.

[0110] The collection, storage, use, processing, transmission, provision and disclosure of user personal information involved in this application are in compliance with relevant laws and regulations and do not violate public order and good morals.

[0111] It should be noted that personal information from users should be collected for legitimate and reasonable purposes and should not be shared or sold outside of these legitimate uses. In addition, such collection / sharing should be carried out after receiving the user's informed consent, including but not limited to notifying the user to read the user agreement / user notice and sign the agreement / authorization including authorization of relevant user information before the user uses the function. In addition, any necessary steps should be taken to protect and safeguard access to such personal information data and ensure that others who have access to personal information data comply with its privacy policy and procedures.

[0112] The present application is expected to provide an implementation scheme for users to selectively block the use or access of personal information data. That is, the present disclosure is expected to provide hardware and / or software to prevent or block access to such personal information data. Once the personal information data is no longer needed, the risk can be minimized by limiting data collection and deleting the data. In addition, when applicable, such personal information is de-identified to protect the privacy of the user.

[0113] In the description of the aforementioned embodiments, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0114] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0115] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0116] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute the instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0117] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0118] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0119] In addition, each functional unit in each embodiment of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0120] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A data transmission method, characterized in that: Executed by a chip, the method includes: Acquire data to be sent, and write the data to be sent into a cache area in sequence, wherein the cache area includes at least one layer of cache units; Receiving space indication information of the cache area, where the space indication information is used to indicate remaining storage space of the cache area; In response to the space indication information indicating that the remaining storage space of the cache area is empty, the cache data in the cache units of each layer in the cache area are sent layer by layer.

2. The method according to claim 1, characterized in that The step of sending the cache data in the cache units of each layer in the cache area layer by layer includes: Monitor the response signal of each layer of cache unit, where the response signal is used to indicate whether the cache data of the corresponding cache unit has been sent; In response to monitoring the response signals of all cache units in the cache area, the response signals of the cache units in each layer in the cache area are reset.

3. The method according to claim 2, characterized in that The method further comprises: After monitoring the response signal of each layer of cache unit, the remaining data to be sent is written into the cache unit that has been sent in sequence until all the data to be sent is written, or the space indication information of the cache area is received again to indicate that the remaining storage space is empty.

4. The method according to claim 3, characterized in that The method further comprises: In response to monitoring a response signal of the lowest cache unit in the cache area, identifying whether cache data exists in the first-layer cache unit of the cache area; In response to the existence of cache data in the first-layer cache unit, the cache data in the cache units of each layer are sent layer by layer and the response signals of the cache units of each layer are monitored.

5. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: Backing up the cache data of the cache units to be sent layer by layer to obtain at least two copies of the cache data; At least two copies of cached data are sent simultaneously.

6. A data transmission method, characterized in that: Executed by a host computer, the method includes: receiving at least two cache data of each layer of cache units sent by the chip; The at least two cached data are compared and verified, and in response to the at least two cached data being completely consistent, any cached data of the cache unit is selected for display.

7. The method according to claim 6, characterized in that The method further comprises: In response to the at least two cached data being not completely consistent, at least two cached data of a next-level cache unit are judged, and the cached data that are completely consistent are displayed.

8. A data transmission device, characterized in that: Executed by a chip, the device comprises: A cache module, used to obtain data to be sent, and write the data to be sent into a cache area in sequence, wherein the cache area includes at least one layer of cache units; A receiving module, used for receiving space indication information of the buffer area, where the space indication information is used for indicating the remaining storage space of the buffer area; The sending module is used for sending the cache data in the cache units of each layer in the cache area layer by layer in response to the space indication information indicating that the remaining storage space of the cache area is empty.

9. A data transmission device, characterized in that: Executed by a host computer, the device includes: A receiving module, used for receiving at least two cache data of each layer of cache unit sent by the chip; The display module is used to compare and verify the at least two cached data, and in response to the at least two cached data being completely consistent, select any cached data of the cache unit for display.

10. An electronic device, characterized in that: include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1-5 or 6-7.

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