Industrial camera and loading method thereof

Abstract

The embodiment of the invention provides an industrial camera and a loading method thereof, and relates to the technical field of industrial cameras. The industrial camera provided by the embodiment of the invention comprises an FPGA module, a control module and a Flash module, a data sending pin of the Flash module is connected with data receiving pins of the FPGA module and the control module; a reset pin of the FPGA module is connected with an output pin of the control module; after the industrial camera is powered on, the Flash module can send a control module / FPGA loading program to the control module and the FPGA module through the data sending pin based on an instruction of the control module, so that the control module / FPGA loading program can start loading. It can be seen that according to the working camera provided by the embodiment of the invention, the Flash module can directly send the FPGA loading program to the FPGA module, so that the FPGA module can be rapidly loaded, the control module does not need to carry out unvarnished transmission, and then the loading speed of the industrial camera can be increased.

Description

Technical Field

[0001] The present invention relates to the technical field of industrial cameras, and in particular to an industrial camera and a loading method thereof. Background Art

[0002] Industrial cameras are a key component in machine vision systems. Their most essential function is to convert optical signals into orderly electrical signals. In practical applications, after the industrial camera is powered on, it needs to be loaded to read the required files and information into the memory for subsequent use.

[0003] In the related technologies, industrial cameras are loaded by transparent transmission schemes, which mainly include: reading the data in the coded flash memory Flash module through the control module, and then transparently transmitting the loading program of the field programmable gate array FPGA module to the FPGA module through the control module after the control module is loaded. In actual applications, the loading speed of this scheme is very slow, up to several minutes, and it cannot meet the needs of users in many application scenarios.

[0004] Therefore, how to improve the loading speed of industrial cameras has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] The present application provides an industrial camera and a loading method thereof, which are used to improve the loading speed of the industrial camera.

[0006] According to a first aspect of an embodiment of the present application, there is provided an industrial camera, comprising: a field programmable gate array (FPGA) module, a microcontroller control module and an encoded flash memory (Flash) module; a data sending pin of the Flash module is connected to a data receiving pin of the FPGA module and a data receiving pin of the control module; a reset pin of the FPGA module is connected to an output pin of the control module; the control module is configured to: in response to the industrial camera being powered on, send a first instruction to a data receiving pin of the Flash module through the data sending pin of the control module; the Flash module is configured to: in response to the first instruction, send a control module loader through the data sending pin of the Flash module; the control module is further configured to: receive and load the control module loader; after loading is completed, control the level of the reset pin of the FPGA module through the output pin of the control module to release the FPGA module from the reset state; and send a second instruction to the data receiving pin of the Flash module through the data sending pin of the control module; the Flash module is further configured to: in response to the second instruction, send the FPGA loader through the data sending pin of the Flash module; the FPGA module is configured to: receive and load the FPGA loader.

[0007] In the industrial camera provided by the embodiment of the present application, the data sending pin of the Flash module is connected to the data receiving pin of the FPGA module and the control module; thus, after the camera is powered on, the Flash module can send the control / FPGA loader program to the data receiving pin of the control module and the FPGA module through the data sending pin of the Flash module based on the instruction sent by the control module, and then the control / FPGA module can be loaded according to the control / FPGA loader program. At the same time, the reset pin of the FPGA module is connected to the output pin of the control module. Before sending the second instruction, the control module controls the level of the reset pin of the FPGA module through the output pin to release the reset state of the FPGA module, so that the FPGA module can receive the FPGA loader program sent by the Flash module.

[0008] It can be seen that in the industrial camera provided by the embodiment of the present application, the Flash module can directly send the FPGA loader to the FPGA module, so that the FPGA module can be loaded quickly. Compared with the related art in which the FPGA loader is transparently transmitted to the FPGA module through the SPI of the control module after the control module is loaded, the industrial camera provided by the embodiment of the present application does not require the control module to be transparently transmitted, and the FPGA module can directly receive the FPGA loader sent by the Flash module for loading, thereby improving the loading speed of the industrial camera.

[0009] In combination with the first implementation method of the first aspect, before controlling the level of the reset pin of the FPGA module through the output pin to release the FPGA module from the reset state, the control module is also configured to: control the level of the reset pin of the FPGA module through the output pin to put the FPGA module into the reset state.

[0010] In combination with the second implementation method of the first aspect, the chip select pin of the control module is connected to the chip select pin of the Flash module; before sending the first instruction to the data receiving pin of the Flash module through the data sending pin of the control module, the control module is also configured to: control the level of the chip select pin of the Flash module through the chip select pin of the control module to put the Flash module into a working state.

[0011] In combination with the third implementation method of the first aspect, before sending the second instruction to the data receiving pin of the Flash module through the data sending pin of the control module, the control module is also configured to: control the level of the chip select pin of the Flash module through the chip select pin of the control module to put the Flash module into a working state.

[0012] In combination with the fourth implementation method of the first aspect, the clock pin of the control module is connected to the clock pin of the Flash module and the clock pin of the FPGA module; before sending the first instruction to the data receiving pin of the Flash module through the data sending pin of the control module, the control module is also configured to: send a first synchronization clock through the clock pin of the control module.

[0013] In combination with the fifth implementation manner of the first aspect, before sending the second instruction to the data receiving pin of the Flash module through the data sending pin of the control module, the control module is further configured to: send a second synchronization clock through the clock pin of the control module.

[0014] In combination with the sixth implementation method of the first aspect, the completion pin of the FPGA module is connected to the input pin of the control module; after receiving and loading the FPGA loader, the FPGA module is also configured to: after the FPGA loader program is loaded, send loading completion information to the input pin of the control module through the completion pin of the FPGA module; the control module is also configured to: receive the loading completion information and determine that the loading of the industrial camera is completed.

[0015] The second aspect of the embodiment of the present application provides a loading method for an industrial camera, which includes: a field programmable gate array FPGA module, a microcontroller control module and an encoded flash memory Flash module; a data sending pin of the Flash module is connected to a data receiving pin of the FPGA module and a data receiving pin of the control module; a reset pin of the FPGA module is connected to an output pin of the control module; the loading method includes: in response to the industrial camera being powered on, the control module sends a first instruction to a data receiving pin of the Flash module through the data sending pin of the control module; after the Flash module receives the first instruction, the control module sends a control module loading program through the data sending pin of the Flash module; the control module receives and loads the control module loading program, and after the loading is completed, controls the voltage of the reset pin of the FPGA module through the output pin of the control module to release the reset state of the FPGA module; the control module sends a second instruction to the data receiving pin of the Flash module through the data sending pin of the control module; after the Flash module receives the second instruction, the FPGA loading program is sent through the data sending pin of the Flash module; the FPGA module receives and loads the FPGA loading program.

[0016] In combination with the first implementation method of the second aspect, before controlling the voltage of the reset pin of the FPGA module through the output pin to release the FPGA module from the reset state, the loading method also includes: the control module controls the voltage of the reset pin of the FPGA module through the output pin to put the FPGA module into the reset state.

[0017] In combination with the second implementation method of the second aspect, the chip select pin of the control module is connected to the chip select pin of the Flash module; before sending the first instruction to the data receiving pin of the Flash module through the data sending pin of the control module, the loading method also includes: the control module controls the voltage of the chip select pin of the Flash module through the chip select pin of the control module to put the Flash module into a working state.

[0018] In combination with the third implementation method of the second aspect, before the control module sends the second instruction to the data receiving pin of the Flash module through the data sending pin of the control module, the loading method also includes: the control module controls the voltage of the chip select pin of the Flash module through the chip select pin of the control module to put the Flash module into a working state.

[0019] In combination with the fourth implementation of the second aspect, the clock pin of the control module is connected to the clock pin of the Flash module and the clock pin of the FPGA module. Before sending the first instruction to the data receiving pin of the Flash module through the data sending pin of the control module, the loading method also includes: the control module sends a first synchronization clock through the clock pin of the control module.

[0020] In combination with the fifth implementation of the second aspect, before the control module sends the second instruction to the data receiving pin of the Flash module through the data sending pin of the control module, the loading method also includes: the control module sends a second synchronization clock through the clock pin of the control module.

[0021] In combination with the sixth implementation of the second aspect, the completion pin of the FPGA module is connected to the input pin of the control module. After the FPGA module receives and loads the FPGA loading program, the loading method further includes: after the loading is completed, the FPGA module sends a loading completion message to the input pin of the control module through the completion pin of the FPGA module; after the control module receives the loading completion message, it determines that the loading of the industrial camera is completed.

[0022] Among them, the beneficial effects described in the second aspect can refer to the analysis of the beneficial effects of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present invention and do not constitute a limitation on the technical solution of the present invention.

[0024] Figure 1 A schematic diagram of the structure of an industrial camera provided in an embodiment of the present application;

[0025] Figure 2A schematic diagram of the structure of another industrial camera provided in an embodiment of the present application;

[0026] Figure 3 A schematic diagram of a process of loading an industrial camera provided in an embodiment of the present application;

[0027] Figure 4 A method flow chart of a loading method for an industrial camera provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0029] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0030] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances. In addition, when describing pipelines, the terms "connected" and "connection" used in this application have the meaning of conduction. The specific meaning needs to be understood in conjunction with the context.

[0031] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0032] Before explaining the embodiments of the present application in detail, some terms involved in the embodiments of the present application are first explained.

[0033] MCU module: MCU module refers to the microcontroller unit module, that is, a microcontroller. Also known as a single-chip microcomputer, it refers to the integration of a computer's central processing unit (CPU), random access memory (RAM), read-only memory image (ROM), timer and multiple I / O interfaces on a single module with the emergence and development of large-scale integrated circuits to form a microcomputer. The control module is usually used to control and manage various peripheral devices, such as sensors, actuators, displays, etc. It can perform various tasks, including data processing, logic control and communication.

[0034] PHY module: PHY module refers to the physical layer module, which is the part responsible for physical transmission in network communication. PHY module is usually used to convert image data into electrical signals and transmit them through the transmission medium. It should be understood that in order to improve the performance of industrial cameras, PHY module can also be used to process image data and control tasks.

[0035] FPGA module: FPGA (Field-Programmable Gate Array) is a programmable logic device that can be reconfigured and reprogrammed according to user needs. The FPGA module contains a large number of programmable logic units and programmable wiring resources. Users can program these resources according to specific application requirements to achieve various functions.

[0036] Flash module: Flash (flash memory) module can store data in the internal circuit. It is a non-volatile memory that can keep the data even after power failure. Flash is usually used to store firmware, operating system, application program and other data. Flash module can also be called flash memory.

[0037] Transparent transmission: Transparent transmission means that the transmission network is only responsible for transmitting the services to be transmitted to the destination node, ensuring the quality of transmission, regardless of the transmission services, without processing the transmitted services. During the data transmission process, the data is not changed in any form, that is, it is not truncated, grouped, encoded, encrypted, or confused, as if the transmission process is transparent and reaches the final recipient intact.

[0038] It should be understood that the control module in the embodiment of the present application can be the above-mentioned MCU module, PHY module or a module integrated with MCU and PHY module, or it can be other modules with control functions (such as system-on-chip module). In the specific application process, a specific control module can be selected according to the needs, and the embodiment of the present application does not make any limitation on this.

[0039] For ease of description, this article takes the control module as an MCU module as an example, that is, the pins of the control module are used as the pins of the MCU module for explanation, but this description method does not constitute a limitation. In actual application, the name of the pin can be changed according to the specific control module.

[0040] It should be noted that the pull-down / pull-up mentioned in the embodiments of the present application refers to the level state of the pin. It should be understood that in some embodiments, if the pin is at a low level, the device / equipment to which the pin belongs will start to perform the work corresponding to the pin, and if the pin is at a high level, the device / equipment to which the pin belongs will not perform the work corresponding to the pin. In other embodiments, if the pin is at a high level, the device / equipment to which the pin belongs will start to perform the work corresponding to the pin, and if the pin is at a low level, the device / equipment to which the pin belongs will not perform the work corresponding to the pin.

[0041] For ease of description, the embodiment of the present application is explained by taking the example that when the pin is at a low level, the device / equipment to which the pin belongs will start to perform the work corresponding to the pin, and when the pin is at a high level, the device / equipment to which the pin belongs will not perform the work corresponding to the pin. That is, pulling the pin low will cause the device / equipment to which the pin belongs to start to perform the work corresponding to the pin, and pulling the pin high will cause the device / equipment to which the pin belongs to not perform the work corresponding to the pin, but this description method does not constitute a limitation to the embodiments of the present application.

[0042] See also Figure 1 , Figure 1 This is a schematic diagram of the structure of an industrial camera provided in an embodiment of the present application. Figure 1 As shown, the industrial camera 10 includes: a control module 11, an FPGA module 12 and a Flash module 13. Among them, the control module 11 is the main control module of the industrial camera 10, responsible for controlling the operation of other modules, and also serves as a protocol conversion module, which can convert the parallel port protocol sent by the FPGA module 12 into a serial port protocol for transmission; the FPGA module 12 is the main program running module, which is used to output the image data to the control module after processing; the Flash module 13 is the offline program storage module of the industrial camera 10, and all the code programs running in the industrial camera 10 are stored therein.

[0043] In some embodiments, the industrial camera 10 may further include a PHY module to implement a communication interface at the physical layer.

[0044] As a feasible implementation method, the control module 11 can be integrated with the PHY module in one module, the control module is responsible for processing data and control tasks, and the PHY module is responsible for implementing the communication interface of the physical layer. This can reduce the number of modules in the industrial camera 10 and improve the performance of the industrial camera 10.

[0045] In some embodiments, the industrial camera 10 may be a USB industrial camera, that is, the industrial camera 10 may include a USB interface. The USB interface is widely used and is equipped on various devices. For example, a USB industrial camera can be directly connected to the USB interface of the computer to work stably. In addition, the USB interface can directly power the USB industrial camera without the need to prepare a separate power supply.

[0046] It should be pointed out that Figure 1 The structure shown does not constitute a limitation on the industrial camera. In other embodiments, the industrial camera may include fewer or more components than shown in the figure, or a combination of certain components, or a different arrangement of components. The embodiments of the present application do not impose any limitations on this.

[0047] It is easy to understand that after the industrial camera 10 is powered on, the control module 11 and the FPGA module 12 need to load the control module loader and the FPGA loader stored in the Flash module 13 into their respective memories, to ensure the subsequent operation of the control module 11 and the FPGA module 12. This process can be called loading the industrial camera.

[0048] In the industrial camera of the related art, the control module 11, the FPGA module 12 and the Flash module 13 are used as follows Figure 1 The connection relationship shown. Figure 1 It can be seen that there is no direct connection between the FPGA module 12 and the Flash module 13 of the industrial camera 10 in the related art. After power-on, the control module 11 first reads the control module loader in the Flash module 13 for loading. After the control module 11 is loaded, the FPGA loader is transparently transmitted to the FPGA module 12 through the serial peripheral interface (Serial Peripheral Interface, SPI) of the control module 11.

[0049] In actual applications, the loading speed of this solution is very slow, taking up to several minutes, and cannot meet user needs in many application scenarios.

[0050] Based on this, the embodiment of the present application provides an industrial camera, such as Figure 2As shown, the Flash module 13 of the industrial camera 10 includes: a data sending pin DO and a data receiving pin DI; the FPGA module 12 includes: a data receiving pin FPGA_CONFIG_DATA0 and a reset pin FPGA_RST; the control module 11 includes: a data sending pin MCU_MOSI, a data receiving pin MCU_MISO, and an output pin MCU_GPIO0.

[0051] Among them, the data sending pin DO of the Flash module 13 is connected to the data receiving pin FPGA_CONFIG_DATA0 of the FPGA module 12 and the data receiving pin MCU_MISO of the control module 11; the reset pin FPGA_RST of the FPGA module 12 is connected to the output pin MCU_GPIO0 of the control module 11.

[0052] The control module 11 is configured to: in response to the camera being powered on, send a first instruction to the data receiving pin DI of the Flash module through the data sending pin MCU_MOSI of the control module.

[0053] The Flash module 12 is configured to: in response to the first instruction, send the control module loader program through the data sending pin DO of the Flash module.

[0054] The control module 11 is also configured to: receive and load the control module loader; after the loading is completed, control the voltage of the reset pin FPGA_RST of the FPGA module 12 through the output pin MCU_GPIO0 of the control module 11 to release the FPGA module 12 from the reset state; and send a second instruction to the data receiving pin DI of the Flash module 13 through the data sending pin MCU_MOSI of the control module 11.

[0055] It should be noted that, since the output pin MCU_GPIO0 of the control module 11 is connected to the reset pin FPGA_RST of the FPGA module 12, that is, the output pin MCU_GPIO0 of the control module 11 can control the level state of the reset pin FPGA_RST of the FPGA module 12, and then control the state of the FPGA module 12. However, the output pin MCU_GPIO0 of the control module 11 defaults to a low level after power-on, that is, the reset pin FPGA_RST of the FPGA module 12 is in a low level state, so that the FPGA module 12 is in a reset state before the control module 11 is loaded. The data sent by the data sending pin DO of the control module 11 is not valid for the FPGA module 12, and the FPGA module 12 cannot be loaded during the loading process of the control module 11.

[0056] After the control module 11 is loaded, the reset state of the FPGA module 12 needs to be released. The level of the reset pin FPGA_RST of the FPGA module 12 is pulled high by the output pin MCU_GPIO0 of the control module 11, so that the FPGA module 12 is released from the reset state.

[0057] The Flash module 13 is further configured to: in response to the second instruction, send the FPGA loader program through the data sending pin DO of the Flash module 13 .

[0058] The FPGA module 12 is configured to receive and load an FPGA loader.

[0059] It can be seen that in the industrial camera provided by the embodiment of the present application, the Flash module 13 can directly send the FPGA loader to the FPGA module 12, so that the FPGA module 12 can be loaded quickly. Compared with the related art in which the FPGA loader is transparently transmitted to the FPGA module 12 through the control module 11 after the control module 11 is loaded, the industrial camera provided by the embodiment of the present application does not need the control module 11 to perform transparent transmission, and the FPGA module 12 can directly receive the FPGA loader sent by the Flash module 13 for loading, thereby improving the loading speed of the industrial camera.

[0060] In some embodiments, during the loading process of the control module 11, the output pin MCU_GPIO0 of the control module 11 may be pulled up, which will cause the level of the reset pin FPGA_RST of the FPGA module 12 to become high, that is, the FPGA module 12 may not be completely in the reset state. At this time, the control module loader sent by the Flash module 13 may affect the FPGA module 12.

[0061] As a feasible implementation method, before controlling the level of the reset pin FPGA_RST of the FPGA module 12 through the output pin MCU_GPIO0 of the control module 11 to release the FPGA module 12 from the reset state, the control module 11 is also configured to: control the voltage of the reset pin FPGA_RST of the FPGA module through the output pin MCU_GPIO0 to put the FPGA module 12 into the reset state.

[0062] That is to say, before releasing the reset state of the FPGA module 12, the control module 11 first pulls down the reset pin FPGA_RST of the FPGA module 12 to put the FPGA module 12 in the reset state, clearing the useless data received by the FPGA module 12 to avoid affecting the subsequent loading of the FPGA module 12.

[0063] In some embodiments, since there are multiple modules in the industrial camera, the multiple modules may be connected on the same communication bus, and the control module 11, as the main control module, needs to determine which module on the communication bus will process the instruction when issuing the instruction. For example, the first instruction and the second instruction in the embodiment of the present application need to be processed by the Flash module 13. Therefore, before issuing the first instruction and the second instruction, the control module 11 needs to give a signal to the Flash module 13 to put the Flash module 13 in a working state.

[0064] Based on this, as a feasible implementation method, please continue to refer to Figure 2 In the industrial camera provided in the embodiment of the present application, the control module 11 further includes a chip select pin MCU_CS, and the Flash module 13 further includes a chip select pin CS. The chip select pin MCU_CS of the control module 11 is connected to the chip select pin CS of the Flash module 13.

[0065] As a feasible implementation method, the industrial camera provided in the embodiment of the present application, before sending the first instruction to the data receiving pin DI of the Flash module 13 through the data sending pin MCU_MOSI of the control module 11, the control module 11 is also configured to: control the voltage of the chip select pin CS of the Flash module 13 through the chip select pin MCU_CS of the control module 11 to put the Flash module 13 into a working state.

[0066] Before the control module 11 sends the first instruction to the Flash module 13, the chip select pin MCU_CS of the control module 11 pulls down the chip select pin CS of the Flash module 13, so that the Flash module 13 is in a working state, so that the control module 11 can read or write to the Flash module 13, that is, it can receive and execute the first instruction sent by the control module 11.

[0067] As a feasible implementation method, before sending the second instruction to the data receiving pin DI of the Flash module 13 through the data sending pin MCU_MOSI of the control module 11, the control module 11 is also configured to: control the voltage of the chip select pin CS of the Flash module 13 through the chip select pin MCU_CS of the control module 11 to put the Flash module 13 into a working state.

[0068] Before the control module 11 sends the second instruction to the Flash module 13, the chip select pin MCU_CS of the control module 11 pulls down the chip select pin CS of the Flash module 13, so that the Flash module 13 is in a working state, so that the control module 11 can read or write to the Flash module 13, that is, it can receive and execute the second instruction sent by the control module 11.

[0069] In some embodiments, data is transmitted frame by frame in the line. If the frequencies of the data transmitting end and the data receiving end are inconsistent, it is very likely that there will be a missed read slip, that is, data loss, resulting in incorrect data transmission. Therefore, before the control module 11 sends the first instruction and the second instruction, it is necessary to adjust the control module 11, the FPGA module 12 and the Flash module 13 to the same frequency.

[0070] Based on this, as a feasible implementation method, please continue to refer to Figure 2 In the industrial camera 10 provided in the embodiment of the present application, the control module 11 further includes a clock pin MCU_CLK, the FPGA module 12 further includes a clock pin FPGA_CONFIG_CLK, and the Flash module 13 further includes a clock pin CLK. The clock pin MCU_CLK of the control module 11 is connected to the clock pin FPGA_CONFIG_CLK of the FPGA module 12 and the clock pin CLK of the Flash module 13.

[0071] As a feasible implementation, before sending the first instruction to the data receiving pin DI of the Flash module 13 through the data sending pin MCU_MOSI of the control module 11, the control module 11 is further configured to send a first synchronous clock through the clock pin MCU_CLK of the control module 11.

[0072] The control module 11 sends the first synchronization clock through the clock pin MCU_CLK of the control module 11. After the clock pin FPGA_CONFIG_CLK of the FPGA module 12 and the clock pin CLK of the Flash module 13 receive the first synchronization clock, the time stamp data between the control module 11, the FPGA module 12 and the Flash module 13 are made consistent, that is, adjusted to the same frequency. In this way, it is possible to avoid the phenomenon of data loss when the Flash module 13 subsequently sends the control module loading program, resulting in the control module 11 being unable to load normally.

[0073] As a feasible implementation, before sending the second instruction to the data receiving pin DI of the Flash module 13 through the data sending pin MCU_MOSI of the control module 11, the control module 11 is further configured to send a second synchronous clock through the clock pin MCU_CLK of the control module 11.

[0074] The control module 11 sends the second synchronization clock through the clock pin MCU_CLK of the control module 11. After the clock pin FPGA_CONFIG_CLK of the FPGA module 12 and the clock pin CLK of the Flash module 13 receive the second synchronization clock, the time stamp data between the control module 11, the FPGA module 12 and the Flash module 13 are made consistent, that is, adjusted to the same frequency. In this way, it is possible to avoid the phenomenon of data loss when the subsequent Flash module 13 sends the FPGA loader, which causes the FPGA module 12 to fail to load normally.

[0075] In some embodiments, since the control module 11 is the main control module (master device), the operation of each module in the industrial camera needs to be controlled by the control module 11, so the FPGA module 12, as a slave device, needs to inform the control module 11 that it has been loaded after loading is completed, so as to facilitate subsequent control by the control module 11.

[0076] Based on this, as a feasible implementation method, please continue to refer to Figure 2 In the industrial camera provided in the embodiment of the present application, the FPGA module 12 also includes a completion pin FPGA_Done, and the control module 11 also includes an input pin MCU_GPIO1. The completion pin FPGA_Done of the FPGA module 12 is connected to the input pin MCU_GPIO1 of the control module 11.

[0077] As a feasible implementation method, after receiving and loading the FPGA loader, the FPGA module 12 is also configured to: after the FPGA loader program is loaded, send the loading completion information to the input pin MCU_GPIO1 of the control module 11 through the completion pin FPGA_Done of the FPGA module 12; the control module 11 is also configured to: receive the loading completion information and determine that the loading of the industrial camera is completed.

[0078] After loading is completed, the FPGA module 12 sends a loading completion message to the control module 11 through the completion pin FPGA_Done of the FPGA module, informing the control module 11 that the loading is completed. After receiving the loading completion message, the control module 11 determines that the industrial camera has been loaded and can perform subsequent operations.

[0079] In some embodiments, see Figure 3 The industrial camera provided in the embodiment of the present application has the following steps in its loading process after power-on:

[0080] S301 . In response to the industrial camera being powered on, the control module 11 sends a first synchronous clock through the clock pin MCU_CLK of the control module, and pulls down the chip select pin CS of the Flash module.

[0081] S302 , the control module 11 sends a first instruction to the data receiving pin DI of the Flash module 13 through the data sending pin MCU_MOSI of the control module.

[0082] S303 , the Flash module 13 responds to the first instruction and sends a control module loading program through the data sending pin DO of the Flash module 13 .

[0083] It can be understood that the data transmission pin DO of the Flash module 12 is connected to the data receiving pin FPGA_CONFIG_DATA0 of the FPGA module and the data receiving pin MCU_MISO of the control module, so the control module loader program is sent through the data transmission pin DO of the Flash module 12 and can be sent to the control module 11 and the FPGA module 12. Since the output pin MCU_GPIO0 of the control module 11 is connected to the reset pin FPGA_RST of the FPGA module 12, and the output pin MCU_GPIO0 of the control module 11 is low level by default after power-on, that is, the reset pin FPGA_RST of the FPGA module 12 is in a low level state, the FPGA module 12 is in a reset state, and the FPGA module 12 does not do any processing after receiving the control module loader program, and the control module 11 can start loading after receiving the control module loader program.

[0084] S304, the control module 11 receives and loads the control module loading program. After the loading is completed, the output pin MCU_GPIO0 of the control module 11 controls the level of the reset pin FPGA_RST of the FPGA module 12 to put the FPGA module 12 in a reset state.

[0085] It should be noted that in order to avoid the situation where the control module 11 fails to control the level of the reset pin of the FPGA module 12 during loading, the level of the reset pin FPGA_RST of the FPGA module 12 is lowered again to ensure that the FPGA module 12 is in a reset state before loading.

[0086] S305 , controlling the level of the reset pin FPGA_RST of the FPGA module 12 through the output pin MCU_GPIO0 of the control module 11 to release the FPGA module 12 from the reset state.

[0087] Before the FPGA module 12 is loaded, it is necessary to release the reset state of the FPGA module 12. The output pin MCU_GPIO0 of the control module 11 is used to pull up the level of the reset pin FPGA_RST of the FPGA module, thereby releasing the reset state of the FPGA module 12.

[0088] S306 , the control module 11 sends a second synchronous clock through the clock pin MCU_CLK of the control module, and pulls down the chip select pin CS of the Flash module 13 .

[0089] S307 , sending a second instruction to the data receiving pin DI of the Flash module 13 through the data sending pin MCU_MOSI of the control module 11 .

[0090] S308 . The Flash module 13 sends the FPGA loader program via the data sending pin DO of the Flash module 13 in response to the second instruction.

[0091] The control module 11 does not perform any processing after receiving the FPGA loading program, and the FPGA module 12 starts loading after receiving the FPGA loading program.

[0092] S309 , after the loading of the FPGA module 12 is completed, the loading completion information is sent to the control module 11 through the completion pin FPGA_Done of the FPGA module 12 .

[0093] After receiving the loading completion information, the control module 11 determines that the industrial camera has been loaded.

[0094] The present application also provides a method for loading an industrial camera, which is applicable to the industrial camera provided in the above embodiment. Figure 4 , the loading method comprises the following steps:

[0095] S401 . In response to the industrial camera being powered on, the control module sends a first instruction to the data receiving pin of the Flash module through the data sending pin of the control module.

[0096] S402: After receiving the first instruction, the Flash module sends a control module loading program through a data sending pin of the Flash module.

[0097] S403, the control module receives and loads the control module loading program, and after the loading is completed, controls the voltage of the reset pin of the FPGA module through the output pin of the control module to release the FPGA module from the reset state.

[0098] S404: The control module sends a second instruction to the data receiving pin of the Flash module through the data sending pin of the control module.

[0099] S405 . After receiving the second instruction, the Flash module sends the FPGA loader program through the data sending pin of the Flash module.

[0100] S406: The FPGA module receives and loads the FPGA loader.

[0101] As a feasible implementation method, before controlling the voltage of the reset pin of the FPGA module through the output pin to release the FPGA module from the reset state, the loading method also includes: the control module controls the voltage of the reset pin of the FPGA module through the output pin to put the FPGA module into the reset state.

[0102] As a feasible implementation method, the chip select pin of the control module is connected to the chip select pin of the Flash module. Before sending the first instruction to the data receiving pin of the Flash module through the data sending pin of the control module, the loading method also includes: the control module controls the voltage of the chip select pin of the Flash module through the chip select pin of the control module to put the Flash module into a working state.

[0103] As a feasible implementation, before S404, the loading method further includes: the control module controls the voltage of the chip select pin of the Flash module through the chip select pin of the control module to put the Flash module into a working state.

[0104] As a feasible implementation method, the clock pin of the control module is connected to the clock pin of the Flash module and the clock pin of the FPGA module. Before sending the first instruction to the data receiving pin of the Flash module through the data sending pin of the control module, the loading method also includes: the control module sends a first synchronous clock through the clock pin of the control module.

[0105] As a feasible implementation manner, before S404, the loading method further includes: the control module sends a second synchronous clock through a clock pin of the control module.

[0106] As a feasible implementation method, the completion pin of the FPGA module is connected to the input pin of the control module. After S406, the loading method further includes: after the loading is completed, the FPGA module sends a loading completion message to the input pin of the control module through the completion pin of the FPGA module; after the control module receives the loading completion message, it determines that the loading of the industrial camera is completed.

[0107] Through the description of the above implementation methods, technical personnel in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0108] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0109] The units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0110] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0111] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a device (which may be a single-chip microcomputer, etc.) or a processor (processor) to perform all or part of the steps of each embodiment method of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, ROM, RAM, embedded multimedia controller (Embedded Multi Media Card, EMMC), electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), disk or optical disk and other media that can store program code.

[0112] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An industrial camera, characterized in that: It includes: a field programmable gate array FPGA module, a control module and a coded flash memory Flash module; The data sending pin of the Flash module is connected to the data receiving pin of the FPGA module and the data receiving pin of the control module; The reset pin of the FPGA module is connected to the output pin of the control module; The control module is configured to: in response to the industrial camera being powered on, send a first instruction to the data receiving pin of the Flash module through the data sending pin of the control module; The Flash module is configured to: in response to the first instruction, send a control module loader program through a data sending pin of the Flash module; The control module is further configured to: receive and load the control module loader; after loading is completed, control the level of the reset pin of the FPGA module through the output pin of the control module to release the reset state of the FPGA module; and send a second instruction to the data receiving pin of the Flash module through the data sending pin of the control module; The Flash module is further configured to: in response to the second instruction, send the FPGA loader program through the data sending pin of the Flash module; The FPGA module is configured to receive and load the FPGA loader.

2. The industrial camera according to claim 1, characterized in that: Before controlling the level of the reset pin of the FPGA module through the output pin to release the FPGA module from the reset state, The control module is further configured to: The level of the reset pin of the FPGA module is controlled through the output pin to put the FPGA module in a reset state.

3. The industrial camera according to claim 1, characterized in that: The chip select pin of the control module is connected to the chip select pin of the Flash module; Before sending the first instruction to the data receiving pin of the Flash module through the data sending pin of the control module, The control module is further configured to: The chip select pin of the control module is used to control the level of the chip select pin of the Flash module so that the Flash module is in a working state.

4. The industrial camera according to claim 3, characterized in that: Before sending the second instruction to the data receiving pin of the Flash module through the data sending pin of the control module, The control module is further configured to: The chip select pin of the control module is used to control the level of the chip select pin of the Flash module so that the Flash module is in a working state.

5. The industrial camera according to any one of claims 1 to 4, characterized in that: The clock pin of the control module is connected to the clock pin of the Flash module and the clock pin of the FPGA module; Before sending the first instruction to the data receiving pin of the Flash module through the data sending pin of the control module, The control module is further configured to: A first synchronous clock is sent through a clock pin of the control module.

6. The industrial camera according to claim 5, characterized in that: Before sending the second instruction to the data receiving pin of the Flash module through the data sending pin of the control module, The control module is further configured to: A second synchronous clock is sent through a clock pin of the control module.

7. The industrial camera according to any one of claims 1 to 4, characterized in that: The completion pin of the FPGA module is connected to the input pin of the control module; After receiving and loading the FPGA loader, The FPGA module is also configured to: After the FPGA loader program is loaded, a loading completion message is sent to an input pin of the control module through a completion pin of the FPGA module; The control module is further configured to: receive the loading completion information and determine that the loading of the industrial camera is completed.

8. A method for loading an industrial camera, characterized in that: The industrial camera comprises: a field programmable gate array FPGA module, a control module and a coded flash memory Flash module; The data sending pin of the Flash module is connected to the data receiving pin of the FPGA module and the data receiving pin of the control module; The reset pin of the FPGA module is connected to the output pin of the control module; The loading method comprises: In response to the industrial camera being powered on, the control module sends a first instruction to the data receiving pin of the Flash module through the data sending pin of the control module; After receiving the first instruction, the Flash module sends a control module loading program through a data sending pin of the Flash module; The control module receives and loads the control module loading program, and after the loading is completed, controls the voltage of the reset pin of the FPGA module through the output pin of the control module to release the FPGA module from the reset state; The control module sends a second instruction to the data receiving pin of the Flash module through the data sending pin of the control module; After receiving the second instruction, the Flash module sends the FPGA loader program through the data sending pin of the Flash module; The FPGA module receives and loads the FPGA loader.

9. The loading method according to claim 8, characterized in that: Before controlling the voltage of the reset pin of the FPGA module through the output pin to release the FPGA module from the reset state, the loading method further includes: The control module controls the voltage of the reset pin of the FPGA module through the output pin to put the FPGA module in a reset state.

10. The loading method according to claim 8, characterized in that: The chip select pin of the control module is connected to the chip select pin of the Flash module; Before sending the first instruction to the data receiving pin of the Flash module through the data sending pin of the control module, the loading method further includes: The control module controls the voltage of the chip select pin of the Flash module through the chip select pin of the control module to put the Flash module into a working state; Before the control module sends a second instruction to the data receiving pin of the Flash module through the data sending pin of the control module, The loading method further comprises: The control module controls the voltage of the chip select pin of the Flash module through the chip select pin of the control module to put the Flash module into a working state.

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