Programmable array readout circuit design method supporting four arbitration modes

Abstract

The invention relates to the technical field of circuit design, and provides a programmable array readout circuit design method supporting four arbitration modes. Different from the design that an existing dynamic visual sensor only supports one arbitration mode, the reading circuit designed through the design method supports four arbitration modes including first-in first-out, sequential row selection, a frame-by-frame method and a region of interest; according to the method, a row request management module can achieve sorting of the sequence of read requests in each row in an array through very low hardware cost, meanwhile, a row number calculation core can achieve high-performance event row arbitration through parallel search hardware, and a programmable array driving module can output flexible and configurable array driving waveforms. Through the reading circuit designed by the invention, when a DVS array signal is read, the array reading circuit not only supports four current mainstream arbitration modes, but also has the advantages of low hardware cost, high performance and programmability.

Description

Technical Field

[0001] The invention relates to the processing field of dynamic vision sensors, and in particular to a design method for a programmable array readout circuit supporting four arbitration modes. Background Art

[0002] Dynamic Vision Sensor (DVS) draws on the visual system of higher organisms. Its pixel structure imitates a visual pathway composed of cones, ON and OFF bipolar cells, and ON and OFF ganglion cells, which can independently sense changes in light intensity and generate outputs. The DVS pixel array is composed of independent photosensitive pixels, each of which independently determines whether it is excited. If it is excited, it generates an ON event or OFF event, and if it is not excited, it does not generate any output.

[0003] Figure 2 The circuit diagram of the DVS pixel is shown in Figure 2, which consists of a logarithmic sensor, a switched capacitor amplifier, a threshold comparator, and an interface logic. The logarithmic sensor is composed of a transistor inverting amplifier operating in the subthreshold region, which is responsible for converting the photocurrent into a logarithmic output voltage, thereby allowing the pixel to span a higher dynamic range of photocurrent without saturation. The next-level switched capacitor amplifier increases the sensor's sensitivity to changes in light intensity by providing high-gain amplification of the input signal. The amplified signal will be transmitted to the threshold comparator that generates ON and OFF events. If the signal change exceeds the set threshold at this time, the threshold comparator will generate a corresponding event and trigger the interface logic circuit to generate a corresponding request signal. When the threshold comparator generates an event, the interface logic circuit and the array readout circuit will interact according to the four-stage handshake protocol. As shown in Figure 2, the threshold comparator generates a corresponding event and triggers the interface logic circuit to generate a corresponding request signal. Figure 3 As shown, the pixel interface logic circuit will first drive the row request signal (Row request, RR) to initiate a row readout request. When the row is selected by the row arbiter in the array readout circuit, the array readout circuit will drive the RA (row confirmation) signal of the row. After receiving the row confirmation signal, the pixel will drive the (column request) signal to initiate a column readout request. When the column arbiter in the array readout circuit selects the column, it will drive the (column confirmation) of the column and sample the coordinates and polarity of the event. The coordinates, polarity and sampling timestamp of the event are packaged and output using the AER expression. After receiving the (column confirmation) signal, the DVS pixel circuit will enter the reset state, and after a short reset time, it will return to the normal stage and continue to monitor the change of light intensity.

[0004] The above-mentioned RR signal and CR signal are driven by pseudo-NMOS structure. Figure 4The schematic diagram of the circuit structure of the RR signal is shown. In this structure, there is an NMOS transistor in each pixel, and its drain is connected together through a physical signal line as a pixel interface to form the RR signal of the row. The PMOS tube connected to the physical signal line plays a pull-up role. The gate control signal EVENT of the NMOS tube in the pixel represents whether an event has occurred in this pixel. If an event has occurred, the signal is high. As long as one pixel in a row has an event, the RR signal of the entire row will complete the state flip from high level to low level. This state flip represents that the row has generated a row request. The driving circuit of the CR signal is the same as the driving circuit of the RR signal.

[0005] The readout of the dynamic vision sensor array is in units of rows. The readout circuit will respond to the CA signals of all pixels containing events in the arbitration row at one time and assign the same timestamp to all events in the row. The difference between the event sensor readout circuits of mainstream manufacturers is mainly reflected in the arbitration method for event row requests. There are currently 4 mainstream arbitration methods:

[0006] (1) First-in, first-out: In 2019, Prophesee, a French company, released a back-illuminated dynamic vision sensor with a resolution of 1280×720. It uses a first-in, first-out arbitration readout circuit (also known as a time-priority arbitration scheme). The array readout circuit records the order in which the row request signal Rreq of each row of pixels is valid, and gives priority to sending the row response signal Rack to the row that sends the Rreq signal earlier. When the pixels in a row are responded to and reset, the Rreq signal is pulled low. When a new event is generated by the pixels in this row, the Rreq signal of this row is pulled high again and enters the first-in, first-out arbitration queue again. According to the first-in, first-out arbitration principle, the readout circuit can ensure a faster response speed when the rate at which the array generates events is low.

[0007] (2) Sequential row selection: The sequential row selection readout circuit does not care about the order in which the DVS pixels send requests when generating a response signal for the row, but reads out the rows with event requests in order from small to large with a uniform row frequency. Samsung's 2019 research report shows that when shooting high-speed moving objects, there is no motion artifact in the event frame mapped by the event stream generated by the sequential row selection readout circuit. However, the sequential row selection readout circuit cannot guarantee that the row that generates the event first is output first, so the time error may be higher than that of the first-in-first-out arbitration readout circuit.

[0008] (3) Frame-by-frame method: In 2017, Samsung proposed a dynamic vision sensor with a resolution of 1280x720 that uses a frame-by-frame method for event readout. The readout circuit first allows the DVS array to accumulate events for a fixed period of time and reads these events out in the form of frames. Some DVS event stream processing algorithms require that events within a fixed period of time be accumulated into frames and then processed. The event readout circuit using the frame-by-frame method directly outputs the accumulated event frame, so in some cases the computational complexity of the subsequent processing system can be reduced. However, this readout circuit sacrifices the high response speed and high temporal resolution characteristics of the DVS array.

[0009] (4) Region of Interest: The arbitration readout circuit based on the region of interest will pre-set a programmable priority for each row, and the array readout circuit will give priority to the row with a high priority when calculating the readout row number. The arbitration readout circuit based on the region of interest can ensure that the events generated by the pixels in a certain area of ​​the screen have a faster response speed, while the events generated by the pixels not in the region of interest will take longer to respond. Summary of the invention

[0010] The present invention proposes a design method for a programmable array readout circuit that supports four arbitration modes, which is used to solve the problem that the sequential row selection readout circuit cannot guarantee that the row that generates the event first is output first, so the time error may be higher than that of the first-in first-out arbitration readout circuit. The frame-by-frame method can reduce the computational complexity of the subsequent processing system. However, the readout circuit sacrifices the characteristics of high response speed and high time resolution of the DVS array. The arbitration readout circuit based on the region of interest can ensure that the events generated by the pixels in a certain area of ​​the screen have a faster response speed, but the events generated by the pixels not in the region of interest require a longer time to respond.

[0011] The present invention proposes a design method for a programmable array readout circuit supporting four arbitration modes, comprising:

[0012] Obtain the resolution of the dynamic vision sensor and determine the bit width parameters of the request bus, row reset bus and row response bus of the array readout circuit;

[0013] Based on the request bus, a row request module and a row number arbitration core are configured; wherein the row request module is used to obtain a row request signal for each pixel in the DVS array, and the row number arbitration core is used to set an arbitration mode for the row request signal;

[0014] Based on the row reset bus, a programmable array driver module is configured; wherein the programmable array driver module is used to generate a drive waveform according to a programmable timing parameter value, and respond to or reset a pixel row in the DVS array;

[0015] Based on the row response bus, a control state machine is configured; wherein the control state machine is used to control the row number arbitration core and the programmable array driver module to read the event row in the DVS array, and read the data and write it into the event queue.

[0016] Preferably, the input of the row request module is a row request signal Rreq in the DVS array and a row reset signal Rrst generated by a programming array driving module.

[0017] Preferably, the row request signal is filtered to remove signal glitches through a preset control logic.

[0018] Preferably, the output signals of the preset control logic are: a load(n) signal and a clear(n) signal;

[0019] The load(n) signal indicates that the row request of the nth row of pixels in the DVS array changes from invalid to valid;

[0020] The clear(n) signal indicates the reset signal after the nth row of pixels in the DVS array is generated and read out.

[0021] Preferably, the bank number arbitration core includes: a first arbitration mode, a second arbitration mode, a third arbitration mode or a fourth arbitration mode;

[0022] Among them, the first arbitration method is to arbitrate by a first-in-first-out method;

[0023] The second arbitration method is to arbitrate by sequential row selection;

[0024] The third arbitration method performs arbitration by frame-by-frame reading;

[0025] The fourth arbitration method is to perform arbitration by setting an area of ​​interest.

[0026] Preferably, the row number arbitration core of the first arbitration mode is internally configured with a first maximum value search circuit with a parallelism of 16;

[0027] The row number arbitration core is also configured with a global maximum value register and a global maximum value sequence number register;

[0028] The first maximum value search circuit has 16 input data comparison operations in each cycle, and outputs the output data with the largest value and the output sequence number;

[0029] The first maximum value search circuit is inserted by a pipeline register of one stage.

[0030] Preferably, the row number arbitration core of the second arbitration mode is used to search for a row signal with an output request from the previous response row number; wherein the number of search rows per cycle is 16, and each row arbitration takes 33 cycles.

[0031] Preferably, the row number arbitration core of the third arbitration method responds to each row of pixels in the array in turn according to a fixed interval.

[0032] Preferably, the row number arbitration core of the fourth arbitration mode is internally configured with a second maximum value search circuit with a parallelism of 16;

[0033] The priority values ​​of each row of the input configuration interface of the second maximum value search circuit are determined.

[0034] Preferably, when the control state machine reads data and writes it into the event queue, the read data of the event queue includes event information, row number and timestamp, and the event queue between the array readout circuit and the processing and interface circuit is in a non-full state.

[0035] The beneficial effects of the above technical solution are:

[0036] The array readout circuit supporting four arbitration modes proposed by the present invention meets the timing requirements of high-frequency (not less than 400MHz) operating frequency, and the total power consumption of the array readout circuit is only 63mW. The array readout circuit of the present invention not only supports the four mainstream arbitration modes, but also has the advantages of low hardware cost, high performance and programmability. In addition, the present invention realizes the flexible configuration of dynamic vision sensor array response and reset waveforms.

[0037] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description and the accompanying drawings.

[0038] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0040] Figure 1 A method flow chart of a method for designing a programmable array readout circuit supporting four arbitration modes in an embodiment of the present invention;

[0041] Figure 2 Schematic diagram of a circuit of a DVS pixel in an embodiment of the present invention;

[0042] Figure 3 is a circuit diagram of a pixel interface logic circuit in an embodiment of the present invention;

[0043] Figure 4 Schematic diagram of the circuit structure of the RR signal in an embodiment of the present invention;

[0044] Figure 5 Schematic diagram of the circuit structure of a programmable dynamic vision sensor array readout circuit supporting four arbitration modes in an embodiment of the present invention;

[0045] Figure 6 A schematic diagram of signal input and output of a request management module of the present invention;

[0046] Figure 7 FIG. 2 is a schematic diagram of the operation of the first-in, first-out arbitration method in an embodiment of the present invention. DETAILED DESCRIPTION

[0047] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0048] like Figure 1 As shown, this embodiment provides a method for designing a programmable array readout circuit that supports four arbitration modes, including:

[0049] Obtain the resolution of the dynamic vision sensor and determine the bit width parameters of the request bus, row reset bus and row response bus of the array readout circuit;

[0050] Based on the request bus, a row request module and a row number arbitration core are configured; wherein the row request module is used to obtain a row request signal for each pixel in the DVS array, and the row number arbitration core is used to set an arbitration mode for the row request signal;

[0051] Based on the row reset bus, a programmable array driver module is configured; wherein the programmable array driver module is used to generate a drive waveform according to a programmable timing parameter value, and respond to or reset a pixel row in the DVS array;

[0052] Based on the row response bus, a control state machine is configured; wherein the control state machine is used to control the row number arbitration core and the programmable array driver module to read the event row in the DVS array, and read the data and write it into the event queue.

[0053] The principle of the above technical solution is:

[0054] The present invention proposes a design method for the structure of a dynamic vision sensor array readout circuit. The readout circuit designed by the design method of the present invention is different from the existing dynamic vision sensor design that only supports one arbitration mode. The structure of the present invention supports four arbitration modes: first-in-first-out, sequential row selection, frame-by-frame method and region of interest.

[0055] In actual implementation, it is assumed that the resolution of the dynamic vision sensor is 512*512, so, Figure 5 The bit widths of the row request bus, row reset bus, and row response bus are all 512, but in fact, the structure can be adapted to other resolutions by expanding the signal bit width.

[0056] The "row request management module" realizes the order of read requests for each row in the array at a very low hardware cost. At the same time, the "row number calculation core" uses parallel search hardware to realize high-performance event row arbitration. The "programmable array driver module" outputs a flexible and configurable array drive waveform. Through the reading circuit designed by the present invention, when reading the DVS array signal, the array read circuit of the present invention not only supports the current four mainstream arbitration methods, but also has the advantages of low hardware cost, high performance and programmability.

[0057] The row number output by the row number arbitration core is sent to the programmable array driver module, which generates a flexible driving waveform according to the programmable timing parameter value to complete the response and reset of the pixel row in the array. The specific implementation method is: the number of cycles of the response and reset process can be configured, and the initial value and signal flip time of the Rrst and Rack signals can be configured at the same time. The programmable array driver module generates the corresponding waveform according to the configured number of cycles, initial value of the signal and flip time, thereby realizing the flexible configuration of the dynamic vision sensor array response and reset waveform.

[0058] The beneficial effects of the above technical solution are:

[0059] The array readout circuit supporting four arbitration modes proposed by the present invention meets the timing requirements of high-frequency (not less than 400MHz) operating frequency, and the total power consumption of the array readout circuit is only 63mW. The array readout circuit of the present invention not only supports the four mainstream arbitration modes, but also has the advantages of low hardware cost, high performance and programmability. In addition, the present invention realizes the flexible configuration of dynamic vision sensor array response and reset waveforms.

[0060] As an embodiment of the present invention, the input of the row request module is the row request signal Rreq in the DVS array and the row reset signal Rrst generated by the programming array driver module.

[0061] In actual implementation, the row request management module is used to record the order in which each row of pixels in the DVS array sends a row request (Rreq) signal. Its structure is as follows: Figure 6 The input of the row request management module is the row request signal Rreq of the array and the row reset signal Rrst generated by the programmable array driver module.

[0062] As an embodiment of the present invention, the row request signal is filtered to remove signal glitches through a preset control logic.

[0063] In actual implementation, the row request of the DVS array is sent to a preset control logic, which filters out signal glitches from analog circuits on the one hand, and performs cross-clock domain synchronization operations on the other hand to prevent the register from entering a metastable state.

[0064] As an embodiment of the present invention, the output signals of the preset control logic are: a load(n) signal and a clear(n) signal;

[0065] The load(n) signal indicates that the row request of the nth row of pixels in the DVS array changes from invalid to valid;

[0066] The clear(n) signal indicates the reset signal after the nth row of pixels in the DVS array is generated and read out.

[0067] In actual implementation, the output of the control logic is the load(n) and clear(n) signals. The load(n) signal indicates that the row request of the nth row of pixels in the DVS array has changed from "invalid" to "valid", and the clear(n) signal indicates that the nth row of pixels in the DVS array has completed the reset after reading. The load(n) signal will set the vld[n] status bit and row counter of the corresponding row to 1, and the clear(n) signal will clear the vld[n] status bit and row counter of the corresponding row to 0. The vld[n] status bit indicates whether the nth row of pixels in the array has generated an output request, and the size of the row counter records the order of the output request of this row and the output requests of other rows. Whenever a row request of any row in the array changes from "invalid" to "valid", the values ​​of all row counters with non-zero values ​​will be increased by 1. Therefore, the larger the value of the row counter, the longer the row request of the row of pixels will wait for a response. In the worst case, the value of the row counter is 511, so the bit width of the row counter is 9 bits. The output of the row request management module is 512 vld status bits and 512 row counter values. The 4 row number arbitration cores will complete the row number arbitration based on this information.

[0068] As an embodiment of the present invention, the bank number arbitration core includes: a first arbitration mode, a second arbitration mode, a third arbitration mode or a fourth arbitration mode;

[0069] Among them, the first arbitration method is to arbitrate by a first-in-first-out method;

[0070] The second arbitration method is to arbitrate by sequential row selection;

[0071] The third arbitration method performs arbitration by frame-by-frame reading;

[0072] The fourth arbitration method is to perform arbitration by setting an area of ​​interest.

[0073] In actual implementation, the four row number arbitration cores respectively implement the first-in-first-out arbitration method, the sequential row selection arbitration method, the frame-by-frame readout method, and the arbitration method based on the region of interest. The structure of the row number arbitration core for first-in-first-out arbitration is as follows: Figure 7 shown.

[0074] As an embodiment of the present invention, the row number arbitration core of the first arbitration mode is internally configured with a first maximum value search circuit with a parallelism of 16;

[0075] The row number arbitration core is also configured with a global maximum value register and a global maximum value sequence number register;

[0076] The first maximum value search circuit has 16 input data comparison operations in each cycle, and outputs the output data with the largest value and the output sequence number;

[0077] The first maximum value search circuit is inserted by a pipeline register of one stage.

[0078] The technical principle of the above technical solution is:

[0079] In actual implementation, there is a maximum value search circuit with a parallelism of 16 inside the row number arbitration core through first-in-first-out arbitration, so that the circuit can complete 16 input data comparison operations in each cycle and output the data with the largest value and its sequence number. A first-level pipeline register is inserted in the 16-parallel maximum value search circuit, so the circuit can operate at a high clock frequency. There is also a global maximum value register and a global maximum value sequence number register inside the row number arbitration core. The global maximum value sequence number register is used to record the row number with the largest row number counter in the entire array. The 512 row number counter values ​​will be sent to the 16-parallel maximum value search circuit in 32 clock cycles, so the time it takes for the row number arbitration core with first-in-first-out arbitration to complete each row number arbitration is 33 clock cycles (32 cycles + 1 pipeline delay).

[0080] As an embodiment of the present invention, the row number arbitration core of the second arbitration mode is used to search for a row signal with an output request from the previous response row number; wherein the number of search rows per cycle is 16, and each row number arbitration takes 33 cycles.

[0081] In actual implementation, the row number arbitration core of sequential row selection will search for rows with output requests starting from the row number of the last response. The number of search rows per cycle is 16, so each row number arbitration also takes 33 clock cycles.

[0082] As an embodiment of the present invention, the row number arbitration core of the third arbitration method sequentially responds to each row of pixels in the array according to a fixed interval.

[0083] In actual implementation, the row number arbitration core using the frame-by-frame readout method only needs to respond to each row of pixels in the array in sequence at fixed intervals, so there is no need for time-consuming arbitration.

[0084] As an embodiment of the present invention, the row number arbitration core of the fourth arbitration mode is internally configured with a second maximum value search circuit with a parallelism of 16;

[0085] The priority values ​​of each row of the input configuration interface of the second maximum value search circuit are determined.

[0086] In actual implementation, the structure of the row number arbitration core based on the region of interest is similar to that of the row number arbitration core for first-in-first-out arbitration, except that the input of the 16-parallel maximum value search circuit no longer comes from the row counter value of the row request management module, but from the row priority value of the configuration interface. Therefore, most of the logic in the row number arbitration core based on the region of interest can reuse the logic in the row number arbitration core for first-in-first-out arbitration, and the time consumption of each row number arbitration is also 33 clock cycles.

[0087] As an embodiment of the present invention, when the control state machine reads data and writes it into the event queue, the read data of the event queue includes event information, row number and timestamp, and the event queue between the array read-out circuit and the processing and interface circuit is in a non-full state.

[0088] In actual implementation, the control state machine is the controller of the entire array readout circuit. When the event queue between the "array readout circuit" and the "processing and interface circuit" is not full, the control state machine will control the row number arbitration core and the programmable array driver module to read the event row in the DVS array and write the read event information, row number and timestamp into the event queue.

[0089] The array readout circuit supporting four arbitration modes is described using Verilog HDL language and synthesized using the standard cell library of SMIC65 nanometer process. The target operating frequency of the array readout circuit is 400MHz. The comprehensive results show that the array readout circuit supporting four arbitration modes can meet the timing requirements of the 400MHz operating frequency. The area and power consumption of each module are shown in Table 1. It can be seen from Table 1 below that the area of ​​the array readout circuit is only about 0.26 square millimeters, which is much smaller than the DVS array area (usually the area of ​​the 512×512 resolution array is 512×512×7μm×7μm=12.85 square millimeters), and will not bring area burden to the dynamic vision sensor chip. At the same time, the total power consumption of the array readout circuit is only 63mW. The experimental results prove that the proposed DVS array readout circuit structure has the characteristics of low hardware cost and high performance.

[0090] Table 1

[0091]

[0092]

[0093] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for designing a programmable array readout circuit supporting four arbitration modes, characterized in that: include: Obtain the resolution of the dynamic vision sensor and determine the bit width parameters of the request bus, row reset bus and row response bus of the array readout circuit; Based on the request bus, a row request module and a row number arbitration core are configured; wherein the row request module is used to obtain a row request signal for each pixel in the DVS array, and the row number arbitration core is used to set an arbitration mode for the row request signal; Based on the row reset bus, a programmable array driver module is configured; wherein the programmable array driver module is used to generate a drive waveform according to a programmable timing parameter value, and respond to or reset a pixel row in the DVS array; Based on the row response bus, a control state machine is configured; wherein the control state machine is used to control the row number arbitration core and the programmable array driver module to read the event row in the DVS array, and read the data and write it into the event queue.

2. A method for designing a programmable array readout circuit supporting four arbitration modes as claimed in claim 1, characterized in that: The input of the row request module is the row request signal Rreq in the DVS array and the row reset signal Rrst generated by the programming array driving module.

3. A method for designing a programmable array readout circuit supporting four arbitration modes as claimed in claim 1, characterized in that: The row request signal is filtered through a preset control logic to filter out signal glitches.

4. A method for designing a programmable array readout circuit supporting four arbitration modes as claimed in claim 3, characterized in that: The output signals of the preset control logic are: a load(n) signal and a clear(n) signal; The load(n) signal indicates that the row request of the nth row of pixels in the DVS array changes from invalid to valid; The clear(n) signal indicates the reset signal after the nth row of pixels in the DVS array is generated and read out.

5. A method for designing a programmable array readout circuit supporting four arbitration modes as claimed in claim 4, characterized in that: The bank number arbitration core includes: the first arbitration method, the second arbitration method, the third arbitration method or the fourth arbitration method; Among them, the first arbitration method is to arbitrate by a first-in-first-out method; The second arbitration method is to arbitrate by sequential row selection; The third arbitration method performs arbitration by frame-by-frame reading; The fourth arbitration method is to perform arbitration by setting an area of ​​interest.

6. A method for designing a programmable array readout circuit supporting four arbitration modes as claimed in claim 5, characterized in that: The row number arbitration core of the first arbitration mode is internally configured with a first maximum value search circuit with a parallelism of 16; The row number arbitration core is also configured with a global maximum value register and a global maximum value sequence number register; The first maximum value search circuit has 16 input data comparison operations in each cycle, and outputs the output data with the largest value and the output sequence number; The first maximum value search circuit is inserted by a pipeline register of one stage.

7. A method for designing a programmable array readout circuit supporting four arbitration modes as claimed in claim 5, characterized in that: The row number arbitration core of the second arbitration mode is used to search for a row signal with an output request from the previous response row number; wherein the number of searched rows per cycle is 16, and the time consumed for each row arbitration is 33 cycles.

8. A method for designing a programmable array readout circuit supporting four arbitration modes as claimed in claim 5, characterized in that: The row number arbitration core of the third arbitration method sequentially responds to each row of pixels in the array according to a fixed interval.

9. A method for designing a programmable array readout circuit supporting four arbitration modes as claimed in claim 5, characterized in that: The row number arbitration core of the fourth arbitration mode is internally configured with a second maximum value search circuit with a parallelism of 16; The priority values ​​of each row of the input configuration interface of the second maximum value search circuit are determined.

10. A method for designing a programmable array readout circuit supporting four arbitration modes as claimed in claim 1, characterized in that: When the control state machine reads data and writes it into the event queue, the read data of the event queue includes event information, row number and timestamp, and the event queue between the array readout circuit and the processing and interface circuit is in a non-full state.

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