Semiconductor element including a plurality of

Abstract

The invention provides a semiconductor element and a preparation method of the semiconductor element. The semiconductor element comprises a substrate; a gate electrode disposed on the substrate; a first metal contact disposed in the gate electrode; a first spacer disposed on a sidewall of the gate electrode; and a second spacer covering the first spacer, wherein the first spacer includes a plurality of dopants.

Description

Technical Field

[0001] This application claims priority to U.S. patent application No. 18 / 507,406 (i.e., the priority date is "November 13, 2023"), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor device and a method for preparing the semiconductor device, and more particularly to a semiconductor device structure including a spacer structure having two or more spacers and a method for preparing the semiconductor device. Background Art

[0003] With the rapid development of the electronics industry, the development of integrated circuits (ICs) has achieved high performance and miniaturization. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation.

[0004] A dynamic random access memory (DRAM) element is a random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Typically, a DRAM is arranged in a square array with one capacitor and one transistor per cell. A vertical transistor has been developed for 4F 2 DRAM cells are developed with F, where F represents the minimum feature width or critical dimension (CD) of the lithography. In advanced DRAM technology, in addition to shrinking the DRAM array cell size, it is also very important to shrink the size of the core and peripheral circuits. In typical CMOS circuits, the core circuits implement the tightest spacing design rules, especially in the sense amplifier and sub-bit line driver circuits. However, the core circuit design rules of 10nm node DRAM begin to challenge the control gate (GC) space rules, and sufficient gaps are required to form a good shape in the GC-GC space, especially starting from the 1Bnm generation and even more advanced nodes, such as 1Cnm and above.

[0005] Currently, in the 1Bnm node, this is only achieved by reducing the GC gap oxide thickness, but due to the lightly-doped drain (LDD) implantation to form a deep source / drain (S / D) junction, it will affect the overall short channel performance of the transistor.

[0006] In the current environment, DRAM manufacturers face the great challenge of further reducing the memory cell area. In addition, the size of the peripheral area of ​​DRAM should be reduced accordingly, which makes the manufacturing process complicated.

[0007] The above “prior art” description only provides background technology, does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0008] An embodiment of the present disclosure provides a semiconductor element. The semiconductor element includes a substrate; a gate electrode disposed on the substrate; a first metal contact disposed in the gate electrode; a first spacer disposed on a side wall of the gate electrode; and a second spacer covering the first spacer; wherein the first spacer includes a plurality of dopants.

[0009] Another embodiment of the present disclosure provides a semiconductor element, which includes a substrate, a gate electrode disposed on the substrate, a first metal contact disposed in the gate electrode, a first spacer disposed on a side wall of the gate electrode, and a trench capacitor disposed above and in contact with the first metal contact.

[0010] Another embodiment of the present disclosure provides a method for preparing a semiconductor element. The preparation method includes providing a substrate and forming a first gate electrode and a second gate electrode above the substrate; forming a first lightly doped region in the substrate and between the first gate electrode and the second gate electrode; forming a first dielectric layer to cover the first gate electrode, the second gate electrode and the substrate; performing an etching technique to pattern the first dielectric layer; forming a first spacer on a side wall of the first gate electrode; forming a second spacer on a side wall of the second gate electrode, wherein the substrate is exposed through the first spacer and the second spacer; forming a second lightly doped region in the substrate and between the first spacer and the second spacer; forming a second dielectric layer to cover the first spacer, the second spacer, the first gate electrode, the second gate electrode and the substrate; performing an etching technique to pattern the second dielectric layer; A third spacer is formed to cover the first spacer; a fourth spacer is formed to cover the second spacer, wherein the substrate is exposed through the spacers; a heavily doped region is formed in the substrate and between the third spacer and the fourth spacer; a plurality of first metal contacts are formed in the first gate electrode and the second gate electrode; a second metal contact is formed in the heavily doped region between the first gate electrode and the second gate electrode; a first dielectric structure is formed above the substrate and between the first gate electrode and the second gate electrode; a second dielectric structure is formed above the first dielectric structure; a third dielectric structure is formed above the second dielectric structure; and a trench capacitor is formed to penetrate the third dielectric structure and the second dielectric structure to reach and contact the first metal contacts formed in the first gate electrode and the second gate electrode.

[0011] The present disclosure provides a method for fabricating a semiconductor device. The method includes a deposition-etch-deposition-etch (DEDE) process rather than a single deposition / single etch process, wherein the DEDE process defines multiple spacers to maintain precisely formed spacers in a tight spacing region. In addition, since multiple cycles of forming spacers are performed, the size of the spacers can be reduced.

[0012] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] A more complete understanding of the present disclosure may be obtained by referring to the detailed description and claims.The present disclosure should also be understood to be associated with the element numbers of the drawings, which represent similar elements throughout the description.

[0014] Figure 1 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0015] Figure 2 is a schematic cross-sectional view illustrating a semiconductor device having a trench capacitor according to some embodiments of the present disclosure.

[0016] Figure 3 It is a schematic flow chart illustrating a method for preparing a semiconductor element according to some embodiments of the present disclosure.

[0017] Figure 4 is a schematic cross-sectional view illustrating one or more stages of an exemplary preparation method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0018] Figure 5 is a schematic cross-sectional view illustrating one or more stages of an exemplary preparation method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0019] Figure 6 is a schematic cross-sectional view illustrating one or more stages of an exemplary preparation method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0020] Figure 7 is a schematic cross-sectional view illustrating one or more stages of an exemplary preparation method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0021] Figure 8 is a schematic cross-sectional view illustrating one or more stages of an exemplary preparation method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0022] Fig. 9is a schematic cross-sectional view illustrating one or more stages of an exemplary preparation method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0023] Fig.10 is a schematic cross-sectional view illustrating one or more stages of an exemplary preparation method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0024] Fig.11 is a schematic cross-sectional view illustrating one or more stages of an exemplary preparation method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0025] Fig.12 is a schematic cross-sectional view illustrating one or more stages of an exemplary preparation method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0026] Fig.13 is a schematic cross-sectional view illustrating one or more stages of an exemplary preparation method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0027] Fig.14 is a schematic cross-sectional view illustrating one or more stages of an exemplary preparation method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0028] Fig.15 is a schematic cross-sectional view illustrating one or more stages of an exemplary preparation method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0029] Fig.16 is a schematic cross-sectional view illustrating one or more stages of an exemplary preparation method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0030] Fig.17 is a schematic cross-sectional view illustrating one or more stages of an exemplary preparation method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0031] Fig.18 is a schematic cross-sectional view illustrating one or more stages of an exemplary preparation method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0032] Fig.19 is a schematic cross-sectional view illustrating one or more stages of an exemplary preparation method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0033] Fig. 20 is a schematic cross-sectional view illustrating one or more stages of an exemplary preparation method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0034] Fig.21is a schematic cross-sectional view illustrating one or more stages of an exemplary preparation method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0035] Fig. 22 is a schematic cross-sectional view illustrating one or more stages of an exemplary preparation method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0036] The reference numerals are described as follows:

[0037] 100: Semiconductor components

[0038] 110: Base

[0039] 121: Lightly doped region

[0040] 122: Lightly doped region

[0041] 131-1: First gate dielectric layer

[0042] 131-2: Second gate dielectric layer

[0043] 132-1: First gate electrode

[0044] 132-1s: Upper surface

[0045] 132-1s1: Surface

[0046] 132-2: Second gate electrode

[0047] 132-2s: Upper surface

[0048] 132-2s1: Surface

[0049] 151-1: Gap substructure

[0050] 151-2: Interstitial substructure

[0051] 151s: Surface

[0052] 160: Adulterants

[0053] 171: Doping area

[0054] 171s: Upper surface

[0055] 173: Second metal contact

[0056] 173s: Upper surface

[0057] 180a: First dielectric structure

[0058] 180a-s1: upper surface

[0059] 180b: Second dielectric structure

[0060] 180c: The third dielectric structure

[0061] 180c-C: Corner

[0062] 180c-s1: upper surface

[0063] 191: Conductive elements

[0064] 191-1: First metal contact

[0065] 191-1s: Upper surface

[0066] 191-2: First metal contact

[0067] 191-2s: Upper surface

[0068] 200: Semiconductor components

[0069] 300: Preparation method

[0070] 302: Steps

[0071] 304: Steps

[0072] 306: Steps

[0073] 308: Steps

[0074] 310: Steps

[0075] 312: Steps

[0076] 314: Steps

[0077] 316: Steps

[0078] 318: Steps

[0079] 1511-1: Interstitial

[0080] 1511-2: Interstitial

[0081] 1511a: Dielectric layer

[0082] 1511p1: Part

[0083] 1512-1: Interstitial

[0084] 1512-1s1: Surface

[0085] 1512-2: Interstitial

[0086] 1512a: Dielectric layer

[0087] C: Trench capacitor

[0088] C1: Lower metal layer

[0089] C1H: Horizontal section

[0090] C1V: Vertical section

[0091] C2: Middle insulation layer

[0092] C3: Upper metal layer

[0093] D1: Distance

[0094] D2: Distance

[0095] H1: Size

[0096] H2: Size

[0097] H3: Size

[0098] OP: Opening

[0099] PL: Photoresist layer

[0100] PML: Patterned Mask Layer

[0101] SO: Sacrificial oxide layer

[0102] SP1: The first step

[0103] SP2: The second step

[0104] SP3: First step

[0105] SP4: Second step

[0106] SW5: Sidewall

[0107] SW61: Part I

[0108] SW62: Part 2

[0109] T1: Thickness

[0110] TR: Groove

[0111] TSC1: Top surface

[0112] W1: first horizontal width

[0113] W2: Second horizontal width DETAILED DESCRIPTION

[0114] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0115] It will be understood that when an element is referred to as being “connected to” or “coupled to” another element, the original element may be directly connected to or coupled to the other element or other intervening elements may be present.

[0116] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive conception of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0117] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the above.

[0118] It should be understood that in the description of the present disclosure, the term "about" is used to change the quantity of the ingredients, components or reactants of the present disclosure, meaning, for example, the quantitative changes that may occur by typical measurements and liquid handling procedures used to prepare concentrates or solutions. Furthermore, inadvertent errors in measurement procedures, differences in the manufacture, source or purity of the ingredients used to make the composition or implement the method, etc. may cause changes. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. Furthermore, in another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2 or 1% of the reported value.

[0119] Figure 1 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0120] The semiconductor device 100 may include an array region (not shown) and a peripheral region (not shown). The array region may be at least partially surrounded by the peripheral region. The array region may be used to form a memory element. For example, the memory element may include a dynamic random access memory (DRAM) element, a one-time programming (OTP) memory element, a static random access memory (SRAM) element, or other suitable memory element. A plurality of columns may be formed in the array region. Each column may include a capacitor and other suitable structures. The array region may include transistors for turning on and / or turning off the memory element.

[0121] In some embodiments, for example, the peripheral region can be used to form amplifier circuits or other suitable circuits. The circuits in the peripheral region can be signally and / or electrically coupled to components (eg, capacitors and transistors) in the array region.

[0122] The semiconductor device 100 may include a substrate 110. The aforementioned components of the array region and the peripheral region may be formed in and / or on the substrate 110. The substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, or the like. The substrate 110 may include an elemental semiconductor, including silicon or germanium in a single crystal form, a polycrystalline form, or an amorphous form; a compound semiconductor material, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy having a gradient SiGe feature, wherein the Si and Ge composition changes from one ratio at one location of the gradient SiGe feature to another ratio at another location. In another embodiment, the SiGe alloy is formed above a silicon substrate. In some embodiments, the SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy.

[0123] In some embodiments, the semiconductor element 100 may further include first and second gate dielectric layers 131 - 1 and 131 - 2 , first and second gate electrodes 132 - 1 and 132 - 2 , spacer structures 151 - 1 and 151 - 2 , a doped region 171 , first and second dielectric structures 180 a and 180 b , and a conductive element 191 .

[0124] In some embodiments, each of the gate dielectric layers 131-1 and 131-2 may be disposed on the substrate 110. Each of the gate dielectric layers 131-1 and 131-2 may have a single layer or may include a multilayer structure. In some embodiments, each of the gate dielectric layers 131-1 and 131-2 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or a combination thereof. In some embodiments, each of the gate dielectric layers 131-1 and 131-2 is a multilayer structure including an interface layer and a high-k dielectric layer (i.e., having a dielectric constant greater than 4). The interface layer may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or a combination thereof. The high-k dielectric layer may include a high-k dielectric material, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, other appropriate high-k dielectric materials, or a combination thereof. In some embodiments, the high-k dielectric material may also be selected from metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, and combinations thereof.

[0125] In some embodiments, each of the gate electrodes 132-1 and 132-2 may be disposed on the substrate 110. The first gate electrode 132-1 may be disposed on the first gate dielectric layer 131-1. The second gate electrode 132-2 may be disposed on the second gate dielectric layer 131-2.

[0126] Each gate electrode 132-1 and 132-2 may include polysilicon, silicon-germanium, and at least one metal material, including elements and compounds such as Mo, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, or other suitable conductive materials known in the art. In some embodiments, each of the gate electrodes 132-1 and 132-2 includes a work function metal layer that provides an n-type metal work function or a p-type metal work function for the metal gate. The p-type metal work function material includes materials such as ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or other suitable materials. The n-type metal work function material includes materials such as hafnium zirconium, titanium, tantalum, aluminum, metal carbides (such as hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or other suitable materials.

[0127] In some embodiments, the gap substructure 151-1 may be disposed on the surface 132-1s1 of the first gate electrode 132-1. In some embodiments, the gap substructure 151-1 may be disposed on a sidewall ( Figure 1 The spacer structure 151-1 may include a spacer 1511-1 and a spacer 1512-1.

[0128] In some embodiments, the spacer 1511-1 may be disposed on the surface 132-1s1 of the first gate electrode 132-1. The spacer 1511-1 may be disposed between the spacer 1512-1 and the first gate electrode 132-1. The spacer 1511-1 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or a combination thereof.

[0129] In some embodiments, interstitial 1511-1 may be doped with a plurality of dopants 160. Each dopant 160 may have a p-type conductivity or an n-type conductivity. In some embodiments, the p-type dopant may include boron (B), other group III elements, or any combination thereof. In some embodiments, the n-type dopant may include arsenic (As), phosphorus (P), other group V elements, or any combination thereof. In some embodiments, dopant 160 may be located at a surface 151s adjacent to interstitial 1511-1. Surface 151s may also be considered an interface between interstitial 1511-1 and 1512-1.

[0130] In some embodiments, spacer 1512-1 may be disposed on spacer 1511-1. In some embodiments, spacer 1512-1 may cover spacer 1511-1. The fabrication techniques of spacers 1511-1 and 1512-1 may include two cycles of depositing and patterning (or etching) dielectric layers. In some embodiments, spacer 1512-1 may cover surface 151s of spacer 1511-1. Spacer 1512-1 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or a combination thereof. In some embodiments, the material of spacer 1512-1 may be the same as the material of spacer 1511-1. In some embodiments, the material of spacer 1512-1 may be different from the material of spacer 1511-1. Spacer 1512-1 may have a surface 1512-1s1 (or outer surface) facing away from spacer 1511-1. In some embodiments, a surface roughness of the surface 151 s may be greater than a surface roughness of the surface 1512 - 1 s 1 .

[0131] In some embodiments, the gap substructure 151-2 may be disposed on the surface 132-2s1 of the second gate electrode 132-2. In some embodiments, the gap substructure 151-2 may be disposed on a sidewall ( Figure 1 The interstitial structure 151-2 may include interstitial 1511-2 and interstitial 1512-2.

[0132] In some embodiments, the spacer 1511-2 may be disposed on the surface 132-2s1 of the second gate electrode 132-2. The spacer 1511-2 may be disposed between the spacer 1512-2 and the second gate electrode 132-2. The spacer 1511-2 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or a combination thereof. The material of the spacer 1511-2 may be the same as the material of the spacer 1511-1. In some embodiments, the spacer 1511-2 may be doped with a plurality of dopants 160.

[0133] In some embodiments, spacer 1512-2 may be disposed on spacer 1511-2. In some embodiments, spacer 1512-2 may cover spacer 1511-2. The fabrication techniques for spacers 1511-2 and 1512-2 may include two cycles of depositing and patterning (or etching) dielectric layers. Spacer 1512-2 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or a combination thereof. In some embodiments, the material of spacer 1512-2 may be the same as the material of spacer 1511-2. In some embodiments, the material of spacer 1512-2 may be different from the material of spacer 1511-2.

[0134] In some embodiments, heavily doped region 171 may be formed in substrate 110. In some embodiments, heavily doped region 171 may be located between gap structures 151-1 and 151-2. In some embodiments, heavily doped region 171 may be located between gap structures 1512-1 and 1512-2. In some embodiments, heavily doped region 171 may be located outside of a region overlapping gap structure 1511-1 along a Z direction. In some embodiments, heavily doped region 171 may be outside of a region overlapping gap structure 1511-2 along a Z direction. Heavily doped region 171 may be used as a source region or a drain region of semiconductor element 100. Heavily doped region 171 may include p-type dopants or n-type dopants.

[0135] In some embodiments, the heavily doped region 171 may have a dimension H1 (eg, width or length) along an X direction. In some embodiments, the dimension H1 of the heavily doped region 171 may be determined by the dimensions of the gap substructures 151-1 and 151-2 ( Figure 1 (not indicated in the table) is determined by

[0136] An upper surface 180a-s1 of the first dielectric structure 180a may be coplanar with the upper surface 132-1s of the first gate electrode 132-1. The upper surface 180a-s1 of the first dielectric structure 180a may be coplanar with the upper surface 132-2s of the second gate electrode 132-2. The first dielectric structure 180a may cover the gap substructure 151-1. The first dielectric structure 180a may cover the gap substructure 151-2. The first dielectric structure 180a may cover the gap substructure 151-2. The first dielectric structure 180a may cover the gap substructure 1511-1. The first dielectric structure 180a may cover the gap substructure 1512-1. The first dielectric structure 180a may cover the gap substructure 1511-2. The first dielectric structure 180a may cover the gap substructure 1512-2. The second dielectric structure 180b may cover the first dielectric structure 180a. In some embodiments, the first dielectric structure 180 a and the second dielectric structure 180 b may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or combinations thereof.

[0137] In some embodiments, the conductive element 191 may be disposed on the substrate 110. In some embodiments, the conductive element 191 may be disposed between the interstitial substructures 151-1 and 151-2. In some embodiments, the conductive element 191 may penetrate the dielectric structures 180a and 180b. In some embodiments, the conductive element 191 may contact the interstitial substructure 151-1. In some embodiments, the conductive element 191 may contact the interstitial substructure 1512-1. In some embodiments, the conductive element 191 may be separated from the interstitial substructure 1511-1 by the interstitial substructure 1512-1. The conductive element 191 may be connected (e.g., electrically connected) to the heavily doped region 171. In some embodiments, the conductive element 191 may include a conductive material such as tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), molybdenum (Mo), tantalum nitride (TaN), titanium, titanium nitride (TiN), the like, or a combination thereof.

[0138] By miniaturizing memory elements (e.g., components in the array region), the size of components in the peripheral region and / or the distance between components are reduced. For example, the size of the source / drain region (e.g., heavily doped region 171), the size of the gate electrode (e.g., gate electrodes 132-1 and 132-2), and the distance between gate electrodes 132-1 and 132-2 in the peripheral region are reduced. However, in order to achieve the electronic performance required of the semiconductor device 100, the size (e.g., thickness) of the gap substructure (e.g., gap substructure 151-1 and 151-2) cannot be proportionally reduced. In a comparative example, the gap substructure manufacturing technique includes a cycle of depositing and patterning a dielectric layer. The dielectric layer deposited between the gate electrodes can have a considerable thickness. As a result, after performing an etching technique, the dielectric layer can remain above the area where the heavily doped region (e.g., source / drain region) is formed. Therefore, the heavily doped region cannot be formed correctly. To solve such a problem, in some embodiments of the present disclosure, the manufacturing technique of a gap substructure (e.g., gap substructures 151-1 and 151-2) may include at least two cycles of depositing and patterning a dielectric layer, which ensures that the dielectric layer can be patterned correctly. As a result, the heavily doped region 171 can be properly formed in the substrate 110.

[0139] In some embodiments, the semiconductor device 100 may further include a lightly doped region 121 and a lightly doped region 122 .

[0140] In some embodiments, the lightly doped region 121 may be located within the substrate 110. The lightly doped region 121 may be located between the interstitial substructures 151-1 and 151-2. In some embodiments, the lightly doped region 121 may overlap the interstitial 1511-1 along the Z direction. In some embodiments, the lightly doped region 121 may overlap the interstitial 1512-1 along the Z direction. In some embodiments, the lightly doped region 121 may overlap the interstitial 1511-2 along the Z direction. In some embodiments, the lightly doped region 121 may overlap the interstitial 1512-2 along the Z direction. The lightly doped region 121 may overlap the heavily doped region 171. The lightly doped region 121 may be used as a lightly doped source (LDS) or a lightly doped drain (LDD). A dopant concentration of the lightly doped region 121 may be less than a dopant concentration of the heavily doped region 171. The lightly doped region 121 may have the same conductivity type as the heavily doped region 171. In some embodiments, the lightly doped region 121 may have a dimension H2 (eg, width or length) along the X direction. In some embodiments, the dimension H2 of the lightly doped region 121 may be determined by a distance ( Figure 1 (not shown) determined by

[0141] In some embodiments, lightly doped region 122 may be located within substrate 110. Lightly doped region 122 may be located between spacers 1511-1 and 1511-2. In some embodiments, lightly doped region 121 may overlap spacer 1512-1 along the Z direction. In some embodiments, lightly doped region 122 may be optional. In some embodiments, lightly doped region 121 may overlap spacer 1512-2 along the Z direction. In some embodiments, a portion 1511p1 of spacer 1511-1 may overlap an area outside lightly doped region 122 along the Z direction. In some embodiments, a portion ( Figure 1The lightly doped region 122 may overlap with an area outside the lightly doped region 122 along the Z direction. The lightly doped region 122 may overlap with the lightly doped region 121. The lightly doped region 122 may overlap with the heavily doped region 171. The lightly doped region 122 may be used as an LDD or an LDS. The dopant concentration of the lightly doped region 122 may be less than the dopant concentration of the heavily doped region 171. The dopant concentration of the lightly doped region 122 may be the same or similar to the dopant concentration of the lightly doped region 121. The lightly doped region 122 may have the same conductivity type as the heavily doped region 171. In some embodiments, the dopant of the lightly doped region 122 may be the same as the dopant 160. For example, when the dopant 160 includes phosphorus, the lightly doped region 122 includes phosphorus. In some embodiments, the lightly doped region 122 may have a dimension H3 (e.g., width or length) along the X direction. In some embodiments, a size H3 of the lightly doped region 122 may be smaller than a size H2 of the lightly doped region 121 .

[0142] In some embodiments, the size H3 of the lightly doped region 122 may be determined by a distance D1 between the spacers 1511-1 and 1512-1. In some embodiments, the size H3 of the lightly doped region 122 may be determined by a thickness T1 of the spacers 1511-1 and 1511-2. In some embodiments, a depth of the lightly doped region 122 may be greater than a depth of the lightly doped region 121.

[0143] In some embodiments, the size H1 of the heavily doped region 171 may be determined by a distance D2 between the spacers 1512 - 1 and 1512 - 2 . In some embodiments, a depth of the heavily doped region 171 may be greater than a depth of the lightly doped region 122 .

[0144] In some embodiments, the manufacturing technique of the spacer structures 151-1 and 151-2 may include at least two cycles of depositing and patterning dielectric layers, and the size H3 of the lightly doped region 122 may be determined and / or controlled by the spacers formed in the first cycle. Therefore, at least two profiles of the LDD (or LDS) may be precisely modified and / or controlled.

[0145] In some embodiments, the semiconductor device 100 may also include a second metal contact 173 and first metal contacts 191 - 1 and 191 - 2 .

[0146] In some embodiments, the second metal contact 173 may be disposed in the substrate 110. In some embodiments, the second metal contact 173 may be disposed in the lightly doped region 121. In some embodiments, the second metal contact 173 may be located between the gate electrodes 132-1 and 132-2. That is, each second metal contact 173 may be located between two adjacent gate electrodes. In some embodiments, the second metal contact 173 may contact the conductive element 191. In some embodiments, the second metal contact 173 is a metal silicide contact. In some embodiments, an upper surface 173s of the second metal contact 173 may be coplanar with an upper surface 171s of the heavily doped region 171.

[0147] In some embodiments, the first metal contact 191-1 may be disposed in the first gate electrode 132-1. In some embodiments, an upper surface 191-1s of the first metal contact 191-1 may be coplanar with an upper surface 132-1s of the first gate electrode 132-1. In some embodiments, the first metal contact 191-1 may contact the second dielectric structure 180b. In some embodiments, the first metal contact 191-1 is a metal silicide contact.

[0148] The first metal contact 191-2 may be disposed on the second gate electrode 132-2. In some embodiments, an upper surface 191-2s of the first metal contact 191-2 may be coplanar with an upper top surface 132-2s of the second gate electrode 132-2. In some embodiments, the first metal contact 191-2 may contact the second dielectric structure 180b. In some embodiments, the first metal contact 191-2 is a metal silicide contact.

[0149] Figure 2 FIG. 2 is a cross-sectional view schematically illustrating a semiconductor device 200 having a trench capacitor C according to some embodiments of the present disclosure. The semiconductor device 200 comprises Figure 1 Based on the semiconductor device 100, the semiconductor device 200 further includes a third dielectric structure 180c and a trench capacitor C.

[0150] The third dielectric structure 180c is disposed above the second dielectric structure 180b. Fig.16180a, the second dielectric structure 180b and the third dielectric structure 180c are formed in the first dielectric structure 180a, the second dielectric structure 180b and the third dielectric structure 180c. The first metal contact 191-1 can be exposed by the trench TR. The first metal contact 191-2 can also be exposed by the trench TR. Since the structures of the first metal contact 191-1 and the first metal contact 191-2 are the same, the diagram of the structure of the first metal contact 191-1 is used as a representative diagram of the first metal contact 191-2, and the diagram of the structure of the first metal contact 191-2 is omitted. The trench TR penetrates the second dielectric structure 180b and the third dielectric structure 180c to reach the upper surface 191-1s of the first metal contact 191-1. The trench capacitor C is set in the trench TR.

[0151] The trench capacitor C is a metal-insulator-metal structure, including a lower metal layer C1, an intermediate insulating layer C2, and an upper metal layer C3. The lower metal layer C1 is disposed along a contour of the trench TR. More specifically, the lower metal layer C1 is disposed to contact the upper surface 191-1s of the first metal contact 191-1 and to cover a side wall SW5 of the second dielectric structure 180b and a first portion SW61 of a side wall of the third dielectric structure 180c. Figure 2 As shown, the lower metal layer C1 includes a horizontal portion C1H and a vertical portion C1V. The horizontal portion C1H contacts the upper surface 191-1s of the first metal contact 191-1, and the vertical portion C1V contacts the sidewall SW5 of the second dielectric structure 180b and the first portion SW61 of the sidewall of the third dielectric structure 180c.

[0152] The middle insulating layer C2 is provided to cover the lower metal layer C1 and the third dielectric structure 180c. More specifically, the middle insulating layer C2 contacts the lower metal layer C1, a second portion SW62 of the sidewall of the third dielectric structure 180c, and an upper surface 180c-s1 of the third dielectric structure 180c. It should be understood that the first portion SW61 and the second portion SW62 of the sidewall of the third dielectric structure are arranged substantially in a straight line. Figure 2 As shown, the middle insulating layer C2 includes a first stepped portion SP1 and a second stepped portion SP2. The first stepped portion SP1 contacts an upper surface TSC1 of the vertical portion C1V of the lower metal layer C1, and the second stepped portion SP2 contacts an upper surface 180c-s1 of the third dielectric structure 180c and a second portion SW62 of the sidewall of the third dielectric structure 180c. Therefore, the second stepped portion SP2 of the middle insulating layer C2 contacts a corner 180c-C (defined by the corner 180c-C) connecting the upper surface 180c-s1 of the third dielectric structure 180c to the second portion SW62 of the sidewall of the third dielectric structure 180c. Figure 2 The dotted circle in the figure indicates contact.

[0153] The upper metal layer C3 is provided to cover the middle insulating layer C2. In some embodiments, the upper metal layer C3 completely covers the middle insulating layer C2. The upper metal layer C3 includes a first stepped portion SP3 and a second stepped portion SP4. The first stepped portion SP3 of the upper metal layer C3 covers the first stepped portion SP1 of the middle insulating layer C2, and the second stepped portion SP4 of the upper metal layer C3 covers the second stepped portion SP2 of the middle insulating layer C2.

[0154] like Figure 2 As shown, a profile of the upper metal layer C3 of the trench capacitor C forms an opening OP extending from the third dielectric structure 180c to the second dielectric structure 180b. The opening OP has a first horizontal width W1 associated with the first stepped portion SP3 of the upper metal layer C3 and a second horizontal width W2 associated with the second stepped portion SP4 of the upper metal layer C3. The second horizontal width W2 is greater than the first horizontal width W1.

[0155] In some embodiments, the lower metal layer C1 includes TiN. In some other embodiments, the lower metal layer C1 includes titanium silicon nitride (TiSiN). In some embodiments, the intermediate insulating layer C2 is a high-k dielectric layer including zirconium oxide (ZrO2), hafnium oxide (HfO2), titanium oxide (TiO2) or a combination thereof. In some embodiments, the upper metal layer C3 includes TiN. In some other embodiments, the upper metal layer C3 includes titanium silicon nitride (TiSiN).

[0156] Figure 3 3 is a flow chart illustrating a method 300 for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0157] The manufacturing method 300 may begin at step 302, where a substrate is provided. A first gate electrode and a second gate electrode may be formed on the substrate.

[0158] The fabrication method 300 may continue with step 304 where a first lightly doped region is formed in the substrate and between the first gate electrode and the second gate electrode.

[0159] The preparation method 300 may continue with step 306, wherein a first dielectric layer is formed to cover the first gate electrode, the second gate electrode, and the substrate. An etching technique is performed to pattern the first dielectric layer. A first spacer may be formed on a side wall of the first gate electrode. A second spacer may be formed on a side wall of the second gate electrode. The substrate may be exposed by the first spacer and the second spacer.

[0160] The fabrication method 300 may continue with step 308 , where a second lightly doped region is formed in the substrate and between the first spacer and the second spacer.

[0161] The preparation method 300 may continue with step 310, wherein a second dielectric layer is formed to cover the first spacer, the second spacer, the first gate electrode, the second gate electrode, and the substrate. An etching technique is performed to pattern the second dielectric layer. A third spacer may be formed to cover the first spacer. A fourth spacer may be formed to cover the second spacer. The substrate may be exposed.

[0162] The fabrication method 300 may continue with step 312 where a heavily doped region is formed in the substrate and between the third spacer and the fourth spacer.

[0163] The fabrication method 300 may continue with step 314 , where a plurality of first metal contacts are formed in the first gate electrode and the second gate electrode, and a second metal contact is formed in the heavily doped region and between the first gate electrode and the second gate electrode.

[0164] The fabrication method 300 may continue with step 316 , where a first dielectric structure is formed over the substrate and between the first gate electrode and the second gate electrode, and a second dielectric structure is formed over the first dielectric structure.

[0165] The fabrication method 300 may continue with step 318 , where a third dielectric structure is formed over the second dielectric structure, and a trench capacitor is formed to penetrate the third dielectric structure and the second dielectric structure to reach and contact a first metal contact formed in the first gate electrode and the second gate electrode.

[0166] Preparation method 300 is merely an example and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional steps may be provided before, during, or after each step of preparation method 300, and some of the steps described may be replaced, eliminated, or reordered for additional embodiments of the preparation method. In some embodiments, preparation method 300 may include Figure 3 In some embodiments, the preparation method 300 may include: Figure 3 One or more steps are depicted.

[0167] Figures 4 to 13 1 is a schematic cross-sectional view illustrating one or more stages of an exemplary preparation method for manufacturing a semiconductor element 100 according to some embodiments of the present disclosure.

[0168] Please refer to Figure 4, a substrate 110 may be provided. A first gate dielectric layer 131-1 and a second gate dielectric layer 131-2 may be formed on the substrate 110. A first gate electrode 132-1 may be formed on the first gate dielectric layer 131-1. A second gate electrode 132-2 may be formed on the second gate dielectric layer 131-2. The manufacturing technology of each of the gate dielectric layers 131-1 and 131-2 and the gate electrodes 132-1 and 132-2 may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD) or other appropriate processes.

[0169] Please refer to Figure 5 , a lightly doped region 121 may be formed in the substrate 110 and between the gate electrodes 132-1 and 132-2. It should be understood that the step of forming the lightly doped region 121 may be performed before the step of forming the gate electrodes 132-1 and 132-2.

[0170] Please refer to Figure 6 A dielectric layer 1511a may be formed to cover the gate electrodes 132-1 and 132-2. The dielectric layer 1511a may cover the substrate 110. For example, the manufacturing technology of the dielectric layer 1511a may include CVD, ALD, PVD, LPCVD, PECVD or other appropriate processes.

[0171] Please refer to Figure 7 An etching technique may be performed. The dielectric layer 1511a may be patterned to form a spacer 1511-1 on a sidewall 132-1s1 of the first gate electrode 132-1 and a spacer 1511-2 on a sidewall 132-2s1 of the second gate electrode 132-2. The substrate 110 may be exposed.

[0172] Please refer to Figure 8 , a lightly doped region 122 may be formed in substrate 110 and between spacers 1511-1 and 1511-2. In some embodiments, spacers 1511-1 and 1511-2 may be doped with a plurality of dopants 160. In some embodiments, dopants 160 may be located adjacent to an outer surface of spacer 1511-1 or an interface between spacers 1511-1 and 1511-2.

[0173] A size of the lightly doped region 122 may be determined by a distance between the spacers 1511 - 1 and 1511 - 2 .

[0174] Please refer to Fig. 9, a dielectric layer 1512a may be formed to cover the gate electrodes 132-1 and 132-2. The dielectric layer 1512a may cover the spacers 1511-1 and 1511-2. The dielectric layer 1512a may cover the substrate 110. For example, the manufacturing technology of the dielectric layer 1512a may include CVD, ALD, PVD, LPCVD, PECVD or other appropriate processes. A material of the dielectric layer 1512a may be the same as a material of the dielectric layer 1511a.

[0175] Please refer to Fig.10 An etching technique may be performed. Dielectric layer 1512a may be patterned to form spacer 1512-1 on spacer 1511-1 and spacer 1512-2 on spacer 1511-2. Substrate 110 may be exposed. Spacer structures 151-1 and 151-2 may be formed.

[0176] Please refer to Fig.11 A heavily doped region 171 may be formed in the substrate 110 and between the spacers 1512 - 1 and 1512 - 2 . A size of the lightly doped region 122 may be determined by a distance between the spacers 1512 - 1 and 1512 - 2 .

[0177] Please refer to Fig.12 , a heat treatment is performed to form at least the portions of the substrate 110 between the first gate electrode 132-1 and the second gate electrode 132-2 in the second metal contact 173, and to form the upper portions of the first gate electrode 132-1 and the second gate electrode 132-2 as the first metal contacts 191-1 and 191-2, respectively. In some embodiments, the second metal contact 173 and the first metal contacts 191-1 and 191-2 are metal silicide contacts. In some embodiments, the heat treatment for forming the second metal contact 173 and the first metal contacts 191-1 and 191-2 is preferably a rapid thermal annealing (RTA) process.

[0178] Please refer to Fig.13, a first dielectric structure 180a may be formed to cover the substrate 110, wherein the first dielectric structure 180a is located between the first gate electrode 132-1 and the second gate electrode 132-2. In some embodiments, an upper surface 180a-s1 of the first dielectric structure 180a may be coplanar with an upper surface 132-1s of the first gate electrode 132-1; and an upper surface 180a-s1 of the first dielectric structure 180a may be coplanar with an upper surface 132-2s of the second gate electrode 132-2. The first dielectric structure 180a may cover the gap substructure 151-1. The first dielectric structure 180a may cover the gap substructure 151-2. The first dielectric structure 180a may cover the gap substructure 1511-1. The first dielectric structure 180a may cover the gap substructure 1512-1. The first dielectric structure 180a may cover the gap substructure 1511-2. The first dielectric structure 180a may cover the spacer 1512-2. A second dielectric structure 180b may be formed to cover the first dielectric structure 180a and the gate electrodes 132-1 and 132-2. A conductive element 191 may be formed to connect to the second metal contact 173 formed in the heavily doped region 171. As a result, a structure such as Figure 1 A semiconductor component 100 is shown.

[0179] Figures 14 to 22 2 is a cross-sectional schematic diagram illustrating one or more stages of an exemplary preparation method for manufacturing a semiconductor device 200 based on the semiconductor device 100 according to some embodiments of the present disclosure.

[0180] like Fig.14 As shown, a photoresist layer PL is patterned to form a patterned mask layer PML on a third dielectric structure 180c. A material of the patterned mask layer PML is the same as a material of the photoresist layer PL. The photoresist layer PL is patterned by performing a lithography process. The photoresist layer PL is exposed to a processing light according to a mask (not shown). The wavelength of the processing light is related to a critical dimension of a trench TR (e.g., Fig.16 ). In some embodiments, the processing light is a deep ultraviolet (DUV) radiation. In other embodiments, the processing light is an extreme ultraviolet (EUV) radiation, and the lithography process is EUV lithography. After exposure to the processing light, the pattern on the mask is transferred to the photoresist layer PL. The photoresist layer PL is then etched according to the transferred pattern to form a patterned mask layer PML.

[0181] like Fig.15As shown, the third dielectric structure 180c and the second dielectric structure 180b are etched according to the patterned mask layer PML, and the upper surface 191-1s of the metal contact 191-1 is exposed after etching. In some embodiments, the third dielectric structure 180c, the second dielectric structure 180b, and the first dielectric structure 180a are etched by a dry etching process such as reactive ion etching (RIE). Fig.16 In some embodiments, the upper surface 191-1s of the first metal contact 191-1 is partially exposed. However, the present disclosure is not limited thereto. In some embodiments, the upper surface 191-1s of the first metal contact 191-1 is completely exposed after etching.

[0182] like Fig.16 As shown, the patterned mask layer PML is removed to expose the upper surface 180c-s1 of the third dielectric structure 180c, and a trench TR is formed. In some embodiments, the trench TR is wider at the third dielectric structure 180c and at a portion of the second dielectric structure 180b away from the first metal contact 191-1, and the trench TR is narrower at a portion of the second dielectric structure 180b adjacent to the first metal contact 191-1, as shown in FIG. Fig.16 shown.

[0183] like Fig.17 As shown, a lower metal layer C1 is deposited on the third dielectric structure 180c and along a profile of the trench TR. In some embodiments, the lower metal layer C1 is deposited by performing a CVD process. The lower metal layer C1 has a substantially uniform thickness along the profile of the trench TR. Fig.17 As shown, the lower metal layer C1 includes a horizontal portion C1H and a vertical portion C1V. The horizontal portion C1H contacts the upper surface 191-1s of the first metal contact 191-1, and the vertical portion C1V contacts a side wall SW5 of the second dielectric structure 180b, a first portion SW61 of a side wall of the third dielectric structure 180c, and a second portion SW62 of a side wall of the third dielectric structure 180c.

[0184] like Fig.18 As shown, a sacrificial oxide layer SO is deposited on the lower metal layer C1. The sacrificial oxide layer SO has a T-shape to fill the trench TR and cover the lower metal layer C1 on the third dielectric structure 180c.

[0185] like Fig.19 As shown, the sacrificial oxide layer SO is etched to form a recess. More specifically, the sacrificial oxide layer SO is etched to a plane corresponding to a boundary between the first portion SW61 of the side wall and the second portion SW62 of the side wall. As a result, a portion of the sacrificial oxide layer SO above the first portion SW61 of the side wall is etched.

[0186] like Fig. 20 As shown, the lower metal layer C1 is etched to expose the upper surface TSC1 of the vertical portion C1V of the lower metal layer C1 and the second portion SW62 of the sidewall of the third dielectric structure 180c. The lower metal layer C1 is etched so that the upper surface TSC1 is coplanar with an upper surface of the sacrificial oxide layer SO. In some embodiments, hydrogen fluoride (HF), nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), or a combination thereof is used as an etchant to etch the lower metal layer C1. In some embodiments, the etching is performed at atmospheric pressure and a temperature of about 285° C. to 300° C.

[0187] like Fig.21 As shown, a residue of the sacrificial oxide layer SO is removed to expose a remaining portion of the lower metal layer C1. In some embodiments, the residue of the sacrificial oxide layer SO is removed by performing a wet etch.

[0188] like Fig. 22 As shown, an intermediate insulating layer C2 is deposited on the lower metal layer C1. More specifically, the intermediate insulating layer C2 is deposited to cover the lower metal layer C1, the second portion SW62 of the sidewall, and the upper surface 181c-s1 of the third dielectric structure 180c. Fig. 22 As shown, the intermediate insulating layer C2 includes a first stepped portion SP1 and a second stepped portion SP2. The first stepped portion SP1 contacts the vertical portion C1V and the upper surface TSC1 of the lower metal layer C1, and the second stepped portion SP2 contacts the second portion SW62 of the sidewall of the third dielectric structure 180c and the upper surface 181c-s1. As a result, the second stepped portion SP2 covers the corner 180c-C of the third dielectric structure 180c, wherein the corner 180c-C is defined by the second portion SW62 of the sidewall of the third dielectric structure 180c and the upper surface 180c-s1.

[0189] After the intermediate insulating layer C2 is deposited, an upper metal layer C3 is deposited on the intermediate insulating layer C2 to form a Figure 2 A semiconductor device 200 is shown.

[0190] An embodiment of the present disclosure provides a semiconductor element. The semiconductor element includes a substrate; a gate electrode disposed on the substrate; a first metal contact disposed in the gate electrode; a first spacer disposed on a side wall of the gate electrode; and a second spacer covering the first spacer; wherein the first spacer includes a plurality of dopants.

[0191] Another embodiment of the present disclosure provides a semiconductor element, which includes a substrate, a gate electrode disposed on the substrate, a first metal contact disposed in the gate electrode, a first spacer disposed on a side wall of the gate electrode, and a trench capacitor disposed above and in contact with the first metal contact.

[0192] Another embodiment of the present disclosure provides a method for preparing a semiconductor element. The preparation method includes providing a substrate and forming a first gate electrode and a second gate electrode above the substrate; forming a first lightly doped region in the substrate and between the first gate electrode and the second gate electrode; forming a first dielectric layer to cover the first gate electrode, the second gate electrode and the substrate; performing an etching technique to pattern the first dielectric layer; forming a first spacer on a side wall of the first gate electrode; forming a second spacer on a side wall of the second gate electrode, wherein the substrate is exposed through the first spacer and the second spacer; forming a second lightly doped region in the substrate and between the first spacer and the second spacer; forming a second dielectric layer to cover the first spacer, the second spacer, the first gate electrode, the second gate electrode and the substrate; performing an etching technique to pattern the second dielectric layer; A third spacer is formed to cover the first spacer; a fourth spacer is formed to cover the second spacer, wherein the substrate is exposed through the spacers; a heavily doped region is formed in the substrate and between the third spacer and the fourth spacer; a plurality of first metal contacts are formed in the first gate electrode and the second gate electrode; a second metal contact is formed in the heavily doped region between the first gate electrode and the second gate electrode; a first dielectric structure is formed above the substrate and between the first gate electrode and the second gate electrode; a second dielectric structure is formed above the first dielectric structure; a third dielectric structure is formed above the second dielectric structure; and a trench capacitor is formed to penetrate the third dielectric structure and the second dielectric structure to reach and contact the first metal contacts formed in the first gate electrode and the second gate electrode.

[0193] Embodiments of the present disclosure provide a method for preparing a semiconductor device. The method includes at least two cycles of depositing a dielectric layer and patterning the dielectric layer to define a plurality of spacers. The spacers defined by the first cycle can be used to define lightly doped regions of different profiles. In addition, by performing multiple cycles of forming spacers, the size of the entire spacer can be reduced.

[0194] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes may be implemented in different ways, and other processes or combinations thereof may be used to replace many of the above processes.

[0195] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor element, comprising: a base; a gate electrode disposed on the substrate; a first metal contact disposed in the gate electrode; A first spacer is disposed on a side wall of the gate electrode; as well as a second spacer covering the first spacer; The first spacer includes a plurality of dopants.

2. The semiconductor device according to claim 1, further comprising: a first lightly doped region disposed in the substrate and adjacent to the gate electrode; as well as A second lightly doped region is disposed in the substrate, wherein a size of the first lightly doped region is different from a size of the second lightly doped region. 3 . The semiconductor device as claimed in claim 2 , wherein the size of the second lightly doped region is determined by a thickness of the first spacer. 4 . The semiconductor device as claimed in claim 2 , wherein a portion of the first spacer does not vertically overlap with the second lightly doped region.

5. The semiconductor device according to claim 2, further comprising: A heavily doped region is disposed in the substrate and adjacent to the second spacer. 6 . The semiconductor device as claimed in claim 1 , wherein the plurality of dopants are located adjacent to an interface between the first spacer and the second spacer.

7. The semiconductor device as claimed in claim 6, wherein the second spacer has an outer surface facing away from the first spacer, and a surface roughness of the interface between the first spacer and the second spacer is greater than a surface roughness of the outer surface of the second spacer.

8. The semiconductor device according to claim 1, further comprising: A conductive through hole penetrates the second spacer.

9. The semiconductor device according to claim 5, further comprising: A second metal contact is disposed in the substrate and in the heavily doped region. 10 . The semiconductor device as claimed in claim 1 , wherein a material of the first spacer is the same as a material of the second spacer.

11. The semiconductor device according to claim 1, further comprising: A first dielectric structure is disposed above the substrate and above the second spacer, wherein the first metal contact is exposed by the first dielectric structure.

12. A semiconductor element, comprising: a base; a gate electrode disposed on the substrate; a first metal contact disposed in the gate electrode; A first spacer is disposed on a side wall of the gate electrode; as well as A trench capacitor is disposed above the first metal contact and contacts the first metal contact.

13. The semiconductor device according to claim 12, further comprising: A second spacer covers the first spacer, wherein the first spacer includes a plurality of dopants. 14 . The semiconductor device of claim 13 , wherein the plurality of dopants in the first spacer are the same as the plurality of dopants in the second lightly doped region. 15 . The semiconductor device as claimed in claim 13 , wherein a material of the second spacer is the same as a material of the first spacer.

16. The semiconductor device according to claim 14, further comprising: A heavily doped region is disposed in the substrate and overlaps the first lightly doped region and the second lightly doped region. 17 . The semiconductor device as claimed in claim 16 , wherein a third dimension of the heavily doped region is smaller than a second dimension of the second lightly doped region along a first direction.

18. The semiconductor device according to claim 16, further comprising: A second metal contact is disposed in the substrate and in the heavily doped region.

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