Semiconductor device having main device region and current sensor region

Abstract

A semiconductor device having a main device region and a current sensor region is provided. The main device region includes a plurality of main device cell regions confined by gate trenches disposed on a first main surface of the semiconductor substrate. The semiconductor device further includes a current sensor region including a plurality of current sensor cell regions confined by gate trenches arranged in the first major surface of the semiconductor substrate. The semiconductor device also includes an interface region disposed between the main device region and the current sensor region. The interface region includes: a shielding region of a second conductivity type disposed on the first main surface of the semiconductor substrate and at least partially covering a bottom of one of the gate trenches defining one of the plurality of main device cell regions or one of the plurality of current sensor cell regions; another region of the second conductivity type disposed on the first main surface of the semiconductor substrate; and a void region of the first conductivity type disposed on the first main surface of the semiconductor substrate and separating the shielding region from the other region.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device having a main device region and a current sensor region. Background Art

[0002] Some power devices include current and temperature sensing mechanisms to monitor overcurrent or overtemperature operating conditions. The output of such sensing mechanisms can be delivered to other control and protection circuits for controlling the operation of one or more power devices. When overcurrent or overtemperature operating conditions are detected, such control and protection circuits operate to disable the power device. The power device should be shut down as early as possible in an appropriate manner to avoid short circuit or overcurrent scenarios. Therefore, a reliable current and temperature sensing scheme for power devices (such as, for example, power semiconductor devices) is needed. Summary of the invention

[0003] According to an example of a semiconductor device, the semiconductor device includes a semiconductor substrate and a main device area. The main device area includes a plurality of main device primitive areas confined by a gate trench arranged on a first main surface of the semiconductor substrate, wherein a gate electrode is arranged in the gate trench. The semiconductor device also includes a current sensor area. The current sensor area includes a plurality of current sensor primitive areas confined by a gate trench arranged on the first main surface of the semiconductor substrate, wherein the gate electrode is arranged in the gate trench. The semiconductor device also includes an interface area arranged between the main device area and the current sensor area. The interface area includes: a shielding area of ​​a second conductivity type, arranged on the first main surface of the semiconductor substrate, and at least partially covering the bottom of one of the gate trenches confining one of the plurality of main device primitive areas or one of the plurality of current sensor primitive areas. The interface area also includes: another area of ​​the second conductivity type, arranged on the first main surface of the semiconductor substrate; and a void area of ​​the first conductivity type, arranged on the first main surface of the semiconductor substrate. The void area separates the shielding area from the another area.

[0004] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, wherein like reference numerals refer to similar or identical elements unless otherwise indicated. The elements of the drawings are not necessarily drawn to scale relative to each other. The features of the various illustrated examples can be combined unless they exclude each other.

[0006] Figure 1 illustrates a partial top view of an exemplary semiconductor device;

[0007] Figure 2A +2B illustrates a cross-sectional view of a semiconductor device;

[0008] Figure 3A +3B illustrates a cross-sectional view of a semiconductor device;

[0009] Figure 4 illustrates a partial top view of an exemplary semiconductor device;

[0010] Figure 5 A circuit schematic diagram illustrating an exemplary electronic system; and

[0011] Figure 6 A top view of a layout of an exemplary semiconductor device is illustrated. DETAILED DESCRIPTION

[0012] The implementation and use of several examples are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a variety of specific situations. The specific examples discussed only illustrate specific ways to implement and use the present invention and do not limit the scope of the present invention.

[0013] The terms "having", "containing", "including", "comprising" and the like are open ended and indicate the presence of stated structures, elements or features but do not exclude the presence of additional elements or features. The articles "a", "an" and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0014] The terms "engaged", "attached", "connected" and / or "coupled" are not intended to mean that the elements or layers must be directly in contact together; intervening elements or layers may be provided between the elements being "engaged", "attached", "connected" and / or "coupled", respectively. However, according to the present disclosure, the above terms may optionally also have the following specific meanings: the elements or layers are directly in contact together, that is, no intervening elements or layers are provided between the elements being "engaged", "attached", "connected" and / or "coupled", respectively.

[0015] The term "electrically connected" describes a permanent low-resistance connection between electrically connected elements, such as a direct contact between the elements involved or a low-resistance connection via metal and / or heavily doped semiconductor material.

[0016] The terms “on” and “over” should not be interpreted as meaning only “directly on” and “directly over.” Conversely, if an element is positioned “on” or “over another element” (for example, a layer is “on” or “over another layer” or “on” or “over a substrate”), another component (for example, another layer) may be positioned between the two elements (for example, if a layer is “on” or “over a substrate,” the other layer may be positioned between the layer and the substrate).

[0017] As shown in the drawings, spatially relative terms (such as, "below," "beneath," "down," "above," "up," "under," etc.) are used herein for convenience of description to describe the relationship of one element or feature to another element(s) or feature(s). The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0018] Next, an exemplary implementation of a semiconductor device having a main device region and a current sensor region is described with reference to the accompanying drawings. Although the exemplary implementation is described in the context of an IGBT (insulated gate bipolar transistor) device, the exemplary implementation can be implemented using other types of transistors, such as MOSFET (metal oxide semiconductor field effect transistor) devices, BJT (bipolar junction transistor) devices, JFET (junction field effect transistor) devices, etc. That means that references to emitters and collectors can be equally applicable to the source and drain of a MOSFET or similar terminals of other types of transistors. In the following implementation, for an n-channel device, the first conductivity type is n-type and the second conductivity type is p-type, while for a p-channel device, the first conductivity type is p-type and the second conductivity type is n-type.

[0019] Figure 1 A partial top view of an exemplary semiconductor device 100 is illustrated. Figure 2A +2B and 3A+3B are shown along Figure 1 1 is a cross-sectional view of the semiconductor device 100 along the line marked AA' in FIG. Figure 2A Compared with +2B and 3A+3B, Figure 1 Contains fewer details.

[0020] The semiconductor device 100 includes a semiconductor substrate 102. The semiconductor substrate 102 may include one or more semiconductor materials of various semiconductor materials used to form semiconductor devices. For example, the semiconductor substrate 102 may include a single element semiconductor (e.g., Si, Ge, etc.), a silicon-on-insulator semiconductor, a binary semiconductor (e.g., SiC, GaN, GaAs, SiGe, etc.), a ternary semiconductor (e.g., AlGaN, InGaAs, InAlAs, etc.). The semiconductor substrate 102 may be a bulk semiconductor material, or may include one or more additional elements, such as, for example, an epitaxial layer grown on the bulk semiconductor material, a field stop region, a buffer layer, a well region, a highly doped region / lowly doped region, etc. The bulk semiconductor material may be referred to as a base semiconductor. The semiconductor substrate 102 has a first major surface 104 and a second major surface 106 opposite to the first major surface 104. The first major surface 104 may be referred to as a front surface, and the second major surface 106 may be referred to as a back surface.

[0021] The semiconductor device 100 further includes a main device region 108 and a current sensor region 110. The main device region 108 includes a plurality of main device primitive regions 114, 114_1, 114_2. Each of the plurality of main device primitive regions 114, 114_1, 114_2 is spatially bounded by gate trenches 116, 116_1-116_4, which are arranged at the first main surface 104 of the semiconductor substrate 102 and extend into the semiconductor substrate 102. Similarly, the current sensor region 110 includes a plurality of current sensor primitive regions 118, 118_1, 118_2. Each of the plurality of current sensor cell regions 118, 118_1, 118_2 is spatially confined by a gate trench 120, 120_1-120_4, which is arranged at the first main surface 104 of the semiconductor substrate 102 and extends into the semiconductor substrate 102. The semiconductor device 100 may be referred to as a trench semiconductor device. The main device region 108 includes power transistor cells, which are coupled in parallel to form a power transistor of the semiconductor device 100. The current sensor region 110 includes current sensor transistor cells, which are coupled in parallel to form a current sensor transistor of the semiconductor device 100. The power transistor may be referred to as a main transistor. The current sensor cells mirror the current flowing in the main device region 108, and the current flowing through the current sensor cells can be used to sense the current flowing through the main transistor, as will be described below in conjunction with Figure 5More details. That means that the current measured in the current sensor cell represents the current flowing through the main device area 108. The power transistor cells and the current sensor transistor cells may have the same configuration, spacing, etc., but there are fewer current sensor transistor cells than power transistor cells, for example, 1 / 10, 1 / 100, 1 / 1000, 1 / 10000 or even fewer cells than power transistor cells. The number of transistor cells coupled in parallel defines the ability to conduct current.

[0022] like Figure 2A +2B and Figure 3A As shown in the cross-sectional view of FIG. 3B, each of the plurality of main device primitive regions 114_1, 114_2 includes a source region 130 of a first conductivity type, the source region 130 being arranged at the first main surface 104 of the semiconductor substrate 102. Each of the plurality of main device primitive regions 114_1, 114_2 also includes a body region 132 of a second conductivity type, the body region 132 separating the source region 130 from a drift region 134 of the first conductivity type, the drift region 134 being arranged in the semiconductor substrate 102. The source region 130 has a higher doping level than the drift region 134. The gate electrode 136 is arranged in the gate trenches 116_1-116_4, which confine the plurality of main device primitive regions 114_1, 114_2. The gate electrode 136 is separated from the semiconductor substrate 102 by a gate dielectric disposed on the sidewalls and bottom of the gate trenches 116_1-116_4. The gate electrode 136 may include metal (eg, Al, Cu, Ni, Pd, etc.), highly doped polysilicon, etc.

[0023] Two adjacent main device primitive regions 114_1, 114_2 are separated by an inter-primitive region. The inter-primitive region may be referred to as a separator region and has a first width w1 measured along a horizontal direction x parallel to the first main surface 104 of the semiconductor substrate 102. The horizontal direction x may be referred to as a lateral direction. Each inter-primitive region includes a shielding region 124_2, 124_3 of a second conductivity type, which is arranged on the first main surface 104 of the semiconductor substrate 102. The shielding regions 124_2, 124_3 may have the same or different doping levels as the main region 132. In one example, the shielding regions 124_2, 124_3 have a lower doping level than the main region 132. Compared with the main region 132, the shielding regions 124_2, 124_3 extend deeper in the semiconductor substrate 102. The shielding regions 124_2, 124_3 at least partially cover the bottom of the gate trenches 116_2-116_4 adjacent to the main device primitive regions 114_1, 114_2. That means that the shielding regions 124_2, 124_3 extend deeper in the semiconductor substrate 102 than the gate trenches 116_2-116_4, and the gate trenches 116_2-116_4 extend at least partially into the shielding regions 124_2, 124_3. The shielding regions 124_2, 124_3 may be floating regions, i.e., regions with which there is no electrical contact. The shielding regions 124_2, 124_3 may protect the bottom of the gate trenches 116_2-116_4 from excessive electric fields. Without the shielding regions 124_2 , 124_3 , the bottom of the gate trenches 116_2 - 116_4 may be subject to high electric fields during switching operations (eg, during turn-off), which can jeopardize the proper functioning of the semiconductor device 100 .

[0024] The gate electrodes 136 adjacent to the main device primitive regions 114_1, 114_2 are electrically connected to each other via a first conductive layer 138, which is formed on the first main surface 104 of the semiconductor substrate 102. The first conductive layer 138 may include a metal (e.g., Al, Cu, Ni, Pd, etc.), highly doped polysilicon, etc. The first conductive layer 138 may include a single layer or a stack of layers including different materials. The first conductive layer 138 may include the same material as the gate electrode 136 and may be manufactured in the same manufacturing step as the gate electrode 136. The first conductive layer 138 is segmented, and the segments of the first conductive layer 138 contact the gate electrode 136 to provide a gate terminal. The first conductive layer 138 is electrically isolated from the shielding regions 124_2, 124_3 and the semiconductor substrate 102 by a first isolation structure 140 or a first isolation layer 140. The first isolation structure 140 / first isolation layer 140 may include a dielectric material. In one example, the first isolation structure 140 / first isolation layer 140 may be a LOCOS (Local Oxidation of Silicon) region. In another example, the first isolation structure 140 / first isolation layer 140 may be an STI (Shallow Trench Isolation) region or any other type of isolation region including at least one of grown and / or deposited oxides or nitrides.

[0025] The first conductive layer 138 is arranged between the first major surface 104 of the semiconductor substrate 102 and the second conductive layer 142. The first conductive layer 138 and the second conductive layer 142 may be referred to as wiring layers. The second conductive layer 142 may include a metal (e.g., Al, Cu, Ni, Pd, etc.), highly doped polysilicon, etc. The second conductive layer 142 may include a single layer or a stack of layers including different materials. The second conductive layer 142 is electrically isolated from the first conductive layer 138 by the second isolation layer 144. The second isolation layer 144 may include a dielectric material, and in one example, it includes at least one of an oxide and a nitride. The second conductive layer 142 is segmented, and the segments of the second conductive layer 142 contact the source region 130 and the body region 132 through the contact opening to provide an emitter terminal of the main device region 108. The emitter terminal of the main device region 108 may be referred to as a first load terminal. In one example (not shown), only the source region 130, but not the body region 132, is contacted by the segments of the second conductive layer 142 through the contact opening.

[0026] The plurality of current sensor primitive regions 118_1, 118_2 may have a structure similar to or identical to the plurality of main device primitive regions 114_1, 114_2. The plurality of current sensor primitive regions 118_1, 118_2 include a source region 146 of a first conductivity type, a body region 148 of a second conductivity type, and a drift region 134 of a first conductivity type, which is common to the drift region 134 of the plurality of main device primitive regions 114_1, 114_2. The current sensor primitive regions 118_1, 118_2 also include a gate electrode 150, which is connected to each other via a first conductive layer 138 to provide a gate terminal. The gate electrode 150 is separated from the semiconductor substrate 102 by a gate dielectric. Sections of the second conductive layer 142 contact source regions 146 and body regions 148 of the current sensor cell regions 118_1, 118_2 via contact openings to provide emitter terminals of the current sensor region 110. Two adjacent current sensor cell regions 118_1, 118_2 are separated by an inter-cell region including shielding regions 122_2, 122_3.

[0027] A collector region 152 of the second conductivity type is formed at the second major surface 106 of the semiconductor substrate 102. The collector region 152 is common to the main device primitive regions 114_1, 114_2 and the current sensor primitive regions 118_1, 118_2. Note that for devices other than IGBTs, such as MOSFETs, the collector region 152 of the second conductivity type is replaced by a drain region of the first conductivity type. A third conductive layer 154 is formed over the second major surface 106 of the semiconductor substrate 102. The third conductive layer 154 may include a metal (e.g., Al, Cu, Ni, Pd, etc.), highly doped polysilicon, etc. The third conductive layer 154 may include a single layer or a stack of layers including different materials. The third conductive layer 154 contacts the collector region 152 to provide a common collector terminal for the main device region 108 and the current sensor region 110. The collector terminal may be referred to as a second load terminal.

[0028] In the main device area 108, the gate electrodes 136 are electrically connected together, the source regions 130 are electrically connected together, and there is a common collector region to form the plurality of power transistor primitives coupled in parallel. The power transistor primitives connected in parallel form a power transistor of the semiconductor device 100. In the current sensor area 110, the gate electrodes 150 are electrically connected together, the source regions 146 are electrically connected together, and there is a common collector region to form the plurality of current sensor primitives coupled in parallel. The current sensor primitives connected in parallel form a current sensor transistor of the semiconductor device 100.

[0029] Within the plurality of main device cell regions 114_1, 114_2 and the plurality of current sensor cell regions 118_1, 118_2, channels are formed in the body regions 132, 148 along the gate trenches 116_1-116_4, 120_1-120_4 to provide a conductive connection between the source regions 130, 146 and the drift region 134. The channels are controlled by a voltage applied to the gate electrodes 136, 150. Within the main device region 108 of the semiconductor device 100, a load current flows in a vertical direction y between a first load terminal located at the first main surface 104 of the semiconductor substrate 102 and a second load terminal located at the second main surface 106 of the semiconductor substrate 102. The vertical direction y is perpendicular to the horizontal direction x. As explained above, the current sensor cells located in the current sensor region 110 mirror the current flowing in the power transistor cells in the main device region 108. Semiconductor device 100 may be referred to as a vertical power semiconductor device, and may be configured to conduct a load current exceeding 1 A, or exceeding 10 A, or exceeding 30 A, or several hundred A, and may also be configured to block a voltage between load terminals in the range of tens to several thousand volts, for example 10 V, 400 V, 650 V, 1.2 kV, 1.7 kV, 3.3 kV, 4.5 kV, 5.5 kV, 6 kV, 6.5 kV.

[0030] like Figure 1 As shown in the partial top view of Figure 2A +2B and Figure 3A As shown in the cross-sectional view of FIG. 3B, the semiconductor device 100 further includes an interface region 112 that separates the main device region 108 from the current sensor region 110. Along the horizontal direction x, the interface region 112 is arranged between the main device region 108 and the current sensor region 110. The interface region 112 may be referred to as a transition region and has a second width w2 measured along the horizontal direction x. The width w2 of the interface region 112 may be greater than the width w1 of at least one of the inter-cell regions of the main device cell regions 114_1, 114_2 and the inter-cell regions of the current sensor cell regions 118_1, 118_2. In one example (not shown), the outermost cells of the main device region 108 and / or the current sensor region 110 (i.e., the cells close to the interface region 112) may be hole collector cells that do not include a source region. In certain operating modes, such as when a power transistor cell is turned off, the hole collector cell may allow charge carriers (eg, holes) to be quickly removed from the drift region 134 .

[0031] The interface region 112 includes a shielding region 122_1 of the second conductivity type, and the shielding region 122_1 is arranged at the first main surface 104 of the semiconductor substrate 102. Figure 2A +2B and Figure 3AAs shown in the cross-sectional view of FIG. 3B, the shielding region 122_1 at least partially covers the bottom of the gate trench 120_1 of the current sensor region 110. The shielding region 122_1 shields the high electric field from the bottom of the gate trench 120_1, which is located at the edge of the current sensor region 110 toward the main device region 108. That means, the shielding region 122_1 is located at the edge or periphery of the current sensor region 110. The shielding region 122_1 may have the same or similar size and doping level as the shielding regions 122_2, 122_3 of the current sensor region 110, and may be manufactured in the same manufacturing steps as the shielding regions 122_2, 122_3 of the current sensor region 110.

[0032] In other examples (not shown), the shielding region 122_1 of the second conductivity type is arranged at the edge or periphery of the main device region 108 and shields the bottom of the gate trench 116_1, which is located at the edge of the main device region 108 facing the current sensor region 110. The shielding region 122_1 may have the same or similar size and doping level as the shielding regions 124_2, 124_3 of the main device region 108, and may be manufactured in the same manufacturing steps as the shielding regions 124_2, 124_3 of the main device region 108. Typically, the shielding region 122_1 of the second conductivity type at least partially covers the bottom of one of the gate trenches confined to one of the plurality of main device primitive regions 114_1, 114_2 or one of the plurality of current sensor primitive regions 118_1, 118_2.

[0033] The interface region 112 also includes another region 124_1, 126 of the second conductivity type. Figure 2AAs shown in the cross-sectional view of FIG. 1A , the further region 124_1 is a further shielding region 124_1 of the second conductivity type, which is arranged at the first major surface 104 of the semiconductor substrate 102. The further shielding region 124_1 partially covers the bottom of the gate trench 116_1 of the main device region 108. The further shielding region 124_1 shields the high electric field from the bottom of the gate trench 116_1, which is located at the edge of the main device region 108 towards the current sensor region 110. That means, the further shielding region 124_1 is located at the edge or periphery of the main device region 108. The further shielding region 124_1 may have the same or similar size and doping level as the shielding regions 124_2, 124_3 of the main device region 108, and may be manufactured in the same manufacturing steps as the shielding regions 124_2, 124_3 of the main device region 108. In other examples (not shown), the further shielding region 124_1 may at least partially cover the bottom of one of the gate trenches 122, 122_1-122_4 of the current sensor region 110. Typically, the shielding region 122_1 of the second conductivity type of the interface region 112 is arranged at an edge of one of the main device region 108 or the current sensor region 110, and the further shielding region 124_1 of the second conductivity type of the interface region 112 is arranged at an edge of the other of the main device region 108 or the current sensor region 110.

[0034] In another example, if Figure 2B As shown in the cross-sectional view of FIG. 3B, the further region 126 of the second conductivity type is a region 126 of the second conductivity type, which is arranged at the first main surface 104 of the semiconductor substrate 102 and is located between the shielding region 122_1 of the interface region 112 and the shielding regions 122_1, 124_1, which are located at the edge of one of the main device region 108 or the current sensor region 110. In an example, the further region 126 may have the same or similar doping level as the shielding regions 124_2, 124_3, 122_2, 122_3 of the main device region 108 or the current sensor region 110. In an example, the further region 126 may extend from the first main surface 104 of the semiconductor substrate 102 to the same depth d1 as the shielding regions 124_2, 124_3, 122_2, 122_3 of the main device region 108 or the current sensor region 110. In one example, the further region 126 may be manufactured in the same manufacturing step as the shielding regions 124_2 , 124_3 , 122_2 , 122_3 of the main device region 108 or the current sensor region 110 .

[0035] In such Figure 2BIn the example shown in the cross-sectional view of FIG. 3B, the further region 126 of the second conductivity type is electrically connected to the source region 130 of the main device region 108 via the contact opening. The further region 126 may include a contact region 156 of the second conductivity type, which improves the electrical contact between the source region 130 of the main device region 108 and the further region 126. The contact region 156 may have a higher doping level than the further region 126 and have the same or similar doping level as the body regions 132, 148 of the main device region 108 and the current sensor region 110. The contact region 156 may be manufactured in the same manufacturing step as the body regions 132, 148 of the main device region 108 and the current sensor region 110. In certain operating modes, such as when the power transistor cell is turned off, the further region 126 may allow charge carriers (e.g., holes) to be quickly removed from the drift region 134. In other examples (not shown), the further region 126 of the second conductivity type is electrically connected to the source region 146 of the current sensor region 110 , or the further region 126 is floating.

[0036] The interface region 112 further comprises a void region 128, 128_1 of the first conductivity type, which is arranged at the first main surface 104 of the semiconductor substrate 102. The void region 128, 128_1 separates the shielding region 122_1 of the second conductivity type from the other region 124_1, 126 of the second conductivity type. There is no physical connection between the shielding region 122_1 of the second conductivity type and the other region 124_1, 126 of the second conductivity type, and the shielding region 122_1 and the other region 124_1, 126 are separated from each other in space. Because of the physical separation of the shielding region 122_1 from the other region 124_1, 126, the shielding region 122_1 is electrically isolated from the other region 124_1, 126 by the void region 128, 128_1. Along the horizontal direction x, the void region 128, 128_1 is arranged between the shield region 122_1 of the second conductivity type and the further region 124_1, 126 of the second conductivity type. In one example, the void region 128, 128_1 has the same doping level as the drift region 134, and the void region 128, 128_1 and the drift region 134 are continuous regions. In another example, the void region 128, 128_1 has a higher doping level than the drift region 134. Figure 2BAs shown in the cross-sectional view of FIG. 3B, in one example, there is another void region 128_2 of the first conductivity type, which is arranged at the first main surface 104 of the semiconductor substrate 102. Along the horizontal direction x, the another void region 128_2 is arranged between the another region 124_1, 126 of the second conductivity type and the shielding regions 122_1, 124_1, which are located at the edge of one of the main device region 108 or the current sensor region 110.

[0037] As described above, the gate electrodes 136 of the main device region 108 are connected to each other via the first conductive layer 138, and the gate electrodes 150 of the current sensor region 110 are connected to each other via the first conductive layer 138. Figure 2A As shown in the cross-sectional view of FIG. 2B, the gate electrode 136 of the main device region 108 is electrically connected to the gate electrode 150 of the current sensor region 110 via the first conductive layer 138. Figure 2B In the example of FIG. 1 , a portion of the electrical connection within the first conductive layer 138 is located at Figure 2B Invisible planes (such as Figure 2B 108 and the current sensor transistor of the current sensor area 110 are turned on / off at the same time. That means, the power transistor of the main device area 108 and the current sensor transistor of the current sensor area 110 are turned on / off at the same time. In one example, by applying a positive voltage to the gate electrode 136 and the gate electrode 150, the power transistor and the current sensor transistor can be turned on or switched on. In addition, by applying a zero voltage or a negative voltage to the gate electrode 136 and the gate electrode 150, the power transistor and the current sensor transistor can be turned off or switched off.

[0038] like Figure 3A As shown in the cross-sectional view of FIG. 1 , in one example, the gate electrode 136 of the main device area 108 is electrically connected to the gate electrode 150 of the current sensor area 110 via the second conductive layer 142. In another example, as shown in FIG. Figure 3B As shown in the cross-sectional view of FIG. 1 , the gate electrode 136 of the main device area 108 is electrically connected to the gate electrode 150 of the current sensor area 110 via the first conductive layer 138 and via the second conductive layer 142. A portion of the electrical connection within the first conductive layer 138 is located at Figure 3B Invisible planes (such as Figure 3BTypically, the gate electrode 136 of the main device area 108 is electrically connected to the gate electrode 150 of the current sensor area 110 via at least the first conductive layer 138. The electrical connection of the gate electrode 136 of the main device area 108 and the gate electrode 150 of the current sensor area 110 is at least partially arranged above the void area 128, 128_1.

[0039] The implementation of the void regions 128, 128_1 allows for reducing or suppressing leakage current flowing from the main device region 108 to the current sensor region 110, and vice versa. In the absence of the void regions 128, 128_1, when the power transistor and the current sensor transistor are turned off, parasitic leakage current may flow from the main device region 108 to the current sensor region 110, and vice versa. Leakage paths involving the body regions 132, 148 of the main device region 108 and the current sensor region 110 may occur, and a channel connecting the body regions 132, 148 may be formed. For example, when the semiconductor device 100 operates at a high temperature, parasitic leakage current may occur. In a state where both the power transistor and the current sensor transistor are turned off, the parasitic leakage current may adversely affect the operation of the semiconductor device 100. For example, when the power transistor and the current sensor transistor are turned off, a measurement of the temperature of the semiconductor device 100 may be performed. In the absence of the void regions 128, 128_1, such temperature measurement may be distorted.

[0040] like Figure 3A As shown in the cross-sectional view of FIG. 3B, the semiconductor device 100 may further include a shielding structure 158, which is arranged in the first conductive layer 138. The shielding structure 158 is at least partially arranged above the void region 128, 128_1. In one example, the shielding structure 158 is arranged above the center of the void region 128, 128_1. In addition, the shielding structure 158 is at least partially arranged under a section of the second conductive layer 142 that electrically connects the gate electrode 136 of the main device region 108 with the gate electrode 150 of the current sensor region 110. The shielding structure 158 shields or mitigates the effect of the gate signal applied to the section of the second conductive layer 142 that electrically connects the gate electrode 136 of the main device region 108 with the gate electrode 150 of the current sensor region 110 on the semiconductor substrate 102. The implementation of the shielding structure 158 allows the formation of a conductive path for charge carriers between the main device region 108 and the current sensor region 110 to be further reduced or suppressed. In one example, the shield structure 158 is electrically biased and electrically connected to the source region 146 of the current sensor region 110. In other examples, the shield structure 158 is electrically connected to the source region 130 of the main device region 108, or the shield structure 158 is floating.

[0041] like Figure 3A As shown in the cross-sectional view of FIG. 3B, the semiconductor device 100 may further include at least one isolation trench 160, which is arranged at the first main surface 104 of the semiconductor substrate 102 and extends into the void region 128, 128_1. An electrode 162 is arranged in the isolation trench 160. The electrode 162 is separated from the semiconductor substrate 102 by a dielectric arranged at the sidewall and bottom of the isolation trench 160. Figure 3A As shown in FIG. 3B , the isolation trench 160 divides the void region 128, 128_1 into two parts. In one example, the electrode 162 is electrically biased and electrically connected to the source region 146 of the current sensor region 110. In other examples, the electrode 162 is electrically connected to the source region 130 of the main device region 108, or the electrode 162 is floating. By implementing the at least one isolation trench 160 and the electrode 162 filled with dielectric, the parasitic current flow from the main device region 108 to the current sensor region 110 is further reduced, and vice versa.

[0042] exist Figure 3A In the example of +3B, one isolation trench 160 is arranged on the first main surface 104 of the semiconductor substrate 102 and extends into the void region 128, 128_1. In other examples (not shown), two or more isolation trenches are arranged on the first main surface 104 of the semiconductor substrate 102 and extend into the void region 128, 128_1. The two or more isolation trenches may be arranged parallel to each other. In another example (not shown), one or more isolation trenches may be arranged in Figure 2B The at least one isolation trench 160 may have at least one of the same width and the same depth as the gate trenches 116, 116_1-116_4, 120, 120_1-120_4 of the current sensor region 110 and the main device region 108. Such a regular structure allows easy manufacturing of the semiconductor device 100, and the manufacturing cost is reduced. The at least one isolation trench 160 may have any type of shape, for example, an open shape (such as a straight stripe) or a closed shape (such as a ring).

[0043] like Figure 3AAs shown in the example of FIG. 3B, the electrode 162 disposed in the at least one isolation trench 160 is electrically connected to the shield structure 158, and there is a physical connection between those two elements. In another example (not shown), only one of the at least one isolation trench 160 and the shield structure 158 is implemented in the semiconductor device 100. In another example (not shown), the electrode 162 disposed in the at least one isolation trench 160 and the shield structure 158 are spatially separated from each other and / or electrically isolated from each other.

[0044] Figure 4 Another partial top view of an exemplary semiconductor device 400 is shown. Figure 1 , 2A +2B, 3A+3B semiconductor device 100, semiconductor device 400 includes a main device region 408, a current sensor region 410 and an interface region 412. In semiconductor device 400, current sensor region 410 is embedded in main device region 408. Figure 4 In the example of , the interface region 412 completely surrounds the current sensor region 410 in the lateral direction. In addition, the void region (not shown) included in the interface region 412 completely surrounds the current sensor region 410 to reduce or suppress leakage current flowing from the main device region 408 to the current sensor region 410, and vice versa, as explained above. In other examples (not shown), the void region may not completely surround the current sensor region 410. Alternatively, the void region may at least partially surround the current sensor region 410 to suppress leakage current flowing from the main device region 408 to the current sensor region 410, and vice versa, as explained above.

[0045] Combination Figure 1 , 2A The semiconductor devices 100 and 400 illustrated and described in FIG. 2B, FIG. 3A, FIG. 3B, and FIG. 4 are provided as examples. Other examples may differ from those described with respect to FIG. Figure 1 , 2A In one example, there may be additional layers disposed on the first major surface 104 of the semiconductor substrate 102 and on the second major surface 106 of the semiconductor substrate 102. Those additional layers may be isolation layers and / or conductive layers. In one example, the shapes and positions of the gate trenches, source regions, body regions, and the one or more isolation trenches may be different from those of the combination. Figure 1 , 2A +2B, 3A+3B, 4 illustrate and describe the content.

[0046] In one example, the gate trenches 116, 116_1-116_4, 120, 120_1-120_4 may be arranged in an array configuration, a grid configuration, or a matrix configuration, similar to the combination of Figure 1 , 2A +2B, 3A+3B, 4 illustrate and describe examples. For example, the power transistor primitive and the current sensor transistor primitive may have a square, hexagonal, or polygonal shape. In another example, the gate trenches 116, 116_1-116_4, 120, 120_1-120_4 may have a strip configuration, wherein the gate trenches may be arranged as stripes extending parallel to each other, and the semiconductor mesas separate those stripe-shaped gate trenches. In another example, the gate trenches may be arranged in a manner that is neither parallel to each other nor orthogonal to each other. In general, the gate trenches may have any type of shape, for example, an open shape (such as, a straight stripe) or, for example, a closed shape (such as, a grid shape).

[0047] Figure 5 A circuit schematic diagram of an exemplary electronic system 550 configured to sense current and temperature of semiconductor device 500 is shown. Electronic system 550 may be part of a power electronics system such as a DC / DC converter, AC / DC converter, DC / AC inverter, AC / AC converter, or the like.

[0048] The semiconductor device 500 is part of an electronic system 550 and includes a main transistor 552, a current sensor transistor 554, and a temperature sensor device 556. The main transistor 552, the current sensor transistor 554, and the temperature sensor device 556 form an integrated circuit that is monolithically integrated in the semiconductor device 500. The semiconductor device 500 may be referred to as a semiconductor die. The collector region of the main transistor 552 and the collector region of the current sensor transistor 554 are both electrically connected to a collector terminal 558 of the semiconductor device 500. The gate electrode of the main transistor 552 and the gate electrode of the current sensor transistor 554 are all electrically connected to a gate terminal 560 of the semiconductor device 500. The source region of the main transistor 552 is electrically connected to an emitter terminal 562 of the semiconductor device 500, and the source region of the current sensor transistor 554 is electrically connected to a sense terminal 564 of the semiconductor device 500. The temperature sensor device 556 is electrically connected between the sense terminal 564 and the emitter terminal 562. That means that a first terminal of the temperature sensor device 556 is electrically connected to the sense terminal 564 and a second terminal of the temperature sensor device 556 is electrically connected to the emitter terminal 562 .

[0049] The main transistor 552 may include a main device region similar to or the same as the main device region 108, 408 explained above. The current sensor transistor 554 may include a current sensor region similar to or the same as the current sensor region 110, 410 explained above. The current sensor transistor 554 mirrors the current flowing in the main transistor 552, and the current flowing through the current sensor transistor 554 can be used to sense the current flowing through the main transistor 552, as will be described in more detail below. An interface region including a shielding region, another shielding region, and a gap region is arranged between the main device region and the current sensor region, as explained above. The interface region may be similar to or the same as the interface region 112, 412 explained above.

[0050] In one example, the temperature sensor device 556 includes at least one diode configured to sense the temperature of the semiconductor device 500, as will be described in more detail below. The anode terminal of the at least one diode is electrically connected to the sensing terminal 564, and the cathode terminal of the at least one diode is electrically connected to the emitter terminal 562. In one example, the temperature sensor device 556 includes a plurality of diodes coupled in series. The plurality of diodes coupled in series may be referred to as a diode stack. In one example, an anti-parallel diode may be coupled between the sensing terminal 564 and the emitter terminal 562 to protect the main transistor 552 and the semiconductor device 500 from damage in the event of ESD (electrostatic discharge). Implementing a diode to sense the temperature of the semiconductor device 500 is merely an example. In other examples, other or additional semiconductor devices (such as, for example, a resistor) may be implemented to sense the temperature of the semiconductor device 500.

[0051] In addition to the semiconductor device 500, the electronic system 550 also includes additional circuit elements configured to sense the current and temperature of the semiconductor device 500. The electronic system 550 includes a switching device 566 and a current sensing resistor 568 coupled in series between the sensing terminal 564 and the emitter terminal 562. In one example, the switching device 566 includes a transistor. In one example, the switching device 566 can be controlled by the same signal 572 as the gate terminal 560 of the semiconductor device 500. In addition, the electronic system 550 includes a current source 570 coupled between the sensing terminal 564 and the emitter terminal 562. The additional circuit elements configured to sense the current and temperature of the semiconductor device 500 are provided as examples. In other examples, different and / or additional circuit elements may be present.

[0052] In the first operating mode, the gate terminal 560 and the switching device 566 of the semiconductor device 500 are switched to a first state. In one example, the first state may be an on state, in which a high voltage or a positive voltage may be applied to the gate terminal 560, and in which the main transistor 552 and the current sensor transistor 554 are conductive. In addition, in the first state, the switching device 566 is conductive and couples the sensing terminal 564 of the semiconductor device 500 to the current sensing resistor 568. In the first operating mode, the current flowing through the current sensor transistor 554 is sensed by sensing the voltage drop across the current sensing resistor 568 as measured between the sensing terminal 564 and the emitter terminal 562. This voltage may be sensed when the main transistor 552 and the current sensor transistor 554 are in a safe on state. Based on the current flowing through the current sensor transistor 554 and the ratio of the size of the main transistor 552 to the size of the current sensor transistor 554, the current flowing through the main transistor 552 may be determined. In the first operating mode, the semiconductor device 500 is configured to allow measurement of the current in the current sensor transistor 554 , and the first operating mode may be referred to as a current sensing mode.

[0053] In the second operating mode, the gate terminal 560 and the switch device 566 of the semiconductor device 500 are switched to a second state. In one example, the second state may be a disconnected state, in which a low voltage, a zero voltage, or a negative voltage may be applied to the gate terminal 560, and in which the main transistor 552 and the current sensor transistor 554 are not conductive. In addition, in the second state, the switch device 566 is not conductive, and the sensing terminal 564 of the semiconductor device 500 is decoupled from the current sensing resistor 568. In the second operating mode, the current source 570 provides a constant current flowing through the temperature sensor device 556 of the semiconductor device 500. The second state configuration allows temperature sensing of the semiconductor device 500 by sensing the voltage drop across the temperature sensor device 556 as measured between the sensing terminal 564 and the emitter terminal 562. The voltage drop may be sensed when the main transistor 552 and the current sensor transistor 554 are in a safe disconnected state. In the second operating mode, the semiconductor device 500 is configured to allow the temperature of the semiconductor device 500 to be measured, and the second operating mode may be referred to as a temperature sensing mode.

[0054] In such Figure 5In the exemplary electronic system 550 shown in , a single terminal of the semiconductor device 500 (the terminal is the sensing terminal 564) is used for both current measurement and temperature measurement. Therefore, the sensing terminal 564 can be referred to as a dual-mode sensing terminal. Via signal 572, switching between current measurement and temperature measurement is performed. When the gate terminal 560 is switched to the first state, the sensing terminal 564 is used to measure the current, and when the gate terminal 560 is switched to the second state, the sensing terminal 564 is used to measure the temperature.

[0055] Figure 6 FIG. 6 is a top view of a layout of an exemplary semiconductor device 600. The semiconductor device 600 may be combined with Figure 5 The semiconductor device 500 shown and described is similar or identical. The gate terminal of the semiconductor device 600 is electrically connected to the gate pad G, the emitter terminal of the semiconductor device 600 is electrically connected to the emitter pad E, and the sense terminal of the semiconductor device 600 is electrically connected to the sense pad S. The semiconductor device 600 is a vertical device, and the gate pad G, the emitter pad E and the sense pad S are arranged on a first major surface of the substrate of the semiconductor device 600. The collector terminal is electrically connected to the collector pad, which is arranged on a second major surface of the substrate opposite to the first major surface. Therefore, the collector pad is Figure 6 Not visible in.

[0056] The semiconductor device 600 includes a temperature sensor region 674 including a device (e.g., semiconductor-based or metal thin film-based) forming a temperature sensor device of the semiconductor device 600. The semiconductor device 600 also includes a current sensor region 612 including a current sensor transistor primitive forming a current sensor transistor of the semiconductor device 600. The semiconductor device 600 also includes a main device region, which is at least partially arranged under the emitter pad E. The main device region includes a power transistor primitive forming a power transistor of the semiconductor device 600. An interface region including a shielding region, a further shielding region, and a void region is arranged between the main device region and the current sensor region 612, as explained above.

[0057] Figure 6 The layout shown in FIG. 6 is only an example. In other examples, the temperature sensor area 674 may be located in a Figure 6 For example, the temperature sensor region 674 may be placed at the center of the semiconductor device 600 or near the center of the semiconductor device 600, or the temperature sensor region 674 may be distributed over the semiconductor device 600. Similarly, the current sensor region 612, the gate pad G, the emitter pad E, and / or the sense pad S may be located at locations other than those shown in FIG. Figure 6 In one example, the emitter pad E may be divided into two or more emitter pads.

[0058] The sensing pad S is used for both current measurement and temperature measurement of the semiconductor device 600. Switching between current measurement and temperature measurement is performed via the gate pad G. Using the sensing pad S for both current measurement and temperature measurement results in minimal effort to access the pad, for example, during bonding, and further allows high active area utilization. In addition, an interface region including a shielding region, another shielding region, and a void region is arranged between the main device region and the current sensor region 612, and suppresses or reduces leakage current flowing from the main device region to the current sensor region 612, and vice versa, as explained above.

[0059] Examples of the invention are summarized here. Other examples can also be understood from the entire specification and claims submitted herein.

[0060] Example 1: A semiconductor device comprises: a semiconductor substrate; a main device area, comprising: a plurality of main device cell areas, confined by gate trenches arranged on a first main surface of the semiconductor substrate, wherein gate electrodes are arranged in the gate trenches; a current sensor area, comprising: a plurality of current sensor cell areas, confined by gate trenches arranged on the first main surface of the semiconductor substrate, wherein gate electrodes are arranged in the gate trenches; and an interface area, arranged between the main device area and the current sensor area, the interface area comprising: a shielding area of ​​a second conductivity type, arranged on the first main surface of the semiconductor substrate and at least partially covering the bottom of one of the gate trenches confining one of the plurality of main device cell areas or one of the plurality of current sensor cell areas, another area of ​​the second conductivity type, arranged on the first main surface of the semiconductor substrate, and a void area of ​​the first conductivity type, arranged on the first main surface of the semiconductor substrate, wherein the void area separates the shielding area from the another area.

[0061] Example 2: A semiconductor device as described in Example 1, wherein the plurality of main device primitive regions and the plurality of current sensor primitive regions include a source region of a first conductivity type, a body region of a second conductivity type, and a drift region of a first conductivity type, wherein the body region separates the drift region from the source region.

[0062] Example 3: The semiconductor device as described in the previous example, wherein the drift region and the void region are continuous regions.

[0063] Example 4: A semiconductor device as described in any of the previous examples, wherein the other region is: another shielding region of the second conductivity type, arranged on the first main surface of the semiconductor substrate and at least partially covering the bottom of one of the gate trenches confining one of the multiple main device primitive regions or one of the multiple current sensor primitive regions.

[0064] Example 5: The semiconductor device of any of Examples 2 or 3, wherein the another region is electrically connected to a source region of the main device cell region.

[0065] Example 6: The semiconductor device of any of the preceding examples, wherein the void region electrically isolates the shielding region from the another region.

[0066] Example 7: The semiconductor device of any of the preceding examples, wherein the interface region completely surrounds the current sensor region.

[0067] Example 8: The semiconductor device as described in any one of Examples 2 to 7 further includes: a shielding structure arranged in a first conductive layer, the first conductive layer is arranged above the first main surface of the semiconductor substrate, wherein the shielding structure is arranged above the gap area.

[0068] Example 9: The semiconductor device of any one of Examples 2 to 8 further includes: at least one isolation trench arranged at the first main surface of the semiconductor substrate and extending into the void region.

[0069] Example 10: The semiconductor device of Examples 8 and 9, wherein an electrode disposed in the at least one isolation trench is electrically connected to a shielding structure.

[0070] Example 11: The semiconductor device of Examples 8 and 9, wherein at least one of the shielding structure and the electrode disposed in the at least one isolation trench is electrically connected to a source region of the current sensor cell region.

[0071] Example 12: The semiconductor device of any of the preceding examples, wherein the gate electrode of the main device region is electrically connected to the gate electrode of the current sensor region via a second conductive layer disposed over the first major surface of the semiconductor substrate.

[0072] Example 13: The semiconductor device of Examples 8 and 12, wherein the first conductive layer is disposed between the first major surface of the semiconductor substrate and the second conductive layer.

[0073] Example 14: A semiconductor device as described in any of the previous examples, wherein

[0074] The main device area also includes: a plurality of shielding areas of the second conductivity type, arranged between two adjacent main device primitive areas confined by a gate trench of the main device area, wherein the plurality of shielding areas are arranged on the first main surface of the semiconductor substrate and at least partially cover the bottom of the confined gate trench; and wherein the current sensor area also includes: a plurality of shielding areas of the second conductivity type, arranged between two adjacent current sensor primitive areas confined by a gate trench of the current sensor area, wherein the plurality of shielding areas are arranged on the first main surface of the semiconductor substrate and at least partially cover the bottom of the confined gate trench.

[0075] Example 15: A semiconductor device as described in any of Examples 2 to 14, further comprising: an emitter / source pad arranged on the first main surface of the semiconductor substrate and electrically connected to a source region arranged in the plurality of main device primitive regions; a sensing pad arranged on the first main surface of the semiconductor substrate and electrically connected to a source region arranged in the plurality of current sensor primitive regions; and a gate pad arranged on the first main surface of the semiconductor substrate and electrically connected to a gate electrode of the main device region and to a gate electrode of the current sensor region.

[0076] Example 16: The semiconductor device of Example 15, further comprising: a temperature sensor region comprising a temperature sensor device, wherein a first terminal of the temperature sensor device is electrically connected to the sensing pad.

[0077] Example 17: A semiconductor device as described in Example 16, wherein when the gate pad is switched to a first state, the semiconductor device is configured to allow the current in the current sensor area to be measured using the sensing pad, and wherein when the gate pad is switched to a second state, the semiconductor device is also configured to allow the temperature of the semiconductor device to be measured using the sensing pad.

[0078] Example 18: The semiconductor device of Example 17, wherein the first state is an on state and the second state is an off state.

[0079] Example 19: A semiconductor device as described in any of Examples 16 to 18, wherein the second terminal of the temperature sensor device is electrically connected to the emitter / source pad.

[0080] Example 20: The semiconductor device of any of Examples 16 to 19, wherein the temperature sensor device includes at least one of a resistor and a plurality of diodes coupled in series.

[0081] Although the present invention has been described with reference to illustrative examples, this description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative examples and other examples of the present invention will be clear to those skilled in the art when referring to the description. Therefore, it is intended that the appended claims cover any such modifications or examples.

Claims

1. A semiconductor device (100, 400, 500, 600), comprising: A semiconductor substrate (102); The main equipment area (108, 408) includes: A plurality of main device primitive regions (114, 114_1, 114_2) are bounded by gate trenches (116, 116_1-116_4) arranged at a first main surface (104) of the semiconductor substrate (102), wherein gate electrodes (136) are arranged in the gate trenches (116, 116_1-116_4); A current sensor area (110, 410, 612), comprising: a plurality of current sensor cell regions (118, 118_1, 118_2) defined by gate trenches (120, 120_1-120_4) arranged at the first main surface (104) of the semiconductor substrate (102), wherein gate electrodes (150) are arranged in the gate trenches (120, 120_1-120_4); and An interface region (112, 412) is arranged between the main device region (108, 408) and the current sensor region (110, 410, 612), the interface region (112, 412) comprising: A shielding region (122_1) of a second conductivity type is arranged on the first main surface (104) of the semiconductor substrate (102) and at least partially covers a bottom of one (120_1) of the gate trenches (116, 116_1-116_4, 120, 120_1-120_4) confining one of the plurality of main device primitive regions (114, 114_1, 114_2) or one of the plurality of current sensor primitive regions (118, 118_1, 118_2), Another region (124_1, 126) of the second conductivity type is arranged on the first main surface (104) of the semiconductor substrate (102), and A void region (128, 128_1) of a first conductivity type is arranged on the first main surface (104) of the semiconductor substrate (102), wherein the void region (128, 128_1) separates the shielding region (122_1) from the other region (124_1, 126).

2. The semiconductor device (100, 400, 500, 600) of claim 1, wherein the plurality of main device primitive regions (114, 114_1, 114_2) and the plurality of current sensor primitive regions (118, 118_1, 118_2) include a source region (130, 146) of the first conductivity type, a body region (132, 148) of the second conductivity type, and a drift region (134) of the first conductivity type, wherein the body region (132, 148) separates the drift region (134) from the source region (130, 146).

3. The semiconductor device (100, 400, 500, 600) as claimed in the preceding claim, wherein the drift region (134) and the void region (128, 128_1) are continuous regions.

4. A semiconductor device (100, 400, 500, 600) as claimed in any one of the preceding claims, wherein the further region (124_1) is: another shielding region of the second conductivity type, arranged on the first main surface (104) of the semiconductor substrate (102), and at least partially covering the bottom of one of the gate trenches (116, 116_1-116_4, 120, 120_1-120_4) confining one of the plurality of main device primitive regions (114, 114_1, 114_2) or one of the plurality of current sensor primitive regions (118, 118_1, 118_2).

5. The semiconductor device (100, 400, 500, 600) of any one of claims 2 or 3, wherein the further region (124_1, 126) is electrically connected to the source region (130) of the main device cell region (114, 114_1, 114_2).

6. The semiconductor device (100, 400, 500, 600) as claimed in any one of the preceding claims, wherein the void region (128, 128_1) electrically isolates the shielding region (122_1) from the further region (124_1, 126).

7. The semiconductor device (100, 400, 500, 600) of any one of the preceding claims, wherein the interface region (112, 412) completely surrounds the current sensor region (110, 410, 612).

8. The semiconductor device (100, 400, 500, 600) according to any one of claims 2 to 7, further comprising: A shielding structure (158) is arranged in a first conductive layer (138), wherein the first conductive layer (138) is arranged on the first main surface (104) of the semiconductor substrate (102), wherein the shielding structure (158) is arranged on the void area (128, 128_1).

9. The semiconductor device (100, 400, 500, 600) according to any one of claims 2 to 8, further comprising: At least one isolation trench (160) is arranged at the first main surface (104) of the semiconductor substrate (102) and extends into the void region (128, 128_1).

10. The semiconductor device (100, 400, 500, 600) of claim 8 and claim 9, wherein an electrode (162) arranged in the at least one isolation trench (160) is electrically connected to the shielding structure (158).

11. The semiconductor device (100, 400, 500, 600) of claim 8 and claim 9, wherein at least one of the shielding structure (158) and the electrode (162) arranged in the at least one isolation trench (160) is electrically connected to the source region (146) of the current sensor cell region (118, 118_1, 118_2).

12. A semiconductor device (100, 400, 500, 600) as claimed in any one of the preceding claims, wherein the gate electrode (136) of the main device area (108, 408) is electrically connected to the gate electrode (150) of the current sensor area (110, 410, 612) by a second conductive layer (142) arranged above the first main surface (104) of the semiconductor substrate (102).

13. The semiconductor device (100, 400, 500, 600) of claim 8 and claim 12, wherein the first conductive layer (138) is arranged between the first major surface (104) of the semiconductor substrate (102) and the second conductive layer (142).

14. The semiconductor device (100, 400, 500, 600) as claimed in any one of the preceding claims, wherein The main equipment area (108, 408) also includes: The plurality of shielding regions (124_2, 124_3) of the second conductivity type are arranged between two adjacent main device primitive regions (114_1, 114_2) confined by gate trenches (116_2-116_4) of the main device region (108, 408), wherein the plurality of shielding regions (124_2, 124_3) are arranged on the first main surface (104) of the semiconductor substrate (102) and at least partially cover the bottom of the confined gate trenches (116_2-116_4); and wherein The current sensor area (110, 410, 612) further includes: The plurality of shielding regions (122_2, 122_3) of the second conductivity type are arranged between two adjacent current sensor cell regions (118_1, 118_2) confined by gate trenches (120_2-120_4) of the current sensor region (110, 410, 612), wherein the plurality of shielding regions (122_2, 122_3) are arranged on the first main surface (104) of the semiconductor substrate (102) and at least partially cover the bottom of the confined gate trenches (120_2-120_4).

15. The semiconductor device (100, 400, 500, 600) according to any one of claims 2 to 14, further comprising: an emitter / source pad (E) disposed on the first major surface (104) of the semiconductor substrate (102) and electrically connected to a source region (130) disposed in the plurality of major device primitive regions (114, 114_1, 114_2); a sensing pad (S) arranged on the first major surface (104) of the semiconductor substrate (102) and electrically connected to a source region (146) arranged in the plurality of current sensor cell regions (118, 118_1, 118_2); and A gate pad (G) is arranged on the first major surface (104) of the semiconductor substrate (102) and is electrically connected to the gate electrode (136) of the main device area (108, 408) and to the gate electrode (150) of the current sensor area (110, 410, 612).

16. The semiconductor device (500, 600) of claim 15, further comprising: A temperature sensor region (674) includes a temperature sensor device (556), wherein a first terminal of the temperature sensor device (556) is electrically connected to the sensing pad (S).

17. The semiconductor device (500, 600) of claim 16, wherein when the gate pad (G) is switched to a first state, the semiconductor device (500, 600) is configured to allow the current in the current sensor region (612) to be measured using the sensing pad (S), and wherein when the gate pad (G) is switched to a second state, the semiconductor device (500, 600) is further configured to allow the temperature of the semiconductor device (500, 600) to be measured using the sensing pad (S).

18. The semiconductor device (500, 600) of claim 17, wherein the first state is an on-state and the second state is an off-state.

19. The semiconductor device (500, 600) of any one of claims 16 to 18, wherein a second terminal of the temperature sensor device (556) is electrically connected to the emitter / source pad (E).

20. The semiconductor device (500, 600) of any one of claims 16 to 19, wherein the temperature sensor device (556) comprises at least one of a resistor and a plurality of diodes coupled in series.

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