A VDMOS trench-type electric field modulation variable doping terminal and preparation method thereof

Abstract

The present invention provides a VDMOS trench-type electric field modulation variable doping terminal and a preparation method thereof. The method includes: epitaxially growing on the upper side of a silicon carbide substrate to obtain a drift layer; forming a blocking layer, etching, ion implanting to form a P+ well region and a P+ region; reforming the blocking layer, etching to form a first groove, a second groove and a third groove; depositing to form a first P-type trench region, a second P-type trench region and a third P-type trench region; reforming the blocking layer, performing thermal diffusion redistribution at a set temperature and for a set time to form a first P-type doping region, a second P-type doping region and a third P-type doping region; reforming the blocking layer, etching, depositing to form an insulating layer; reforming the blocking layer, etching, depositing to form a source metal layer and a cut-off ring metal layer; reforming the blocking layer, etching, depositing to form a high-resistivity conductor layer, and removing the blocking layer to solve the breakdown problem caused by electric field concentration and improve the reliability of the device.

Description

Technical Field

[0001] The present invention relates to a VDMOS trench-type electric field modulation variable doping terminal and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion. Based on the device structure design, due to the lateral distribution of the electric field in the transverse direction at the edge of the repeating cell, electric field concentration occurs, resulting in breakdown at the device edge. The traditional cell uses a field limiting ring structure with the same doping concentration to suppress electric field concentration. Since the doping concentration and spacing distribution of the field limiting ring are equal, the electric field intensity distribution gradually decreases, and there are still high and low differences in the electric field distribution. The breakdown risk in the area near the P+ well region is still relatively high. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a VDMOS trench-type electric field modulation variable doping terminal and a preparation method thereof, to solve the breakdown problem caused by electric field concentration and improve the reliability of the device.

[0004] In a first aspect, the present invention provides a preparation method of a VDMOS trench-type electric field modulation variable doping terminal, including the following steps:

[0005] Step 1: Epitaxially grow on the upper side of a silicon carbide substrate to obtain a drift layer;

[0006] Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P+ well region and a P+ region;

[0007] Step 3: Remove the blocking layer, re-form the blocking layer, etch the blocking layer to form a through hole, and etch the drift layer to form a first groove, a second groove, and a third groove;

[0008] Step 4: Remove the blocking layer, re-form the blocking layer, etch the blocking layer to form a through hole, and etch downward the second groove and the third groove;

[0009] Step 5: Remove the blocking layer, re-form the blocking layer, etch the blocking layer to form a through hole, and etch downward the third groove;

[0010] Step 6: Remove the blocking layer, re-form the blocking layer, etch the blocking layer to form a through hole, and deposit a silicon carbide material to form a first P-type trench region;

[0011] Step 7: Remove the blocking layer, re-form the blocking layer, etch the blocking layer to form a through hole, and deposit a silicon carbide material to form a second P-type trench region;

[0012] Step 8: Remove the barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, deposit silicon carbide material, and form a third P-type trench region;

[0013] Step 9: Remove the barrier layer, reform the barrier layer, and perform thermal diffusion redistribution on the first P-type trench region, the second P-type trench region, and the third P-type trench region at a set temperature and for a set time to form a first P-type doped region, a second P-type doped region, and a third P-type doped region; the main junction includes the first P-type doped region and the first P-type trench region; the first field limit ring includes the second P-type doped region and the second P-type trench region; the second field limit ring includes the third P-type doped region and the third P-type trench region, and the P+ well region, the first P-type doped region, the second P-type doped region, and the third P-type doped region are connected in sequence;

[0014] Step 10: Remove the barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, and deposit to form an insulating layer;

[0015] Step 11: Remove the barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, and deposit to form a source metal layer and a cutoff ring metal layer;

[0016] Step 12: Remove the barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, deposit to form a high-resistivity conductor layer, and remove the barrier layer.

[0017] In a second aspect, the present invention provides a VDMOS trench-type electric field modulation variable doping terminal, and the silicon carbide VDMOS is prepared by using the preparation method of a VDMOS trench-type electric field modulation variable doping terminal described in the first aspect.

[0018] The advantages of the present invention are as follows:

[0019] First, by setting a high-resistivity conductor layer at the top of the device terminal structure, when the drain bears voltage, there is a voltage difference between the source metal layer and the cutoff ring metal layer. The high-resistivity conductor layer makes the voltage evenly distributed in this region, and then a uniformly distributed electric field is formed under the insulating layer, suppressing the breakdown problem caused by the electric field concentration near the P+ well region;

[0020] Second, the present invention constructs a first P-type doped region, a second P-type doped region, and a third P-type doped region with gradually decreasing concentration, gradually decreasing width, and gradually increasing depth in the extending direction from the P+ well region to the cutoff ring metal layer. The first P-type doped region reduces the electric field strength at the interface with the P+ well region, the second P-type doped region reduces the electric field strength at the interface with the first P-type doped region, and the third P-type doped region reduces the electric field strength at the interface with the second P-type doped region and the drift layer;

[0021] 3. The gradually increasing depths of the first P-type doping region, the second P-type doping region, and the third P-type doping region are to extend the interface with the maximum electric field intensity towards the interior of the device, avoiding the influence of the electric field on the electric field distribution near the cutoff ring metal layer at the device surface and affecting the device reliability. Description of the Drawings

[0022] The present invention will be further described below with reference to the drawings in conjunction with embodiments.

[0023] Figure 1 It is a schematic diagram of a VDMOS trench-type electric field modulation variable doping terminal of the present invention.

[0024] Figure 2 It is a process cross-section of a VDMOS trench-type electric field modulation variable doping terminal of the present invention Figure 1 。

[0025] Figure 3 It is a process cross-section of a VDMOS trench-type electric field modulation variable doping terminal of the present invention Figure 2 。

[0026] Figure 4 It is a process cross-section of a VDMOS trench-type electric field modulation variable doping terminal of the present invention Figure 3 。

[0027] Figure 5 It is a process cross-section of a VDMOS trench-type electric field modulation variable doping terminal of the present invention Figure 4 。

[0028] Figure 6 It is a process cross-section of a VDMOS trench-type electric field modulation variable doping terminal of the present invention Figure 5 。

[0029] Figure 7 It is a process cross-section of a VDMOS trench-type electric field modulation variable doping terminal of the present invention Figure 6 。

[0030] Figure 8 It is a process cross-section of a VDMOS trench-type electric field modulation variable doping terminal of the present invention Figure 7 。

[0031] Figure 9 It is a process cross-section of a VDMOS trench-type electric field modulation variable doping terminal of the present invention Figure 8 。

[0032] Figure 10 It is a process cross-section of a VDMOS trench-type electric field modulation variable doping terminal of the present invention Figure 9 。

[0033] Figure 11Process cross-section of a VDMOS trench-type electric field modulation variable doping terminal according to the present invention Figure 10 。

[0034] Figure 12 Process cross-section of a VDMOS trench-type electric field modulation variable doping terminal according to the present invention Figure 10 I.

[0035] Figure 13 Process cross-section of a VDMOS trench-type electric field modulation variable doping terminal according to the present invention Figure 10 II. Specific embodiments

[0036] To facilitate understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0038] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as "directly on", "in contact with", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below may be denoted as the second element, component, region, layer or part.

[0039] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. can be used herein to describe the relationship of one element or feature described in the figure with other elements or features. It should be understood that, in addition to the orientations described in the figure, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the attached drawing is flipped, an element or feature described as "under other elements" or "beneath it" or "under it" will be oriented "above" other elements or features. Therefore, the exemplary terms "under" and "beneath" can include both upper and lower orientations. In addition, the device can also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are accordingly interpreted.

[0040] As used herein, the singular forms of "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that terms such as "comprising" or "having" etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0041] As Figures 1 to 13 shown, an embodiment of the present application provides a method for preparing a VDMOS trench-type electric field modulation variable doping terminal, including the following steps:

[0042] Step 1: Epitaxially grow on the upper side of the silicon carbide substrate 1 to obtain a drift layer 2;

[0043] Step 2: Form a blocking layer 8 above the drift layer 2, etch the blocking layer 8 to form a through hole, and perform ion implantation to form a P+ well region 21 and a P+ region 25;

[0044] Step 3: Remove the blocking layer 8, reform the blocking layer 8, etch the blocking layer 8 to form a through hole, and etch the drift layer 2 to form a first groove 26, a second groove 27, and a third groove 28;

[0045] Step 4: Remove the blocking layer 8, reform the blocking layer 8, etch the blocking layer 8 to form a through hole, and etch downward the second groove 27 and the third groove 28;

[0046] Step 5: Remove the blocking layer 8, reform the blocking layer 8, etch the blocking layer 8 to form a through hole, and etch downward the third groove 28;

[0047] Step 6: Remove the barrier layer 8, reform the barrier layer 8, etch the barrier layer 8 to form a through hole, deposit a silicon carbide material, and form a first P-type trench region 222;

[0048] Step 7: Remove the barrier layer 8, reform the barrier layer 8, etch the barrier layer 8 to form a through hole, deposit a silicon carbide material, and form a second P-type trench region 232;

[0049] Step 8: Remove the barrier layer 8, reform the barrier layer 8, etch the barrier layer 8 to form a through hole, deposit a silicon carbide material, and form a third P-type trench region 242;

[0050] Step 9: Remove the barrier layer 8, reform the barrier layer 8, set the temperature to 1200 degrees Celsius, set the time to 80 minutes, and perform thermal diffusion redistribution on the first P-type trench region 222, the second P-type trench region 232, and the third P-type trench region 242 to form a first P-type doped region 221, a second P-type doped region 231, and a third P-type doped region 241; The main junction 22 includes the first P-type doped region 221 and the first P-type trench region 222; The first field limit ring 23 includes the second P-type doped region 231 and the second P-type trench region 232; The second field limit ring 24 includes the third P-type doped region 241 and the third P-type trench region 242, and the P+ well region 21, the first P-type doped region 221, the second P-type doped region 231, and the third P-type doped region 241 are connected in sequence;

[0051] Step 10: Remove the barrier layer 8, reform the barrier layer 8, etch the barrier layer 8 to form a through hole, and deposit to form an insulating layer 3;

[0052] Step 11: Remove the barrier layer 8, reform the barrier layer 8, etch the barrier layer 8 to form a through hole, deposit, and form a source metal layer 7 and a cutoff ring metal layer 4;

[0053] Step 12: Remove the barrier layer 8, reform the barrier layer 8, etch the barrier layer 8 to form a through hole, deposit, form a high-resistivity conductor layer 6, and remove the barrier layer 8.

[0054] In this embodiment, preferably, the lower sides of the first P-type doped region 221, the second P-type doped region 231, and the third P-type doped region 241 are all arc-shaped.

[0055] In this embodiment, preferably, the depth of the P+ region 25 is less than the depth of the first P-type doped region 221.

[0056] In this embodiment, preferably, it further includes a high-resistivity conductor layer 6. The lower side of the high-resistivity conductor layer 6 is connected to the insulating layer 3. The left side of the high-resistivity conductor layer 6 is connected to the source metal layer 7, and the right side of the high-resistivity conductor layer 6 is connected to the cutoff ring metal layer 4.

[0057] Preferably, in this embodiment, the thickness of the high-resistivity conductor layer 6 is greater than that of the insulating layer 3.

[0058] As Figure 1 shown, the terminal obtained by the above manufacturing method includes:

[0059] A silicon carbide substrate 1; a drain metal layer 5 is provided on the lower side of the silicon carbide substrate 1;

[0060] A drift layer 2 is provided on the upper side of the silicon carbide substrate 1. A P+ well region 21, a main junction 22, a first field limiting ring 23, a second field limiting ring 24, and a P+ region 25 are provided in the drift layer 2. The P+ well region 21, the main junction 22, the first field limiting ring 23, and the second field limiting ring 24 are connected in sequence. The P+ region 25 is provided at one end of the drift layer 2 and is located on one side of the second field limiting ring 24;

[0061] An insulating layer 3, the lower side of the insulating layer 3 is respectively connected to the P+ well region 21, the main junction 22, the first field limiting ring 23, the second field limiting ring 24, the drift layer 2, and the P+ region 25; the width of the main junction 22 is greater than that of the first field limiting ring 23, and the width of the first field limiting ring 23 is greater than that of the second field limiting ring 24; the depth of the main junction 22 is less than that of the first field limiting ring 23, and the depth of the first field limiting ring 23 is less than that of the second field limiting ring 24;

[0062] A cutoff ring metal layer 4, the lower side of the cutoff ring metal layer 4 is connected to the P+ region 25; a source metal layer 7 is connected to the P+ region 25 and the drift layer 2.

[0063] Preferably, in this embodiment, the main junction 22 includes a first P-type doped region 221 and a first P-type trench region 222. The first P-type doped region 221 is connected to the P+ well region 21, and the first P-type trench region 222 is provided in the first P-type doped region 221; the first field limiting ring 23 includes a second P-type doped region 231 and a second P-type trench region 232. The second P-type trench region 232 is provided in the second P-type doped region 231, and the second P-type doped region 231 is connected to the first P-type doped region 221; the second field limiting ring 24 includes a third P-type doped region 241 and a third P-type trench region 242. The third P-type trench region 242 is provided in the third P-type doped region 241, and the third P-type doped region 241 is connected to the second P-type doped region 231;

[0064] The width of the first P-type trench region 222 is greater than that of the second P-type trench region 232, and the width of the second P-type trench region 232 is greater than that of the third P-type trench region 242;

[0065] The depth of the first P-type trench region 222 is less than the depth of the second P-type trench region 232, and the depth of the second P-type trench region 232 is less than the depth of the third P-type trench region 242;

[0066] The width of the first P-type doping region 221 is greater than the width of the second P-type doping region 231, and the width of the second P-type doping region 231 is greater than the width of the third P-type doping region 241;

[0067] The depth of the first P-type doping region 221 is less than the depth of the second P-type doping region 231, and the depth of the second P-type doping region 231 is less than the depth of the third P-type doping region 241.

[0068] In this embodiment, preferably, the doping concentration of the first P-type trench region 222 is greater than the doping concentration of the second P-type trench region 232, and the doping concentration of the second P-type trench region 232 is greater than the doping concentration of the third P-type trench region 242;

[0069] The doping concentration of the first P-type doping region 221 is greater than the doping concentration of the second P-type doping region 231, and the doping concentration of the second P-type doping region 231 is greater than the doping concentration of the third P-type doping region 241.

[0070] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18 cm -3 , the doping concentration of the N-type drift layer is 5-9e16 cm -3 , the doping concentration of the third P-type doping region 241 is 2-8e16 cm -3 , the doping concentration of the second P-type doping region 231 is 0.8-5e17 cm -3 , the doping concentration of the first P-type doping region 221 is 0.5-5e18 cm -3 , the doping concentrations of the P+ well region 21 and the P+ region 25 are both 5-8e18 cm -3 , the doping concentration of the third P-type trench region 242 is 2-8e17 cm -3 , the doping concentration of the second P-type trench region 232 is 0.8-5e18 cm -3 , the doping concentration of the first P-type doping region 221 is 0.5-5e19 cm -3 , the material of the insulating layer 3 can be silicon dioxide, and the materials of the source metal layer 7 and the cutoff ring metal layer 4 can be one metal among Al, Cu, Ni or an alloy of several metals, and the high-resistivity conductor layer 6 is a SIPOS material or lightly doped polysilicon;

[0071] The doping concentrations of the silicon carbide substrate 1, the drift layer 2, and the p+ well region 21 are considered in the traditional design structure of the planar-gate silicon carbide VDMOS device. The doping concentrations of the third P-type trench region 242, the second P-type trench region 232, and the first P-type trench region 222 are for forming the third P-type doped region 241, the second P-type doped region 231, and the first P-type doped region 221 with corresponding concentrations under the conditions of the thermal diffusion process. The doping concentrations of the third P-type doped region 241, the second P-type doped region 231, and the first P-type doped region 221 are for forming a distribution where the P-type doping concentration gradually decreases from the P+ well region 21 to the first P-type doped region 221, the second P-type doped region 231, the third P-type doped region 241 to the cutoff ring metal layer 4;

[0072] As Figure 1 shown, where d1 is 10 μm, d2 is 6 μm, d3 is 3 μm, w1 is 2 μm, w2 is 1 μm, w3 is 0.5 μm. This is the width design optimized for the electric field distribution matching the doping concentration and the distribution situation generated by thermal diffusion under the doping conditions of the trench region;

[0073] The depth of the P+ well region 21 is 1 μm, the depth of the first P-type doped region 221 is 1.5 μm, the depth of the second P-type doped region 231 is 2 μm, the depth of the third P-type doped region 241 is 3 μm, the depth of the third P-type trench region 242 is 2 μm, the depth of the second P-type trench region 232 is 1.2 μm, and the depth of the first P-type trench region 222 is 0.7 μm. This is for forming a structure where the depths of the P+ well region 21, the first P-type doped region 221, the second P-type doped region 231, and the third P-type doped region 241 gradually increase. The depth of the trench region is for forming the doped region with the corresponding depth;

[0074] The preparation method of the doped region in the device terminal adopts the thermal diffusion method. Since the trench is etched, the thermal diffusion depth of the device can be guaranteed. At the same time, compared with ion implantation, the thermal diffusion causes less lattice damage to the device, and the reliability and stability of the device are higher;

[0075] The thickness of the insulating layer 3 of the device is 100 nm, the thickness of the high-resistivity conductor layer 6 is 500 nm, and the thicknesses of the source metal layer 7 and the cutoff ring metal layer 4 are both 600 nm;

[0076] By setting the high-resistivity conductor layer 6 at the top of the device terminal structure, when the drain bears voltage, there is a voltage difference between the source metal layer 7 and the cutoff ring metal layer 4. The high-resistivity conductor layer 6 makes the voltage evenly distributed in this region, and then a uniformly distributed electric field is formed under the insulating layer 3, suppressing the breakdown problem caused by the electric field concentration near the P+ well region 21;

[0077] A first P-type doped region 221, a second P-type doped region 231, and a third P-type doped region 241 with gradually decreasing concentration, gradually decreasing width, and gradually increasing depth are constructed in the direction of the extension of the cut-off ring metal layer 4 from the P+ well region 21. The first P-type doped region 221 reduces the electric field strength at the interface with the P+ well region 21, the second P-type doped region 231 reduces the electric field strength at the interface with the first P-type doped region 221, and the third P-type doped region 241 reduces the electric field strength at the interfaces with the second P-type doped region 231 and the drift layer 2. The function of the P+ region 25 is to guide the potential of the cut-off ring metal layer 4 to the inside of the electrical appliance, ensuring that it does not affect the reverse breakdown voltage of the device.

[0078] The depths of the first P-type doped region 221, the second P-type doped region 231, and the third P-type doped region 241 gradually increase to extend the interface with the maximum electric field strength towards the inside of the device, avoiding the electric field affecting the electric field distribution near the cut-off ring metal layer 4 at the device surface and affecting the device reliability.

[0079] Although the specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered by the scope protected by the claims of the present invention.

Claims

1. A preparation method of a VDMOS trench-type electric field modulation variable doping terminal, characterized in that: It includes the following steps: Step 1: Epitaxial growth on the upper side of a silicon carbide substrate to obtain a drift layer; Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, perform ion implantation to form a P+ well region and a P+ region; Step 3: Remove the blocking layer in Step 2, reform the blocking layer, etch the blocking layer to form a through hole, and etch the drift layer to form a first groove, a second groove, and a third groove; Step 4: Remove the blocking layer in Step 3, reform the blocking layer, etch the blocking layer to form a through hole, and etch the second groove and the third groove downward; Step 5: Remove the blocking layer in Step 4, reform the blocking layer, etch the blocking layer to form a through hole, and etch the third groove downward; Step 6: Remove the blocking layer in Step 5, reform the blocking layer, etch the blocking layer to form a through hole, deposit silicon carbide material to form a first P-type trench region; Step 7: Remove the blocking layer in Step 6, reform the blocking layer, etch the blocking layer to form a through hole, deposit silicon carbide material to form a second P-type trench region; Step 8: Remove the blocking layer in Step 7, reform the blocking layer, etch the blocking layer to form a through hole, deposit silicon carbide material to form a third P-type trench region; Step 9: Remove the blocking layer in Step 8, reform the blocking layer, at a set temperature and for a set time, perform thermal diffusion redistribution on the first P-type trench region, the second P-type trench region, and the third P-type trench region to form a first P-type doped region, a second P-type doped region, and a third P-type doped region; the main junction includes the first P-type doped region and the first P-type trench region; the first field limiting ring includes the second P-type doped region and the second P-type trench region; the second field limiting ring includes the third P-type doped region and the third P-type trench region, and the P+ well region, the first P-type doped region, the second P-type doped region, and the third P-type doped region are connected in sequence; Step 10: Remove the blocking layer in Step 9, reform the blocking layer, etch the blocking layer to form a through hole, and deposit to form an insulating layer; Step 11: Remove the blocking layer in Step 10, reform the blocking layer, etch the blocking layer to form a through hole, deposit to form a source metal layer and a cutoff ring metal layer; Step 12: Remove the blocking layer in Step 11, reform the blocking layer, etch the blocking layer to form a through hole, deposit to form a high-resistivity conductor layer, and remove the reformed blocking layer.

2. The preparation method of a VDMOS trench-type electric field modulation variable doping terminal according to claim 1, characterized in that: The specific content of Step 9 is as follows: Remove the blocking layer, reform the blocking layer, set the temperature to 1200 degrees Celsius, set the time to 80 minutes, perform thermal diffusion redistribution on the first P-type trench region, the second P-type trench region, and the third P-type trench region to form a first P-type doped region, a second P-type doped region, and a third P-type doped region; the main junction includes the first P-type doped region and the first P-type trench region; the first field limiting ring includes the second P-type doped region and the second P-type trench region; the second field limiting ring includes the third P-type doped region and the third P-type trench region, and the P+ well region, the first P-type doped region, the second P-type doped region, and the third P-type doped region are connected in sequence; The width of the first P-type trench region is greater than the width of the second P-type trench region, and the width of the second P-type trench region is greater than the width of the third P-type trench region; The depth of the first P-type trench region is less than the depth of the second P-type trench region, and the depth of the second P-type trench region is less than the depth of the third P-type trench region; The width of the first P-type doping region is greater than the width of the second P-type doping region, and the width of the second P-type doping region is greater than the width of the third P-type doping region; The depth of the first P-type doping region is less than the depth of the second P-type doping region, and the depth of the second P-type doping region is less than the depth of the third P-type doping region.

3. The manufacturing method of a VDMOS trench-type electric field modulation graded doping terminal as described in claim 2, characterized in that: The doping concentration of the first P-type trench region is greater than the doping concentration of the second P-type trench region, and the doping concentration of the second P-type trench region is greater than the doping concentration of the third P-type trench region; The doping concentration of the first P-type doping region is greater than the doping concentration of the second P-type doping region, and the doping concentration of the second P-type doping region is greater than the doping concentration of the third P-type doping region.

4. The manufacturing method of a VDMOS trench-type electric field modulation variable doping terminal as claimed in claim 2, wherein: The lower sides of the first P-type doping region, the second P-type doping region, and the third P-type doping region are all arc-shaped.

5. The preparation method of a VDMOS trench-type electric field modulation variable doping terminal according to claim 2, characterized in that: The depth of the P+ region is less than the depth of the first P-type doping region.

6. The manufacturing method of a VDMOS trench-type electric field modulation variable doping terminal as described in claim 1, wherein: It further includes a high-resistivity conductor layer, and the lower side of the high-resistivity conductor layer is connected to the insulating layer.

7. The manufacturing method of a VDMOS trench-type electric field modulation variable doping terminal according to claim 6, characterized in that: The thickness of the high-resistivity conductor layer is greater than the thickness of the insulating layer.

8. A VDMOS trench-type electric field modulation variable doping terminal, characterized in that, The terminal is prepared by the preparation method described in any one of claims 1 to 7.

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