Enclosed shield gate field effect transistor and manufacturing method thereof

Abstract

The invention provides an enclosed shield gate field effect transistor and a manufacturing method thereof, and relates to the technical field of semiconductors. The enclosed shield gate field effect transistor comprises a silicon mesa region, a shield gate, a control gate and an oxide layer, the shield gate and the control gate surround the silicon mesa region, the shield gate, the control gate and the silicon mesa region are arranged at intervals, and the oxide layer is filled among the shield gate, the control gate and the silicon mesa region; part of the shield grid is located below the control grid, and the other part of the control grid is led out independently. According to the enclosed shield gate field effect transistor and the manufacturing method thereof provided by the invention, the electric field modulation effect is more optimized, the more uniform shield gate potential is realized, the more uniform switching characteristic is realized, the power consumption is reduced, and the local current concentration is inhibited.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to an enclosed shielded gate field-effect transistor and its fabrication method. Background Technology

[0002] The shielded-gate MOS structure is based on the trench gate structure, but introduces a shielded gate (SG). This acts as a field plate structure, providing lateral auxiliary depletion and achieving two-dimensional electric field depletion in the drift region. This modulates the original triangular electric field distribution into an approximately rectangular one, achieving a charge balance effect. This significantly reduces the EPI resistance in the drift region, improving voltage withstand while lowering on-resistance. Therefore, with the same resistance specifications, the chip area can be greatly reduced.

[0003] However, conventional shielding barriers have several problems:

[0004] 1. Generally, a strip-shaped shielding grid structure along the Y direction is adopted. In this way, the shielding grid can only provide lateral auxiliary depletion in the X direction, which is a two-dimensional charge balance effect and limits the electric field modulation effect.

[0005] 2. Because the shielding gate is located below the gate, it cannot be effectively led out. The shielding gate is a polycrystalline structure, which introduces parasitic resistance. This leads to uneven distribution of the shielding gate potential, causing avalanche problems and gate punch-through problems.

[0006] 3. In conventional structures, bringing out the lower shield gate will cause an interruption in the upper gate, which will prevent the effective interconnection of the gate polysilicon. This will lead to a more complex layout and uneven switching, resulting in excessive switching losses or concentrated current during switching, which may cause device failure.

[0007] In summary, existing technologies suffer from poor electric field modulation, uneven potential distribution, and susceptibility to device failure due to shielded gate MOS structures. Summary of the Invention

[0008] The purpose of this application is to provide an enclosed shielded gate field-effect transistor and its fabrication method, so as to solve the problems of poor electric field modulation effect, uneven potential distribution and easy device failure of the shielded gate MOS structure in the prior art.

[0009] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0010] On one hand, this application provides an enclosed shielded gate field-effect transistor, which includes a silicon mesa region, a shielding gate, a control gate, and an oxide layer. The shielding gate and the control gate are both disposed around the silicon mesa region, and the shielding gate, the control gate, and the silicon mesa region are all spaced apart. The oxide layer fills the spaces between the shielding gate, the control gate, and the silicon mesa region.

[0011] Part of the shielding grid is located below the control grid, while another part of the shielding grid is led out independently.

[0012] Optionally, the control gate includes a field plate structure and a contact structure, the field plate structure is connected to the contact structure, the field plate structure is located below the control gate, and the contact structures are spaced apart around the silicon mesa region.

[0013] Optionally, the surface of the contact structure is flush with the surface of the control gate.

[0014] Optionally, the number of contact structures is multiple, and the multiple contact structures are arranged in a regular polygon around the silicon mesa region.

[0015] Optionally, the enclosed shielded field-effect transistor further includes an ILD layer and a source metal. The ILD layer has a first contact hole at a position opposite to the contact structure. The first contact hole is filled with contact metal, and the contact structure is connected to the source metal through the first contact hole.

[0016] Optionally, the silicon mesa region includes a drift region, a P-type body region, and an N-type source region arranged layer by layer from bottom to top. The enclosed shielded gate field-effect transistor also includes an ILD layer and a source metal. The ILD layer has a second contact hole extending to the P-type body region. The second contact hole is filled with contact metal. The P-type body region is connected to the source metal through the second contact hole.

[0017] Optionally, the silicon mesa region is configured as a regular polygon or a circle.

[0018] On the other hand, this application also provides a method for manufacturing an enclosed shielded gate field-effect transistor, used to manufacture the above-mentioned enclosed shielded gate field-effect transistor, the method comprising:

[0019] Provide an epitaxial layer;

[0020] Based on the epitaxial layer, trenches are etched, leaving multiple independent silicon mesa regions;

[0021] A shielding gate, a control gate, and an oxide layer are fabricated based on the trench. The shielding gate and the control gate are both disposed around the silicon mesa region. The shielding gate, the control gate, and the silicon mesa region are all spaced apart, and the oxide layer fills the spaces between the shielding gate, the control gate, and the silicon mesa region.

[0022] Optionally, the steps of fabricating the shielding gate, control gate, and oxide layer based on the trench include:

[0023] Based on the oxygen layer of the trench growth field;

[0024] Polycrystalline silicon is deposited based on the trenches;

[0025] The deposited polysilicon is etched to form a shielding gate;

[0026] Etch away excess field oxide layer;

[0027] Based on the growth of a gate oxide layer within the trench;

[0028] Polysilicon is deposited within the trench to form a control gate.

[0029] Optionally, after the step of depositing polysilicon within the trench and forming a control gate, the method further includes:

[0030] P-type ion implantation is performed in the silicon mesa region to form a P-type body region;

[0031] N-type ion implantation is performed on the surface of the P-type body region to form an N-type source region;

[0032] An ILD layer is grown on the surface of the N-type source region, the shielding gate, and the control gate;

[0033] The ILD layer is etched to form a first contact hole and a second contact hole, and contact metal is deposited based on the first contact hole and the second contact hole; wherein, the contact metal of the first contact hole contacts the shielding gate, and the contact metal of the second contact hole contacts the P-type body region.

[0034] Source metal is deposited on the surface of the ILD layer.

[0035] Compared with the prior art, this application has the following advantages:

[0036] This application provides a shielded-gate field-effect transistor (FET) and its fabrication method. The shielded-gate FET includes a silicon mesa region, a shielding gate, a control gate, and an oxide layer. Both the shielding gate and the control gate surround the silicon mesa region, and are spaced apart. The oxide layer fills the spaces between the shielding gate, the control gate, and the silicon mesa region. Part of the shielding gate is located below the control gate, while another part of the control gate is independently led out. On one hand, because the shielding gate and the control gate surround the silicon mesa region in the provided shielded-gate FET, a three-dimensional charge depletion effect is provided, resulting in a more optimized electric field modulation effect, thereby further improving the breakdown voltage and reducing the on-resistance. On the other hand, since some shielding gates are independently led out, the polysilicon of the shielding gate can be directly connected to the source metal, reducing the parasitic resistance of the shielding gate, achieving a more uniform shielding gate potential, improving avalanche capability, and suppressing gate punch-through. Furthermore, the control gates can be effectively interconnected, simplifying the layout, achieving more uniform switching characteristics, reducing power consumption, and suppressing local current concentration.

[0037] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 Figure 1 This is a schematic diagram of a shielded gate field-effect transistor embodiment in the prior art.

[0040] Figure 2 This is a schematic diagram of the structure of the enclosed shielded gate field-effect transistor embodiment of this application.

[0041] Figure 3 This is a schematic diagram of another structure in an embodiment of the enclosed shielded gate field-effect transistor of this application.

[0042] Figure 4 This is a first cross-sectional schematic diagram of an embodiment of the enclosed shielded gate field-effect transistor of this application.

[0043] Figure 5 This is a second cross-sectional schematic diagram of an embodiment of the enclosed shielded gate field-effect transistor of this application.

[0044] Figure 6This is a third cross-sectional schematic diagram of an embodiment of the enclosed shielded gate field-effect transistor of this application.

[0045] Figure 7 This is a schematic diagram of the first planar structure of an embodiment of the enclosed shielded gate field-effect transistor of this application.

[0046] Figure 8 This is a schematic diagram of the second planar structure of an embodiment of the enclosed shielded gate field-effect transistor of this application.

[0047] Figure 9 This is a schematic diagram of the third planar structure of an embodiment of the enclosed shielded gate field-effect transistor of this application.

[0048] Figure 10 This is a schematic diagram of the fourth planar structure of an embodiment of the enclosed shielded gate field-effect transistor of this application.

[0049] Figure 11 This is a schematic flowchart illustrating an embodiment of the method for fabricating an enclosed shielded gate field-effect transistor according to this application.

[0050] Figure 12 For this application Figure 11 A flowchart illustrating the sub-steps of S106.

[0051] Figure 13 This is a schematic diagram of the planar structure of trench etching in an embodiment of the method for fabricating an enclosed shielded gate field-effect transistor of this application.

[0052] Figure 14 This is a schematic diagram of trench etching in the first cross-section of an embodiment of the fabrication method of the enclosed shielded gate field-effect transistor of this application.

[0053] Figure 15 This is a schematic diagram of trench etching in the third cross-section of an embodiment of the fabrication method of the enclosed shielded gate field-effect transistor of this application.

[0054] Figure 16 This is a schematic diagram of the planar structure of the field oxide layer growth in an embodiment of the enclosed shielded gate field-effect transistor fabrication method of this application.

[0055] Figure 17 This is a schematic diagram of the field oxide layer growth in the first cross-section of an embodiment of the fabrication method of the enclosed shielded gate field-effect transistor of this application.

[0056] Figure 18 This is a schematic diagram of the field oxide layer growth in the third cross section of an embodiment of the fabrication method of the enclosed shielded gate field-effect transistor of this application.

[0057] Figure 19 This is a schematic diagram of the planar structure of the polycrystalline deposition of the shielding gate in an embodiment of the fabrication method of the enclosed shielded gate field-effect transistor of this application.

[0058] Figure 20 This is a schematic diagram of the polycrystalline deposition of the shielding gate in the first cross-section of an embodiment of the fabrication method of the enclosed shielded gate field-effect transistor of this application.

[0059] Figure 21 This is a schematic diagram of polycrystalline deposition of the shielding gate in the third cross-section of an embodiment of the fabrication method of the enclosed shielded gate field-effect transistor of this application.

[0060] Figure 22 This is a schematic diagram of the planar structure of the shielded gate etching in an embodiment of the method for fabricating an enclosed shielded gate field-effect transistor of this application.

[0061] Figure 23 This is a schematic diagram of the etching of the shielding gate in the first cross section of an embodiment of the fabrication method of the enclosed shielded gate field-effect transistor of this application.

[0062] Figure 24 This is a schematic diagram of the etching of the shielding gate in the third cross section of an embodiment of the fabrication method of the enclosed shielded gate field-effect transistor of this application.

[0063] Figure 25 This is a schematic diagram of the field oxide layer etching in the first cross section of an embodiment of the fabrication method of the enclosed shielded gate field-effect transistor of this application.

[0064] Figure 26 This is a schematic diagram of the field oxide layer etching in the third cross section of an embodiment of the fabrication method of the enclosed shielded gate field-effect transistor of this application.

[0065] Figure 27 This is a schematic diagram of the gate oxide layer growth in the first cross-section of an embodiment of the enclosed shielded gate field-effect transistor fabrication method of this application.

[0066] Figure 28 This is a schematic diagram of the gate oxide layer growth in the third cross-section of an embodiment of the fabrication method of the enclosed shielded gate field-effect transistor of this application.

[0067] Figure 29 This is a schematic diagram of the control gate polycrystalline deposition in the first cross-section of an embodiment of the fabrication method of the enclosed shielded gate field-effect transistor of this application.

[0068] Figure 30 This is a schematic diagram of the polycrystalline deposition of the interconnect gate in the third cross-section of an embodiment of the fabrication method of the enclosed shielded gate field-effect transistor of this application.

[0069] In the picture:

[0070] 100-Shielding gate; 101-Field plate structure; 102-Contact structure; 110-Second contact hole; 120-First contact hole; 200-Silicon mesa region; 201-Epipolar layer; 202-P-type body region; 2021-N-type source region; 300-Control gate; 301-Functional gate; 302-Interconnect gate; 400-Oxide layer; 401-Field oxide layer; 402-Gate oxide layer; 500-ILD layer; 600-Source metal. Detailed Implementation

[0071] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0072] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0073] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0074] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0075] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0076] As described in the background section, current shielding grid structures suffer from poor performance. For example... Figure 1The diagram shown is a cross-sectional view of a shielded gate field-effect transistor in the prior art. In the diagram, G represents the gate, SG represents the shielded gate structure, Nepi represents the N-type epitaxial layer, Nsub represents the N-type substrate, Pbody represents the P-type body region, contact represents the contact hole, which is filled with contact metal, and N+ represents the N-type doped region.

[0077] Depend on Figure 1 It is known that the shielding gate structure adopts a strip structure along the Y direction, which means that the shielding gate structure can only provide lateral auxiliary depletion in the X direction, resulting in a two-dimensional charge balance effect that limits the electric field modulation effect. Simultaneously, the shielding gate structure is located below the gate and cannot be effectively led out. The shielding gate is a polycrystalline structure, which introduces parasitic resistance, leading to non-uniform distribution of the gate potential and causing avalanche and gate punch-through problems. Furthermore, based on... Figure 1 The structure shown would cause an interruption in the upper gate if the lower shield gate were to be brought out, preventing the effective interconnection of the gate polysilicon. This would lead to a complex layout and uneven switching, resulting in excessive switching losses or concentrated current during switching, which could cause device failure.

[0078] In view of this, in order to solve the above problems, this application provides an enclosed shielded gate field-effect transistor, and the enclosed shielded gate field-effect transistor provided in this application is described exemplarily below:

[0079] Please see Figure 2 and Figure 3 The enclosed shielded field-effect transistor provided in this application includes a silicon mesa region 200, a shielding gate 100, a control gate 300, and an oxide layer 400. The shielding gate 100 and the control gate 300 are both arranged to surround the silicon mesa region 200. The shielding gate 100, the control gate 300, and the silicon mesa region 200 are all spaced apart, and the oxide layer 400 fills the spaces between the shielding gate 100, the control gate 300, and the silicon mesa region 200. Part of the shielding gate 100 is located below the control gate 300, and another part of the shielding gate 100 is independently led out.

[0080] On the one hand, in the enclosed-gate field-effect transistor provided in the application, both the shielding gate 100 and the control gate 300 surround the silicon mesa region 200, ensuring that each independent silicon mesa region 200 is surrounded by the surrounding shielding gate 100. This provides a three-dimensional charge depletion effect, resulting in a more optimized electric field modulation effect, thereby further improving the breakdown voltage and reducing the on-resistance. On the other hand, since each shielding gate 100 is independently led out, it can be directly connected to the source metal 600, reducing the parasitic resistance of the shielding gate 100, achieving a more uniform shielding gate potential, improving avalanche capability, and suppressing gate punch-through. Furthermore, the control gates 300 can be effectively interconnected, simplifying the layout, achieving more uniform switching characteristics, reducing power consumption, and suppressing local current concentration. In summary, the enclosed shielded gate field-effect transistor provided in this application has an independently led-out shielded gate 100, effective gate interconnection, and an enclosed shielded gate 100 structure with three-dimensional charge depletion, which can achieve higher voltage, lower resistance, more uniform switching characteristics, and stronger avalanche capability.

[0081] It should be noted that the aforementioned silicon mesa region 200 is made of silicon. The upper part of the silicon mesa region 200 is used as a filler region, and the part outside the upper body region of the silicon mesa region 200 is the drift region.

[0082] Understandably, the constituent elements of the field plate structure 101 are the same as those of the conventional shielding grid 100, both being polycrystalline structures, the difference being the different shapes they form.

[0083] In a specific implementation, the silicon mesa region 200 can be etched to form deep trenches, thereby forming several independent silicon mesa regions 200. Each silicon mesa region 200 is surrounded by a deep trench. A shielding gate 100 is filled in the deep trench to form the above-mentioned field plate structure 101, so that the field plate structure 101 surrounds the silicon mesa region 200. Since the drift region is part of the silicon mesa region 200, the field plate structure 101 can also surround the above-mentioned drift region.

[0084] The shielding gate 100 includes a field plate structure 101 and a contact structure 102. The field plate structure 101 and the contact structure 102 are connected. The field plate structure 101 is located below the control gate 300. The contact structures 102 are spaced around the silicon mesa region 200, and the surface of the contact structure 102 is flush with the surface of the control gate 300.

[0085] Furthermore, there are multiple contact structures 102, and the multiple contact structures 102 form a regular polygon around the silicon mesa region 200.

[0086] In addition, the enclosed shielded field-effect transistor also includes an ILD layer 500 and a source metal 600. The ILD layer 500 is provided with a first contact hole 120 at a position opposite to the contact structure 102. The first contact hole 120 is filled with contact metal, and the contact structure 102 is connected to the source metal 600 through the first contact hole 120.

[0087] It should be noted that the contact structure 102 and the field plate structure 101 mentioned above are both part of the shielding grid 100. That is, the shielding grid 100 involved in this embodiment is an integral structure.

[0088] It is understood that the aforementioned first contact hole 120 may be a contact hole for leading the shielding gate 100 to contact the source metal 600.

[0089] It should be noted that, since the shielding gate 100 of the conventional structure is located below the control gate 300 and cannot be effectively led out, and the shielding gate 100 is a polycrystalline structure, it will generate parasitic resistance, resulting in uneven distribution of the potential of the shielding gate 100, thereby causing avalanche problem and gate punch-through problem.

[0090] In specific implementations, such as Figure 3 As shown, similar to the conventional structure, the control gate 300 of the enclosed shielded gate 100 field-effect transistor involved in this embodiment is also located above the shielded gate 100, specifically above the field plate structure 101. However, the enclosed shielded gate 100 field-effect transistor involved in this embodiment can be independently led out through the contact structure 102 and connected to the source metal 600 through the source contact layer.

[0091] It should be understood that since each independent silicon mesa region 200 is surrounded by the surrounding contact structure 102, the contact structure 102 around the silicon mesa region 200 can provide auxiliary depletion to the central silicon mesa region 200, thereby providing a three-dimensional charge depletion effect. Compared with the conventional shielding gate 100, which can only provide lateral auxiliary depletion in the X direction, it has a more optimized electric field modulation effect, thereby further improving the withstand voltage and reducing the on-resistance.

[0092] like Figure 3 As shown, the contact structure 102 can be a structure led out from the field plate structure 101. The contact structure 102 can be independently led out from the four corners of the field plate structure 101 and connected to the source metal 600 through the contact metal, thereby reducing the parasitic resistance generated by the shield gate 100, providing a more uniform potential distribution of the shield gate 100, improving avalanche capability, and suppressing gate penetration and false turn-on.

[0093] It should be understood that, as Figure 2As shown, oxide layers 400 are provided between the field plate structure 101 and the control gate 300, between the contact structure 102 and the control gate 300, and between the control gate 300 and the silicon mesa region 200 for isolation. For ease of understanding, Figure 3 The oxide layer 400 is omitted in the text; in the actual structure, this oxide layer 400 exists in... Figure 3 The gaps within are used to isolate the various structures.

[0094] It should be noted that the above Figure 3 In the above, the first direction AA' and the second direction BB' can be the directions between adjacent silicon mesa regions 200, the third direction CC' and the fourth direction DD' can be the directions between adjacent contact structures 102, and the fifth direction EE' and the sixth direction FF' can be the directions between silicon mesa regions 200 and contact structures 102.

[0095] Based on this, the control gate 300 includes a functional gate 301 and an interconnect gate 302. The functional gate 301 is located between two adjacent silicon mesa regions 200, and the interconnect gate 302 is located between the silicon mesa region 200 and the contact structure 102. The functional gate 301 and the interconnect gate 302 are connected.

[0096] In this embodiment, the silicon mesa region 200 is set as a regular polygon or a circle, and please refer to [link / reference]. Figure 4 , Figure 4 For along Figure 3 The cross-sectional view obtained by cutting in the first direction AA' or the second direction BB'. Figure 4 In the process, the silicon mesa region 200 includes a drift region, a P-type body region 202, and an N-type source region 2021 arranged layer by layer from bottom to top. The enclosed shielded gate field-effect transistor also includes an ILD layer 500 and a source metal 600. A second contact hole 110 extending to the P-type body region 202 is provided in the ILD layer 500. The second contact hole 110 is filled with contact metal, and the P-type body region 202 is connected to the source metal 600 through the second contact hole 110. The P-type body region 202 is located above the silicon mesa region 200.

[0097] It should be noted that the P-type body region 202 can be formed by P-body implantation above the silicon mesa region 200. Correspondingly, the area below the P-type body region 202 in the silicon mesa region 200 is the drift region. The P-type body region 202 is disposed above the epitaxial layer 201 in the silicon mesa region 200. Since the silicon mesa region 200 is surrounded by the aforementioned field plate structure 101, the P-type body region 202 is also surrounded by the field plate structure 101.

[0098] It should be understood that, Figure 4The system also includes an N-type source region 2021, an ILD layer 500, and a source metal 600. The N-type source region 2021 is located in the upper region of the body region. The ILD layer 500 is located above the N-type source region 2021 and covers the entire enclosed shielding gate 100 field-effect transistor. The source metal 600 is located above the ILD layer 500. A second contact hole 110 is opened in the ILD layer 500 and extends into the P-type body region 202. Correspondingly, the N-type source region 2021 located in the P-type body region 202 is located around the source contact layer. Thus, the P-type body region 202 can be led out to the source metal 600 through the contact metal in the second contact hole 110.

[0099] The control gate 300 electrode 301 and the interconnect gate 302 are both disposed above the field plate structure 101; the control gate 300 electrode 301 is located between adjacent silicon mesa regions 200; the interconnect gate 302 is located between the contact structure 102 and the silicon mesa region 200, and is in contact with the control gate 300 electrode 301.

[0100] It should be noted that, as Figure 4 As shown, the control gate 300 located above the field plate structure 101 can be divided into a control gate 300 electrode 301 and an interconnect gate 302. Further, referring to... Figure 4 The gate between adjacent silicon mesa regions 200 is a control gate 300 pole 301, which has the same function as the gate in the conventional shielding gate 100 structure. The gate between the above-mentioned contact structure 102 and the silicon mesa region 200 is an interconnect gate 302.

[0101] In a specific implementation, the area between the contact structure 102 and the silicon mesa region 200 is relatively narrow, which can easily separate the gates, making the gates not a whole. Therefore, by introducing interconnect gates 302 to connect the control gate 300 poles 101 together, the gates are effectively interconnected to form a whole gate, which can provide more uniform switching characteristics and suppress local current concentration. Ultimately, this structure can achieve stronger avalanche capability.

[0102] It should be understood that, in the above Figure 4 In China, due to Figure 4 It is along the above Figure 4 The cross-sectional view obtained by cutting in the first direction AA' or the second direction BB', therefore Figure 4 The gate in the control gate is a control gate 300 electrode 301, wherein an oxide layer 400 is provided between the control gate 300 electrode 301 and the field plate structure 101 to isolate the control gate 300 electrode 301 and the field plate structure 101.

[0103] Furthermore, for ease of understanding, please refer to Figure 5 This explanation does not limit the scope of this solution. Figure 5 To follow the above Figure 3 Cross-sectional view obtained by cutting along the CC' or DD' direction. Figure 5 In this case, since both the CC' and DD' directions pass through the same contact structure 102, therefore... Figure 5 The gate is a control gate 300 electrode 301 located between adjacent silicon mesa regions 200. The contact structure 102 and the field plate structure 101 are interconnected to form an integral shielding gate 100. Each of the contact structures 102 has a first contact hole 120. The integral shielding gate 100 can be connected to the source metal 600 through the contact metal in the first contact hole 120, thereby reducing the parasitic resistance generated by the shielding gate 100, achieving a more uniform potential distribution of the shielding gate 100, thereby improving avalanche capability and suppressing gate penetration.

[0104] It should be noted that the above Figure 5 The overall shielding grid 100, which is composed of the intermediate contact structure 102 and the field plate structure 101, is provided with the oxide layer 400 between the control grid 300 pole 301 for isolation. The epitaxial layer 201 is located below the field plate structure 101 and is also provided with the oxide layer 400 between it and the field plate structure 101.

[0105] Furthermore, for ease of understanding, please refer to Figure 6 , Figure 6 This is a third cross-sectional schematic diagram of an embodiment of the enclosed shielded gate 100 field-effect transistor of this application. Figure 6 It can be along the above Figure 3 A cross-sectional view obtained by cutting along the EE' or FF' direction. Figure 6 Since the EE' or FF' direction both pass through the diagonal contact structure 102, the gate is an interconnect gate 302 located between the lead-out shield gate 100 pole 102 and the silicon mesa region 200 to connect each control gate 300 pole 301. A source contact layer is provided above the contact structure 102 to contact the source metal 600, so that the shield gate 100 can be led out while the gate is effectively interconnected.

[0106] It should be understood that the above Figure 6 In the process, the area between each field plate structure 101 is the silicon mesa region 200. The silicon mesa region 200 can be divided into the lower epitaxial layer 201 and the upper P-type body region 202. The P-type body region 202 can be injected with source regions, or it can be led out to the source metal 600 through the source contact layer.

[0107] In this embodiment, the silicon mesa region 200 surrounded by the field plate structure 101 is a regular polygonal structure or a circular structure. For example, please refer to... Figures 7-11 The silicon mesa region 200 surrounded by the field plate structure 101 can be a regular square, a regular hexagon, or a triangle.

[0108] For ease of understanding, please refer to Figure 7 This explanation does not limit the scope of this solution. Figure 7 This is a schematic diagram of the first planar structure of an embodiment of the enclosed shielded gate 100 field-effect transistor of the present invention. Figure 7 This can be considered as a top view of the enclosed shielding gate 100 field-effect transistor involved in the above embodiments. Figure 7 In the above, the first direction AA' and the sixth direction FF' are related to the above. Figure 3 The first direction AA' and the sixth direction FF' are consistent. Accordingly, the contact structure 102 is independently led out. At the same time, the field plate structure 101 is located below the control gate 300, and the silicon mesa region 200 surrounded by the field plate structure 101 is circular.

[0109] It should be understood that the oxide layer 400 is provided between the silicon mesa region 200 and the control gate 300, and the oxide layer 400 is provided between the contact structure 102 and the control gate 300.

[0110] Figures 8-10 In the diagram, since the field plate structure 101 is located below the control gate 300, it is shown in dashed lines. The silicon mesa region 200 surrounded by the field plate structure 101 has an octagonal shape and can also be led out through the contact structure 102. The gates are effectively interconnected and have three-dimensional charge depletion, which can achieve higher voltage, lower resistance, more uniform switching characteristics, and stronger avalanche capability.

[0111] It should be understood that the above Figure 8 -to Figure 10 The planar structure diagrams of the enclosed shielded gate 100 field-effect transistors shown can all be formed by means of the embodiments of the present invention, except as described above. Figures 8 to 11 The enclosed shielded gate 100 field-effect transistor shown can also be other structures that can achieve the purpose of the present invention, and this embodiment does not limit them.

[0112] Furthermore, to achieve the above objectives, the present invention also proposes a method for fabricating an enclosed shielded gate 100 field-effect transistor, referring to... Figure 11 , Figure 11 This is a schematic flowchart illustrating an embodiment of the method for fabricating a field-effect transistor with an enclosed shielded gate 100 according to the present invention.

[0113] like Figure 11 As shown, in this embodiment, the method for fabricating the enclosed shielded gate 100 field-effect transistor includes the following steps:

[0114] S102 provides an epitaxial layer 201.

[0115] S104 etches trenches based on the epitaxial layer 201, leaving multiple independent silicon mesa regions 200.

[0116] S106, a shielding gate 100, a control gate 300, and an oxide layer 400 are fabricated based on trenches. The shielding gate 100 and the control gate 300 are both arranged to surround the silicon mesa region 200. The shielding gate 100, the control gate 300, and the silicon mesa region 200 are all spaced apart, and the oxide layer 400 is filled between the shielding gate 100, the control gate 300, and the silicon mesa region 200.

[0117] Among them, such as Figure 12 As shown, S106 includes:

[0118] S1061, based on the oxygen layer of the trench growth field;

[0119] S1062, based on trench-deposited polysilicon;

[0120] S1063, etching the deposited polysilicon to form a shielding gate 100;

[0121] S1064, etching away excess field oxide layer;

[0122] S1065, based on the growth of a gate oxide layer within the trench;

[0123] S1066 is based on polysilicon deposited in the trench and forming a control gate 300.

[0124] In addition, the method also includes:

[0125] S108, P-type ion implantation is performed in the silicon mesa region 200 to form a P-type body region 202;

[0126] S110, N-type ion implantation is performed on the surface of the P-type body region 202 to form the N-type source region 2021;

[0127] S112, an ILD layer 500 is grown on the surface of the N-type source region 2021, the shielding gate 100 and the control gate 300;

[0128] S114, the ILD layer 500 is etched to form a first contact hole 120 and a second contact hole 110, and contact metal is deposited based on the first contact hole 120 and the second contact hole 110; wherein, the contact metal of the first contact hole 120 contacts the shielding gate 100, and the contact metal of the second contact hole 110 contacts the P-type body region 202.

[0129] S116, based on surface deposition of source metal 600 on ILD layer 500.

[0130] It should be noted that the embodiments of the method for fabricating the enclosed shielded gate 100 field-effect transistor of the present invention are described above. Figure 7Taking the first planar structure diagram shown as an example, the process flow of this embodiment is explained using the first direction AA' and the sixth direction FF' mentioned above.

[0131] It is understandable that the aforementioned silicon mesa region 200 can be a structure made of silicon, and correspondingly, the drift region can be the area below the silicon mesa region 200.

[0132] For ease of understanding, please refer to Figure 13 This explanation does not limit the scope of this solution. Figure 13 This is a schematic diagram of the planar structure of trench etching in an embodiment of the method for fabricating the enclosed shielded gate 100 field-effect transistor of the present invention. Figure 13 In the above, the first direction AA' and the sixth direction FF' can be the same as the above. Figure 7 The directions involved are consistent. Before etching, the silicon mesa region 200 can be the entire complete wafer. Through etching, trenches are etched to make the silicon mesa region 200 become several individual silicon mesa regions 200.

[0133] For ease of understanding, please refer to Figure 14 This explanation does not limit the scope of this solution. Figure 14 This is a schematic diagram of trench etching in the first cross-section of an embodiment of the fabrication method of the enclosed shielded gate 100 field-effect transistor of the present invention. Figure 14 In order to form a region between adjacent silicon mesa regions 200 where control gate 300 poles are subsequently set, the first trench etched between adjacent silicon mesa regions 200 does not need to be too wide.

[0134] For ease of understanding, please refer to Figure 15 This explanation does not limit the scope of this solution. Figure 15 This is a schematic diagram of trench etching in the third cross-section of an embodiment of the fabrication method of the enclosed shielded gate 100 field-effect transistor of the present invention. Figure 15 In order to form a shielding lead-out region and an interconnect gate 302 region between the diagonally distributed silicon mesa regions 200, a second trench with a width greater than the width of the first trench is required.

[0135] In the specific implementation, deep trench etching is used to leave each independent silicon mesa region 200. The bottom of each silicon mesa region 200 is still preserved without etching, so that the silicon mesa regions 200 are connected together from below. The depth of the trench etching can be determined by the device withstand voltage.

[0136] It should be understood that the first and second grooves mentioned above are interconnected integral grooves, the difference being their widths.

[0137] Polysilicon deposition is then performed. In a specific implementation, the shielding gate 100 is polysilicon deposited in the first trench and the second trench to form the shielding gate 100. Then the shielding gate 100 is etched to form the enclosed shielding gate 100. Since each silicon mesa region 200 is surrounded by the trench, the enclosed shielding gate 100 formed can surround each silicon mesa region 200.

[0138] Furthermore, a field oxide layer 401 is grown within the trench, and a shielding grid 100 setting area exists within the field oxide layer 401.

[0139] It should be noted that by growing a field oxide layer 401 in the above-mentioned trench, a charge balance effect is provided together with the subsequent shielding gate 100, wherein the thickness of the oxide layer 400 can be determined by the required withstand voltage.

[0140] It is understood that the area where the shielding gate 100 is set can be the area where polycrystalline deposition of the shielding gate 100 is performed to form the area enclosing the shielding gate 100 and the area where the shielding gate 100 is led out.

[0141] refer to Figure 16 This explanation does not limit the scope of this solution. Figure 16 This is a schematic diagram of the planar structure of the field oxide layer 401 grown in an embodiment of the method for fabricating the enclosed shielded gate 100 field-effect transistor of the present invention. Figure 16 In the process, the field oxide layer 401 is grown at the edge or sidewall of the first and second trenches. In order to ensure the successful deposition of the subsequent shielding gate 100, the thickness of the field oxide layer 401 needs to be controlled and gaps are left, that is, the field oxide layer 401 is formed around each silicon mesa region 200.

[0142] refer to Figure 17 This explanation does not limit the scope of this solution. Figure 17 This is a schematic diagram of the growth of the field oxide layer 401 in the first cross-section of an embodiment of the fabrication method of the enclosed shielded gate 100 field-effect transistor of the present invention. Figure 17 In the first trench between each adjacent silicon mesa region 200, the field oxide layer 401 is grown on the sidewall or edge of the first trench. By controlling the thickness of the field oxide layer 401, the field oxide layer 401 does not completely cover the first trench, leaving a certain gap for subsequent polycrystalline deposition of the shielding gate 100.

[0143] For ease of understanding, please refer to Figure 18 This explanation does not limit the scope of this solution. Figure 18 This is a schematic diagram of the growth of the field oxide layer 401 in the third cross-section of an embodiment of the fabrication method of the enclosed shielded gate 100 field-effect transistor of the present invention. Figure 18In the second trench between each adjacent silicon mesa region 200, the field oxide layer 401 is grown on the sidewall or edge of the second trench. By controlling the thickness of the field oxide layer 401, the field oxide layer 401 does not completely cover the first trench, leaving a certain gap for subsequent polycrystalline deposition of the shielding gate 100.

[0144] It should be noted that the gaps left by the mid-field oxide layer 401 in the first and second trenches can be the area for setting the shielding grid 100.

[0145] In a specific implementation, the shielding gate 100 is polycrystalline deposited in the area where the shielding gate 100 is set, that is, in the gap formed by the field oxide layer 401 in the first trench and the second trench, so that the shielding gate 100 formed is located in the gap formed by the field oxide layer 401, that is, the field oxide layer 401 covers the shielding gate 100 formed.

[0146] For ease of understanding, please refer to Figure 19 This explanation does not limit the scope of this solution. Figure 19 This is a schematic diagram of the planar structure of the polycrystalline deposition of the shielding gate 100 in an embodiment of the fabrication method of the enclosed shielding gate 100 field-effect transistor of the present invention. Figure 19 In this process, since a shielding gate 100 is formed in the trench, the shielding gate 100 replaces the original area of ​​the trench, forming a structure in which the shielding gate 100 surrounds the silicon mesa region 200. In this process, the presence of the field oxide layer 401 effectively isolates the shielding gate 100 and the silicon mesa region 200.

[0147] For ease of understanding, please refer to Figure 20 This explanation does not limit the scope of this solution. Figure 20 This is a schematic diagram of the polycrystalline deposition of the shielding gate 100 in the first cross-section of an embodiment of the fabrication method of the enclosed shielding gate 100 field-effect transistor of the present invention. Figure 20 In the first trench between each adjacent silicon mesa region 200, a shielding gate 100 is polycrystalline deposited in the gap formed by the field oxide layer 401, thereby forming the shielding gate 100 in the gap.

[0148] For ease of understanding, please refer to Figure 21 This explanation does not limit the scope of this solution. Figure 21 This is a schematic diagram of the polycrystalline deposition of the shielding gate 100 in the third cross-section of an embodiment of the fabrication method of the enclosed shielding gate 100 field-effect transistor of the present invention. Figure 21 In the second trench between each adjacent silicon mesa region 200, a shielding gate 100 is polycrystalline deposited in the gap formed by the field oxide layer 401, thereby forming the shielding gate 100 in the gap.

[0149] It should be understood that the shielding gate 100 at this time surrounds each individual silicon mesa region 200. This enclosed layout provides a three-dimensional charge depletion effect, with an optimized electric field distribution, providing higher withstand voltage and lower on-resistance.

[0150] For ease of understanding, please refer to Figure 22 This explanation does not limit the scope of this solution. Figure 22 This is a schematic diagram of the planar structure of the shielding gate 100 etched in an embodiment of the method for fabricating the enclosed shielding gate 100 field-effect transistor of the present invention. Figure 22 In order to form the enclosing shielding grid 100 and the lead-out shielding grid 100, the shielding grid 100 in the aforementioned trench needs to be etched. Figure 22 The shielding grid 100 that is independently led out can be the contact structure 102 mentioned above, and the shielding grids 100 connected together below the contact structure 102 can be the field plate structure 101.

[0151] It should be noted that, since the trenches between the aforementioned silicon mesa regions 200 are divided into a first trench and a second trench, the trench includes both a first trench and a second trench. The width of the first trench is less than the width of the second trench. Step S203 includes:

[0152] For ease of understanding, please refer to Figure 23 This explanation does not limit the scope of this solution. Figure 23 This is a schematic diagram of the etching of the shielding gate 100 in the first cross-section of an embodiment of the method for fabricating the enclosed shielding gate 100 field-effect transistor of the present invention. Figure 23 In the first trench between each silicon mesa region 200, the area above the shielding gate 100 is etched to form a field plate structure 101, wherein this step retains the field oxide layer 401 in the upper region.

[0153] It should be understood that the upper region of the field plate structure 101 described above can be used to form subsequent interconnect gates 302.

[0154] It should be noted that, since the second trench needs to form the lead-out shielding gate 100, and the shielding gate 100 has already filled the second trench before etching, the lead-out shielding gate 100 can be formed by etching a small portion on the left and right sides of the upper region of the shielding gate 100, leaving the middle region.

[0155] For ease of understanding, please refer to Figure 24 This explanation does not limit the scope of this solution. Figure 24 This is a schematic diagram of the etching of the shielding gate 100 in the third cross-section of an embodiment of the method for fabricating the enclosed shielding gate 100 field-effect transistor of the present invention. Figure 24In the second trench between each silicon mesa region 200, a small portion of the left end and a small portion of the right end of the area above the shielding gate 100 are etched to form the contact structure 102. Simultaneously, the field plate structure 101 is located below the shielding gate 100, thus placing the contact structure 102 above the field plate structure 101. This step preserves the field oxide layer 401 in the upper region.

[0156] It should be understood that the region formed between the contact structure 102 and the field oxide layer 401 can be used to form the subsequent interconnect gate 302.

[0157] In a specific implementation, the gate, body, and source regions are distributed in the structure of the silicon mesa region 200, the field plate structure 101, the contact structure 102, and the trench of the field oxide layer 401, thereby forming an enclosed shielded gate 100 field-effect transistor.

[0158] In a specific implementation, in the structure formed by the silicon mesa region 200 and the enclosing shielding gate 100, the field oxide layer 401 in the first trench and the second trench is etched simultaneously, and the etching stops when it reaches the surface of the field plate structure 101.

[0159] For ease of understanding, please refer to Figure 25 This explanation does not limit the scope of this solution. Figure 25 This is a schematic diagram of the etching of the field oxide layer 401 in the first cross-section of an embodiment of the fabrication method of the enclosed shielded gate 100 field-effect transistor of the present invention. Figure 25 In the process, the field oxide layer 401 is etched in the first trench between each silicon mesa region 200, and the etching stops when it reaches the surface of the field plate structure 101, so that the field oxide layer 401 above the field plate structure 101 is etched away.

[0160] For ease of understanding, please refer to Figure 26 This explanation does not limit the scope of this solution. Figure 26 This is a schematic diagram of the etching of the field oxide layer 401 in the third cross-section of an embodiment of the fabrication method of the enclosed shielded gate 100 field-effect transistor of the present invention. Figure 26 In the process, the field oxide layer 401 is etched in the second trench between each silicon mesa region 200, and the etching stops when it reaches the surface of the field plate structure 101, so that the field oxide layer 401 above the field plate structure 101 is etched away.

[0161] It should be noted that the gate oxide layer 402 and the field oxide layer 401 mentioned above are both oxide layers 400 with the same structure, the difference being their different positions.

[0162] In a specific implementation, the gate oxide layer 402 is grown by a thermo-oxidative process, so that the gate oxide layer 402 is formed on the field plate structure 101.

[0163] For ease of understanding, please refer to Figure 27 This explanation does not limit the scope of this solution. Figure 27 This is a schematic diagram of the growth of the gate oxide layer 402 in the first cross-section of an embodiment of the fabrication method of the enclosed shielded gate 100 field-effect transistor of the present invention. Figure 27 In the first trench between each silicon mesa region 200, a gate oxide layer 402 is grown above the field plate structure 101. At the same time, the gate oxide layer 402 does not completely fill the area above the field plate structure 101, but leaves a certain gap to form the subsequent control gate 300 electrode.

[0164] For ease of understanding, please refer to Figure 28 This explanation does not limit the scope of this solution. Figure 28 This is a schematic diagram of the growth of the gate oxide layer 402 in the third cross-section of an embodiment of the fabrication method of the enclosed shielded gate 100 field-effect transistor of the present invention. Figure 28 In the second trench between each silicon mesa region 200, a gate oxide layer 402 is grown above the field plate structure 101. At the same time, the gate oxide layer 402 does not completely fill the area above the field plate structure 101, but leaves a certain gap on both sides of the contact structure 102 to form the subsequent control gate 300 electrode.

[0165] For ease of understanding, please refer to Figure 29 This explanation does not limit the scope of this solution. Figure 29 This is a schematic diagram of the polycrystalline deposition of the control gate 300 electrode in the first cross-section of an embodiment of the fabrication method of the enclosed shielded gate 100 field-effect transistor of the present invention. Figure 29 In the first trench between each silicon mesa region 200, a gate polysilicon deposition is performed in the gap left by the gate oxide layer 402 above the field plate structure 101, so that the formed control gate 300 electrode 301 is covered by the gate oxide layer 402.

[0166] For ease of understanding, please refer to Figure 30 This explanation does not limit the scope of this solution. Figure 30 This is a schematic diagram of the polycrystalline deposition of the interconnect gate 302 in the third cross-section of an embodiment of the fabrication method of the enclosed shielded gate 100 field-effect transistor of the present invention. Figure 30 In the second trench between each silicon mesa region 200, a gate polysilicon deposition is performed above the field plate structure 101 and in the gap left by the gate oxide layer 402 on both sides of the contact structure 102, so that the formed control gate 300 electrode 301 is covered by the gate oxide layer 402.

[0167] The subsequent fabrication of conventional P-type body region 202 ion implantation, N-type source region 2021 ion implantation, ILD layer 500, contact holes, and source metal 600 will not be elaborated here.

[0168] In summary, this application provides a shielded-gate field-effect transistor and its fabrication method. The shielded-gate field-effect transistor includes a silicon mesa region, a shielding gate, a control gate, and an oxide layer. Both the shielding gate and the control gate surround the silicon mesa region, and are spaced apart. The oxide layer fills the spaces between the shielding gate, the control gate, and the silicon mesa region. Part of the shielding gate is located below the control gate, while another part of the control gate is independently led out. On one hand, because the shielding gate and the control gate surround the silicon mesa region in the shielded-gate field-effect transistor provided in this application, a three-dimensional charge depletion effect is provided, resulting in a more optimized electric field modulation effect, thereby further improving the breakdown voltage and reducing the on-resistance. On the other hand, since some shielding gates are independently led out, the polycrystalline shielding gate can be directly connected to the source metal, reducing the parasitic resistance of the shielding gate, achieving a more uniform shielding gate potential, improving avalanche capability, and suppressing gate punch-through. Furthermore, the control gates can be effectively interconnected, simplifying the layout, achieving more uniform switching characteristics, reducing power consumption, and suppressing local current concentration.

[0169] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0170] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A type of enclosed shielded grid field-effect transistor, characterized in that, The enclosed shielded field-effect transistor includes a silicon mesa region, a shielding gate, a control gate, and an oxide layer. The shielding gate and the control gate are both disposed around the silicon mesa region. The shielding gate, the control gate, and the silicon mesa region are all spaced apart, and the oxide layer fills the spaces between the shielding gate, the control gate, and the silicon mesa region. Part of the shielding grid is located below the control grid, while another part of the shielding grid is led out independently.

2. The enclosed shielded grid field-effect transistor as described in claim 1, characterized in that, The shielding grid includes a field plate structure and a contact structure. The field plate structure is connected to the contact structure. The field plate structure is located below the control grid, and the contact structures are spaced apart around the silicon mesa region.

3. The enclosed shielded grid field-effect transistor as described in claim 2, characterized in that, The surface of the contact structure is flush with the surface of the control gate.

4. The enclosed shielded grid field-effect transistor as described in claim 2, characterized in that, The number of contact structures is multiple, and the multiple contact structures form a regular polygon around the silicon mesa region.

5. The enclosed shielded grid field-effect transistor as described in claim 2, characterized in that, The enclosed shielded gate field-effect transistor further includes an ILD layer and a source metal. The ILD layer is provided with a first contact hole at a position opposite to the contact structure. The first contact hole is filled with contact metal, and the contact structure is connected to the source metal through the first contact hole.

6. The enclosed shielded grid field-effect transistor as described in claim 1, characterized in that, The silicon mesa region includes a drift region, a P-type body region, and an N-type source region arranged layer by layer from bottom to top. The enclosed shielded gate field-effect transistor also includes an ILD layer and a source metal. The ILD layer has a second contact hole extending to the P-type body region. The second contact hole is filled with contact metal. The P-type body region is connected to the source metal through the second contact hole.

7. The enclosed shielded grid field-effect transistor as described in claim 1, characterized in that, The silicon mesa area is configured as a regular polygon or a circle.

8. A method for manufacturing an enclosed shielded field-effect transistor, characterized in that, The method for manufacturing an enclosed shielded field-effect transistor as described in any one of claims 1 to 7 comprises: Provide an epitaxial layer; Based on the epitaxial layer, trenches are etched, leaving multiple independent silicon mesa regions; A shielding gate, a control gate, and an oxide layer are fabricated based on the trench. The shielding gate and the control gate are both disposed around the silicon mesa region. The shielding gate, the control gate, and the silicon mesa region are all spaced apart, and the oxide layer fills the spaces between the shielding gate, the control gate, and the silicon mesa region.

9. The method for manufacturing an enclosed shielded field-effect transistor as described in claim 8, characterized in that, The steps for fabricating the shielding grid, control grid, and oxide layer based on the trench include: Based on the oxygen layer of the trench growth field; Polycrystalline silicon is deposited based on the trenches; The deposited polysilicon is etched to form a shielding gate; Etch away any excess field oxide layer; Based on the growth of a gate oxide layer within the trench; Polysilicon is deposited within the trench to form a control gate.

10. The method for manufacturing an enclosed shielded field-effect transistor as described in claim 9, characterized in that, After the steps of depositing polysilicon within the trench and forming a control gate, the method further includes: P-type ion implantation is performed in the silicon mesa region to form a P-type body region; N-type ion implantation is performed on the surface of the P-type body region to form an N-type source region; An ILD layer is grown on the surface of the N-type source region, the shielding gate, and the control gate; The ILD layer is etched to form a first contact hole and a second contact hole, and contact metal is deposited based on the first contact hole and the second contact hole; wherein, the contact metal of the first contact hole contacts the shielding gate, and the contact metal of the second contact hole contacts the P-type body region. Source metal is deposited on the surface of the ILD layer.

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