Transistor and preparation method thereof

Abstract

The invention provides a transistor and a preparation method thereof. The transistor comprises a channel layer, a barrier layer, a P-type gallium nitride layer, a grid electrode and a dielectric layer, the channel layer, the barrier layer and the P-type gallium nitride layer are sequentially stacked, the P-type gallium nitride layer is of a step structure, the step structure is provided with a step top surface and a step bottom surface, the grid electrode is located on the step top surface, and the dielectric layer covers the barrier layer, the P-type gallium nitride layer and the grid electrode. The P-type gallium nitride layer is of a step structure, so that electric field distribution can be optimized, current on the top surface of the step is reduced, influence of a surface state on channel current is reduced, and grid leakage is reduced. The gate is located on the top surface of the step, and the step structure can transfer an electric field peak value from the gate edge to the region of the bottom surface of the step, thereby reducing the electric field intensity of the gate edge, effectively suppressing the electric field peak effect of the gate edge, improving the breakdown voltage of the Schottky barrier of the P-type gallium nitride layer, and improving the withstand voltage of the gate. The reliability of the transistor is improved by reducing electric leakage and improving withstand voltage.

Description

Technical Field

[0001] The present disclosure relates to the field of light-emitting power devices, and in particular to a transistor and a method for preparing the same. Background Art

[0002] Transistors are widely used in wireless communications, RF amplification, satellite communications, radar systems, and efficient power management due to their excellent power handling capabilities and low noise characteristics.

[0003] The related technology provides a transistor, which includes a channel layer, a barrier layer, a P-type gallium nitride layer, a gate and a dielectric layer. The channel layer, the barrier layer, the P-type gallium nitride layer and the gate are stacked in sequence, and the dielectric layer covers the barrier layer, the P-type gallium nitride layer and the gate.

[0004] In related technologies, how to reduce transistor gate leakage is a focus of current research. Summary of the invention

[0005] The embodiments of the present disclosure provide a transistor and a method for manufacturing the same, which can significantly improve the gate leakage of the transistor and enhance the stability of the transistor. The technical solution is as follows:

[0006] In one aspect, a transistor is provided, comprising:

[0007] Channel layer, barrier layer, P-type gallium nitride layer, gate and dielectric layer;

[0008] The channel layer, the barrier layer and the P-type gallium nitride layer are stacked in sequence, the P-type gallium nitride layer is in a step structure, the step structure has a step top surface and a step bottom surface, the gate is located on the step top surface, and the dielectric layer covers the barrier layer, the P-type gallium nitride layer and the gate.

[0009] Optionally, the step structure is an annular step structure arranged along an edge of the P-type gallium nitride layer.

[0010] Optionally, the distance between the top surface of the step and the bottom surface of the step is 40 to 90 nm.

[0011] Optionally, the distance between the bottom surface of the step and the surface of the barrier layer is 5 to 20 nm.

[0012] Optionally, the transistor further includes an ion implantation layer, which is obtained by performing ion implantation on the P-type gallium nitride layer, the ion implantation layer is located at the bottom surface of the step, and the dielectric layer also covers the ion implantation layer.

[0013] Optionally, the ion implantation layer has a thickness of 40 to 95 nm.

[0014] In another aspect, a method for manufacturing a transistor includes:

[0015] manufacturing a channel layer;

[0016] forming a barrier layer on the channel layer;

[0017] A P-type gallium nitride layer and a gate are fabricated on the barrier layer, wherein the P-type gallium nitride layer has a step structure, the step structure has a step top surface and a step bottom surface, and the gate is located on the step top surface;

[0018] A dielectric layer is manufactured, wherein the dielectric layer covers the barrier layer, the P-type gallium nitride layer and the gate.

[0019] Optionally, forming a P-type gallium nitride layer and a gate on the barrier layer includes:

[0020] Sequentially forming a P-type gallium nitride film layer and a gate metal layer on the barrier layer;

[0021] Making a first mask pattern on the gate metal layer;

[0022] Performing a patterning process on the gate metal layer under the shielding of the first mask pattern to obtain the gate;

[0023] Performing ion implantation on the P-type gallium nitride film layer so that the upper portion of the P-type gallium nitride film layer becomes an ion implantation film layer;

[0024] forming a second mask pattern on the first mask pattern;

[0025] Performing patterning on the P-type gallium nitride film layer and the ion implantation film layer under the shielding of the second mask pattern to obtain the P-type gallium nitride layer and the ion implantation layer located on the step bottom surface of the P-type gallium nitride layer;

[0026] The first mask pattern and the second mask pattern are removed.

[0027] Optionally, forming a P-type gallium nitride layer and a gate on the barrier layer includes:

[0028] Sequentially forming a P-type gallium nitride film layer and a gate metal layer on the barrier layer;

[0029] Making a first mask pattern on the gate metal layer;

[0030] Performing a patterning process on the gate metal layer under the shielding of the first mask pattern to obtain the gate;

[0031] forming a second mask pattern on the first mask pattern;

[0032] Performing patterning on the P-type gallium nitride film layer under the shielding of the second mask pattern to obtain the P-type gallium nitride layer;

[0033] The first mask pattern and the second mask pattern are removed.

[0034] Optionally, when the P-type gallium nitride film layer is subjected to ion implantation, the depth of the ion implantation is 40 to 95 nm.

[0035] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0036] In the disclosed embodiment, the P-type gallium nitride layer has a step structure, which can optimize the electric field distribution, reduce the current on the top of the step, and reduce the influence of the surface state on the channel current, thereby reducing gate leakage. The gate is located on the top of the step, and the step structure can transfer the electric field peak from the gate edge to the area on the bottom of the step, thereby reducing the electric field strength at the gate edge, making the electric field distribution more uniform, effectively suppressing the electric field peak effect at the gate edge, and increasing the breakdown voltage of the Schottky barrier of the P-type gallium nitride layer, thereby increasing the gate withstand voltage. By reducing leakage and increasing withstand voltage, the reliability of the transistor is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 It is a structural schematic diagram of a transistor provided by the related technology;

[0039] Figure 2 is a schematic structural diagram of a transistor provided by an embodiment of the present disclosure;

[0040] Figure 3 is a schematic structural diagram of a transistor provided by an embodiment of the present disclosure;

[0041] Figure 4 is a flow chart of a transistor manufacturing method provided by an embodiment of the present disclosure;

[0042] Figure 5 is a flow chart of another transistor manufacturing method provided by an embodiment of the present disclosure;

[0043] Figure 6 is a transistor structure diagram during a manufacturing process provided by an embodiment of the present disclosure;

[0044] Figure 7is a transistor structure diagram during a manufacturing process provided by an embodiment of the present disclosure;

[0045] Figure 8 is a transistor structure diagram during a manufacturing process provided by an embodiment of the present disclosure;

[0046] Fig. 9 is a transistor structure diagram during a manufacturing process provided by an embodiment of the present disclosure;

[0047] Fig.10 is a transistor structure diagram during a manufacturing process provided by an embodiment of the present disclosure;

[0048] Fig.11 is a transistor structure diagram during a manufacturing process provided by an embodiment of the present disclosure;

[0049] Fig.12 is a transistor structure diagram during a manufacturing process provided by an embodiment of the present disclosure;

[0050] Fig.13 is a transistor structure diagram during a manufacturing process provided by an embodiment of the present disclosure;

[0051] Fig.14 is a transistor structure diagram during a manufacturing process provided by an embodiment of the present disclosure;

[0052] Fig.15 is a flow chart of another transistor manufacturing method provided by an embodiment of the present disclosure;

[0053] Fig.16 is a transistor structure diagram during a manufacturing process provided by an embodiment of the present disclosure;

[0054] Fig.17 is a transistor structure diagram during a manufacturing process provided by an embodiment of the present disclosure;

[0055] Fig.18 It is a transistor structure diagram during a manufacturing process provided by an embodiment of the present disclosure.

[0056] The reference numerals are as follows:

[0057] 100: substrate; 101: channel layer; 102: barrier layer; 103: P-type gallium nitride layer; 104: gate; 105: dielectric layer; 106: ion implantation layer; 107: source; 108: drain; 109: buffer layer;

[0058] 201: a first mask layer; 202: a second mask layer;

[0059] 1001: top surface of step; 1002: bottom surface of step;

[0060] 1030: P-type gallium nitride film layer; 1040: gate metal layer; 1060: ion implantation film layer; 2010: first mask pattern; 2020: second mask pattern. DETAILED DESCRIPTION

[0061] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0062] At present, gallium nitride enhanced high mobility (E-mode HEMT) usually makes a P-type gallium nitride layer on the barrier layer to deplete the two-dimensional electron gas (2DEG). In order to reduce process costs, a self-aligned mode is usually used to obtain the gate, that is, a gate layer is grown on the P-type gallium nitride layer, and then the gate is patterned to be consistent in shape and size with the P-type gallium nitride layer. However, there is a leakage problem when the gate and the side of the P-type gallium nitride layer are flush. To solve the leakage problem, related technologies use dielectric intercalation technology, such as Figure 1 As shown, after etching the gate 103 and the P-type gallium nitride layer 104, a dielectric layer 105 is deposited to reduce leakage. However, this method only increases the distance of the side leakage path and has limited effect on reducing leakage.

[0063] Figure 2 is a schematic diagram of the structure of a transistor provided by an embodiment of the present disclosure. Figure 2 The transistor includes: a channel layer 101, a barrier layer 102, a P-type gallium nitride layer 103, a gate 104 and a dielectric layer 105.

[0064] Among them, the channel layer 101, the barrier layer 102 and the P-type gallium nitride layer 103 are stacked in sequence, the P-type gallium nitride layer 103 has a step structure, and the step structure has a step top surface 1001 and a step bottom surface 1002. The gate 104 covers the step top surface 1002 of the P-type gallium nitride layer 103, and the dielectric layer 105 covers the barrier layer 102, the P-type gallium nitride layer 103 and the gate 104.

[0065] In the disclosed embodiment, the P-type gallium nitride layer has a step structure, which can optimize the electric field distribution, reduce the current on the top of the step, and reduce the influence of the surface state on the channel current, thereby reducing gate leakage. The gate is located on the top of the step, and the step structure can transfer the electric field peak from the gate edge to the area on the bottom of the step, thereby reducing the electric field strength at the gate edge, making the electric field distribution more uniform, effectively suppressing the electric field peak effect at the gate edge, and increasing the breakdown voltage of the Schottky barrier of the P-type gallium nitride layer, thereby increasing the gate withstand voltage. By reducing leakage and increasing withstand voltage, the reliability of the transistor is improved.

[0066] In the embodiment of the present disclosure, the step structure is an annular step structure arranged along the edge of the P-type gallium nitride layer 103 .

[0067] It should be noted that the ring shape here can be a circular ring, a rectangular ring, or other ring shapes.

[0068] In this implementation, the annular step structure arranged along the edge can optimize the electric field distribution to the greatest extent, reduce the current on the top surface of the step, effectively block the current, and reduce gate leakage.

[0069] In other embodiments, the step structure may be a half ring, or may be composed of multiple sections.

[0070] In the embodiment of the present disclosure, the distance between the step top surface 1001 and the step bottom surface 1002 is 40-90 nm.

[0071] The distance between the step top surface 1001 and the step bottom surface 1002 is also the height of the step.

[0072] In this implementation, the step height of the above value will neither cause the P-type GaN layer below the step to be too thin, thereby affecting the consumption of the two-dimensional electron gas by the P-type GaN layer; nor will it affect the suppression of the gate edge electric field peak effect due to the step height being too small.

[0073] Exemplarily, the distance between the step top surface 1001 and the step bottom surface 1002 is 60 nm.

[0074] In the embodiment of the present disclosure, the distance between the step bottom surface 1002 and the surface of the barrier layer 102 is 5-20 nm.

[0075] The distance between the bottom surface 1002 of the step and the surface of the barrier layer 102 is also the width of the step.

[0076] In this implementation, by using the step width of the above value, the distance of the leakage path on the side of the P-GaN layer can be increased, thereby reducing leakage.

[0077] Exemplarily, the distance between the step bottom surface 1002 and the surface of the barrier layer 102 is 10 nm.

[0078] In the embodiment of the present disclosure, the thickness of the P-type gallium nitride layer 103 may be 70-100 nm.

[0079] The thickness here refers to the entire thickness of the P-type gallium nitride layer 103 .

[0080] In this implementation, the thickness of the P-type gallium nitride layer 103 can provide sufficient thickness support for forming a step structure, and will not affect the overall size due to excessive thickness.

[0081] Exemplarily, the thickness of the P-type gallium nitride layer 103 is 80 nm.

[0082] In the embodiment of the present disclosure, the P-type gallium nitride layer 103 may be a P-type gallium nitride layer doped with Mg, Zn or Ca.

[0083] In this implementation, the above-mentioned ion doping can effectively increase the hole concentration and conductivity of the P-type gallium nitride layer and enhance the device performance.

[0084] Exemplarily, the P-type gallium nitride layer 103 may be a Mg-doped P-type gallium nitride layer.

[0085] In the embodiment of the present disclosure, the hole concentration of the P-type gallium nitride layer 103 can be 0.8×10 17 ~3×10 17 cm -3 .

[0086] In this implementation, the hole concentration is not too high to reduce the carrier mobility, nor too low to increase the resistance.

[0087] For example, the hole concentration of the P-type gallium nitride layer 103 is 2×10 17 cm -3 .

[0088] Figure 3 is a schematic diagram of the structure of a transistor provided by an embodiment of the present disclosure. Figure 3 The transistor further includes: an ion implantation layer 106 , which is obtained by implanting ions into the P-type gallium nitride layer 103 , the ion implantation layer 106 is located at the bottom surface 1002 of the step, and the dielectric layer 105 also covers the ion implantation layer 106 .

[0089] In this implementation, the leakage channel is reduced by providing an ion implantation layer, thereby further reducing gate leakage.

[0090] In the embodiment of the present disclosure, the thickness of the ion implantation layer 106 may be 40-90 nm.

[0091] In this implementation, the ion implantation layer having the above-mentioned thickness can match the height of the step structure, thereby suppressing leakage current without affecting the overall size.

[0092] Illustratively, the thickness of the ion implantation layer 106 is 60 nm.

[0093] In the embodiment of the present disclosure, the inner edge of the ion implantation layer 106 is flush with the outer edge of the gate 104 , and the outer edge of the ion implantation layer 106 is flush with the outer edge of the P-type gallium nitride layer 103 .

[0094] In the embodiment of the present disclosure, the transistor may further include: a substrate 100 , a source 107 , a drain 108 and a buffer layer 109 .

[0095] The buffer layer 109 , the channel layer 101 , the barrier layer 102 and the P-type gallium nitride layer 103 are sequentially stacked on the substrate 100 , and the source 107 and the drain 108 are connected to the channel layer 101 through the dielectric layer 105 and the barrier layer 102 .

[0096] In the embodiment of the present disclosure, the substrate 100 may be any one of substrates such as a sapphire patterned substrate, a Si substrate, and a SiC substrate. The embodiment of the present disclosure does not limit the material of the substrate 100.

[0097] Exemplarily, the substrate 100 is a Si substrate. Si has good electrical conductivity and thermal conductivity, which can ensure that the chip has good heat dissipation.

[0098] Of course, in other embodiments, the transistor may not have a substrate, and the present disclosure is not limited to this.

[0099] In the embodiment of the present disclosure, the channel layer 101 may be a GaN channel layer, and the thickness of the channel layer 101 may be 200-300 nm.

[0100] Exemplarily, the thickness of the channel layer 101 is 250 nm.

[0101] In the embodiment of the present disclosure, the barrier layer 102 may be Al x Ga 1-x N barrier layers, wherein 0.1≤x≤0.3.

[0102] For example, the barrier layer 102 may be Al x Ga 1-x N barrier layers, where x=0.2.

[0103] In the embodiment of the present disclosure, the thickness of the barrier layer 102 may be 5-25 nm.

[0104] Exemplarily, the thickness of the barrier layer 102 is 15 nm.

[0105] In the embodiment of the present disclosure, the gate 104 may be a TiN gate.

[0106] In the embodiment of the present disclosure, the thickness of the gate 104 may be 80-120 nm.

[0107] By way of example, the thickness of the gate 104 may be 100 nm.

[0108] In the embodiment of the present disclosure, the dielectric layer 105 may be a dielectric layer made of SiO 2 , Si 3 N 4 or SiON.

[0109] Exemplarily, the dielectric layer 105 is a SiO 2 dielectric layer.

[0110] In the embodiment of the present disclosure, the thickness of the dielectric layer 105 may be 0.1-2 μm.

[0111] Exemplarily, the thickness of the dielectric layer 105 is 1 μm.

[0112] In the embodiment of the present disclosure, the source 107 may be a source made of Ti, Al or TiN.

[0113] Exemplarily, the source 107 is a TiN source.

[0114] In the embodiment of the present disclosure, the drain 108 may be a drain made of Ti, Al or TiN.

[0115] Exemplarily, the drain 108 is a TiN drain.

[0116] In the embodiment of the present disclosure, the buffer layer 109 may be a buffer layer made of AlN, AlGaN, InGaN or GaN.

[0117] Exemplarily, the buffer layer 109 is an AlN / AlGaN buffer layer.

[0118] In the embodiment of the present disclosure, the thickness of the buffer layer 109 may be 1.5-5 μm.

[0119] Exemplarily, the thickness of the buffer layer 109 is 3 μm.

[0120] Figure 4 is a flow chart of a transistor manufacturing method provided by an embodiment of the present disclosure. Figure 4 The method steps include:

[0121] S11 . Manufacturing a channel layer.

[0122] S12. Fabricating a barrier layer on the channel layer.

[0123] S13, manufacturing a P-type gallium nitride layer and a gate on the barrier layer, wherein the P-type gallium nitride layer has a step structure, the step structure has a step top surface and a step bottom surface, and the gate is located on the step top surface.

[0124] S14, manufacturing a dielectric layer, wherein the dielectric layer covers the barrier layer, the P-type gallium nitride layer and the gate.

[0125] In the disclosed embodiment, the P-type gallium nitride layer has a step structure, which can optimize the electric field distribution, reduce the current on the top of the step, and reduce the influence of the surface state on the channel current, thereby reducing gate leakage. The gate is located on the top of the step, and the step structure can transfer the electric field peak from the gate edge to the area on the bottom of the step, thereby reducing the electric field strength at the gate edge, making the electric field distribution more uniform, effectively suppressing the electric field peak effect at the gate edge, and increasing the breakdown voltage of the Schottky barrier of the P-type gallium nitride layer, thereby increasing the gate withstand voltage. By reducing leakage and increasing withstand voltage, the reliability of the transistor is improved.

[0126] Figure 5 is a flow chart of another transistor manufacturing method provided by an embodiment of the present disclosure. Figure 5 The method steps include:

[0127] S21, sequentially growing a buffer layer, a channel layer, a barrier layer and a P-type gallium nitride film layer on the substrate.

[0128] Figure 6 is a transistor structure diagram in a manufacturing process provided by an embodiment of the present disclosure. Figure 6 A buffer layer 109 , a channel layer 101 , a barrier layer 102 and a P-type gallium nitride film layer 1030 are sequentially stacked on the substrate 100 .

[0129] In the embodiment of the present disclosure, the substrate may be any one of a sapphire patterned substrate, a Si substrate, a SiC substrate and the like.

[0130] Exemplarily, the substrate is a Si substrate.

[0131] In one example, step S21 includes:

[0132] The first step is to make a buffer layer.

[0133] In the embodiment of the present disclosure, the buffer layer may be a buffer layer made of AlN, AlGaN, InGaN or GaN.

[0134] Exemplarily, the buffer layer is an AlN / AlGaN buffer layer.

[0135] In the embodiment of the present disclosure, the thickness of the buffer layer may be 1.5-5 μm.

[0136] Exemplarily, the thickness of the buffer layer is 3 μm.

[0137] The second step is to make the channel layer.

[0138] In the embodiment of the present disclosure, the channel layer may be a GaN channel layer, and the thickness of the channel layer may be 200-300 nm.

[0139] Exemplarily, the thickness of the channel layer is 250 nm.

[0140] The third step is to make the barrier layer.

[0141] In the embodiment of the present disclosure, the barrier layer may be Al x Ga 1-x N barrier layers, wherein 0.1≤x≤0.3.

[0142] For example, the barrier layer may be Al x Ga 1-x N barrier layers, where x=0.2.

[0143] In the embodiment of the present disclosure, the thickness of the barrier layer may be 5-25 nm.

[0144] Exemplarily, the thickness of the barrier layer is 15 nm.

[0145] The fourth step is to make the P gallium nitride film layer.

[0146] In the embodiment of the present disclosure, the thickness of the P-type gallium nitride film layer can be 70-100 nm, which can ensure that the thickness is sufficient when making the ion implantation layer or etching.

[0147] Exemplarily, the thickness of the P-type gallium nitride film layer is 80 nm.

[0148] In the embodiment of the present disclosure, the P-type gallium nitride film layer may be a P-type gallium nitride film layer doped with Mg, Zn or Ca.

[0149] In this implementation, the above-mentioned ion doping can effectively increase the hole concentration and conductivity of the P-type gallium nitride film layer and enhance the device performance.

[0150] Exemplarily, the P-type gallium nitride film layer may be a Mg-doped P-type gallium nitride film layer.

[0151] In the embodiment of the present disclosure, the hole concentration of the P-type gallium nitride film layer can be 0.8×10 17 ~3×10 17 cm -3 .

[0152] In this implementation, the hole concentration is not too high to reduce the carrier mobility, nor too low to increase the resistance.

[0153] For example, the hole concentration of the P-type gallium nitride film is 2×10 17 cm -3 .

[0154] S22, manufacturing a gate metal layer on the P-type gallium nitride film layer.

[0155] In the embodiment of the present disclosure, the gate metal layer may be a TiN gate metal layer.

[0156] In the disclosed embodiment, the thickness of the gate metal layer may be 80-120 nm.

[0157] Exemplarily, the thickness of the gate metal layer may be 100 nm.

[0158] S23, making a first mask pattern on the gate metal layer.

[0159] Exemplarily, S23 may include: manufacturing a first mask layer on the gate metal layer; and performing photolithography on the first mask layer to obtain a first mask pattern.

[0160] Among them, photolithography can include:

[0161] The first step is to form a photoresist mask layer on the first mask layer.

[0162] The second step is to expose and develop the photoresist mask layer.

[0163] Step 3: etching the first mask layer.

[0164] Step 4: remove the photoresist mask layer to obtain a first mask pattern.

[0165] Figure 7 is a transistor structure diagram in a manufacturing process provided by an embodiment of the present disclosure. Figure 7 , the gate metal layer 1040 covers the P-type gallium nitride layer 103 , and the first mask pattern 2010 covers the gate metal layer 1040 .

[0166] In the embodiment of the present disclosure, a plasma enhanced chemical vapor deposition (PECVD) first mask pattern is used.

[0167] In the embodiment of the present disclosure, the first mask pattern may be a SiO 2 layer.

[0168] S24, performing a patterning process on the gate metal layer under the shielding of the first mask pattern to obtain a gate.

[0169] Figure 8 is a transistor structure diagram in a manufacturing process provided by an embodiment of the present disclosure. Figure 8 , a patterning process is performed under the shielding of the first mask pattern 2010 to obtain the gate 104 .

[0170] In the disclosed embodiment, the angle of etching the gate metal layer is 75-90°.

[0171] Exemplarily, the angle at which the gate metal layer is etched is 80°.

[0172] S25, performing ion implantation treatment on the P-type gallium nitride film layer, so that the upper portion of the P-type gallium nitride film layer becomes an ion implantation film layer.

[0173] Fig. 9 is a transistor structure diagram in a manufacturing process provided by an embodiment of the present disclosure. Fig. 9 , a portion of the P-type gallium nitride film layer 1030 is processed to form an ion implantation film layer 1060 .

[0174] In the embodiment of the present disclosure, an ion implanter is used to implant ions into the P-type gallium nitride film layer to form an ion implantation film layer.

[0175] In the embodiment of the present disclosure, the implanted ions include He ions, F ions, C ions and N ions.

[0176] In the disclosed embodiment, the depth of ion implantation can be 40 to 95 nm. The above ion implantation depth is neither too thick, which causes the P-type gallium nitride film layer below the step to be too thin, thereby affecting the consumption of the two-dimensional electron gas by the P-type gallium nitride film layer; nor too thin, which affects the suppression of the peak effect of the electric field at the gate edge.

[0177] Exemplarily, the depth of ion implantation is 60 nm.

[0178] In the embodiment of the present disclosure, the thickness of the P-type gallium nitride film layer without ion implantation may be 5 nm to 20 nm.

[0179] By using the thickness of the above value, the distance of the leakage path on the side of the P-type gallium nitride can be increased, thereby reducing leakage.

[0180] Exemplarily, the thickness of the P-type gallium nitride film layer without ion implantation is 10 nm.

[0181] S26, making a second mask pattern on the first mask pattern.

[0182] Fig.10 is a transistor structure diagram in a manufacturing process provided by an embodiment of the present disclosure. Fig.10 The second mask pattern 2020 covers a portion of the ion implantation film layer 1060 and the sidewall of the gate 104 .

[0183] In the embodiment of the present disclosure, PECVD is used to manufacture the second mask pattern.

[0184] In the embodiment of the present disclosure, the second mask pattern may be a SiO 2 layer.

[0185] In the embodiment of the present disclosure, the thickness of the second mask pattern may be 50-150 nm.

[0186] Exemplarily, the thickness of the second mask pattern is 100 nm.

[0187] In one example, step S26 includes:

[0188] The first step is to form a second mask layer on the ion implantation film layer.

[0189] The second step is to perform patterning on the second mask layer to form a second mask pattern.

[0190] In the disclosed embodiment, an inductively coupled plasma etching (ICP) etcher is used to pattern the second mask layer.

[0191] In another example, the second mask layer is patterned using a first ICP etcher.

[0192] The third step is to perform patterning on the ion implanted film layer and the P-type gallium nitride film layer.

[0193] In the embodiment of the present disclosure, an ICP etcher is used to perform patterning on the ion implanted film layer and the P-type gallium nitride film layer.

[0194] In another example, a second ICP etcher is used to pattern the ion implantation film layer and the P-type gallium nitride film layer.

[0195] S27, performing patterning on the P-type gallium nitride film layer and the ion implantation film layer under the shielding of the second mask pattern to obtain a P-type gallium nitride layer and an ion implantation layer located on the step bottom surface of the P-type gallium nitride layer.

[0196] Fig.11 is a transistor structure diagram during a manufacturing process provided by an embodiment of the present disclosure. Fig.11 , the first mask pattern 2010 covers the gate 104 , and the second mask pattern 2020 covers the ion implantation layer 106 and the sidewall of the gate 104 .

[0197] S28, removing the first mask pattern and the second mask pattern.

[0198] Fig.12 is a transistor structure diagram during a manufacturing process provided by an embodiment of the present disclosure. Fig.12 The P-type gallium nitride layer 103 has a step structure, the gate 104 is on the step top surface 1001 of the P-type gallium nitride layer 103 , and the ion implantation layer 106 is on the step bottom surface 1002 of the P-type gallium nitride layer 103 .

[0199] In the embodiment of the present disclosure, wet etching with a high etching selectivity ratio is used to remove the first mask layer and the second mask layer.

[0200] In the embodiment of the present disclosure, the etching solution may be a buffered oxide etchant (BOE).

[0201] S29, manufacturing a dielectric layer, wherein the dielectric layer covers the barrier layer, the P-type gallium nitride layer and the gate.

[0202] Fig.13 is a transistor structure diagram in a manufacturing process provided by an embodiment of the present disclosure. Fig.13 The dielectric layer 105 covers the surfaces of the barrier layer 102 , the P-type gallium nitride layer 103 , the gate 104 and the ion implantation layer 106 .

[0203] In the embodiment of the present disclosure, the dielectric layer may be a dielectric layer made of SiO2, Si3N4 or SiON.

[0204] Exemplarily, the dielectric layer is a SiO2 dielectric layer.

[0205] In the embodiment of the present disclosure, the thickness of the dielectric layer may be 0.1-2 μm.

[0206] Exemplarily, the thickness of the dielectric layer is 1 μm.

[0207] In the embodiments of the present disclosure, atomic layer deposition (ALD) may be used to grow a stress regulating layer between deposited dielectric layers.

[0208] In the embodiment of the present disclosure, the stress regulating layer may be an AlN layer with a thickness of 1 to 5 nm.

[0209] Exemplarily, the stress regulating layer may be a 3 nm AlN layer.

[0210] S30, making a source electrode and a drain electrode.

[0211] See again Figure 3 The source 107 and the drain 108 are connected to the channel layer 101 through the dielectric layer 105 and the barrier layer 102 .

[0212] In one example, step S30 includes:

[0213] In the first step, the dielectric layer and the channel layer are etched to form a through hole.

[0214] The second step is to make the source and drain.

[0215] In the embodiment of the present disclosure, the source electrode may be a source electrode made of Ti, Al or TiN.

[0216] Illustratively, the source is a TiN source.

[0217] In the embodiment of the present disclosure, the drain may be a drain made of Ti, Al or TiN.

[0218] Illustratively, the drain is a TiN drain.

[0219] Fig.14 is a transistor structure diagram during a manufacturing process provided by an embodiment of the present disclosure. Fig.14 The source 107 and the drain 108 are connected to the barrier layer 102 through the dielectric layer 105 .

[0220] In another example, only the dielectric layer may be etched, and the source and the drain are connected to the barrier layer.

[0221] Fig.15 is a flow chart of another transistor manufacturing method provided by an embodiment of the present disclosure. Fig.15 , this method is similar to Figure 5 The main difference is that no ion implantation layer is made. The method comprises the following steps:

[0222] S31 , sequentially forming a P-type gallium nitride film layer and a gate metal layer on the barrier layer.

[0223] This step can refer to step S21 to step S22, which will not be repeated here.

[0224] S32, making a first mask pattern on the gate metal layer.

[0225] This step may refer to step S23 and will not be described in detail here.

[0226] S33, performing patterning on the gate metal layer under the shielding of the first mask pattern to obtain a gate.

[0227] This step may refer to step S24 and will not be described in detail here.

[0228] Fig.16 is a transistor structure diagram during a manufacturing process provided by an embodiment of the present disclosure. Fig.16 The P-type gallium nitride film layer 1030 is etched to have a step structure.

[0229] Exemplarily, the etching depth of the P-type gallium nitride film layer may be 40-95 nm, and the thickness of the unetched P-type gallium nitride film layer may be 5-20 nm.

[0230] S34, making a second mask pattern on the first mask pattern.

[0231] This step may refer to step S26 and will not be described in detail here.

[0232] Fig.17is a transistor structure diagram in a manufacturing process provided by an embodiment of the present disclosure. Fig.17 The second mask pattern 2020 covers a portion of the P-type gallium nitride film layer 1030 and the first mask pattern 2010 .

[0233] S35 , performing patterning on the P-type gallium nitride film layer under the shielding of the second mask pattern to obtain the P-type gallium nitride layer.

[0234] This step does not include an ion implantation layer, and the second mask pattern is directly produced on the gallium nitride film layer and the first mask pattern.

[0235] S36, removing the first mask pattern and the second mask pattern.

[0236] Fig.18 is a transistor structure diagram in a manufacturing process provided by an embodiment of the present disclosure. Fig.18 The P-type gallium nitride layer 103 has a step structure, and the gate 104 is on the top surface of the step of the P-type gallium nitride layer 103 .

[0237] S37, manufacturing a dielectric layer, wherein the dielectric layer covers the barrier layer, the P-type gallium nitride layer and the gate.

[0238] This step can refer to step S29 and will not be repeated here.

[0239] S38, making a source and a drain.

[0240] This step may refer to step S30 and will not be described in detail here.

[0241] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A transistor, characterized in that: The transistor comprises: a channel layer (101), a barrier layer (102), a P-type gallium nitride layer (103), a gate (104) and a dielectric layer (105); The channel layer (101), the barrier layer (102) and the P-type gallium nitride layer (103) are stacked in sequence, the P-type gallium nitride layer (103) is in a step structure, the step structure has a step top surface (1001) and a step bottom surface (1002), the gate (104) is located on the step top surface, and the dielectric layer (105) covers the barrier layer (102), the P-type gallium nitride layer (103) and the gate (104).

2. The transistor according to claim 1, characterized in that The step structure is an annular step structure arranged along the edge of the P-type gallium nitride layer (103).

3. The transistor according to claim 1, characterized in that The distance between the step top surface (1001) and the step bottom surface (1002) is 40 to 90 nm.

4. The transistor according to claim 1, characterized in that The distance between the bottom surface of the step (1002) and the surface of the barrier layer (102) is 5 to 20 nm.

5. The transistor according to any one of claims 1 to 4, characterized in that: The transistor further comprises an ion implantation layer (106), wherein the ion implantation layer (106) is obtained by implanting ions into the P-type gallium nitride layer (103), the ion implantation layer (106) is located at the bottom surface of the step, and the dielectric layer (105) also covers the ion implantation layer (106).

6. The transistor according to claim 5, characterized in that The thickness of the ion implantation layer (106) is 40-95 nm.

7. A method for preparing a transistor, characterized in that: The transistor preparation method comprises: manufacturing a channel layer; forming a barrier layer on the channel layer; A P-type gallium nitride layer and a gate are fabricated on the barrier layer, wherein the P-type gallium nitride layer has a step structure, the step structure has a step top surface and a step bottom surface, and the gate is located on the step top surface; A dielectric layer is manufactured, wherein the dielectric layer covers the barrier layer, the P-type gallium nitride layer and the gate.

8. The transistor manufacturing method according to claim 7, characterized in that: Fabricating a P-type gallium nitride layer and a gate on the barrier layer, comprising: Sequentially forming a P-type gallium nitride film layer and a gate metal layer on the barrier layer; Making a first mask pattern on the gate metal layer; Performing a patterning process on the gate metal layer under the shielding of the first mask pattern to obtain the gate; Performing ion implantation on the P-type gallium nitride film layer, so that the upper portion of the P-type gallium nitride film layer becomes an ion implantation film layer; forming a second mask pattern on the first mask pattern; Performing patterning on the P-type gallium nitride film layer and the ion implantation film layer under the shielding of the second mask pattern to obtain the P-type gallium nitride layer and the ion implantation layer located on the step bottom surface of the P-type gallium nitride layer; The first mask pattern and the second mask pattern are removed.

9. The transistor manufacturing method according to claim 7, characterized in that: Fabricating a P-type gallium nitride layer and a gate on the barrier layer, comprising: Sequentially forming a P-type gallium nitride film layer and a gate metal layer on the barrier layer; Making a first mask pattern on the gate metal layer; Performing a patterning process on the gate metal layer under the shielding of the first mask pattern to obtain the gate; forming a second mask pattern on the first mask pattern; Performing patterning on the P-type gallium nitride film layer under the shielding of the second mask pattern to obtain the P-type gallium nitride layer; The first mask pattern and the second mask pattern are removed.

10. The transistor manufacturing method according to claim 8, characterized in that: When the P-type gallium nitride film layer is subjected to ion implantation, the depth of the ion implantation is 40 to 95 nm.

Images