ESD protection device and chip

Abstract

The present disclosure relates to an ESD protection device and a chip. The device comprises: an N-type drift region; a first P-type doped region, which is located in the N-type drift region; a first N-type doped region, which is located in the N-type drift region; a Schottky barrier structure, which comprises a Schottky metal layer, wherein the Schottky metal layer, together with a semiconductor material that comes into contact with the bottom of the Schottky metal layer, forms a Schottky barrier; a P well, which is connected to the N-type drift region; a second N-type doped region, which is at least partially located in the P well; a second P-type doped region, which is at least partially located in the P well; and a gate electrode, which is located above a region between the first N-type doped region and the second N-type doped region, wherein the first P-type doped region, the first N-type doped region and the Schottky metal layer are connected to an anode, and the gate electrode, the second N-type doped region and the second P-type doped region are connected to a cathode. The present disclosure can increase the holding voltage of the ESD protection device, thereby improving the latch-up immunity capability of the ESD protection device.

Description

ESD protection devices and chips Cross-references to related applications

[0000] This application claims to have been filed with the Chinese Patent Office on July 22, 2024, application number 2024109861777, invention. Priority is claimed in the Chinese patent application entitled “ESD Protection Device and Chip”, the entire contents of which are incorporated herein by reference. Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to an ESD protection device, and also to a chip. Background Technology

[0002] With the rapid development of the integrated circuit (IC) industry, chips are exhibiting greater diversity and complexity in manufacturing processes, packaging forms, and application requirements. The reliability issues of ICs caused by electrostatic discharge (ESD) are becoming increasingly prominent. For example, in newly manufactured automobiles, electronic devices are becoming more numerous and their functions more complex. Traditional systems such as electric wipers, in-vehicle air conditioning, headlights, and audio systems, along with modern intelligent control systems, operate independently within the same system without interfering with each other. A sudden electrostatic pulse can affect the normal operation of these systems, and in severe cases, may cause malfunctions.

[0003] The dangers of ESD are obvious and have already drawn the attention of system engineers, integrated circuit design engineers, and process development engineers. While the design of low-voltage ESD protection devices is relatively mature, the design of high-voltage ESD protection devices still faces significant challenges, such as poor robustness and insufficient latch-up resistance. ESD design has also shifted from PCB (Printed Circuit Board) level protection to on-chip integrated circuit design. Summary of the Invention

[0004] Therefore, it is necessary to provide an ESD protection device and chip with strong robustness and strong anti-latch-up capability.

[0005] An ESD protection device includes: an N-type drift region; a first P-type doped region located within the N-type drift region; a first N-type doped region located within the N-type drift region; a Schottky barrier structure including a Schottky metal layer, the Schottky metal layer and a semiconductor material in contact with its bottom forming a Schottky barrier, the semiconductor material being located within the N-type drift region; a P-well connected to the N-type drift region; a second N-type doped region, at least partially located within the P-well; a second P-type doped region, at least partially located within the P-well; and a gate located above the region between the first N-type doped region and the second N-type doped region; wherein the first P-type doped region, the first N-type doped region, and the Schottky metal layer are connected to the anode of the ESD protection device, and the gate, the second N-type doped region, and the second P-type doped region are connected to the cathode of the ESD protection device.

[0006] The aforementioned ESD protection device, by adding a first P-type doped region to the anode, forms an ESD protection structure of GGNMOS (Gate-Ground NMOS, i.e., gate-grounded NMOS) plus SCR (Silicon Controlled Rectifier). It utilizes the strong robustness and low on-resistance of SCR, and the Schottky barrier structure can increase the sustaining voltage of the ESD protection device, thereby improving the latch-up resistance of the ESD protection device.

[0007] In one embodiment, the Schottky barrier structure and the first N-type doped region are alternately arranged in the direction of the conductive channel width.

[0008] In one embodiment, the second N-type doped region and the second P-type doped region are arranged alternately in the direction of the conductive channel width.

[0009] In one embodiment, a third P-type doped region, at least partially located in the P-well, is further included, with the second P-type doped region located between the third P-type doped region and the first P-type doped region; the third P-type doped region is connected to the cathode of the ESD protection device.

[0010] In one embodiment, a shallow trench isolation structure is also included between the second P-type doped region and the third P-type doped region.

[0011] In one embodiment, the first P-type doped region is located between the first N-type doped region and the second N-type doped region.

[0012] In one embodiment, the Schottky barrier structure constitutes a Schottky diode, the Schottky metal layer serves as the positive electrode of the Schottky diode, and the semiconductor material serves as the negative electrode of the Schottky diode.

[0013] In one embodiment, the first N-type doped region serves as the drain region of the GGNMOS, the second N-type doped region serves as the source region of the GGNMOS, and the gate serves as the gate of the GGNMOS.

[0014] In one embodiment, a P-type region is further included, in which the second N-type doped region and the second P-type doped region are located, the doping concentration of the P-type region is greater than the doping concentration of the P-well, and the P-type region is in direct contact with the N-type drift region.

[0015] In one embodiment, the third P-type doped region is located in the P-type region.

[0016] In one embodiment, the ESD protection device further includes a field oxide layer above a region between the first P-type doped region and the second N-type doped region; the gate extends from a position near the second N-type doped region toward the field oxide layer and onto the field oxide layer.

[0017] In one embodiment, the doping concentration of the first N-type doped region and the second N-type doped region is greater than the doping concentration of the N-type drift region.

[0018] In one embodiment, the doping concentration of the first P-type doped region and the second P-type doped region is greater than the doping concentration of the P-well.

[0019] In one embodiment, the doping concentration of the first P-type doped region and the second P-type doped region is greater than the doping concentration of the P-type region.

[0020] In one embodiment, the doping concentration of the third P-type doped region is greater than the doping concentration of the P-type region.

[0021] A chip comprising the ESD protection device described in any of the foregoing embodiments.

[0022] The chip described above uses the ESD protection device of the aforementioned embodiment for ESD protection, taking advantage of the strong robustness and low on-resistance of SCR, and the Schottky barrier structure can increase the sustaining voltage of the ESD protection device, thereby improving the latch-up resistance of the ESD protection device. Attached Figure Description

[0023] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0024] Figure 1 shows a circuit architecture in the related technology that incorporates an ESD protection device.

[0025] Figure 2 is a schematic diagram of the structure of an ESD protection device in one embodiment of this application.

[0026] Figure 3 is a top view of the ESD protection device in one embodiment of the present application, showing the second N-type doped region 144 and the second P-type doped region 154 (not shown in Figure 2) in region 10, the first N-type doped region 142 and the Schottky barrier structure 141 (not shown in Figure 2) in region 20, and the second N-type doped region 144 and the second P-type doped region 154 (not shown in Figure 2) in region 30.

[0027] Figure 4 is an equivalent circuit diagram of an ESD protection device in one embodiment of this application. Detailed Implementation

[0028] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0030] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0031] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0033] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of this disclosure. Thus, variations from the shapes shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this disclosure should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of this disclosure.

[0034] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0035] Referring to Figure 1, in related technologies, ESD protection devices are connected to integrated circuits through an anode (also known as the positive electrode) and a cathode (also known as the negative electrode) for ESD protection.

[0036] Adding ESD protection devices to integrated circuit ports allows the devices to meet ESD standard requirements without latch-up. To enhance the latch-up resistance of high-voltage ESD protection devices, two approaches are needed: firstly, increase the sustaining voltage of the ESD protection device to be higher than the operating voltage of the protected circuit port; secondly, increase the sustaining current of the ESD protection device to be higher than the operating current of the protected circuit port.

[0037] An exemplary ESD protection device involves inserting P+ into the anode of a GGNMOS (Gate-Grounded N-channel Metal Oxide Semiconductor) that uses a P-well as the channel. This forms an ESD protection structure for both the GGNMOS and SCR (Silicon Controlled Rectifier), enhancing the device's current discharge capability and improving its robustness. However, it has significant hysteresis and is prone to latch-up.

[0038] Another exemplary ESD protection device exists, which uses a parasitic NPN transistor to control a floating LDMOS (Lateral Double-diffused MOS) structure within the device. This reduces the electron emission of the LDMOS-SCR device, increases the holding voltage, and enhances the current discharge capability of the N-type conductive channel of the floating LDMOS structure, thereby improving the device's ESD robustness. This device has a quasi-double-infeld structure, with the left and right sides connected in parallel. The left side is an SCR structure, and the right side is an NPN-controlled floating LDMOS. The discharge current is increased due to the left-side SCR, but the NPN-controlled LDMOS provides a smaller increase in holding voltage.

[0039] This application proposes an ESD protection device that utilizes the advantages of the SCR structure, such as strong robustness and low on-resistance. Furthermore, a Schottky diode is added to the anode to enhance the latch-up resistance of the ESD protection device, thus realizing an electrostatic protection circuit design with latch-up resistance, strong robustness, and low on-resistance.

[0040] Figure 2 is a schematic diagram of the structure of an ESD protection device in one embodiment of this application. Figure 3 is a top view of the ESD protection device in one embodiment of this application, showing the second N-type doped region 144 and the second P-type doped region 154 (not shown in Figure 2) in region 10, the first N-type doped region 142 and the Schottky barrier structure 141 (not shown in Figure 2) in region 20, and the second N-type doped region 144 and the second P-type doped region 154 (not shown in Figure 2) in region 30.

[0041] As shown in Figures 2 and 3, the ESD protection device includes an N-type drift region 130, a first P-type doped region 152, a first N-type doped region 142, a Schottky barrier structure 141, a P-well 122, a second N-type doped region 144, a second P-type doped region 154, and a gate 170. The structure shown in Figure 2 is symmetrical from left to right, so most of the structures in Figure 2 are labeled only on one side.

[0042] The first P-type doped region 152 and the first N-type doped region 142 are located in the N-type drift region 130. The Schottky barrier structure 141 includes a Schottky metal layer, which forms a Schottky barrier with the semiconductor material located in the N-type drift region 130 in contact with its bottom. In one embodiment of this application, the Schottky metal layer includes at least one metal element selected from Ti, Pt, Ni, Cr, W, Mo, and Co, and forms a metal silicide with the silicon in contact with its bottom through heat treatment. The P-well 122 is connected to the N-type drift region 130. In one embodiment of this application, the N-type drift region 130 is located in the P-well 122. The second N-type doped region 144 and the second P-type doped region 154 are at least partially located in the P-well 122. The gate 170 is located above the region between the first N-type doped region 142 and the second N-type doped region 144.

[0043] The first P-type doped region 152, the first N-type doped region 142, and the Schottky metal layer are connected to the anode of the ESD protection device, and the gate 170, the second N-type doped region 144, and the second P-type doped region 154 are connected to the cathode of the ESD protection device.

[0044] The aforementioned ESD protection device, by adding a first P-type doped region 152 to the anode, forms an ESD protection structure of GGNMOS (Gate-Grounded NMOS) plus SCR (Silicon Controlled Rectifier), utilizing the advantages of SCR such as strong robustness and low on-resistance, and increasing the conduction uniformity of the device. Furthermore, the Schottky barrier structure 141 can increase the sustaining voltage of the ESD protection device, thereby improving its latch-up resistance.

[0045] Figure 4 is an equivalent circuit diagram of an ESD protection device in one embodiment of this application. A first N-type doped region 142 serves as the drain region of the GGNMOS M1, a second N-type doped region 144 serves as the source region of the GGNMOS M1, and a gate 170 serves as the gate of the GGNMOS M1. Parasitic PNP transistors Q1 and Q2 form a PNPN SCR. Specifically, a first P-type doped region 152 serves as the emitter of the parasitic PNP transistor Q1, an N-type drift region 130 serves as the base of the parasitic PNP transistor Q1, and a P-well 122 serves as the collector of the parasitic PNP transistor Q1; an N-type drift region 130 serves as the collector of the parasitic NPN transistor Q2, a P-well 122 serves as the base of the parasitic NPN transistor Q2, and a second N-type doped region 144 serves as the emitter of the parasitic NPN transistor Q2. In Figure 4, resistor Rdp is the equivalent resistance of P-well 122, and Rnm is the equivalent resistance of N-type drift region 130. In one embodiment of this application, GGNMOS M1 is an NLDMOS.

[0046] In one embodiment of this application, the Schottky barrier structure 141 and the first N-type doped region 142 are alternately arranged in the width direction of the conductive channel (i.e., the Y-axis direction in FIG3). In one embodiment of this application, the Schottky barrier structure 141 constitutes a Schottky diode D1, the Schottky metal layer serves as the positive electrode of the Schottky diode D1, the N-type drift region 130 serves as the negative electrode of the Schottky diode D1, and the resistor Rsch in FIG4 is the equivalent resistance from the negative electrode of the Schottky diode D1 to the conductive channel (the conductive channel of GGNMOS M1). By adjusting the length ratio of the first N-type doped region 142 to the Schottky barrier structure 141 in the width direction of the conductive channel, the sustaining voltage of the ESD protection device can be adjusted. In one embodiment of this application, the length ratio of the first N-type doped region 142 to the Schottky barrier structure 141 in the width direction of the conductive channel in FIG3 is 1:4.

[0047] In one embodiment of this application, the second N-type doped region 144 and the second P-type doped region 154 are arranged alternately in the direction of the conductive channel width, as shown in FIG3. The trigger voltage of the ESD protection device can be adjusted by regulating the length ratio of the second N-type doped region 144 to the second P-type doped region 154 in the direction of the conductive channel width. In one embodiment of this application, the length ratio of the second P-type doped region 154 to the second N-type doped region 144 in the direction of the conductive channel width is 1:2.

[0048] In one embodiment of this application, the ESD protection device further includes a third P-type doped region 156 at least partially located in the P-well 122. A second P-type doped region 154 is located between the third P-type doped region 156 and the first P-type doped region 152. The third P-type doped region 156 is connected to the cathode of the ESD protection device.

[0049] In one embodiment of this application, the ESD protection device further includes a P-type region 124, a second N-type doped region 144, and a second P-type doped region 154 located within the P-type region 124. The doping concentration of the P-type region 124 is greater than that of the P-well 122, and the P-type region 124 is in direct contact with the N-type drift region 130. By providing the P-type region 124, electrostatic breakdown can occur at the boundary between the P-type region 124 and the N-type drift region 130, thereby reducing the surface electric field of the device and preventing premature failure of the ESD protection device. In one embodiment of this application, the P-type region 124 is located within the P-well 122. In the embodiment shown in FIG. 2, a third P-type doped region 156 is located within the P-type region 124.

[0050] In one embodiment of this application, the first P-type doped region 152 is located between the first N-type doped region 142 and the second N-type doped region 144, which can form a shorter SCR path.

[0051] In one embodiment of this application, the ESD protection device further includes a field oxide layer 160 located above the region between the first P-type doped region 152 and the second N-type doped region 144. A gate 170 extends from a position near the second N-type doped region 144 toward and onto the field oxide layer 160.

[0052] In one embodiment of this application, the ESD protection device further includes a shallow trench isolation (STI) structure 180. The shallow trench isolation structure 180 is disposed between the second P-type doped region 154 and the third P-type doped region 156. In one embodiment of this application, a shallow trench isolation structure 180 is also provided on the side of the third P-type doped region 156 away from the drift region 130.

[0053] In one embodiment of this application, a gate dielectric layer is further provided between the gate 170 and the underlying P-type region 124. In another embodiment of this application, the gate dielectric layer may comprise conventional dielectric materials such as silicon oxides, nitrides, and oxides of nitride having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0054] In one embodiment of this application, the gate 170 is made of polysilicon. In other embodiments, metals, metal nitrides, metal silicides or other similar compounds may also be used as the material of the gate 170.

[0055] In one embodiment of this application, the doping concentration of the first N-type doped region 142 and the second N-type doped region 144 is greater than the doping concentration of the N-type drift region 130. In one embodiment of this application, the doping concentration of the first P-type doped region 152 and the second P-type doped region 154 is greater than the doping concentration of the P-well 122. Further, the doping concentration of the first P-type doped region 152 and the second P-type doped region 154 is greater than the doping concentration of the P-type region 124. In one embodiment of this application, the doping concentration of the third P-type doped region 156 is greater than the doping concentration of the P-well 122; further, the doping concentration of the third P-type doped region 156 is greater than the doping concentration of the P-type region 124.

[0056] In one embodiment of this application, the contact holes of the third P-type doped region 156, the second P-type doped region 154, the second N-type doped region 144, and the gate 170 on the left side of FIG2 are all connected to the first metal interconnect. Similarly, the contact holes of the third P-type doped region 156, the second P-type doped region 154, the second N-type doped region 144, and the gate 170 on the right side of FIG2 are all connected to the third metal interconnect. The contact holes of the first N-type doped region 142, the Schottky metal layer, and the first P-type doped region 152 are all connected to the second metal interconnect. The first and third metal interconnects lead to a cathode, which serves as the first electrical stress terminal of the ESD protection device. The second metal interconnect leads to an anode, which serves as the second electrical stress terminal of the ESD protection device.

[0057] Based on all the foregoing embodiments, the ESD protection device of this application adds a first P-type doped region 152 to the anode of the traditional GGNMOS as the ESD protection device, forming a GGNMOS plus SCR structure, which can increase the uniformity and robustness of device conduction. Simultaneously, the anode N+ is designed with an ohmic contact and a Schottky contact topology to achieve adjustable sustaining voltage (by adjusting the ratio of the ohmic contact and Schottky contact topologies, the sustaining voltage and trigger voltage of the ESD protection device can be adjusted), improving its latch-up resistance. By adding a P-type region 124, electrostatic breakdown occurs at the boundary between the P-type region 124 and the N-type drift region 130, reducing the surface electric field of the device and preventing premature failure of the ESD protection device. For the topologies of the second N-type doped region 144 and the second P-type doped region 154, the trigger voltage of the ESD protection device can be adjusted by adjusting the ratio of the second N-type doped region 144 to the second P-type doped region 154.

[0058] This application provides a chip that includes the ESD protection device described in any of the foregoing embodiments, that is, the integrated circuit of the chip is protected against ESD by the ESD protection device described in the foregoing embodiments.

[0059] In the description of this specification, references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0060] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0061] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. An ESD protection device, comprising: an N-type drift region; a first P-type doped region in the N-type drift region; a first N-type doped region in the N-type drift region; a Schottky barrier structure comprising a Schottky metal layer, the Schottky metal layer forming a Schottky barrier with a semiconductor material in contact with a bottom of the Schottky metal layer, the semiconductor material being in the N-type drift region; a P-well connected to the N-type drift region; a second N-type doped region at least partially in the P-well; a second P-type doped region at least partially in the P-well; a gate over a region between the first N-type doped region and the second N-type doped region; wherein the first P-type doped region, the first N-type doped region and the Schottky metal layer connect an anode of the ESD protection device, and the gate, the second N-type doped region and the second P-type doped region connect a cathode of the ESD protection device.

2. The ESD protection device of claim 1, wherein, The Schottky barrier structure and the first N-type doped region are arranged alternately in a width direction of a conductive channel.

3. The ESD protection device according to claim 1 or 2, wherein, The second N-type doped region and the second P-type doped region are arranged alternately in the width direction of the conductive channel. 4.The ESD protection device of any one of claims 1-3, further comprising a third P-type doped region at least partially in the P-well, the second P-type doped region is between the third P-type doped region and the first P-type doped region; the third P-type doped region connects the cathode of the ESD protection device. 5.The ESD protection device of claim 4, further comprising a shallow trench isolation structure between the second P-type doped region and the third P-type doped region.

6. The ESD protection device according to any one of claims 1-5, wherein, The first P-type doped region is between the first N-type doped region and the second N-type doped region.

7. The ESD protection device according to any one of claims 1-6, wherein, The Schottky barrier structure forms a Schottky diode, the Schottky metal layer is a positive electrode of the Schottky diode, the semiconductor material is a negative electrode of the Schottky diode. 8.The ESD protection device of any one of claims 1-7, wherein: the first N-type doped region is a drain region of a gate-grounded N-type metal-oxide-semiconductor (GGNMOS), the second N-type doped region is a source region of the GGNMOS, the gate is a gate of the GGNMOS. 9.The ESD protection device of any one of claims 1-8, further comprising a P-type region, the second N-type doped region and the second P-type doped region are in the P-type region, a doping concentration of the P-type region is greater than a doping concentration of the P-well, the P-type region is in direct contact with the N-type drift region.

10. The ESD protection device of any of claims 1-9, wherein, a ratio of the length of the first N-type doped region to the length of the Schottky barrier structure in the width direction of the conductive channel is 1:4;a ratio of the length of the second N-type doped region to the length of the second P-type doped region in the width direction of the conductive channel is 1:

2. 11.The ESD protection device of claim 4 or 5, further comprising a P-type region, the third N-type doped region is in the P-type region.

12. The ESD protection device of claim 11, wherein a doping concentration of the third P-type doped region is greater than a doping concentration of the P-type region.

13. The ESD protection device of claim 9, wherein, a doping concentration of the first and second N-type doped regions is greater than a doping concentration of the N-type drift region; a doping concentration of the first and second P-type doped regions is greater than a doping concentration of the P-well; and a doping concentration of the first and second P-type doped regions is greater than a doping concentration of the P-type region.

14. The ESD protection device of any one of claims 1-13, further comprising: a field oxide layer over a region between the first P-type doped region and the second N-type doped region, the gate extending from a position proximate the second N-type doped region to the field oxide layer and onto the field oxide layer.

15. A chip comprising the ESD protection device of any one of claims 1-14.

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