Tensile strain high hole mobility field effect transistor and preparation method thereof

Abstract

The invention discloses a tensile strain high-hole mobility field effect transistor, which comprises a base substrate, a substrate, a buffer layer, a barrier layer, an insertion layer, a spatial isolation layer, a hole supply layer, a source electrode, a drain electrode and a gate electrode, the substrate is made of a polycrystalline AlN material, and a plurality of blind holes are formed in the substrate; when the buffer layer grows on the substrate, the material of the buffer layer grows on the surface of the substrate and the side walls of the plurality of blind holes and is combined to introduce tensile strain; the barrier layer is located on the buffer layer, the insertion layer is located on the barrier layer, the spatial isolation layer is located on the insertion layer, the hole supply layer is located on the spatial isolation layer, and the source electrode, the drain electrode and the gate electrode are located on the hole supply layer. The invention also discloses a preparation method of the tensile strain high hole mobility field effect transistor. According to the invention, the epitaxy of the p-channel heterojunction is carried out on the polycrystalline AlN substrate with the blind holes, so that the introduction and distribution of stress can be accurately controlled, and the hole mobility is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of field effect transistors, and in particular to a tensile strain high hole mobility field effect transistor and a preparation method thereof. Background Art

[0002] Compared with silicon materials used in traditional electronic power devices, III-nitride semiconductor materials have superior properties such as large bandgap, high breakdown electric field strength, high saturated electron mobility, large thermal conductivity, small dielectric constant, and strong radiation resistance. In addition, the polarization-induced carrier density in gallium nitride is independent of temperature. Therefore, gallium nitride (GaN) is considered to be a good candidate material for power integrated circuits used in harsh environmental conditions.

[0003] In the past two years, GaN-based complementary logic circuits have been studied and demonstrated, and monolithic GaN CL gates with true "CMOS-like" behavior have been obtained. GaN-based complementary logic integrated circuits are currently in their infancy, and the performance of the device needs to be further optimized. The carrier concentration and mobility need to be improved, especially the low channel mobility and high on-resistance of the current GaN-based p-channel field effect transistor. On the one hand, the ionization energy of Mg impurities in GaN is very high, and the hole concentration is low; on the other hand, the large effective mass of holes greatly limits the hole mobility. Through first-principles calculations, it is found that the introduction of biaxial tensile strain in GaN can raise the spin-orbit coupling split band to above the light hole band and the heavy hole band. This effect changes the order of the top of the valence band and the characteristics of the wave function, which can greatly reduce the effective mass of holes and thus achieve the hole mobility of GaN. At present, the common method of introducing the required stress distribution in GaN during the metal organic chemical vapor deposition (MOCVD) growth process is to use a substrate with a larger lattice constant and change the barrier layer material. However, due to the lattice mismatch, the crystal growth quality will be degraded. Therefore, the existing GaN-based p-channel field effect transistors have low hole mobility and lack effective means to improve the hole mobility. The introduction of tensile stress is unstable and it is difficult to control the introduced stress intensity. The introduction of stress is difficult and can easily cause film cracking. The introduction of stress will introduce a large number of defects and dislocations, making it difficult to obtain high-quality materials. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a tensile strain high hole mobility field effect transistor and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0005] A first aspect of an embodiment of the present invention provides a tensile strain high hole mobility field effect transistor, comprising: a substrate, a buffer layer, a barrier layer, an insertion layer, a space isolation layer, a hole supply layer, a source electrode, a drain electrode and a gate electrode;

[0006] The substrate comprises: a base substrate and a substrate located on the base substrate;

[0007] The substrate is made of polycrystalline AlN material, and a plurality of blind holes are opened on the substrate; the plurality of blind holes are evenly arranged;

[0008] Wherein, the buffer layer is located on the substrate, and when the buffer layer is grown on the substrate, the material of the buffer layer grows and merges on the substrate surface and the sidewalls of the plurality of blind holes to introduce tensile strain;

[0009] The barrier layer is located on the buffer layer, the insertion layer is located on the barrier layer, the space isolation layer is located on the insertion layer, the hole supply layer is located on the space isolation layer, and the source electrode, the drain electrode and the gate electrode are located on the hole supply layer.

[0010] In one embodiment of the present invention, the plurality of blind holes form an array, and two adjacent columns or rows of blind holes are staggered with each other.

[0011] In one embodiment of the present invention, the buffer layer is made of GaN material, the barrier layer is made of AlGaN material with an Al component of 20%-40%, the insertion layer is made of AlN material, the space isolation layer is made of GaN material, and the hole supply layer is made of p-type doped GaN material.

[0012] In one embodiment of the present invention, the blind hole is prepared by inductively coupled plasma etching.

[0013] In one embodiment of the present invention, the thickness of the substrate is 2 μm-4 μm, the diameter of the blind hole is 1 μm-3 μm, and the depth is 100 nm-800 nm; the center distance between two adjacent blind holes is 6 μm-10 μm;

[0014] The thickness of the buffer layer is 2 μm-4 μm;

[0015] The thickness of the barrier layer is 15nm-60nm;

[0016] The thickness of the insertion layer is 1nm-3nm;

[0017] The thickness of the space isolation layer is 5nm-10nm;

[0018] The dopant of the hole supply layer is Mg, and the doping concentration is 1×10 19 cm -3 -6×10 19 cm -3 , thickness is 20nm-80nm.

[0019] A second aspect of an embodiment of the present invention provides a method for preparing a tensile strain high hole mobility field effect transistor, comprising the following steps:

[0020] Step 1: growing a substrate on a base substrate; wherein the substrate is made of polycrystalline AlN material;

[0021] Step 2: preparing a plurality of blind holes on the substrate, wherein the plurality of blind holes are evenly arranged;

[0022] Step 3, growing a buffer layer on the substrate; wherein the material of the buffer layer grows on the substrate surface and the sidewalls of the plurality of blind holes and merges to introduce tensile strain;

[0023] Step 4: grow a barrier layer on the buffer layer, grow an insertion layer on the barrier layer, grow a space isolation layer on the insertion layer, grow a hole supply layer on the space isolation layer, and prepare a source electrode, a drain electrode and a gate electrode on the hole supply layer.

[0024] In one embodiment of the present invention, the plurality of blind holes form an array, and two adjacent columns or rows of blind holes are staggered with each other.

[0025] In one embodiment of the present invention, the specific steps of step 1 include:

[0026] The substrate is grown on the base substrate by adopting a controlled sputtering method or a physical vapor transport method.

[0027] In one embodiment of the present invention, the specific steps of step 2 include:

[0028] A plurality of blind holes are etched on the substrate by inductively coupled plasma etching.

[0029] In one embodiment of the present invention, the buffer layer is made of GaN material and has a thickness of 2 μm-4 μm;

[0030] The barrier layer is made of AlGaN material with an Al component of 20%-40% and a thickness of 15nm-60nm;

[0031] The insertion layer is made of AlN material with a thickness of 1nm-3nm;

[0032] The space isolation layer is made of GaN material with a thickness of 5nm-10nm;

[0033] The hole supply layer is made of p-type doped GaN material, the dopant is Mg, and the doping concentration is 1×10 19 cm -3 -6×10 19 cm -3 , thickness is 20nm-80nm.

[0034] Beneficial effects of the present invention:

[0035] The present invention can grow a p-channel heterojunction incoherently by using a polycrystalline AlN substrate, and at the same time, a hole is opened on the polycrystalline AlN substrate, and the epitaxial material grows in both longitudinal and lateral directions on the surface of the polycrystalline AlN substrate and in the blind hole and merges laterally, introducing tensile strain, and using stress to change the order of the top of the valence band and the characteristics of the wave function, thereby reducing the effective mass of the hole, realizing the preparation of a tensile strain p-channel heterojunction, thereby improving the hole mobility, and the strain state can be accurately controlled by different blind hole sizes and the spacing between the blind holes. At the same time, the preparation method of polycrystalline AlN is diverse, the growth process is simple, the controllability is strong, and the preparation process is simple. The size of the blind hole can accurately adjust the stress, improve the stability of growth processes such as MOCVD, ensure the quality of the material, and accurately control the mobility, which helps to reduce the impact of process changes on the quality of the film and improve the consistency and reliability of production.

[0036] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0037] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0039] Figure 1 A schematic structural diagram of a tensile strain high hole mobility field effect transistor provided by an embodiment of the present invention;

[0040] Figure 2 A schematic diagram of the process of a method for preparing a tensile strain high hole mobility field effect transistor provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0042] like Figure 1 As shown, a first aspect of an embodiment of the present invention provides a tensile strain high hole mobility field effect transistor, comprising: a substrate, a buffer layer 5, a barrier layer 6, an insertion layer 7, a space isolation layer 8, a hole supply layer 9, a source electrode 10, a drain electrode 11 and a gate electrode 13.

[0043] The substrate comprises: a base substrate 1 and a base plate 2 located on the base substrate 1 .

[0044] The substrate 2 is made of polycrystalline AlN material, and a plurality of blind holes 3 are formed on the substrate 2; the plurality of blind holes 3 are evenly arranged, the blind holes 3 are of the same size, and the spacing between two adjacent blind holes 3 is equal. The buffer layer 5 is located on the substrate 2, and when the buffer layer 5 is grown on the substrate 2, the material of the buffer layer 5 grows and merges on the surface of the substrate 2 and the side walls of the plurality of blind holes 3 to introduce tensile strain.

[0045] The barrier layer 6 is located on the buffer layer 5 , the insertion layer 7 is located on the barrier layer 6 , the space isolation layer 8 is located on the insertion layer 7 , the hole supply layer 9 is located on the space isolation layer 8 , and the source electrode 10 , the drain electrode 11 and the gate electrode 13 are located on the hole supply layer 9 .

[0046] In this embodiment, a p-channel heterojunction can be grown incoherently by using a polycrystalline AlN substrate 2, and a hole is opened on the polycrystalline AlN substrate 2 at the same time. During the growth of the epitaxial material on the polycrystalline AlN substrate 2, nuclei are first formed at different sites, and then grow in both the lateral and longitudinal directions on the surface of the polycrystalline AlN substrate 2 and in the blind hole 3. After the lateral growth extends for a certain distance, the materials nucleated at different sites will meet and merge (the materials on the surface of the substrate 2 merge with each other laterally and the materials in the blind hole 3 merge laterally). After the longitudinal growth extends for a certain distance, the materials on the surface of the substrate 2 and the materials in the blind hole 3 merge laterally, thereby introducing tensile strain during the merging, using stress to reduce the effective mass of the hole, realizing the preparation of a tensile strain p-channel heterojunction, and thus greatly improving the hole mobility. The strain state can be accurately controlled by different sizes of the blind holes 3 and the spacing between the blind holes 3. At the same time, the preparation method of polycrystalline AlN is diverse, the growth process is simple, the controllability is strong, and the preparation process is simple. The size of the blind hole 3 can accurately adjust the stress, improve the stability of growth processes such as MOCVD, ensure material quality, and accurately control the mobility, which helps to reduce the impact of process changes on film quality and improve production consistency and reliability.

[0047] At the same time, the method of introducing tensile strain using the polycrystalline AlN substrate 2 is applicable to the growth of various III-nitride semiconductor materials and heterostructures, and has broad application prospects.

[0048] In addition, after the epitaxial materials are merged at the blind hole 3 , a cavity is generated at the bottom of the blind hole 3 .

[0049] Preferably, a plurality of blind holes 3 form an array, and two adjacent columns or rows of blind holes 3 are staggered. Therefore, regular hexagons can be formed in any three consecutive columns of blind holes 3, which is similar to the crystal structure of nitride and is conducive to the growth of nitride.

[0050] The substrate 2 is made of polycrystalline AlN material with a thickness of 2μm-4μm, and can be prepared by, but not limited to, magnetron sputtering, physical vapor transport (PVT) and other methods. The blind holes 3 are prepared by inductively coupled plasma etching (ICP), with a diameter of 1μm-3μm and a depth of 100nm-800nm. The center spacing between two adjacent blind holes 3 is 6μm-10μm.

[0051] The buffer layer 5 is made of GaN material with a thickness of 2μm-4μm. The barrier layer 6 is made of AlGaN material with an Al component of 20%-40% and a thickness of 15nm-60nm. The insertion layer 7 is made of AlN material with a thickness of 1nm-3nm. The space isolation layer 8 is made of GaN material with a thickness of 5nm-10nm. The hole supply layer 9 is made of p-type doped GaN material, the dopant is Mg, and the doping concentration is 1×10 19 cm -3 -6×10 19 cm -3 , thickness is 20nm-80nm.

[0052] A second aspect of an embodiment of the present invention provides a method for preparing a tensile strain high hole mobility field effect transistor, which is used to prepare the field effect transistor provided by the first aspect of an embodiment of the present invention, comprising the following steps:

[0053] Step 1: growing a substrate 2 on a base substrate 1; wherein the substrate 2 is made of polycrystalline AlN material.

[0054] Step 2: prepare a plurality of blind holes 3 on the substrate 2, wherein the plurality of blind holes 3 are evenly arranged.

[0055] Step 3: growing a buffer layer 5 on the substrate 2. The material of the buffer layer 5 grows and merges on the surface of the substrate 2 and the sidewalls of the plurality of blind holes 3 to introduce tensile strain.

[0056] Step 4: grow a barrier layer 6 on the buffer layer 5, grow an insertion layer 7 on the barrier layer 6, grow a space isolation layer 8 on the insertion layer 7, grow a hole supply layer 9 on the space isolation layer 8, and prepare a source electrode 10, a drain electrode 11 and a gate electrode 13 on the hole supply layer 9.

[0057] The specific preparation method of this embodiment is further described below: comprising the following steps:

[0058] Step S11, growing a substrate 2 of 2 μm-4 μm on a base substrate 1; the substrate 2 is made of polycrystalline AlN material.

[0059] Step S12, on the substrate 2, blind holes 3 with a diameter of 1 μm-3 μm, a depth of 100 nm-800 nm, and a spacing of 6 μm-10 μm are prepared by inductively coupled plasma etching. Multiple blind holes 3 are evenly arranged, and multiple blind holes 3 form an array, and two adjacent columns or rows of blind holes 3 are staggered with each other.

[0060] Step S13, growing a buffer layer 5 of GaN material with a thickness of 2 μm-4 μm on the substrate 2 by using MOCVD process. The material of the buffer layer 5 grows and merges on the surface of the substrate 2 and the sidewalls of the plurality of blind holes 3 to introduce tensile strain.

[0061] Step S14: on the buffer layer 5, a barrier layer 6 of AlGaN material with an Al content of 20% to 40% and a thickness of 15 nm to 60 nm is grown by MOCVD process.

[0062] Step S15 , growing an insertion layer 7 of AlN material with a thickness of 1 nm to 3 nm on the barrier layer 6 by using a MOCVD process.

[0063] Step S16: on the insertion layer 7, a space isolation layer 8 of GaN material with a thickness of 5 nm to 10 nm is grown by using a MOCVD process.

[0064] Step S17 , growing a hole supply layer 9 of p-type doped GaN material with a thickness of 20 nm to 80 nm on the space isolation layer 8 by using a MOCVD process.

[0065] Step S18, depositing Ni / Au metal stack (50nm / 100nm) on the hole supply layer 9 by electron beam evaporation process, and annealing at 550°C in an O2 environment to form ohmic contacts of the source electrode 10 and the drain electrode 11 in the p-FET.

[0066] Step S19 , using low damage GaN etching technology to etch the hole supply layer 9 to a depth of 10 nm-70 nm, and annealing at 450° C. in a N 2 atmosphere to form a gate groove 12 .

[0067] Step S20 , depositing a W / Au (20nm / 100nm) metal stack on the gate groove 12 by magnetron sputtering to form a gate electrode 13 of the p-FET, and completing the preparation to obtain the field effect transistor provided in the first embodiment of the present invention.

[0068] Preferably, the substrate 2 is 3 μm thick, the blind hole 3 is 2 μm in diameter, the hole depth is 100 nm, the spacing is 8 μm, the buffer layer 5 is 4 μm thick, the barrier layer 6 is 30 nm thick and the Al composition is 25%, the insertion layer 7 is 2 nm thick, the space isolation layer 8 is 10 nm thick, the hole supply layer 9 is 30 nm thick and the doping concentration is 3×10 19 cm-3 Taking the preparation method of tensile strained GaN-based p-FETs as an example, the preparation method of this embodiment is specifically described:

[0069] Step S21: Select the base substrate 1 material, such as Figure 2 As shown in (a).

[0070] Sapphire was selected as the base substrate 1 .

[0071] Step S22: Preparation of substrate 2, such as Figure 2 As shown in (b).

[0072] The polycrystalline AlN layer with a thickness of 3 μm was grown by PVT method.

[0073] Step S23: Opening a hole in the substrate 2, such as Figure 2 As shown in (c).

[0074] The ICP method is used to open holes in the substrate 2, with Cl2 / BCl3 mixed gas as the etching gas, Cl2 flow rate of 70sccm, BCl3 flow rate of 5sccm, etching rate of 55nm / min, etching time of 1.5min, etching depth of 100nm, and blind holes 3 with a diameter of 2μm are formed on the AlN surface. The centers of two adjacent blind holes 3 are 8μm apart. Regular hexagons can be found in any three consecutive rows of blind holes 3, which is similar to the crystal structure of nitrides and is conducive to the growth of nitrides.

[0075] Step S24: epitaxially growing a buffer layer 5, such as Figure 2 As shown in (d).

[0076] The product prepared in step S23 is placed in an MOCVD reaction chamber, the temperature of the reaction chamber is raised to 960°C, the pressure of the reaction chamber is maintained at 30 Torr, and a nitrogen source with a flow rate of 2500 sccm and a gallium source with a flow rate of 180 sccm are introduced at the same time, and a GaN buffer layer 5 with a thickness of 4 μm is grown on the AlN substrate 2 using the MOCVD process.

[0077] Step S25: epitaxial barrier layer 6, such as Figure 2 As shown in (e).

[0078] The temperature of the reaction chamber was raised to 1010°C, the pressure of the reaction chamber was maintained at 20 Torr, and a nitrogen source with a flow rate of 2500 sccm, a gallium source with a flow rate of 60 sccm, and an aluminum source with a flow rate of 300 sccm were introduced simultaneously to grow an Al layer with a thickness of 30 nm on the buffer layer 5. 0.25 Ga 0.75 N barrier layer 6.

[0079] Step S26: epitaxial insertion layer 7, such as Figure 2 As shown in (f).

[0080] The temperature of the reaction chamber is maintained at 1010° C., the pressure of the reaction chamber is maintained at 20 Torr, and a nitrogen source with a flow rate of 3200 sccm and an aluminum source with a flow rate of 400 sccm are introduced simultaneously to grow an AlN insertion layer 7 with a thickness of 2 nm on the barrier layer 6.

[0081] Step S27: epitaxially extending the space isolation layer 8, such as Figure 2 As shown in (g).

[0082] The temperature of the reaction chamber is lowered to 960° C., the pressure of the reaction chamber is maintained at 20 Torr, and a nitrogen source with a flow rate of 2500 sccm and a gallium source with a flow rate of 180 sccm are introduced simultaneously to grow a GaN space isolation layer 8 with a thickness of 10 nm on the insertion layer 7 .

[0083] Step S28: epitaxially growing the hole supply layer 9, such as Figure 2 As shown in (h).

[0084] The temperature of the reaction chamber is maintained at 960°C, and the pressure of the reaction chamber is maintained at 20 Torr. A nitrogen source with a flow rate of 2500 sccm, a gallium source with a flow rate of 180 sccm, and a magnesium source with a flow rate of 100 sccm are introduced simultaneously to grow a p-type GaN hole supply layer 9 with a thickness of 30 nm on the space isolation layer 8.

[0085] Step S29: Make the source electrode 10 and the drain electrode 11, such as Figure 2 As shown in (i).

[0086] A Ni / Au metal stack with a thickness of 50 nm / 100 nm is deposited on the hole supply layer 9 by electron beam evaporation process. After annealing in an O2 environment at 550°C for 5 minutes, a source electrode 10 and a drain electrode 11 are formed on the hole supply layer 9.

[0087] Step S30: etching the gate groove 12, such as Figure 2 As shown in (j).

[0088] The hole supply layer 9 is etched using a low-damage Cl2 / BCl3 slow etching process with an etching rate of 2.4nm / min and an etching depth of 20nm. The sample is then surface treated with NH3:H2O (1:6) at 55°C for 5 minutes to remove surface contaminants and residual photoresist, and annealed in a N2 environment at 450°C for 5 minutes to reduce surface damage caused by etching, thereby obtaining a gate groove 12.

[0089] Step S31: Making the gate electrode 13, such as Figure 2 As shown in (k).

[0090] A W / Au metal stack with a thickness of 20 nm / 100 nm is deposited on the gate groove 12 by a magnetron sputtering process to form a gate electrode 13 .

[0091] Through the above implementation method, the tensile strained GaN-based high hole mobility p-channel field effect transistor of the present invention can effectively control the strain and greatly improve the hole mobility.

[0092] The present invention significantly improves the mobility: stress is used to change the effective mass of the holes, thereby greatly improving the mobility.

[0093] The stress introduction of the present invention is simple: the preparation methods of polycrystalline AlN are diverse, the growth process is simple, the controllability is strong, and there is no need to introduce complex processes.

[0094] The present invention improves process stability: adjusting the size of the blind hole can accurately adjust the stress, improve the stability of growth processes such as MOCVD, ensure material quality, and accurately control mobility. This helps to reduce the impact of process changes on film quality and improve production consistency and reliability.

[0095] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0096] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0097] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0098] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0099] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0100] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A tensile strain high hole mobility field effect transistor, characterized in that: include: substrate, buffer layer, barrier layer, insertion layer, space isolation layer, hole supply layer, source electrode, drain electrode and gate electrode; The substrate comprises: a base substrate and a substrate located on the base substrate; The substrate is made of polycrystalline AlN material, and a plurality of blind holes are opened on the substrate; the plurality of blind holes are evenly arranged; Wherein, the buffer layer is located on the substrate, and when the buffer layer is grown on the substrate, the material of the buffer layer grows and merges on the substrate surface and the sidewalls of the plurality of blind holes to introduce tensile strain; The barrier layer is located on the buffer layer, the insertion layer is located on the barrier layer, the space isolation layer is located on the insertion layer, the hole supply layer is located on the space isolation layer, and the source electrode, the drain electrode and the gate electrode are located on the hole supply layer.

2. A tensile strain high hole mobility field effect transistor according to claim 1, characterized in that: The plurality of blind holes form an array, and two adjacent columns or rows of blind holes are staggered with each other.

3. The tensile strain high hole mobility field effect transistor according to claim 1, characterized in that: The buffer layer is made of GaN material, the barrier layer is made of AlGaN material with an Al component of 20%-40%, the insertion layer is made of AlN material, the space isolation layer is made of GaN material, and the hole supply layer is made of p-type doped GaN material.

4. A tensile strain high hole mobility field effect transistor as claimed in claim 2, characterized in that: The blind hole is prepared by inductively coupled plasma etching.

5. The tensile strain high hole mobility field effect transistor according to claim 2, characterized in that: The thickness of the substrate is 2 μm-4 μm, the diameter of the blind hole is 1 μm-3 μm, and the depth is 100 nm-800 nm; the center distance between two adjacent blind holes is 6 μm-10 μm; The thickness of the buffer layer is 2 μm-4 μm; The thickness of the barrier layer is 15nm-60nm; The thickness of the insertion layer is 1nm-3nm; The thickness of the space isolation layer is 5nm-10nm; The dopant of the hole supply layer is Mg, and the doping concentration is 1×10 19 cm -3 -6×10 19 cm -3 , thickness is 20nm-80nm.

6. A method for preparing a tensile strain high hole mobility field effect transistor, characterized in that: The following steps are involved: Step 1: growing a substrate on a base substrate; wherein the substrate is made of polycrystalline AlN material; Step 2: preparing a plurality of blind holes on the substrate, wherein the plurality of blind holes are evenly arranged; Step 3, growing a buffer layer on the substrate; wherein the material of the buffer layer grows on the substrate surface and the sidewalls of the plurality of blind holes and merges to introduce tensile strain; Step 4: grow a barrier layer on the buffer layer, grow an insertion layer on the barrier layer, grow a space isolation layer on the insertion layer, grow a hole supply layer on the space isolation layer, and prepare a source electrode, a drain electrode and a gate electrode on the hole supply layer.

7. The method for preparing a tensile strain high hole mobility field effect transistor according to claim 6, characterized in that: The plurality of blind holes form an array, and two adjacent columns or rows of blind holes are staggered with each other.

8. The method for preparing a tensile strain high hole mobility field effect transistor according to claim 6, characterized in that: The specific steps of step one include: The substrate is grown on the base substrate by adopting a controlled sputtering method or a physical vapor transport method.

9. The method for preparing a tensile strain high hole mobility field effect transistor according to claim 6, characterized in that: The specific steps of step 2 include: A plurality of blind holes are etched on the substrate by inductively coupled plasma etching.

10. The method for preparing a tensile strain high hole mobility field effect transistor according to claim 6, characterized in that: The buffer layer is made of GaN material and has a thickness of 2 μm-4 μm; The barrier layer is made of AlGaN material with an Al component of 20%-40% and a thickness of 15nm-60nm; The insertion layer is made of AlN material with a thickness of 1nm-3nm; The space isolation layer is made of GaN material with a thickness of 5nm-10nm; The hole supply layer is made of p-type doped GaN material, the dopant is Mg, and the doping concentration is 1×10 19 cm -3 -6×10 19 cm -3 , thickness is 20nm-80nm.

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