A gallium nitride transistor and a method of fabricating the same

Abstract

The application discloses a gallium nitride transistor and a preparation method thereof, and relates to the technical field of semiconductor devices. The gallium nitride transistor comprises a substrate, a plurality of superlattice structures arranged in sequence on one side of the substrate, and interval cavities between adjacent two superlattice structures. The superlattice structure comprises a channel layer and a barrier layer arranged in a stack. The channel layer and the barrier layer of each second superlattice structure, the barrier layer of a first superlattice structure, and a first groove and a second groove located on opposite sides of each superlattice structure are penetrated. A source and a drain are respectively located in the first groove and the second groove and are in contact with each superlattice structure. A dielectric structure is located between the source and the drain, is located in each interval cavity, and covers the surface of each superlattice structure. A gate is located between the source and the drain and is arranged around the dielectric structure. According to the technical scheme, the gate around the dielectric structure covering the surface of each superlattice structure is arranged, and the control effect of the gate on the conductive channel layer is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a gallium nitride transistor and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) has a wide bandgap and high saturated electron drift velocity, making high electron mobility transistors (HEMTs) based on gallium nitride a promising candidate for next-generation high-power, high-frequency switching applications.

[0003] In existing technologies, superlattice epitaxial structures are commonly used to increase the current density of gallium nitride (GaN) transistors, effectively improving carrier transport and enhancing GaN transistor performance. However, due to the relatively thick conductive channel layer in the superlattice epitaxial structure, the gate's control over carrier flow in the conductive channel layer is poor, thus limiting the performance and stability of GaN transistors. Therefore, it is urgent to solve the technical problem of poor gate control over the conductive channel layer in the superlattice epitaxial structure of GaN transistors. Summary of the Invention

[0004] This invention provides a gallium nitride transistor and its fabrication method to improve the control effect of the gate on the conductive channel layer, thereby enhancing the performance and stability of the gallium nitride transistor.

[0005] A first aspect of the present invention provides a gallium nitride transistor, the gallium nitride transistor comprising:

[0006] Substrate;

[0007] A plurality of superlattice structures are located on one side of the substrate and arranged sequentially; there is a spacer cavity between any two adjacent superlattice structures; each superlattice structure includes a channel layer and a barrier layer stacked together; the superlattice structure closest to the substrate is the first superlattice structure, and the other superlattice structures located on the side of the first superlattice structure away from the substrate are all second superlattice structures.

[0008] A first trench and a second trench penetrate the channel layer and the barrier layer of each of the second superlattice structures, as well as the barrier layer of the first superlattice structure; the first trench and the second trench are located on opposite sides of each of the superlattice structures;

[0009] The source electrode is located in the first trench and in contact with each of the superlattice structures, and the drain electrode is located in the second trench and in contact with each of the superlattice structures;

[0010] A dielectric structure located between the source and the drain and within each of the spacers and covering the surface of each of the superlattice structures;

[0011] A gate located between the source and the drain and surrounding the dielectric structure.

[0012] Optionally, the dielectric structure includes at least a gate dielectric layer located between the source and the drain and covering each of the superlattice surfaces, and covering each of the superlattice surfaces within the spaced cavity, as well as the source and drain surfaces.

[0013] Optionally, the dielectric structure further includes a conductive dielectric layer located on the side of the gate dielectric layer opposite to the superlattice structure and covering the gate dielectric layer.

[0014] Optionally, the gate dielectric layer includes at least one of a silicon oxide layer and an aluminum oxide layer, and the conductive dielectric layer includes a titanium nitride layer.

[0015] Optionally, along the arrangement direction of each superlattice structure, the thickness L1 of the spacer cavity between two adjacent superlattice structures ranges from 20nm to 70nm.

[0016] Optionally, the thickness L2 of the channel layer is in the range of 15nm≤L2≤100nm;

[0017] The thickness L3 of the barrier layer has a range of 15nm ≤ L3 ≤ 50nm.

[0018] Optionally, along the arrangement direction of the first groove and the second groove, the width W1 of the first groove has a range of values ​​of W1≥5μm, and the width W2 of the second groove has a range of values ​​of W2≥5μm.

[0019] A second aspect of the present invention provides a method for fabricating a gallium nitride transistor, the method comprising:

[0020] Provide substrate;

[0021] Multiple superlattice structures and a barrier layer located between two adjacent superlattice structures are sequentially formed on one side of the substrate; wherein, the superlattice structure includes a channel layer and a barrier layer stacked together; the superlattice structure closest to the substrate is the first superlattice structure, and the other superlattice structures located on the side of the first superlattice structure away from the substrate are all second superlattice structures;

[0022] A first trench and a second trench are formed, penetrating the channel layer and barrier layer of each of the second superlattice structures and the barrier layer of the first superlattice structure; wherein the first trench and the second trench are located on opposite sides of each of the superlattice structures;

[0023] A source electrode in contact with each of the superlattice structures is formed in the first trench, and a drain electrode in contact with each of the superlattice structures is formed in the second trench;

[0024] Remove the barrier layers between each of the superlattice structures;

[0025] A dielectric structure is formed between the source and the drain; wherein the dielectric structure is located within each of the spacer cavities and on the surface covering each of the superlattice structures;

[0026] A gate is formed between the source and the drain, and surrounding the dielectric structure.

[0027] Optionally, a dielectric structure is formed between the source and the drain, comprising:

[0028] A gate dielectric layer is formed between the source and the drain and covering each of the superlattice surfaces, as well as covering each of the superlattice surfaces within the spaced cavity and the surfaces of the source and the drain;

[0029] A conductive dielectric layer is formed on the side opposite to the superlattice structure and covering the gate dielectric layer.

[0030] Optionally, removing the barrier layer between each of the superlattice structures includes:

[0031] Selective etching was performed using a hydrofluoric acid solution to remove the barrier layers between the superlattice structures.

[0032] The technical solution of this invention improves the current carrying capacity of gallium nitride transistors by forming multiple superlattice structures arranged sequentially on one side of the substrate of a gallium nitride transistor. Each superlattice structure includes a channel layer and a barrier layer stacked together to form multiple conductive channels. After patterning the multiple superlattice structures, a first trench and a second trench are formed on opposite sides of the multiple superlattice structures. A source is formed in the first trench and a drain is formed in the second trench. Both the source and drain are in direct contact with the channel layer in the first superlattice structure, which helps to reduce contact resistance, ensure the structural stability of the gallium nitride transistor, and guarantee the effective transport of charge carriers in the conductive channels of the gallium nitride transistor. Furthermore, by setting a dielectric structure covering the surface of each superlattice structure between the source and drain and within each spaced cavity, the depletion effect of the gallium nitride transistor can be enhanced while ensuring good contact between adjacent superlattice structures. This effectively reduces leakage current between adjacent superlattice structures, lowers energy loss, and improves the electrical performance of the gallium nitride transistor. Simultaneously, by setting a gate between the source and drain and surrounding the dielectric structure, the dielectric structure can form electrical isolation between each superlattice structure and the gate, avoiding current leakage and interference. The gate can more comprehensively cover and control each superlattice structure in multiple superlattice structures, and can more effectively control the carrier transport efficiency and performance in the conductive channel of the gallium nitride transistor. This improves the gate's control effect on the conductive channel layer of the gallium nitride transistor, thereby enhancing the performance and stability of the gallium nitride transistor.

[0033] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of a gallium nitride transistor device structure provided in an embodiment of the present invention;

[0036] Figure 2 This is a schematic diagram of another gallium nitride transistor device structure provided in an embodiment of the present invention;

[0037] Figure 3 This is a schematic flowchart of a method for fabricating a gallium nitride transistor according to an embodiment of the present invention;

[0038] Figure 4 This is a schematic diagram of the fabrication process of a gallium nitride transistor provided in an embodiment of the present invention;

[0039] Figure 5 This is a schematic flowchart of a method for preparing a dielectric structure according to an embodiment of the present invention;

[0040] Figure 6 This is a schematic diagram of the preparation process of a dielectric structure provided in an embodiment of the present invention. Detailed Implementation

[0041] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0043] Figure 1 This is a schematic diagram of a gallium nitride transistor device structure provided in an embodiment of the present invention, as shown below. Figure 1As shown, a gallium nitride transistor includes: a substrate 1; multiple superlattice structures arranged sequentially on one side of the substrate 1; a spacer cavity between any two adjacent superlattice structures; each superlattice structure includes a channel layer 01 and a barrier layer 02 stacked together; the superlattice structure closest to the substrate 1 is a first superlattice structure 201, and the other superlattice structures located on the side of the first superlattice structure 201 away from the substrate 1 are all second superlattice structures; the channel layer 01 and barrier layer 02 penetrating each second superlattice structure, and the first superlattice junction... The barrier layer 02 of structure 201 has a first trench 21 and a second trench 22; the first trench 21 and the second trench 22 are located on opposite sides of each superlattice structure; a source 501 located in the first trench 21 and in contact with each superlattice structure, and a drain 503 located in the second trench 22 and in contact with each superlattice structure; a dielectric structure 4 located between the source 501 and the drain 503 and within each spacer cavity, and covering the surface of each superlattice structure; and a gate 502 located between the source 501 and the drain 503 and surrounding the dielectric structure.

[0044] Specifically, substrate 1 can be understood as the material that supports the entire device structure of the gallium nitride transistor. For example, substrate 1 can be one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, and silicon, or any other material capable of growing group III nitrides.

[0045] Multiple superlattice structures are arranged sequentially on one side of substrate 1. The superlattice structure closest to substrate 1 is the first superlattice structure 201, and the other superlattice structures located on the side of the first superlattice structure 201 away from substrate 1 are all second superlattice structures. The specific number of superlattice structures can be designed according to actual needs. This embodiment of the invention does not specifically limit this number. For ease of description, unless otherwise specified, please refer to the following. Figure 1In this embodiment of the invention, a first superlattice structure 201, a first second superlattice structure 202, a second second superlattice structure 203, and a third second superlattice structure 204 are provided on one side of a substrate 1 to illustrate the technical solution of the present invention. Each of the first superlattice structure 201, the first second superlattice structure 202, the second second superlattice structure 203, and the third second superlattice structure 204 includes a channel layer 01 and a barrier layer 02 stacked together. For example, the channel layer 01 can be a GaN layer, and the barrier layer 02 can be an AlGaN layer; that is, a combination of periodically stacked GaN and AlGaN layers is provided on one side of the substrate 1. Understandably, in each superlattice structure, the AlGaN layer has a larger bandgap, while the GaN layer has a smaller bandgap and higher carrier mobility. When AlGaN and GaN layers are stacked, the GaN layer provides a channel with high carrier mobility. Simultaneously, the larger bandgap of the AlGaN layer helps form a stable energy level structure between the AlGaN and GaN layers. This energy level structure prevents carrier scattering in the conductive channels of the gallium nitride transistor, thereby improving the carrier transport efficiency and current density of the gallium nitride transistor. It is also understandable that setting multiple superlattice structures arranged sequentially on one side of substrate 1 is equivalent to forming multiple conductive channels on one side of substrate 1, thus increasing the number of carrier transport channels. Through the parallel effect of multiple conductive channels, the movement path of carriers in the device becomes more diversified and balanced, reducing congestion when carriers migrate in a single channel, thereby improving the current carrying capacity of the gallium nitride transistor and significantly improving its current transport efficiency and performance. Furthermore, the first superlattice structure 201 is located at the bottom layer of multiple superlattice structures and is in contact with the substrate 1. The first superlattice structure 201 is the first superlattice structure formed. The GaN layer in the first superlattice structure 201 can serve as a buffer layer to reduce the stress caused by lattice mismatch between the substrate 1 and multiple superlattice structures. This helps to optimize the growth and performance of subsequent layer structures, thereby improving the overall stability of the gallium nitride transistor structure and the electrical performance of the gallium nitride transistor.

[0046] It is also understandable that a spacer cavity can be set between any two adjacent superlattice structures; for example, continue to refer to... Figure 1A first spacer cavity 301 is provided between the first superlattice structure 201 and the first and second superlattice structures 202; a second spacer cavity 302 is provided between the first and second superlattice structures 202 and 203; and a third spacer cavity 303 is provided between the second and third superlattice structures 203 and 204. By forming spacer cavities between any two adjacent superlattice structures, a basis is provided for subsequently forming dielectric structures covering the surfaces of each superlattice structure within each spacer cavity. This effectively reduces charge interference between adjacent superlattice structures, contributing to improved stability and reliability of gallium nitride transistors. Furthermore, it reduces carrier leakage between adjacent superlattice structures, thereby reducing energy loss and improving the efficiency and stability of gallium nitride transistors.

[0047] Continue to refer to Figure 1 After patterning multiple superlattice structures, a first trench 21 and a second trench 22 can be formed on opposite sides of the multiple superlattice structures along the first direction X. Specifically, the first trench 21 and the second trench 22 can be understood as recesses formed on opposite sides of the multiple superlattice structures along the first direction X, which are used to define the source region and drain region in the gallium nitride transistor, providing a basis for the subsequent formation of the source 501 in the first trench 21 and the drain 503 in the second trench 22. Furthermore, the first trench 21 and the second trench 22 penetrate the channel layer 01 and barrier layer 02 of each of the second superlattice structures, as well as the barrier layer 02 of the first superlattice structure 201. That is, the bottom of the first trench 21 and the second trench 22 are both the channel layer 01 in the first superlattice structure 201, so that the source 501 formed in the first trench 21 and the drain 503 formed in the second trench 22 can directly contact the GaN layer in the first superlattice structure 201, thereby forming an ohmic contact with a low Schottky barrier. This helps to reduce contact resistance, facilitates the transport of charge carriers between the source 501 and the drain 503, and improves the electrical performance and power consumption characteristics of the gallium nitride transistor. It is also understood that the width of the first trench 21 along the first direction X and the width of the second trench 22 along the first direction X can be the same, so as to ensure that the width of the source 501 formed in the first trench 21 along the first direction X and the width of the drain 503 formed in the second trench 22 along the first direction X are the same, so that the charge carriers can flow uniformly between the source 501 and the drain 503, thereby optimizing the performance and stability of the gallium nitride transistor.

[0048] Furthermore, a source 501 is disposed in the first trench 21, and a drain 503 is disposed in the second trench 22. Both the source 501 and the drain 503 are in contact with the GaN layer at the bottom of the first trench 21 and the second trench 22, which helps to reduce contact resistance. At the same time, both the source 501 and the drain 503 are also in contact with each superlattice structure. For example, continue to refer to Figure 1 The width of the source 501 along the first direction X is equal to the width of the first trench 21 along the first direction X, and the width of the drain 503 along the first direction X is equal to the width of the second trench 22 along the first direction X. Furthermore, the height of the source 501 and the drain 503 along the second direction Y is consistent with the height of the multiple superlattice structures along the second direction Y, which ensures the structural stability of the gallium nitride transistor and the effective transport of charge carriers in the conductive channel of the gallium nitride transistor.

[0049] A dielectric structure 4 covering the surface of each superlattice structure is disposed between the source electrode 501 and the drain electrode 503 and within each spaced cavity. (Continuing to refer to...) Figure 1 The dielectric structure 4 is located in the first spacer cavity 301 between the first superlattice structure 201 and the first second superlattice structure 202, the second spacer cavity 302 between the first second superlattice structure 202 and the second second superlattice structure 203, and the third spacer cavity 303 between the second second superlattice structure 203 and the third second superlattice structure 204. At the same time, the dielectric structure 4 covers the surfaces of the first second superlattice structure 202, the second second superlattice structure 203, and the third second superlattice structure 204, so that the first superlattice structure 201, the first second superlattice structure 202, the second second superlattice structure 203, and the third second superlattice structure 204 can be stably contacted through the dielectric structure 4. It is understandable that by providing a dielectric structure 4 covering the surface of each superlattice structure between the source 501 and the drain 503 and within each spaced cavity, the depletion effect of the gallium nitride transistor can be enhanced while ensuring good contact between any two adjacent superlattice structures. This effectively reduces leakage current between adjacent superlattice structures and lowers energy loss. Simultaneously, when the gate surrounding the dielectric structure 4 is subsequently generated, the dielectric structure 4 can form electrical isolation between each superlattice structure and the gate, thereby avoiding current leakage and interference. The gate can more effectively control the carrier transport efficiency and performance in the conductive channel of the gallium nitride transistor, thus improving the efficiency and reliability of the gallium nitride transistor. It is also understandable that the first superlattice structure 201 is the basic structure among multiple superlattice structures, and no dielectric structure is provided corresponding to the first superlattice structure 201 to ensure the structural stability and reliability of the gallium nitride transistor.

[0050] Furthermore, a gate 502 is disposed between the source 501 and the drain 503 and surrounding the dielectric structure. When a voltage is applied to the gate 502 and the threshold voltage of the gallium nitride transistor is reached, a current channel can be formed between the source 501 and the drain 503, allowing charge carriers to flow between the source 501 and the drain 503, thereby generating current and turning on the gallium nitride transistor. When the voltage applied to the gate 502 does not meet the threshold voltage condition of the gallium nitride transistor, a current channel cannot be formed between the source 501 and the drain 503, thereby turning on the gallium nitride transistor. Because the gate 502 is arranged around the dielectric structure, and the dielectric structure is located within each spaced cavity and covers the surface of each superlattice structure, the gate 502 can more comprehensively cover and control each superlattice structure in the multiple superlattice structures. This increases the control area of ​​the gate 502 over the conductive channel, thereby improving the control effect of the gate 502 on the conductive channel layer of the gallium nitride transistor, enhancing the depletion effect of the gallium nitride transistor, effectively reducing the leakage current between two adjacent superlattice structures, and improving the switching speed and performance of the gallium nitride transistor. It is understood that, provided that the width of the gate 502 along the first direction X is less than the width of the multiple superlattice structures along the first direction X, and that the gate 502 can surround the dielectric structure, the width of the gate 502 along the first direction X and the height along the second direction Y can be designed according to actual needs, and this embodiment of the invention does not specifically limit this.

[0051] In this embodiment, by forming multiple superlattice structures arranged sequentially on one side of the substrate of the gallium nitride (GaN) transistor, each superlattice structure includes a stacked channel layer and a barrier layer to form multiple conductive channels, the current carrying capacity of the GaN transistor is improved. After patterning the multiple superlattice structures, a first trench and a second trench are formed on opposite sides of the multiple superlattice structures. The source is formed in the first trench and the drain is formed in the second trench. Both the source and drain are in direct contact with the channel layer in the first superlattice structure, which helps to reduce contact resistance, ensure the structural stability of the GaN transistor, and guarantee the effective transport of charge carriers in the conductive channels of the GaN transistor. In addition, by providing a dielectric structure covering the surface of each superlattice structure between the source and drain and in each spacer cavity, the depletion effect of the GaN transistor can be enhanced while ensuring good contact between two adjacent superlattice structures. This effectively reduces the leakage current between two adjacent superlattice structures, reduces energy loss, and improves the electrical performance of the GaN transistor. Meanwhile, by placing the gate between the source and drain and around the dielectric structure, the dielectric structure can form electrical isolation between each superlattice structure and the gate, avoiding current leakage and interference. The gate can more comprehensively cover and control each superlattice structure in multiple superlattice structures. The gate can more effectively control the carrier transport efficiency and performance in the conductive channel of the gallium nitride transistor, thereby improving the gate's control effect on the conductive channel layer of the gallium nitride transistor and improving the performance and stability of the gallium nitride transistor.

[0052] Optional, Figure 2 This is a schematic diagram of another gallium nitride transistor device structure provided in an embodiment of the present invention, as shown below. Figure 2 As shown, the dielectric structure 4 includes at least a gate dielectric layer 6 located between the source 501 and the drain 503 and covering each superlattice surface, as well as covering each superlattice surface within the spaced cavity and the surfaces of the source 501 and the drain 503.

[0053] Specifically, the gate dielectric layer 6 fills the first spacer cavity 301 between the first superlattice structure 201 and the first and second superlattice structures 202, the second spacer cavity 302 between the first and second superlattice structures 202 and the second and second superlattice structures 203, and the third spacer cavity 303 between the second and second superlattice structures 203 and the third and second superlattice structures 204. The gate dielectric layer 6 covers the surfaces of the first and second superlattice structures 202, the second and second superlattice structures 203, and the third and second superlattice structures 204, thus covering the perimeter of each superlattice structure. Specifically, the gate dielectric layer 6 can be understood as an insulating layer used to isolate the gate 502 from each superlattice structure. In an optional embodiment, the gate dielectric layer 6 includes at least one of a silicon oxide layer and an aluminum oxide layer. Both silicon oxide and aluminum oxide layers have good insulating properties, which helps to optimize the performance and reliability of gallium nitride transistors. It is understandable that by providing a gate dielectric layer covering the surfaces of each superlattice and the surfaces of each superlattice within the spaced cavities, electrical isolation can be formed between each superlattice structure and the gate 502 through the gate dielectric layer 6, thereby avoiding current leakage and interference. Simultaneously, the width of the gate dielectric layer 6 along the first direction X is equal to the width of the multiple superlattice structures along the first direction X, allowing the gate dielectric layer 6 to contact the surfaces of the source 501 and drain 503 in the first trench 21 and second trench 22 located on opposite sides of the multiple superlattice structures along the first direction X. This allows the gate dielectric layer 6 to also act as an insulating layer isolating the source 501 and drain 503 from each superlattice structure. When the gate voltage abnormally increases, the gate dielectric layer 6 can protect the gallium nitride transistor, thereby improving the performance and stability of the gallium nitride transistor. It is also understandable that the first superlattice structure 201 is the basic structure among multiple superlattice structures. If a gate dielectric layer 6 is set for the first superlattice structure 201, it may cause several superlattice structures to become unstable, increasing the risk of instability of gallium nitride transistors, and may even cause them to fall or be damaged. Therefore, a gate dielectric layer 6 is not set for the first superlattice structure 201 to ensure the structural stability and reliability of gallium nitride transistors.

[0054] Optional, continue to refer to Figure 2 The dielectric structure 4 also includes a conductive dielectric layer 7 located on the side of the gate dielectric layer 6 away from the superlattice structure and covering the gate dielectric layer 6.

[0055] Specifically, the conductive dielectric layer 7 is located on the side of the gate dielectric layer 6 away from the superlattice structure and covers the gate dielectric layer 6. That is, the conductive dielectric layer 7 fills the first spacer cavity 301 between the first superlattice structure 201 and the first second superlattice structure 202, the second spacer cavity 302 between the first second superlattice structure 202 and the second second superlattice structure 203, and the third spacer cavity 303 between the second second superlattice structure 203 and the third second superlattice structure 204, and covers the outer periphery of the gate dielectric layer 6, so that the first superlattice structure 201, the first second superlattice structure 202, the second second superlattice structure 203 and the third second superlattice structure can be stably contacted through the conductive dielectric layer 7. Specifically, the conductive dielectric layer 7 can be understood as a hierarchical structure with certain conductivity. In an optional embodiment, the conductive dielectric layer 7 includes a titanium nitride layer. The titanium nitride layer has low resistivity and good conductivity, which effectively improves the interface characteristics between each superlattice structure and the gate, improves the carrier transport efficiency in the conductive channel of the gallium nitride transistor, and helps to optimize the performance and reliability of the gallium nitride transistor. It is understood that by setting the conductive dielectric layer 7 covering the gate dielectric layer 6 on the side of the gate dielectric layer 6 away from the superlattice structure, the depletion effect of the gallium nitride transistor can be enhanced while ensuring good contact between two adjacent superlattice structures. This effectively reduces the leakage current between two adjacent superlattice structures and reduces energy loss. At the same time, when the gate 502 surrounding the conductive dielectric layer 7 is subsequently generated, the gate 502 can more effectively control the carrier transport efficiency and performance in the conductive channel of the gallium nitride transistor, thereby improving the efficiency and reliability of the gallium nitride transistor. Furthermore, because a gate dielectric layer 6 is disposed between the conductive dielectric layer 7 and the source 501 and drain 503, the width of the conductive dielectric layer along the first direction X is smaller than the width of the multiple superlattice structures between the source 501 and drain 503 along the first direction X. This ensures that the conductive dielectric layer does not directly contact the source 501 and drain 503 in the first trench 21 and second trench 22 formed on opposite sides of the multiple superlattice structures along the first direction X, thereby effectively preventing short circuits between the source 501 and drain 503 and improving the stability and reliability of the gallium nitride transistor. It can also be understood that the first superlattice structure 201 is the basic structure among the multiple superlattice structures. To avoid instability in several superlattice layers, a gate dielectric layer 6 is not disposed corresponding to the first superlattice structure 201. Similarly, a conductive dielectric layer 7 is not disposed corresponding to the first superlattice structure 201 to ensure the structural stability and reliability of the gallium nitride transistor.

[0056] Optional, continue to refer to Figure 2 As shown, along the arrangement direction of each superlattice structure, the thickness L1 of the spacer cavity between two adjacent superlattice structures ranges from 20nm to 70nm.

[0057] Specifically, along the arrangement direction of each superlattice structure, i.e. along the second direction Y, the thickness L1 of the spacer cavity between two adjacent superlattice structures is between 20 nm and 70 nm. This thickness range provides a certain range of thickness variation for the dielectric structure that fills the spacer cavity between two adjacent superlattice structures and covers the surface of each superlattice structure. Under the premise of ensuring that the two adjacent dielectric structures are in contact with each other, the thickness of each dielectric structure can be designed according to actual needs, thereby adjusting the electrical performance and characteristics of gallium nitride transistors to meet different application requirements and optimize the performance and stability of gallium nitride transistors.

[0058] Optional, continue to refer to Figure 2 As shown, the thickness L2 of the channel layer 01 ranges from 15nm to 100nm; the thickness L3 of the barrier layer 02 ranges from 15nm to 50nm.

[0059] Specifically, in each of the multiple superlattice structures, the thickness L2 of the GaN channel layer is between 15 nm and 100 nm, and the thickness L3 of the AlGaN barrier layer is between 15 nm and 50 nm. This range of GaN and AlGaN layer thicknesses ensures both a moderate thickness for each superlattice structure and the stability of the gallium nitride transistor. It is understood that a thicker GaN layer helps reduce surface states and defects, thereby increasing carrier mobility. Therefore, setting the GaN layer thickness L2 between 15 nm and 100 nm helps the GaN layer form channels with high carrier mobility. Setting the AlGaN layer thickness L3 between 15 nm and 50 nm ensures a stable energy level structure between the AlGaN and GaN layers, preventing carrier scattering in the conductive channel of the gallium nitride transistor, thus improving the carrier transport efficiency and current density of the gallium nitride transistor. By setting the thickness of each GaN layer and each AlGaN layer in a multi-layer superlattice structure within an appropriate range, the performance and stability of gallium nitride transistors were optimized.

[0060] Optional, continue to refer to Figure 2 As shown, along the arrangement direction of the first groove 21 and the second groove 22, the width W1 of the first groove 21 has a range of values ​​of W1≥5μm, and the width W2 of the second groove 22 has a range of values ​​of W2≥5μm.

[0061] Specifically, the width W1 of the first trench 21 formed after patterning multiple superlattice structures along the arrangement direction of the first trench 21 and the second trench 22 is greater than or equal to 5 μm, that is, the width W1 of the first trench 21 along the first direction X is greater than or equal to 5 μm. The width W2 of the second trench 22 formed after patterning multiple superlattice structures along the arrangement direction of the first trench 21 and the second trench 22 is greater than or equal to 5 μm, that is, the width W2 of the second trench 22 along the first direction X is greater than or equal to 5 μm. It is understood that the source 501 is disposed in the first trench 21 and the drain 503 is disposed in the second trench 22. Therefore, the width of the first trench 21 and the second trench 22 along the first direction X is both greater than or equal to 5μm. This ensures that the first trench 21 and the second trench 22 can provide sufficient space to accommodate the source 501 and the drain 503, so that the width of the formed source 501 and drain 503 along the first direction X is appropriate. This ensures the structural stability of the gallium nitride transistor and the effective transport of charge carriers in the conductive channel of the gallium nitride transistor, thereby improving the performance and stability of the gallium nitride transistor.

[0062] Based on the same inventive concept, this invention also provides a method for fabricating a gallium nitride transistor. Figure 3 This is a schematic flowchart of a gallium nitride transistor fabrication method provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of the fabrication process of a gallium nitride transistor according to an embodiment of the present invention, combined with... Figure 3 and Figure 4 As shown, the method for fabricating this gallium nitride transistor includes:

[0063] S101, Provide substrate.

[0064] Specifically, substrate 1 can be understood as the material that supports the entire device structure of the gallium nitride transistor. For example, substrate 1 can be one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, and silicon, or any other material capable of growing group III nitrides.

[0065] S102, Multiple superlattice structures and a barrier layer located between two adjacent superlattice structures are sequentially formed on one side of the substrate.

[0066] The superlattice structure includes a channel layer and a barrier layer stacked together. The superlattice structure closest to the substrate is the first superlattice structure, and the other superlattice structures located on the side of the first superlattice structure away from the substrate are the second superlattice structures.

[0067] Specifically, using epitaxial growth technology, multiple superlattice structures and a barrier layer 03 located between two adjacent superlattice structures are formed on one side of substrate 1. Each superlattice structure includes a channel layer 01 and a barrier layer 02 stacked together. For example, the channel layer 01 can be a GaN layer, the barrier layer 02 can be an AlGaN layer, and the barrier layer 03 can be a SiN layer or a SiO2 layer. In an optional embodiment, GaN, AlGaN, and SiN layers can be sequentially deposited on one side of substrate 1 using epitaxial growth technology. This forms multiple stacked superlattice structures and a barrier layer 03 located between two adjacent superlattice structures on one side of substrate 1, effectively forming multiple conductive channels on one side of substrate 1. This increases the number of carrier transport channels and significantly improves the current transport efficiency and performance of gallium nitride transistors. It is also understandable that by forming a barrier layer between two adjacent superlattice structures through epitaxial growth technology, a foundation is laid for the subsequent formation of spacer cavities between the two adjacent superlattice structures, and for the subsequent formation of dielectric structures covering the surface of each superlattice structure within each spacer cavity. This reduces the leakage of charge carriers between the two adjacent superlattice structures, thereby reducing energy loss and improving the efficiency and stability of gallium nitride transistors.

[0068] It is also understandable that by setting the barrier layer 03 as a SiN layer or a SiO2 layer, a basis is provided for the subsequent removal of the barrier layer between each superlattice structure using wet etching technology. When using wet etching technology to selectively etch multiple superlattice structures, the SiN layer or SiO2 layer has a higher etching rate than the GaN layer and AlGaN layer, so that the SiN layer or SiO2 layer can be etched quickly, while protecting the GaN layer and AlGaN layer from the erosion of wet etching. This helps to maintain the integrity of the GaN layer and AlGaN layer when forming a spacer cavity between two adjacent superlattice structures, thereby improving the performance and stability of gallium nitride transistors.

[0069] S103, forming a first trench and a second trench that penetrate the channel layer and barrier layer of each second superlattice structure, as well as the barrier layer of the first superlattice structure.

[0070] The first trench 21 and the second trench 22 are located on opposite sides of each superlattice structure.

[0071] For example, multiple superlattice structures can be patterned using methods such as photolithography, etching, or laser processing to form a first trench 21 and a second trench 22 within the multiple superlattice structures. Specifically, the first trench 21 and the second trench 22 are recesses formed on both sides along the first direction X in the multiple superlattice structures, used to define the source region and drain region in the gallium nitride transistor. Furthermore, the bottom of both the first trench 21 and the second trench 22 is a GaN layer in the first superlattice structure 201, so that the source 501 formed subsequently in the first trench 21 and the drain 503 formed in the second trench 22 can directly contact the GaN layer in the first superlattice structure 201, thereby forming a low Schottky barrier ohmic contact, which helps to reduce contact resistance and improve the electrical performance and power consumption characteristics of the gallium nitride transistor.

[0072] In an optional embodiment, multiple superlattice structures are patterned using Cl2 / BCl3 plasma through plasma etching technology. - The ion energy breaks the Ga-N bonds in multiple superlattice structures and removes them by using a dry gas, such as nitrogen, thereby achieving precise patterning of multiple superlattice structures and reducing the fabrication cost. This allows for the formation of a first trench 21 and a second trench 22 in multiple superlattice structures, providing a basis for the subsequent formation of a source 501 in the first trench 21 and a drain 503 in the second trench 22.

[0073] S104. A source electrode in contact with each superlattice structure is formed in the first trench, and a drain electrode in contact with each superlattice structure is formed in the second trench.

[0074] For example, the source and drain may be formed by first forming a metal layer on the entire surface of the device, and then removing the metal layer by processes such as photolithography and etching, leaving the metal portions of the source and drain; or by forming the source and drain by processes such as electron beam evaporation and chemical vapor deposition.

[0075] Specifically, both the source 501 and the drain 503 are in contact with the GaN layer at the bottom of the first trench 21 and the second trench 22. At the same time, both the source 501 and the drain 503 are in contact with multiple superlattice structures, which ensures the structural stability of the gallium nitride transistor when the blocking layer between the multiple superlattice structures is removed in the future, and also ensures the effective transport of charge carriers in the conductive channel of the gallium nitride transistor.

[0076] In an optional embodiment, a first metal structure is formed in the first trench 21 and a second metal structure is formed in the second trench 22 using an electron beam evaporation process. The metal structures formed by electron beam evaporation can provide good metal contact, which helps to reduce contact resistance and improve the performance and efficiency of the gallium nitride transistor. Rapid annealing of the first and second metal structures forms the source 501 and drain 503 in the first trench 21 and the second trench 22, respectively. Rapid annealing improves the bonding between the metal structures and the GaN layer at the bottom of the first and second trenches 21 and 22, enhances the stability of the metal-semiconductor relationship, reduces interface resistance, and improves the reliability of the gallium nitride transistor. The first and second metal structures include at least one of Ni, Al, Ti, and Au.

[0077] S105, Remove the barrier layers between each superlattice structure.

[0078] For example, the method of removing the barrier layer 03 between the superlattice structures may include selectively removing the target layer by utilizing the difference in reactivity between the superlattice structures and the barrier layer in a specific chemical solution; or selectively etching by utilizing the difference in physical properties between the superlattice structures and the barrier layer; or selectively etching the barrier layer by adjusting the laser energy and wavelength of the laser etching.

[0079] In an optional embodiment, removing the barrier layer 03 between the superlattice structures includes selective etching with a hydrofluoric acid solution to remove the barrier layer 03 between the superlattice structures.

[0080] Specifically, wet etching technology is used to selectively etch multiple superlattice structures. For example, the etching solution used in the wet etching technology can include HF solution, NH4OH solution, and a mixture of HF solution and NH4OH solution. When selectively etching multiple superlattice structures using the etching solution, the SiN layer or SiO2 layer in the barrier layer 03 has a higher etching rate than the GaN layer and AlGaN layer, so that the SiN layer or SiO2 layer can be etched quickly, while protecting the GaN layer and AlGaN layer from the erosion of wet etching. This helps to maintain the integrity of the GaN layer and AlGaN layer when removing the barrier layer between each superlattice structure, ensuring the formation of spacer cavities between two adjacent superlattice structures. This provides a basis for the subsequent formation of dielectric structures covering the surface of each superlattice structure in each spacer cavity, which can reduce the leakage of charge carriers between two adjacent superlattice structures, thereby reducing energy loss and improving the efficiency and stability of gallium nitride transistors.

[0081] S106, forming a dielectric structure located between the source and drain.

[0082] Among them, the dielectric structure 4 is located in each spaced cavity and on the surface covering each superlattice structure.

[0083] Specifically, using atomic layer deposition (ALD) technology, a dielectric structure 4 is formed on the periphery of each second superlattice structure within multiple superlattice structures. ALD technology can be understood as the alternating deposition of different atomic layers on the periphery of each second superlattice structure to achieve precise formation of the dielectric structure 4 on the periphery of each second superlattice structure. It is understood that the formation of the dielectric structure can include first forming the dielectric structure on the entire device surface, and then removing the dielectric structure portions on the source and drain surfaces through processes such as photolithography and etching, leaving the dielectric structure portions located within the spaced cavities and covering the surfaces of each superlattice structure. It is also understandable that the dielectric structure 4 fills the gaps formed after removing the barrier layer 03 between two adjacent superlattice structures. Simultaneously, the dielectric structure 4 covers the surface of each superlattice structure, achieving enhanced depletion effect of the gallium nitride transistor while ensuring good contact between any two adjacent superlattice structures. This effectively reduces leakage current between adjacent superlattice structures and lowers energy loss. Furthermore, when the gate 502 surrounding the dielectric structure 4 is subsequently generated, the dielectric structure 4 can form electrical isolation between each superlattice structure and the gate 502, thereby avoiding current leakage and interference. The gate 502 can more effectively control the carrier transport efficiency and performance in the conductive channel of the gallium nitride transistor, thus improving the efficiency and reliability of the gallium nitride transistor. It is also understandable that the first superlattice structure 201 is the basic structure among multiple superlattice structures, and the dielectric structure 4 is not provided corresponding to the first superlattice structure 201 to ensure the structural stability and reliability of the gallium nitride transistor.

[0084] In an alternative embodiment, such as Figure 5 and Figure 6 As shown, a dielectric structure 4 is formed between the source and drain, comprising:

[0085] S1061. A gate dielectric layer is formed between the source and drain and covers each superlattice surface, as well as the superlattice surfaces within the spaced cavities and the source and drain surfaces.

[0086] Specifically, using atomic layer deposition (ALD) technology, a gate dielectric layer 6 is formed on the periphery of each second superlattice structure in a plurality of superlattice structures. ALD technology can be understood as depositing different atomic layers alternately layer by layer on the periphery of each second superlattice structure to achieve precise formation of the gate dielectric layer 6 on the outer edge of each second superlattice structure. The gate dielectric layer 6 fills the gaps formed after removing the barrier layer 03 between adjacent superlattice structures and covers the surface of each superlattice structure, thereby forming electrical isolation between the superlattice structure and the subsequently formed gate 502, thus preventing current leakage and interference. In an optional embodiment, the gate dielectric layer 6 includes at least one of a silicon oxide layer and an aluminum oxide layer. Simultaneously, the width of the gate dielectric layer along the first direction X is equal to the width of the multiple superlattice structures along the first direction X, so that the gate dielectric layer 6 can contact the surfaces of the source 501 and drain 503 in the first trench 21 and second trench 22 located on opposite sides of the multiple superlattice structures along the first direction X. This allows the gate dielectric layer 6 to also act as an insulating layer isolating the source 501 and drain 503 from the multiple superlattice structures. When the gate voltage abnormally increases, the gate dielectric layer can protect the gallium nitride transistor, improving its performance and stability. It can also be understood that the first superlattice structure 201 is the basic structure among the multiple superlattice structures, and a gate dielectric layer is not provided corresponding to the first superlattice structure 201 to ensure the structural stability and reliability of the gallium nitride transistor.

[0087] S1062, Form a conductive dielectric layer located on the side opposite to the superlattice structure and covering the gate dielectric layer.

[0088] Specifically, using atomic layer deposition (ALD) technology, a conductive dielectric layer 7 covering the gate dielectric layer 6 is formed on the side facing away from the superlattice structure. ASD can be understood as depositing different atomic layers alternately layer by layer on the gate dielectric layer 6 around each second superlattice structure to achieve precise formation of the conductive dielectric layer 7 on the gate dielectric layer 6 around each second superlattice structure. It is understood that by setting a conductive dielectric layer 7 covering the gate dielectric layer 6 on the side facing away from the superlattice structure, the depletion effect of the gallium nitride transistor can be enhanced while ensuring good contact between adjacent superlattice structures. This effectively reduces the leakage current between adjacent superlattice structures. Simultaneously, when the gate 502 surrounding the conductive dielectric layer 7 is subsequently formed, the gate 502 can more effectively control the carrier transport efficiency and performance in the conductive channel of the gallium nitride transistor, improving the efficiency and reliability of the gallium nitride transistor. In an optional embodiment, the conductive dielectric layer includes a TiN layer. Furthermore, since a gate dielectric layer 6 is disposed between the conductive dielectric layer 7 and the source 501 and drain 503, the width of the conductive dielectric layer 7 along the first direction X is smaller than the width of the multiple superlattice structures along the first direction X. This ensures that the conductive dielectric layer 7 does not directly contact the source 501 and drain 503 located on opposite sides of the multiple superlattice structures along the first direction X, forming the first trench 21 and the second trench 22, thereby effectively preventing short circuits between the source and drain. It can also be understood that the first superlattice structure 201 is the basic structure among the multiple superlattice structures, and no conductive dielectric layer is disposed corresponding to the first superlattice structure 201 to ensure the structural stability and reliability of the gallium nitride transistor.

[0089] S107. A gate is formed between the source and drain and surrounds the dielectric structure.

[0090] For example, the gate can be formed by first forming a metal layer on the entire surface of the device, and then removing part of the metal layer by processes such as photolithography and etching, leaving the metal part of the gate; or by forming the gate by processes such as electron beam evaporation or chemical vapor deposition.

[0091] Specifically, the gate 502 is arranged around the dielectric structure 4, which is located in each spaced cavity and covers the surface of each superlattice structure. Therefore, the gate 502 can more comprehensively cover and control each superlattice structure in multiple superlattice structures, increasing the control area of ​​the channel by the gate 502. This improves the control effect of the gate 502 on the conductive channel layer of the gallium nitride transistor, enhances the depletion effect of the gallium nitride transistor, effectively reduces the leakage current between two adjacent superlattice structures, and improves the switching speed and performance of the gallium nitride transistor.

[0092] In an optional embodiment, a third metal structure surrounding the dielectric structure is formed using an electron beam evaporation process to form the gate 502 surrounding the dielectric structure 4. The electron beam evaporation process enables high-precision metal deposition, ensuring accurate positioning and formation of the gate 502, and improving the stability and electrical performance of the gallium nitride transistor. The third metal structure includes at least one of Ni, Al, Ti, and Au.

[0093] The above-described method for fabricating gallium nitride (GaN) transistors can be used to fabricate the GaN transistors provided in any embodiment of the present invention, which possess the corresponding functions and beneficial effects of GaN transistors. Technical details not described in detail in this embodiment can be found in the GaN transistors provided in any embodiment of the present invention.

[0094] Since the gallium nitride (GaN) transistor fabrication method described above can be used to fabricate the GaN transistor in the embodiments of this invention, those skilled in the art can understand the specific implementation methods and various variations of the GaN transistor fabrication method described in these embodiments based on the GaN transistor. Therefore, how the GaN transistor fabrication method is implemented to fabricate the GaN transistor in the embodiments of this invention will not be described in detail here. Any method used by those skilled in the art to fabricate the GaN transistor in the embodiments of this invention falls within the scope of protection of this application.

[0095] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this invention can be achieved, and this is not limited herein.

[0096] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A gallium nitride transistor, characterized in that, include: Substrate; Multiple superlattice structures are located on one side of the substrate and arranged sequentially; there is a spacer cavity between any two adjacent superlattice structures; The superlattice structure includes a channel layer and a barrier layer stacked together; the superlattice structure closest to the substrate is the first superlattice structure, and the other superlattice structures located on the side of the first superlattice structure away from the substrate are all second superlattice structures. A first trench and a second trench penetrate the channel layer and the barrier layer of each of the second superlattice structures, as well as the barrier layer of the first superlattice structure; the first trench and the second trench are located on opposite sides of each of the superlattice structures; The source electrode is located in the first trench and in contact with each of the superlattice structures, and the drain electrode is located in the second trench and in contact with each of the superlattice structures; A dielectric structure located between the source and the drain and within each of the spacers and covering the surface of each of the superlattice structures; A gate located between the source and the drain and surrounding the dielectric structure.

2. The gallium nitride transistor according to claim 1, characterized in that, The dielectric structure includes at least a gate dielectric layer located between the source and the drain and covering the surfaces of each of the superlattice structures, and covering the surfaces of each of the superlattice structures within the spaced cavity, as well as the surfaces of the source and the drain.

3. The gallium nitride transistor according to claim 2, characterized in that, The dielectric structure further includes a conductive dielectric layer located on the side of the gate dielectric layer opposite to the superlattice structure and covering the gate dielectric layer.

4. The gallium nitride transistor according to claim 3, characterized in that, The gate dielectric layer includes at least one of a silicon oxide layer and an aluminum oxide layer, and the conductive dielectric layer includes a titanium nitride layer.

5. The gallium nitride transistor according to claim 1, characterized in that, Along the arrangement direction of each superlattice structure, the thickness L1 of the spacer cavity between two adjacent superlattice structures ranges from 20nm to 70nm.

6. The gallium nitride transistor according to claim 1, wherein the thickness L2 of the channel layer is in the range of 15nm≤L2≤100nm; The thickness L3 of the barrier layer has a range of 15nm ≤ L3 ≤ 50nm.

7. The gallium nitride transistor according to claim 1, characterized in that, Along the arrangement direction of the first groove and the second groove, the width W1 of the first groove has a range of values ​​of W1≥5μm, and the width W2 of the second groove has a range of values ​​of W2≥5μm.

8. A method for fabricating a gallium nitride transistor, characterized in that, include: Provide substrate; Multiple superlattice structures and a barrier layer located between two adjacent superlattice structures are sequentially formed on one side of the substrate; wherein, the superlattice structure includes a channel layer and a barrier layer stacked together; the superlattice structure closest to the substrate is the first superlattice structure, and the other superlattice structures located on the side of the first superlattice structure away from the substrate are all second superlattice structures; A first trench and a second trench are formed, penetrating the channel layer and barrier layer of each of the second superlattice structures and the barrier layer of the first superlattice structure; wherein the first trench and the second trench are located on opposite sides of each of the superlattice structures; A source electrode in contact with each of the superlattice structures is formed in the first trench, and a drain electrode in contact with each of the superlattice structures is formed in the second trench; Remove the barrier layer between each of the superlattice structures to form a spacer cavity between any two adjacent superlattice structures; A dielectric structure is formed between the source and the drain; wherein the dielectric structure is located within each of the spacer cavities and on the surface covering each of the superlattice structures; A gate is formed between the source and the drain, and surrounding the dielectric structure.

9. The method for fabricating a gallium nitride transistor according to claim 8, characterized in that, Forming a dielectric structure located between the source and the drain includes: A gate dielectric layer is formed between the source and the drain and covers the surfaces of each of the superlattice structures, as well as the surfaces of each of the superlattice structures within the spaced cavity and the surfaces of the source and the drain. A conductive dielectric layer is formed on the side opposite to the superlattice structure and covering the gate dielectric layer.

10. The method for fabricating a gallium nitride transistor according to claim 8, characterized in that, Removing the barrier layers between the superlattice structures includes: Selective etching was performed using a hydrofluoric acid solution to remove the barrier layers between the superlattice structures.

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