Depletion type vertical discrete NMOS element and manufacturing method thereof
By designing depleted vertical discrete NMOS components, using N-type epitaxial layer, P-type well region and gate structures, the problem that existing NMOS components cannot be turned on at low voltages is solved, and efficient performance in low voltage and high power scenarios is achieved.
Patent Information
- Application Number
- CN202311482541.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-08
- Publication Date
- 2025-05-13
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
Existing NMOS components fail to conduct at low gate voltage, limiting their application range, especially in low voltage and high power scenarios.
A depletion-type vertical discrete NMOS element is designed, which includes an N-type epitaxial layer, a P-type well region, a gate, an N-type source and an N-type drain, and connects the P-type well region and the gate through the N-type region to form a channel to achieve conduction and shutdown operations.
This design enables the NMOS element to remain on at low gate voltage, suitable for low voltage and high power applications, while having low leakage current and low loss.
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Figure CN119997549A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a depletion type vertical discrete NMOS element, and in particular to a depletion type vertical discrete NMOS element with a wider application range and a manufacturing method thereof. Background Art
[0002] In the prior art enhancement NMOS device, when the gate voltage is zero or negative, the NMOS device is in the off state, and its source to drain is not conducting. When a positive gate voltage is applied to the gate, an electron channel is formed from the source to the drain, so that the NMOS device enters the conducting state. The prior art NMOS device can only be turned on when the gate has a positive voltage, so it cannot be applied to applications related to low gate voltage, and has a limited application range.
[0003] Based on improving the limitation of the above application range, the present invention proposes a depletion-type vertical discrete NMOS element, which can be suitable for applications such as low gate voltage and high power. The depletion-type vertical discrete NMOS element of the present invention also has the advantages of lower leakage current and low loss. Summary of the invention
[0004] In one aspect, the present invention provides a depletion-type vertical discrete NMOS device, comprising: an N-type epitaxial layer formed on an N-type substrate, the N-type epitaxial layer having a top surface (top a P-type well region formed in the N-type epitaxial layer; a gate formed and connected to the outside of the N-type epitaxial layer; an N-type source formed in the N-type epitaxial layer, wherein the N-type source is adjacent to the P-type well region; an N-type drain including a portion of the N-type substrate, wherein the N-type drain is adjacent to the outside of the N-type epitaxial layer; and an N-type region formed and connected between the P-type well region and the gate to provide a channel, thereby electrically connecting the N-type source and the N-type drain in a conduction operation, and electrically isolating the N-type source and the N-type drain in a turn-off operation; wherein, when a gate voltage of zero voltage is applied to the gate, the depletion-type vertical discrete NMOS element is in the conduction operation.
[0005] In one embodiment, the depletion-mode vertical discrete NMOS device is a planar device, wherein the gate is formed and connected to the upper surface of the N-type epitaxial layer, and the channel is parallel to the upper surface.
[0006] In one embodiment, the depletion-mode vertical discrete NMOS device is a trench device, wherein the gate is formed and connected to a side surface of the N-type epitaxial layer, and the channel is parallel to the side surface and perpendicular to the upper surface.
[0007] In one embodiment, the depletion-mode vertical discrete NMOS device further includes a shielded gate formed below the gate and connected to the N-type epitaxial layer.
[0008] In one embodiment, the N-type substrate or the N-type epitaxial layer is a semiconductor of silicon or silicon carbide.
[0009] In one embodiment, an N-type impurity of the N-type region includes nitrogen, phosphorus, arsenic, antimony or bismuth.
[0010] In one embodiment, the N-type region is formed by an ion implantation process step, wherein an implantation angle of the ion implantation process step is between 0 and 90 degrees.
[0011] In one embodiment, the N-type epitaxial layer has a volume resistivity of 45 Ohm-cm.
[0012] In another aspect, the present invention provides a method for manufacturing a depletion-type vertical discrete NMOS device, comprising: forming an N-type epitaxial layer on an N-type substrate, the N-type epitaxial layer having a top surface and a bottom surface opposite to each other; forming a P-type well region in the N-type epitaxial layer; forming and connecting a gate outside the N-type epitaxial layer; forming an N-type source in the N-type epitaxial layer, wherein the N-type source is adjacent to the P-type well region; forming an N-type drain adjacent to the outside of the N-type epitaxial layer, wherein the N-type drain includes a portion of the N-type substrate; and forming an N-type region connected between the P-type well region and the gate to provide a channel, thereby electrically connecting the N-type source and the N-type drain in an on operation, and electrically isolating the N-type source and the N-type drain in an off operation; wherein, when a gate voltage of zero voltage is applied to the gate, the depletion-type vertical discrete NMOS device is in the on operation.
[0013] In one embodiment, the depletion-mode vertical discrete NMOS device manufacturing method further includes: etching the N-type epitaxial layer to form a trench and the side surface.
[0014] In one embodiment, the depletion-mode vertical discrete NMOS device manufacturing method further includes: forming a shielded gate under the gate and connected to the N-type epitaxial layer.
[0015] In one embodiment, the depletion-mode vertical discrete NMOS device manufacturing method further includes: forming the N-type region by an ion implantation process step, wherein an implantation angle of the ion implantation process step is between 0 and 90 degrees.
[0016] The following is a detailed description through specific embodiments to make it easier to understand the purpose, technical content, characteristics and effects achieved by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 A cross-sectional diagram of a depletion-mode vertical discrete NMOS device is shown according to an embodiment of the present invention.
[0018] Figure 2 A cross-sectional diagram of a depletion-mode vertical discrete NMOS device is shown according to another embodiment of the present invention.
[0019] Figure 3 A cross-sectional diagram of a depletion-mode vertical discrete NMOS device is shown according to another embodiment of the present invention.
[0020] Figure 4A-4E A cross-sectional schematic diagram showing a method for manufacturing a depletion-mode vertical discrete NMOS device according to an embodiment of the present invention.
[0021] Figure 5A-5E A cross-sectional schematic diagram showing a method for manufacturing a depletion-mode vertical discrete NMOS device according to an embodiment of the present invention.
[0022] Figure 6A-6F A cross-sectional schematic diagram showing a method for manufacturing a depletion-mode vertical discrete NMOS device according to an embodiment of the present invention.
[0023] Figure 7A-7F A cross-sectional schematic diagram showing a method for manufacturing a depletion-mode vertical discrete NMOS device according to an embodiment of the present invention.
[0024] Explanation of symbols in the figure
[0025] 10, 20, 30: Depletion-mode vertical discrete NMOS devices
[0026] 11, 21, 31, 41, 51, 61, 71: N-type substrate
[0027] 111, 211, 311, 411, 511, 611, 711: N-type epitaxial layer
[0028] 111a, 211a, 311a, 411a, 511a, 611a, 711a: upper surface
[0029] 111b, 211b, 311b, 411b, 511b, 611b, 711b: bottom surface
[0030] 12, 22, 32, 42, 52, 62, 72: P-type well region
[0031] 13, 23, 33, 43, 53, 63, 73: N-type source
[0032] 14, 24, 34, 44, 54, 64, 74: N-type area
[0033] 141, 241, 341, 441, 541, 641, 741: Channels
[0034] 15, 25, 35, 45, 55, 65, 75: Gate
[0035] 151, 251, 351, 451, 551, 651, 751: Dielectric area
[0036] 152, 252, 352, 452, 552, 652, 752: Conductor area
[0037] 211c, 311c, 611c, 711c: side surface
[0038] 36, 76: Shielding grid
[0039] 361, 761: Dielectric area
[0040] 362, 762: Conductor area DETAILED DESCRIPTION
[0041] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the accompanying drawings. The drawings in the present invention are schematic, mainly intended to show the process steps and the up-down order relationship between the layers, and the shape, thickness and width are not drawn according to scale.
[0042] See also Figure 1 , Figure 1 A cross-sectional view of a depletion-type vertical discrete NMOS device is shown according to an embodiment of the present invention. Figure 1 As shown, the depletion-mode vertical discrete NMOS device 10 includes an N-type epitaxial layer 111 , a P-type well region 12 , a gate 15 , an N-type source 13 , an N-type drain, and an N-type region 14 .
[0043] The N-type epitaxial layer 111 is formed on the N-type substrate 11 and has N-type conductivity. Figure 1 The N-type substrate 11 is, for example but not limited to, an N-type semiconductor N-type substrate. The N-type epitaxial layer 111 is, for example, formed on the N-type substrate 11 by an epitaxial step.
[0044] Please continue reading Figure 1The P-type well region 12 is formed in the N-type epitaxial layer 111 by, for example, an ion implantation process step, and has a P-type conductivity. The gate 15 is formed and connected to the outside of the N-type epitaxial layer 111. The gate 15 includes a dielectric region 151 and a conductor region 152, wherein the dielectric region 151 is located on the upper surface 111a and connected to the upper surface 111a, which is well known to those skilled in the art and will not be described in detail here. The N-type source 13 is formed in the N-type epitaxial layer 111 by, for example, an ion implantation process step, and has an N-type conductivity. Figure 1 As shown, the N-type source 13 is adjacent to the P-type well region 12. The N-type drain includes a portion of the N-type substrate 11, wherein the N-type drain is adjacent to the outside of the N-type epitaxial layer 111, that is, adjacent to the lower surface 111b; from another point of view, the portion of the N-type substrate 11 is used as the N-type drain of the depletion-type vertical discrete NMOS device 10.
[0045] Please continue reading Figure 1 The N-type region 14 is formed in the N-type epitaxial layer 111 by an ion implantation process step, and is connected between the P-type well region 12 and the gate 15 to provide a channel 141, so that the N-type source 13 is electrically connected to the N-type drain during the on operation, and the N-type source 13 is electrically isolated from the N-type drain during the off operation. When the gate voltage applied to the gate 15 is zero voltage, the depletion-type vertical discrete NMOS device 10 is in the on operation.
[0046] In one embodiment, if Figure 1 As shown, the depletion-mode vertical discrete NMOS device 10 is a planar device, wherein the gate 15 is formed and connected to the upper surface 111 a of the N-type epitaxial layer 111 , and the channel 141 is parallel to the upper surface 111 a .
[0047] In one embodiment, the N-type substrate 11 or the N-type epitaxial layer 111 of the depletion-mode vertical discrete NMOS device 10 is a semiconductor of silicon or silicon carbide.
[0048] In one embodiment, the N-type impurities of the N-type region 14 include nitrogen, phosphorus, arsenic, antimony, or bismuth.
[0049] In one embodiment, the N-type epitaxial layer 111 has a volume resistivity of 45 Ohm-cm.
[0050] It should be noted that in Figure 1 In the embodiment of the present invention, the so-called depletion-type vertical discrete NMOS device 10 is a planar device, which means that the depletion-type vertical discrete NMOS device 10 is a planar device in the horizontal direction (such as Figure 1 As indicated by the dashed arrow in the figure, the same below), the N-type region 14 is located on a plane, and the channel 141 is parallel to the upper surface 111a.
[0051] It should be noted that the gate 15 includes a conductive conductor region 152 and a dielectric region 151 connected to the upper surface 111a, wherein the conductor region 152 is used as an electrical contact of the gate 15, formed on and connected to the dielectric region 151. This is well known to those skilled in the art and will not be described in detail here.
[0052] It should be noted that the aforementioned “N-type” and “P-type” refer to the process in which, in a depletion-type vertical discrete NMOS element, impurities of different conductivity types are doped into a semiconductor component region (such as, but not limited to, the aforementioned N-type epitaxial layer 111, the P-type well region 12, the gate 15, the N-type source 13, the N-type drain, and the N-type region 14) to make the semiconductor component region N or P type, wherein the N-type and the P-type are conductivity types with opposite electrical properties to each other.
[0053] See also Figure 2 , Figure 2 According to another embodiment of the present invention, a cross-sectional view of a depletion-type vertical discrete NMOS device is shown. Figure 2 As shown, the depletion-mode vertical discrete NMOS device 20 includes an N-type epitaxial layer 211 , a P-type well region 22 , a gate 25 , an N-type source 23 , an N-type drain, and an N-type region 24 .
[0054] The N-type epitaxial layer 211 is formed on the N-type substrate 21 and has an N-type conductivity. The N-type epitaxial layer 211 has an upper surface 211a and a lower surface 211b opposite to each other in the vertical direction. In this embodiment, the N-type epitaxial layer 211 also has a side surface 211c in the horizontal direction. The N-type substrate 21 is, for example but not limited to, an N-type semiconductor N-type substrate. The N-type epitaxial layer 211 is, for example, formed on the N-type substrate 21 by an epitaxial step.
[0055] Please continue reading Figure 2 The P-type well region 22 is formed in the N-type epitaxial layer 211 by, for example, an ion implantation process step, and has a P-type conductivity. The gate 25 is formed and connected to the outside of the N-type epitaxial layer 211. The gate 25 includes a dielectric region 251 and a conductor region 252, wherein the dielectric region 251 is connected to the side surface 211c. The N-type source 23 is formed in the N-type epitaxial layer 211 by, for example, an ion implantation process step, and has an N-type conductivity. Figure 2 As shown, the N-type source 23 is adjacent to the P-type well region 22. The N-type drain includes a portion of the N-type substrate 21, wherein the N-type drain is adjacent to the outside of the N-type epitaxial layer 211, that is, adjacent to the lower surface 111b; from another point of view, the portion of the N-type substrate 21 is used as the N-type drain of the depletion-type vertical discrete NMOS device 20.
[0056] Please continue reading Figure 2The N-type region 24 is formed in the N-type epitaxial layer 211 by an ion implantation process step, and is connected between the P-type well region 22 and the gate 25 to provide a channel 241, so that the N-type source 23 is electrically connected to the N-type drain during the on operation, and the N-type source 23 is electrically isolated from the N-type drain during the off operation. When the gate voltage applied to the gate 15 is zero voltage, the depletion-type vertical discrete NMOS device 10 is in the on operation.
[0057] In one embodiment, if Figure 2 As shown, the depletion-mode vertical discrete NMOS device 20 is a trench device, wherein the gate 25 is formed and connected to the side surface 211 c of the N-type epitaxial layer 211 , and the channel 241 is parallel to the side surface 211 c and perpendicular to the upper surface 211 a .
[0058] In one embodiment, the N-type substrate 21 or the N-type epitaxial layer 211 of the depletion-mode vertical discrete NMOS device 20 is a semiconductor of silicon or silicon carbide.
[0059] In one embodiment, the N-type impurities of the N-type region 24 include nitrogen, phosphorus, arsenic, antimony, or bismuth.
[0060] In one embodiment, the N-type epitaxial layer 211 has a volume resistivity of 45 Ohm-cm.
[0061] It should be noted that in Figure 2 In the embodiment, the so-called depletion-type vertical discrete NMOS element 20 is a trench element, which means that in the horizontal direction, the N-type epitaxial layer 211 has a sunken trench, and the N-type region 24 is not located on a plane, and the channel 241 is parallel to the side surface 211c and perpendicular to the upper surface 211a.
[0062] See also Figure 3 , Figure 3 A cross-sectional diagram of a depletion-mode vertical discrete NMOS device is shown according to another embodiment of the present invention. Figure 3 The depletion-mode vertical discrete NMOS device 30 is similar to Figure 2 A depletion-type vertical discrete NMOS element 20, such as Figure 3 As shown, the depletion type vertical discrete NMOS device 30 comprises: an N-type epitaxial layer 311, a P-type well region 32, a gate 35, an N-type source 33, an N-type drain, an N-type region 34, and an N-type substrate 31, wherein the gate 35 comprises a dielectric region 351 and a conductor region 352, the N-type epitaxial layer 311 has an upper surface 311a, a lower surface 311b, and a side surface 311c, and the N-type region 34 is used to provide a channel 341. Please refer to the aforementioned structure Figure 2 The description is not repeated here.
[0063] The difference between the depletion type vertical discrete NMOS device 20 and the depletion type vertical discrete NMOS device 30 is that the depletion type vertical discrete NMOS device 30 further includes a shielded gate 36, which is formed below the gate 35 and connected to the N-type epitaxial layer 311. The shielded gate 36 includes a dielectric region 361 and a conductor region 362, wherein the dielectric region 361 is connected to the outside of the side surface 311c. The shielded gate 36 is used to reduce the electric field coupling effect between the gate 35 and the channel 341, thereby improving the performance of the depletion type vertical discrete NMOS device 30. The shielded gate 36 is separated from the gate 35, not directly connected, and electrically disconnected.
[0064] See also Figure 4A-4E , Figure 4A-4E A cross-sectional schematic diagram showing a method for manufacturing a depletion-mode vertical discrete NMOS device according to an embodiment of the present invention. Figure 4A-4E Yes Display Figure 1 An embodiment of a method for manufacturing a depletion-type vertical discrete NMOS element 10. Figure 4A As shown, firstly, an N-type substrate 41 is provided, and then, for example but not limited to, an epitaxial step is used to form an N-type epitaxial layer 411 on the N-type substrate 41. The N-type epitaxial layer 411 is vertically (eg Figure 4A Next, an N-type drain is formed adjacent to the outside of the N-type epitaxial layer 411, wherein the N-type drain includes a portion of the N-type substrate 41. In other words, a portion of the N-type substrate 41 is used as the N-type drain of the depletion-type vertical discrete NMOS device.
[0065] Then, if Figure 4B As shown, for example, a P-type well region 42 is formed in the N-type epitaxial layer 411 by an ion implantation process. In this embodiment, an ion implantation process is first used to implant P-type ions under the upper surface 411a, and the implanted area is connected to the upper surface 411a; when the subsequent N-type region 44 is formed, the N-type ions with a higher concentration implanted will cover the P-type ions with a lower concentration near the upper surface 411a, and the semiconductor region with a P-type conductivity will be converted into an N-type conductivity region. This is well known to those skilled in the art and will not be described in detail here. Next, please refer to Figure 4C For example, an N-type source 43 is formed in the N-type epitaxial layer 411 by an ion implantation process, and the N-type source 43 is adjacent to the P-type well region 42. Figure 4D As shown, an ion implantation process is performed to form an N-type region 44 connected to the P-type well region 42. Figure 4E As shown, a gate 45 is formed and connected to the outside of the N-type epitaxial layer 411 . In this embodiment, the gate 45 includes a dielectric region 451 and a conductor region 452 , wherein the dielectric region 451 is located on the upper surface 411 a and connected to the upper surface 411 a .
[0066] It should be noted that in the above ion implantation process step for forming the N-type region 44, the implantation angle of the ion implantation is between 0 and 90 degrees, and in this embodiment, the implantation angle is 0 degree. It should be noted that the so-called implantation angle of the ion implantation refers to the angle between the advancing direction of the ion beam and the normal direction of the channel in the ion implantation process step.
[0067] Please continue reading Figure 4E The N-type region 44 is connected between the P-type well region 42 and the gate 45 to provide a channel 441, so that the N-type source 43 is electrically connected to the N-type drain during the on operation, and the N-type source 43 is electrically isolated from the N-type drain during the off operation.
[0068] It should be noted that Figure 4A-4E The depletion-type vertical discrete NMOS device manufactured by the manufacturing method is a planar device, that is, the gate 45 is formed and connected to the upper surface 411a of the N-type epitaxial layer 411, in the horizontal direction, the N-type region 44 is located on a plane, and the channel 441 is parallel to the upper surface 411a.
[0069] See also Figure 5A-5E , Figure 5A-5E A cross-sectional schematic diagram showing a method for manufacturing a depletion-mode vertical discrete NMOS device according to an embodiment of the present invention. Figures 5A-5E Yes Display Figure 1 Another embodiment of a method for manufacturing a depletion-type vertical discrete NMOS element 10 is shown. Figure 5A As shown, firstly, an N-type substrate 51 is provided, and then, for example but not limited to, an epitaxial step is used to form an N-type epitaxial layer 511 on the N-type substrate 51, wherein the N-type epitaxial layer 511 has an upper surface 511a and a lower surface 511b opposite to each other in the vertical direction. Then, an N-type drain is formed adjacent to the outer portion and lower portion of the N-type epitaxial layer 511, wherein the N-type drain includes a portion of the N-type substrate 51. In other words, a portion of the N-type substrate 51 is used as an N-type drain of a depletion-type vertical discrete NMOS device.
[0070] Then, if Figure 5B As shown, an ion implantation process is performed to form an N-type region 54 in the N-type epitaxial layer 511. Figure 5C As shown, for example, a P-type well region 52 is formed in the N-type epitaxial layer 511 by an ion implantation process, so that the N-type region 54 is connected to the P-type well region 52. Next, please refer to Figure 5D For example, an N-type source 53 is formed in the N-type epitaxial layer 511 by an ion implantation process, and the N-type source 53 is adjacent to the P-type well region 52. Figure 5EAs shown, a gate 55 is formed and connected to the outside of the N-type epitaxial layer 511. In this embodiment, the gate 55 includes a dielectric region 551 and a conductor region 552, wherein the dielectric region 551 is located on the upper surface 511a and connected to the upper surface 511a.
[0071] It should be noted that in the above ion implantation process step for forming the N-type region 54 , the implantation angle of the ion implantation is between 0 and 90 degrees. In the present embodiment, the implantation angle is 0 degree.
[0072] Please continue reading Figure 5E The N-type region 54 is connected between the P-type well region 52 and the gate 55 to provide a channel 541, so that the N-type source 53 is electrically connected to the N-type drain during the on operation, and the N-type source 53 is electrically isolated from the N-type drain during the off operation.
[0073] It should be noted that Figure 5A-5E The depletion-type vertical discrete NMOS device manufactured by the manufacturing method is a planar device, that is, the gate 55 is formed and connected to the upper surface 511a of the N-type epitaxial layer 511, in the horizontal direction, the N-type region 54 is located on a plane, and the channel 541 is parallel to the upper surface 511a.
[0074] It should be noted that Figure 1 The depletion-type vertical discrete NMOS device 10 of the embodiment can be composed of Figure 4A-4E Made by a manufacturing method or by Figure 5A-5E Made by the manufacturing method.
[0075] See also Figure 6A-6F , Figure 6A-6F A cross-sectional schematic diagram showing a method for manufacturing a depletion-mode vertical discrete NMOS device according to an embodiment of the present invention. Figure 6A-6F Yes Display Figure 2 An embodiment of a method for manufacturing a depletion-type vertical discrete NMOS element 20. Fig. 6A As shown, firstly, an N-type substrate 61 is provided, and then, for example but not limited to, an N-type epitaxial layer 611 is formed on the N-type substrate 61 by an epitaxial step, wherein the N-type epitaxial layer 611 has an upper surface 611a and a lower surface 611b opposite to each other in a vertical direction. Then, an N-type drain is formed adjacent to the outer portion and lower portion of the N-type epitaxial layer 611, wherein the N-type drain includes a portion of the N-type substrate 61. In other words, a portion of the N-type substrate 61 is used as an N-type drain of a depletion-type vertical discrete NMOS device.
[0076] Then, if Figure 6B As shown, for example, a P-type well region 62 is formed in the N-type epitaxial layer 611 by an ion implantation process. Figure 6CAs shown, a portion of the N-type epitaxial layer 611 (including a portion of the P-type well region 62) is etched in the vertical direction to form a trench and a side surface 611c. Fig.6D As shown, an ion implantation process is performed to form an N-type region 64 connected to the P-type well region 62 and the N-type epitaxial layer 611. Fig. 6E As shown, a gate 65 is formed and connected to the outside of the N-type epitaxial layer 611. In this embodiment, the gate 65 includes a dielectric region 651 and a conductor region 652, wherein the dielectric region 651 is connected to the side surface 611c. Fig. 6F As shown, an N-type source 63 is formed in the N-type epitaxial layer 611 by, for example, an ion implantation process, and the N-type source 63 is adjacent to the P-type well region 62 .
[0077] It should be noted that in the above ion implantation process step for forming the N-type region 64 , the implantation angle of the ion implantation is between 0 and 90 degrees.
[0078] Please continue reading Fig. 6F The N-type region 64 is connected between the P-type well region 62 and the gate 65 to provide a channel 641, so that the N-type source 63 is electrically connected to the N-type drain during the on operation, and the N-type source 63 is electrically isolated from the N-type drain during the off operation.
[0079] It should be noted that Figure 6A-6F The depletion-type vertical discrete NMOS element manufactured by the manufacturing method is a trench element, that is, the gate 65 is formed and connected to the side surface 611c of the N-type epitaxial layer 611, in the horizontal direction, the N-type epitaxial layer 611 has a sunken trench, and the N-type region 64 is not located on a plane, and the channel 641 is parallel to the side surface 611c and perpendicular to the upper surface 611a.
[0080] See also Figure 7A-7F , Figure 7A-7F A cross-sectional schematic diagram showing a method for manufacturing a depletion-mode vertical discrete NMOS device according to an embodiment of the present invention. Figure 7A-7F Yes Display Figure 3 A method for manufacturing a depletion-type vertical discrete NMOS element 30 according to an embodiment of the present invention. First, Figure 7A-7D In the present invention, the formation method and steps of the N-type substrate 71, the N-type epitaxial layer 711, the upper surface 711a, the lower surface 711b, the P-type well region 72, the side surface 711c and the N-type region 74 are the same as those of Figure 6A-6D , please refer to the above Figure 6A-6D The description is not repeated here.
[0081] Next, see Fig. 7E, forming a gate 75 and connecting to the outside of the N-type epitaxial layer 711. In this embodiment, the gate 75 includes a dielectric region 751 and a conductor region 752, wherein the dielectric region 751 is connected to the side surface 711c. Fig. 7E As shown, a shield gate 76 is formed below the gate 75 and connected to the N-type epitaxial layer 711. In this embodiment, the shield gate 76 includes a dielectric region 761 and a conductor region 762, and the dielectric region 761 is connected to the side surface 711c. Figure 7F As shown, an N-type source 73 is formed in the N-type epitaxial layer 711 by, for example, an ion implantation process, and the N-type source 73 is adjacent to the P-type well region 72 .
[0082] Please continue reading Figure 7F The N-type region 74 is connected between the P-type well region 72 and the gate 75, and is connected between the N-type epitaxial layer 711 and the shielding gate 76 to provide a channel 741, thereby electrically connecting the N-type source 73 and the N-type drain during the on operation, and electrically isolating the N-type source 73 and the N-type drain during the off operation.
[0083] It should be noted that Figure 7A-7F The depletion-type vertical discrete NMOS element manufactured by the manufacturing method is a trench element, that is, the gate 75 is formed and connected to the side surface 711c of the N-type epitaxial layer 711, in the horizontal direction, the N-type epitaxial layer 711 has a sunken trench, and the N-type region 74 is not located on a plane, and the channel 741 is parallel to the side surface 711c and perpendicular to the upper surface 711a.
[0084] The present invention has been described above with respect to the preferred embodiments, but the above is only to make it easy for those skilled in the art to understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Under the same spirit of the present invention, those skilled in the art can think of various equivalent changes. For example, other process steps or structures, such as deep well regions, etc., can be added without affecting the main characteristics of the component; for example, lithography technology is not limited to mask technology, but may also include electron beam lithography technology. All of these can be derived by analogy based on the teachings of the present invention. In addition, the various embodiments described are not limited to individual applications, but may also be used in combination, such as but not limited to the use of two embodiments together. Therefore, the scope of the present invention should cover the above and all other equivalent changes. In addition, any embodiment of the present invention does not necessarily achieve all purposes or advantages, and therefore, any of the claims should not be limited to this.
Claims
1. A depletion-mode vertical discrete NMOS device, comprising: An N-type epitaxial layer is formed on an N-type substrate, and the N-type epitaxial layer has an upper surface and a lower surface opposite to each other; A P-type well region formed in the N-type epitaxial layer; a gate formed and connected to the outside of the N-type epitaxial layer; An N-type source formed in the N-type epitaxial layer, wherein the N-type source is adjacent to the P-type well region; an N-type drain, comprising a portion of the N-type substrate, wherein the N-type drain is adjacent to and below the outer portion of the N-type epitaxial layer; and An N-type region formed and connected between the P-type well region and the gate to provide a channel so as to electrically connect the N-type source and the N-type drain in an on operation and electrically isolate the N-type source and the N-type drain in an off operation; in, When a gate voltage of zero voltage is applied to the gate, the depletion-type vertical discrete NMOS device is in the on operation.
2. The depletion-mode vertical discrete NMOS device according to claim 1, wherein: The depletion-type vertical discrete NMOS device is a planar device, wherein the gate is formed and connected to the upper surface of the N-type epitaxial layer, and the channel is parallel to the upper surface.
3. The depletion-mode vertical discrete NMOS device according to claim 1, wherein: The depletion type vertical discrete NMOS element is a trench element, wherein the gate is formed and connected to the outside of a side surface of the N-type epitaxial layer, and the channel is parallel to the side surface and perpendicular to the upper surface.
4. The depletion-mode vertical discrete NMOS device according to claim 3, wherein: The invention also comprises a shielding gate formed under the gate and connected to the N-type epitaxial layer.
5. The depletion-mode vertical discrete NMOS device according to claim 1, wherein: The N-type substrate or the N-type epitaxial layer is a semiconductor of silicon or silicon carbide.
6. The depletion-mode vertical discrete NMOS device according to claim 1, wherein: An N-type impurity of the N-type region includes nitrogen, phosphorus, arsenic, antimony or bismuth.
7. The depletion-mode vertical discrete NMOS device according to claim 1, wherein: The N-type region is formed by an ion implantation process step, wherein an implantation angle of the ion implantation process step is between 0 and 90 degrees.
8. The depletion-mode vertical discrete NMOS device according to claim 1, wherein: The N-type epitaxial layer has a volume resistivity of 45 Ohm-cm.
9. A method for manufacturing a depletion-mode vertical discrete NMOS device, comprising: Forming an N-type epitaxial layer on an N-type substrate, the N-type epitaxial layer having an upper surface and a lower surface opposite to each other; forming a P-type well region in the N-type epitaxial layer; forming and connecting a gate outside the N-type epitaxial layer; forming an N-type source in the N-type epitaxial layer, wherein the N-type source is adjacent to the P-type well region; forming an N-type drain adjacent to and below the outer portion of the N-type epitaxial layer, wherein the N-type drain includes a portion of the N-type substrate; and Forming an N-type region connected between the P-type well region and the gate to provide a channel, thereby electrically connecting the N-type source and the N-type drain during an on operation, and electrically isolating the N-type source and the N-type drain during an off operation; in, When a gate voltage of zero voltage is applied to the gate, the depletion-type vertical discrete NMOS device is in the on operation.
10. The method for manufacturing a depletion-type vertical discrete NMOS device according to claim 9, wherein: The depletion-type vertical discrete NMOS device is a planar device, wherein the gate is formed and connected to the upper surface of the N-type epitaxial layer, and the channel is parallel to the upper surface.
11. The method for manufacturing a depletion-type vertical discrete NMOS device according to claim 9, wherein: The depletion type vertical discrete NMOS element is a trench element, wherein the gate is formed and connected to the outside of a side surface of the N-type epitaxial layer, and the channel is parallel to the side surface and perpendicular to the upper surface.
12. The method for manufacturing a depletion-type vertical discrete NMOS device according to claim 11, wherein: The method also includes etching the N-type epitaxial layer to form a trench and the side surface.
13. The method for manufacturing a depletion-type vertical discrete NMOS device according to claim 11, wherein: The method also includes forming a shielding gate below the gate and connecting the N-type epitaxial layer.
14. The method for manufacturing a depletion-type vertical discrete NMOS device according to claim 9, wherein: The N-type substrate or the N-type epitaxial layer is a semiconductor of silicon or silicon carbide.
15. The method for manufacturing a depletion-type vertical discrete NMOS device according to claim 9, wherein: An N-type impurity of the N-type region includes nitrogen, phosphorus, arsenic, antimony or bismuth.
16. The method for manufacturing a depletion-type vertical discrete NMOS device according to claim 9, wherein: The method further comprises: forming the N-type region by an ion implantation process step, wherein an implantation angle of the ion implantation process step is between 0 and 90 degrees.
17. The method for manufacturing a depletion-type vertical discrete NMOS device according to claim 9, wherein: The N-type epitaxial layer has a volume resistivity of 45 Ohm-cm.