Semiconductor device, isolation structure and manufacturing method of isolation structure

Abstract

The invention relates to a semiconductor device, an isolation structure and a manufacturing method of the isolation structure, and the isolation structure comprises a buried region which is located in a substrate; a second conductivity type region on the buried region; the second conduction type buffer layer is located in the second conduction type region, and the doping concentration of the second conduction type buffer layer is larger than that of the second conduction type region; the first well region is located on the second conduction type buffer layer, and the doping concentration of the first well region is smaller than that of the second conduction type buffer layer; and a second well region on the buried region, the second well region laterally surrounding the second conductivity type buffer layer and the first well region. According to the invention, the second conductive type buffer layer has enough upward back-diffusion capability for the second conductive type region above the second conductive type buffer layer, and can provide better RESURF capability for the drift region of the device main body to obtain higher isolation withstand voltage.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device, and also to an isolation structure and a method for manufacturing the isolation structure. Background Art

[0002] Taking N-type devices as an example, the exemplary fully isolated N-channel laterally diffused metal oxide semiconductor field effect transistor (Fully isolated NLDMOS) usually adopts a structure in which a P-type epitaxial layer is epitaxially grown on an N-type buried layer (N-bury), and then an NLDMOS device and a peripheral isolation ring are formed on the P-type epitaxial layer. The substrate lead (Psub), isolation lead (ISO) and bulk lead (Bulk) of the device will parasitize a PNP structure distributed in both the horizontal and vertical directions. When the device is working normally, the two PN junctions of the PNP are reverse biased to form junction isolation, thereby forming isolation between the inside of the device and the substrate and other structures outside the device.

[0003] The above-mentioned fully isolated NLDMOS structure is limited by the process of the isolation ring implant diffusion depth, so the thickness of the P-type epitaxial layer cannot be too thick, otherwise the implant depth of the isolation ring cannot reach a sufficient depth (the depth of the N-type buried layer), which will affect the contact between the isolation ring and the N-type buried layer. This results in the thickness of the P-type epitaxial layer between the drift region (N-drift) at the drain (Drain) end of the NLDMOS and the N-type buried layer at the ISO end being limited, thereby limiting the isolation withstand voltage. Summary of the invention

[0004] Based on this, it is necessary to provide an isolation structure with higher voltage resistance.

[0005] An isolation structure comprises: a buried region, located in a substrate, and having a first conductivity type; a second conductivity type region, located on the buried region; the first conductivity type and the second conductivity type are opposite conductivity types; a second conductivity type buffer layer, located in the second conductivity type region, the doping concentration of the second conductivity type buffer layer being greater than the doping concentration of the second conductivity type region; a first well region, located on the second conductivity type buffer layer, the first well region having the second conductivity type, the doping concentration of the first well region being less than the doping concentration of the second conductivity type buffer layer; a second well region, having the first conductivity type, located on the buried region, the second well region laterally surrounding the second conductivity type buffer layer and the first well region; wherein the area of ​​the second conductivity type region located on the second conductivity type buffer layer is used to form a device body.

[0006] The above isolation structure, by arranging a second conductive type buffer layer with a higher doping concentration in the second conductive type region, enables the second conductive type buffer layer to have sufficient upward reverse diffusion capability to the second conductive type region above, and enables the second conductive type buffer layer to have a lower contact resistance with the structure above it, so that carriers (holes when the first conductive type is N-type and the second conductive type is P-type) can be better derived. The second conductive type buffer layer can also provide better RESURF capability for the drift region of the device body, thereby obtaining a higher isolation withstand voltage.

[0007] In one of the embodiments, the second conductive type region includes a first epitaxial layer and a second epitaxial layer on the first epitaxial layer, and the second epitaxial layer is located on the second conductive type buffer layer.

[0008] In one embodiment, the second well region includes a deep well located in the second conductive type layer, and a first conductive type well region located above the buried region and below the deep well.

[0009] In one embodiment, the first conductivity type well region is located in the first epitaxial layer, and the deep well is located in the second epitaxial layer.

[0010] In one embodiment, the thickness of the deep well is greater than the thickness of each of the first conductivity type well regions.

[0011] In one of the embodiments, the bottom of the first well region is in direct contact with the second conductive type buffer layer.

[0012] In one of the embodiments, the isolation structure further includes a buried layer lead-out region located in the deep well, and the buried layer lead-out region has a first conductivity type.

[0013] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0014] It is also necessary to provide a semiconductor device with higher withstand voltage.

[0015] A semiconductor device comprises a substrate, a device body and an isolation structure isolating the device body from the substrate, wherein the isolation structure is the isolation structure described in any of the aforementioned embodiments, and the substrate has a second conductivity type.

[0016] In one embodiment, the device body includes a source region, a drain region and a drift region of an N-channel laterally diffused metal oxide semiconductor field effect transistor, and the semiconductor device also includes a gate of the N-channel laterally diffused metal oxide semiconductor field effect transistor, the gate is located above the area between the source region and the drain region, and the source region, the drain region and the drift region have a first conductivity type.

[0017] In one embodiment, the source region is located in the first well region, the drain region is located in the drift region, and the device body further includes: a body lead-out region having a second conductivity type, the body lead-out region is located in the first well region, and the doping concentration of the body lead-out region is greater than the doping concentration of the first well region.

[0018] In one of the embodiments, the semiconductor device further includes: a third well region having a second conductivity type and located on the substrate and outside the second well region.

[0019] In one embodiment, the body lead region is located between the source region and the second well region.

[0020] It is also necessary to provide a method for manufacturing an isolation structure.

[0021] A method for manufacturing an isolation structure, comprising: obtaining a substrate with a buried region formed on the upper portion, the buried region having a first conductivity type; forming a first film layer on the buried region, the first film layer having a second conductivity type; the first conductivity type and the second conductivity type are opposite conductivity types; forming a second conductivity type buffer layer in the first film layer, the doping concentration of the second conductivity type buffer layer being greater than the doping concentration of the first film layer; forming a second film layer on the first film layer, the second film layer having a second conductivity type; forming a first well region, a second well region and a device body, the second well region being formed on the buried region, the device body, the first well region and the second conductivity type buffer layer being formed in an area surrounded by the second well region, the first well region having the second conductivity type, the second well region having the first conductivity type, and the doping concentration of the second conductivity type buffer layer being greater than the doping concentration of the first well region.

[0022] The manufacturing method of the isolation structure forms a second conductive type buffer layer with a higher doping concentration in the first film layer, so that the second conductive type buffer layer has sufficient upward reverse diffusion capability to the second film layer above, and has a lower contact resistance between the second conductive type buffer layer and the structure above it, so that carriers can be better extracted. The second conductive type buffer layer can also provide better RESURF capability for the drift region of the device body, thereby obtaining a higher isolation withstand voltage.

[0023] In one embodiment, the step of forming the second well region includes: before forming the second film layer, forming a first conductivity type well region in the first film layer by photolithography and ion implantation; forming a deep well in the second film layer by photolithography and ion implantation.

[0024] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0026] Figure 1 is a schematic diagram of a cross-sectional structure of an exemplary NLDMOSFET;

[0027] Figure 2 is a schematic cross-sectional structural diagram of a semiconductor device with an isolation structure in one embodiment of the present application;

[0028] Figure 3a to Figure 3d Is adopted Figure 4 A schematic diagram of the cross-sectional structure of a device during the process of manufacturing an isolation structure by the method shown;

[0029] Figure 4 is a flow chart of a method for manufacturing an isolation structure in one embodiment of the present application;

[0030] Figure 5 It is a schematic cross-sectional structure diagram of a semiconductor device with an isolation structure in another embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0033] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0034] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0035] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0036] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0037] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0038] Figure 1 The cross-sectional structure diagram of an exemplary N-channel laterally diffused metal oxide semiconductor field effect transistor (NLDMOSFET) is shown. The Psub end (including the substrate lead-out region 129 and the P well 128), the ISO end (including the buried layer lead-out region 125 and the N well 126) and the Bulk end (including the body lead-out region 123 and the P well 124) of the device will parasitize a PNP structure distributed in both the horizontal and vertical directions. When the device is working normally, the two PN junctions of the PNP structure are reverse biased to form junction isolation. Due to the process limitation of the isolation ring implantation diffusion depth, the thickness of the P-type epitaxial layer 130 of the above-mentioned Fully isolated NLDMOS structure cannot be too thick, otherwise the implantation depth of the isolation ring cannot reach a sufficient depth (the depth of the N-type buried layer 122), which will affect the contact between the isolation ring and the N-type buried layer 122.

[0039] Figure 2 is a schematic cross-sectional structure diagram of a semiconductor device with an isolation structure in an embodiment of the present application, Figure 2The structure shown is bilaterally symmetrical, so only the structure on one side is labeled. The isolation structure includes a buried region 222, a second conductive type region 230, a second conductive type buffer layer 233, a first well region 224, and a second well region 220. The buried region 222 is located in the substrate 210 and has a first conductive type. The second conductive type region 230 is located on the buried region 222. The second conductive type buffer layer 233 is located in the second conductive type region 230, and the doping concentration of the second conductive type buffer layer 233 is greater than the doping concentration of the second conductive type region 230. Figure 2 In the illustrated embodiment, the second conductive type region 230 includes a first epitaxial layer 232 and a second epitaxial layer 234 on the first epitaxial layer 232, and the second epitaxial layer 234 is located on the second conductive type buffer layer 233. The first well region 224 is located on the second conductive type buffer layer 233, and the first well region 224 has the second conductive type, and the doping concentration of the first well region 224 is less than the doping concentration of the second conductive type buffer layer 233. The second well region 220 has the first conductive type and is located on the buried region 222. The second well region 220 is a closed loop structure in the lateral direction, thereby surrounding the second conductive type buffer layer 233 and the first well region 224 in the lateral direction. Figure 2 The structure shown also includes a third well region 228. The third well region 228 has the second conductivity type and is located on the substrate 210 and outside the second well region 220. The third well region 228 can lead out the substrate 210. The area of ​​the second conductivity type region 230 located on the second conductivity type buffer layer 233 is used to form the device body.

[0040] The above isolation structure, by arranging a second conductive type buffer layer 233 with a higher doping concentration in the second conductive type region 230, enables the second conductive type buffer layer 233 to have sufficient upward reverse diffusion capability to the second conductive type region 230 (i.e., the second epitaxial layer 234) above, and enables the second conductive type buffer layer 233 to have a lower contact resistance with the structure above it (i.e., the contact resistance between the second conductive type buffer layer 233 and the first well region 224 is smaller), so that carriers can be better derived. The second conductive type buffer layer 233 can also provide a better RESURF capability for the drift region of the device body, thereby obtaining a higher isolation withstand voltage.

[0041] In one embodiment of the present application, the substrate 210 is a semiconductor substrate, and its material may be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc. Figure 2 In the illustrated embodiment, the material of the substrate 210 is single crystal silicon of the second conductivity type.

[0042] In one embodiment of the present application, the semiconductor device is an NLDMOSFET, and the device body includes a source region 242, a drain region 244, and a drift region 231 of the NLDMOSFET. The semiconductor device also includes a gate 252 of the NNLDMOSFET, and the gate 252 is located above the region between the source region 242 and the drain region 244. The source region 242, the drain region 244, and the drift region 231 are N-type regions. In one embodiment of the present application, the doping concentration of the source region 242 and the drain region 244 is greater than the doping concentration of the drift region 231. Figure 2 In the illustrated embodiment, the first well region 224 is located between the second well region 220 and the drift region 231 .

[0043] In one embodiment of the present application, the gate 252 is made of polysilicon. In other embodiments, metal, metal nitride, metal silicide or similar compounds may be used as the gate material. In one embodiment of the present application, a gate dielectric layer ( Figure 2 The gate dielectric layer may include conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in a vacuum), or the gate dielectric layer may include a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs). The gate 252 may extend to the top of the source region 242 or to the edge of the source region 242, i.e., overlap with a portion of the edge of the source region 242, or be tangent to the edge of the source region 242.

[0044] In one embodiment of the present application, the second well region 220 includes a deep well 226 located in the second conductive type layer 230, and a first conductive type well region 227 located above the buried region 222 and below the deep well 226. In one embodiment of the present application, the first conductive type well region 227 is formed in the first epitaxial layer 232 by ion implantation after the first epitaxial layer 232 is formed, and the well can be pushed after the ion implantation. After the first conductive type well region 227 is formed, a second epitaxial layer 234 is formed on the first epitaxial layer 232, and then a deep well 226 is formed in the second epitaxial layer 234 by ion implantation, and the well can be pushed after the ion implantation. By forming the second well region 220 by this two-step implantation, the overall junction depth of the second well region 220 can be deeper when the ion implantation energy is limited. If the second well region 220 is not split into two implantations, the implantation energy requirement for the implantation machine will be very high. In one embodiment of the present application, the thickness of the deep well 226 is greater than the thickness of the first conductive type well region 227. In one embodiment of the present application, the bottom of the second well region 220 is in direct contact with the buried region 222 .

[0045] In one embodiment of the present application, the bottom of the first well region 224 is in direct contact with the second conductive type buffer layer 233. The device body further includes a body lead-out region 223 located in the first well region 224. The body lead-out region 223 has the second conductive type, and its doping concentration is greater than the doping concentration of the first well region 224. The second conductive type buffer layer 233 can be led out through the body lead-out region 223.

[0046] In one embodiment of the present application, the source region 242 is located in the first well region 224, and the drain region 244 is located in the drift region 231. In one embodiment of the present application, the doping concentration of the first well region 224 is greater than the doping concentration of the second conductive type layer 230.

[0047] In one embodiment of the present application, the isolation structure further includes a substrate lead-out region 229 located in the third well region 228. The substrate lead-out region 229 has a second conductivity type, and a doping concentration greater than that of the third well region 228. In one embodiment of the present application, the isolation structure further includes a buried layer lead-out region 225 located in the deep well 226. The buried layer lead-out region 225 has a first conductivity type, and a doping concentration greater than that of the deep well 226. In one embodiment of the present application, the semiconductor device further includes an insulating isolation structure 272. Further, the insulating isolation structure 272 may be a shallow trench isolation structure (STI). The insulating isolation structure 272 may be disposed between the substrate lead-out region 229 and the buried layer lead-out region 225, between the buried layer lead-out region 225 and the body lead-out region 223, between the body lead-out region 223 and the source region 242, between the source region 242 and the drain region 244, and the like. A portion of the gate 252 is located above the insulating isolation structure 272 between the source region 242 and the drain region 244 .

[0048] when Figure 2 When the semiconductor device in the structure shown is an NLDMOSFET, the substrate 210 is a P-type substrate, the buried region 222 is an N-type buried layer, the second well region 220 composed of the first conductive type well region 227 and the deep well 226 is an N-well, the buried layer lead-out region 225 is an N+ region, the third well region 228 and the first well region 224 are deep P-wells, the substrate lead-out region 229, the body lead-out region 223 and the second conductive type buffer layer 233 are P+ regions, the first epitaxial layer 232 and the second epitaxial layer 234 are P-type epitaxial layers, the drift region 231 is an N-type drift region, and the source region 242 and the drain region 244 are N+ regions.

[0049] The present application accordingly provides a method for manufacturing an isolation structure, which can be used to manufacture the isolation structure described in any of the aforementioned embodiments. Figure 4 : is a flow chart of a method for manufacturing an isolation structure in an embodiment of the present application, comprising the following steps:

[0050] S410, obtaining a substrate with a buried region formed on the upper portion.

[0051] Reference Figure 3a , the buried region 322 has a first conductivity type. In one embodiment of the present application, the substrate 310 is a semiconductor substrate, and its material can be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI). Figure 3aIn the embodiment shown, the constituent material of the substrate 310 is single crystal silicon of the second conductivity type. In one embodiment of the present application, the first conductivity type is N type and the second conductivity type is P type; in another embodiment of the present application, the first conductivity type is P type and the second conductivity type is N type.

[0052] In one embodiment of the present application, step S410 includes photolithography on the substrate 310 , and then ion implantation (implanting first conductive type ions) and well driving to form a buried region 322 .

[0053] S420, forming a first film layer on the buried region.

[0054] exist Figure 3b In the illustrated embodiment, step S420 is to perform a first epitaxial growth on the buried region 322 to form a first epitaxial layer 332 (ie, a first film layer), and the first film layer has a second conductivity type.

[0055] S430 , forming a second conductive type buffer layer in the first film layer.

[0056] exist Figure 3b In the illustrated embodiment, photolithography is performed on the first epitaxial layer 332 , and then ion implantation (implantation of second conductive type ions) is performed to form the second conductive type buffer layer 333 .

[0057] S440, forming a second film layer on the first film layer.

[0058] exist Figure 3c In the illustrated embodiment, step S440 is to perform a second epitaxial growth on the first epitaxial layer 332 to form a second epitaxial layer 334 (ie, a second film layer), and the second film layer has a second conductivity type.

[0059] The isolation is achieved by the dual epitaxial structure of the first epitaxial layer 332 and the second epitaxial layer 334, and the thickness of the two epitaxial layers can be flexibly controlled according to the withstand voltage requirements of the device design. In addition, while growing the second epitaxial layer 334, the epitaxial process can help the second conductive type buffer layer 333 to diffuse upward better.

[0060] S450, forming a first well region, a second well region and a device body.

[0061] The second well region 320 is formed on the buried region 322. The device body, the first well region 324 and the second conductive type buffer layer 333 are formed in the area surrounded by the second well region 320. The second well region 320 has the first conductive type. The doping concentration of the second conductive type buffer layer 333 is greater than the doping concentration of the first well region 324. In one embodiment of the present application, step S450 also includes forming a third well region 328. The third well region 328 is formed outside the second well region 320, and the third well region 328 has the second conductive type. Figure 3c In the illustrated embodiment, the second well region 320 includes a deep well 326 located in the second epitaxial layer 334 , and a first conductivity type well region 327 located above the buried region 322 and below the deep well 326 .

[0062] The manufacturing method of the isolation structure forms a second conductive type buffer layer 333 with a higher doping concentration in the first film layer, so that the second conductive type buffer layer 333 has sufficient upward anti-diffusion capability to the second film layer above, and the second conductive type buffer layer 333 has a lower contact resistance with the structure above it, so that carriers can be better extracted. The second conductive type buffer layer can also provide better RESURF capability for the drift region of the device body, thereby obtaining a higher isolation withstand voltage.

[0063] In one embodiment of the present application, the second well region 320 includes a first conductivity type well region 327 and a deep well 326. The steps of forming the second well region 320 include:

[0064] Before forming the second epitaxial layer 334 , a first conductive type well region 327 is formed in the first epitaxial layer 332 by photolithography and ion implantation (implanting first conductive type ions). After the implantation of the first conductive type ions, well driving may be performed.

[0065] A deep well 326 is formed in the second epitaxial layer 334 by photolithography and ion implantation (implantation of first conductivity type ions).

[0066] When the device withstands a high voltage and the buried junction is deep, forming the second well region 320 through two ion implantations can reduce the injection energy required for each well injection, thereby meeting higher withstand voltage requirements and avoiding the impact of high-energy injection on process fluctuations and the requirements for the injection machine (high-energy injection machines are more expensive).

[0067] In one embodiment of the present application, the third well region 328 and the first well region 324 are formed by photolithography and ion implantation.

[0068] In one embodiment of the present application, step S450 of forming the device body includes forming a drift region 331. The drift region 331 has a first conductivity type and can be formed by photolithography and ion implantation. After performing ion implantation of the third well region 328, the first well region 324, and the drift region 331, a push-well may be performed. The first well region 324 is formed between the drift region 331 and the second well region 320.

[0069] Reference Figure 3d In one embodiment of the present application, step S450 further includes the step of forming an insulating isolation structure 372. In one embodiment of the present application, the insulating isolation structure 372 may be a STI.

[0070] In one embodiment of the present application, step S450 further includes forming a gate dielectric layer ( Figure 3d (not shown) and the gate 352.

[0071] In one embodiment of the present application, step S450 further includes the step of forming a P+ region and an N+ region by ion implantation, including forming a source region 342, a drain region 344, a buried layer lead-out region 325, a substrate lead-out region 329, and a body lead-out region 323. The source region 342 and the body lead-out region 323 are formed in the first well region 324, the drain region 344 is formed in the drift region 331, the buried layer lead-out region 325 is formed in the deep well 326, and the substrate lead-out region 329 is formed in the third well region 328.

[0072] exist Figure 3d In the illustrated embodiment, the semiconductor device is an NLDMOSFET, the substrate 310 is a P-type substrate, the buried region 322 is an N-type buried layer, the second well region composed of the first conductive type well region 327 and the deep well 326 is an N-well, the buried layer lead-out region 325 is an N+ region, the third well region 328 and the first well region 324 are deep P-wells, the body lead-out region 323, the substrate lead-out region 329 and the second conductive type buffer layer 333 are P+ regions, the first epitaxial layer 332 and the second epitaxial layer 334 are P-type epitaxial layers, the drift region 331 is an N-type drift region, and the source region 342 and the drain region 344 are N+ regions.

[0073] Figure 5 is a schematic diagram of a partial cross-sectional structure of a semiconductor device with an isolation structure in another embodiment of the present application, which is Figure 3d The main difference of the structure shown is that the device main region includes a body region 341 of the second conductivity type, the source region 342 is located in the body region 341, and the drain region 344 is arranged in the drift region 331 and is located between the deep well 326 and the body region 341 (also between the deep well 326 and the source region 342). Figure 5The Fully isolated NLDMOS structure shown in the figure also increases the vertical penetration isolation withstand voltage from the drain port to the buried layer lead-out port by adding a second conductive type buffer layer 333 between the vertical drain port and the buried layer lead-out port (i.e., the area between the drain region 344 and the buried layer lead-out region 325 and located above the buried region 322).

[0074] It should be understood that, although the various steps in the flowchart of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0075] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0076] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0077] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. An isolation structure, characterized in that: include: a buried region, located in the substrate, having a first conductivity type; A second conductive type region, located on the buried region; The first conductivity type and the second conductivity type are opposite conductivity types; A second conductive type buffer layer is located in the second conductive type region, and the doping concentration of the second conductive type buffer layer is greater than the doping concentration of the second conductive type region; A first well region, located on the second conductive type buffer layer, the first well region has the second conductive type, and the doping concentration of the first well region is less than the doping concentration of the second conductive type buffer layer; A second well region, having a first conductivity type, is located on the buried region, and the second well region laterally surrounds the second conductivity type buffer layer and the first well region; The second conductive type region is located in an area on the second conductive type buffer layer and is used to form a device body.

2. The isolation structure according to claim 1, characterized in that: The second conductive type region includes a first epitaxial layer and a second epitaxial layer on the first epitaxial layer, and the second epitaxial layer is located on the second conductive type buffer layer.

3. The isolation structure according to claim 1 or 2, characterized in that: The second well region includes a deep well located in the second conductive type layer, and a first conductive type well region located above the buried region and below the deep well.

4. The isolation structure according to claim 3, characterized in that: The thickness of the deep well is greater than the thickness of the first conductivity type well region; and / or The bottom of the first well region is in direct contact with the second conductive type buffer layer.

5. The isolation structure according to claim 1, characterized in that: The first conductivity type is N type, and the second conductivity type is P type.

6. A semiconductor device comprising a substrate, a device body and an isolation structure isolating the device body from the substrate, characterized in that: The isolation structure is the isolation structure according to any one of claims 1 to 5, and the substrate has a second conductivity type.

7. The semiconductor device according to claim 6, characterized in that The device body includes a source region, a drain region and a drift region of an N-channel laterally diffused metal oxide semiconductor field effect transistor, and the semiconductor device also includes a gate of the N-channel laterally diffused metal oxide semiconductor field effect transistor, wherein the gate is located above the region between the source region and the drain region, and the source region, the drain region and the drift region have a first conductivity type.

8. The semiconductor device according to claim 6, characterized in that The source region is located in the first well region, the drain region is located in the drift region, and the device body further comprises: a body lead region having a second conductivity type, the body lead region is located in the first well region, and the doping concentration of the body lead region is greater than the doping concentration of the first well region; The semiconductor device further includes: a third well region having a second conductivity type and located on the substrate and outside the second well region.

9. A method for manufacturing an isolation structure, comprising: Obtaining a substrate having a buried region formed on an upper portion, wherein the buried region has a first conductivity type; forming a first film layer on the buried region, wherein the first film layer has a second conductivity type; the first conductivity type and the second conductivity type are opposite conductivity types; forming a second conductive type buffer layer in the first film layer, wherein the doping concentration of the second conductive type buffer layer is greater than the doping concentration of the first film layer; forming a second film layer on the first film layer, wherein the second film layer has a second conductivity type; A first well region, a second well region and a device body are formed, wherein the second well region is formed on the buried region, and the device body, the first well region and a second conductive type buffer layer are formed in an area surrounded by the second well region, wherein the first well region has a second conductive type, and the second well region has a first conductive type, and the doping concentration of the second conductive type buffer layer is greater than the doping concentration of the first well region.

10. The method for manufacturing an isolation structure according to claim 9, characterized in that: The step of forming the second well region comprises: Before forming the second film layer, forming a first conductivity type well region in the first film layer by photolithography and ion implantation; A deep well is formed in the second film layer by photolithography and ion implantation.

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