Isolation structure, semiconductor device and manufacturing method of isolation structure

Abstract

The invention relates to an isolation structure, a semiconductor device and a manufacturing method of the isolation structure, and the isolation structure comprises a buried region which is located in a substrate; the super junction main body comprises at least one layer of second conduction type region and at least one layer of first conduction type region, the second conduction type region and the first conduction type region are alternately arranged on the buried region in the vertical direction, and the structure, closest to the buried region, of the super junction main body is the second conduction type region; the first well region is located on the buried region, and the super junction main body is surrounded by the first well region; the second conductive type layer is located on the super junction main body, and the area, surrounded by the first well region, in the second conductive type layer is used for forming a device main body; and the second well region is positioned on the substrate and on the outer side of the first well region. According to the invention, the super junction structure in which the second conductive type regions and the first conductive type regions are alternately arranged is formed between the buried region and the second conductive type layer, so that higher isolation withstand voltage can be obtained.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to an isolation structure, a semiconductor device, and a method for manufacturing the isolation structure. Background Art

[0002] Taking N-type devices as an example, the exemplary fully isolated N-channel laterally diffused metal oxide semiconductor field effect transistor (Fully isolated NLDMOS) usually adopts a structure in which a P-type epitaxial layer is epitaxially grown on an N-type buried layer (N-bury), and then an NLDMOS device and a peripheral isolation ring are formed on the P-type epitaxial layer. The substrate lead (Psub), isolation lead (ISO) and bulk lead (Bulk) of the device will parasitize a PNP structure distributed in both the horizontal and vertical directions. When the device is working normally, the two PN junctions of the PNP are reverse biased to form junction isolation, thereby forming isolation between the inside of the device and the substrate and other structures outside the device.

[0003] The above-mentioned fully isolated NLDMOS structure is limited by the process of the isolation ring implant diffusion depth, so the thickness of the P-type epitaxial layer cannot be too thick, otherwise the implant depth of the isolation ring cannot reach a sufficient depth (the depth of the N-type buried layer), which will affect the contact between the isolation ring and the N-type buried layer. This results in the thickness of the P-type epitaxial layer between the drift region (N-drift) at the drain (Drain) end of the NLDMOS and the N-type buried layer at the ISO end being limited, thereby limiting the isolation withstand voltage. Summary of the invention

[0004] Based on this, it is necessary to provide an isolation structure with higher voltage resistance.

[0005] An isolation structure comprises: a buried region, located in a substrate, and having a first conductivity type; a super junction body, comprising at least one layer of a second conductivity type region and at least one layer of a first conductivity type region, wherein the second conductivity type region and the first conductivity type region are arranged alternately vertically on the buried region, and the structure of the super junction body closest to the buried region is a second conductivity type region; the first conductivity type and the second conductivity type are opposite conductivity types; a first well region, having the first conductivity type, located on the buried region, and the first well region surrounds the super junction body in the horizontal direction; a second conductivity type layer, located on the super junction body, and an area of ​​the second conductivity type layer surrounded by the first well region is used to form a device body.

[0006] The isolation structure can obtain a higher isolation withstand voltage by forming a super junction structure in which the second conductivity type region and the first conductivity type region are alternately arranged between the buried region and the second conductivity type layer.

[0007] In one embodiment, the doping concentration of each of the first conductivity type regions is less than the doping concentration of the buried region.

[0008] In one embodiment, the first well region includes a deep well located in the second conductive type layer, and a plurality of first conductive type well regions located above the buried region and below the deep well, the number of the first conductive type well regions being equal to the sum of the number of the first conductive type regions and the second conductive type regions; the doping concentration of each of the first conductive type well regions and the deep well is greater than the doping concentration of the first conductive type region.

[0009] In one embodiment, the thickness of the deep well is greater than the thickness of each of the first conductivity type well regions.

[0010] In one of the embodiments, it further includes a buried layer lead-out region located in the deep well, wherein the buried layer lead-out region has a first conductivity type.

[0011] In one embodiment, the bottom of the first well region is in direct contact with the buried region.

[0012] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0013] It is also necessary to provide a semiconductor device with higher withstand voltage.

[0014] A semiconductor device comprises a substrate, a device body and an isolation structure isolating the device body from the substrate, wherein the isolation structure is the isolation structure described in any of the aforementioned embodiments, and the substrate has a second conductivity type.

[0015] In one embodiment, the device body includes a source region, a drain region and a drift region of an N-channel laterally diffused metal oxide semiconductor field effect transistor, and the semiconductor device also includes a gate of the N-channel laterally diffused metal oxide semiconductor field effect transistor, the gate is located above the area between the source region and the drain region, and the source region, the drain region and the drift region have a first conductivity type.

[0016] In one embodiment, it also includes a second conductive type well region located between the first well region and the drift region, the source region is located in the second conductive type well region, the drain region is located in the drift region, and the device body also includes a body lead-out region located in the second conductive type well region, the body lead-out region has a second conductive type, and the doping concentration of the body lead-out region is greater than the doping concentration of the second conductive type well region.

[0017] In one embodiment, the semiconductor device further includes: a second well region having a second conductivity type and located on the substrate and outside the first well region

[0018] In one embodiment, the doping concentration of the second conductive type well region is greater than the doping concentration of the second conductive type layer.

[0019] In one embodiment, the body lead region is located between the source region and the first well region.

[0020] It is also necessary to provide a method for manufacturing an isolation structure.

[0021] A method for manufacturing an isolation structure, comprising: obtaining a substrate having a buried region formed on the upper portion, the buried region having a first conductivity type; forming a second conductivity type region on the buried region; forming a first conductivity type region on the second conductivity type region; forming a second conductivity type layer on the first conductivity type region; forming a first well region and a device body, the first well region being formed on the buried region, the device body being formed in an area surrounded by the first well region, the first well region having a first conductivity type.

[0022] The manufacturing method of the isolation structure can obtain a higher isolation withstand voltage by forming a super junction structure in which the second conductivity type region and the first conductivity type region are alternately arranged between the buried region and the second conductivity type layer.

[0023] In one embodiment, the step of forming a second conductive type region on the buried region, and the step of forming a first conductive type region on the second conductive type region, include forming at least one layer of the second conductive type region and at least one layer of the first conductive type region on the buried region, and the second conductive type region and the first conductive type region are alternately arranged vertically on the buried region to form a super junction structure.

[0024] In one embodiment, the step of forming the first well region includes: forming a first conductive type well region in the first conductive type region by ion implantation each time a layer of the first conductive type region is formed; forming a first conductive type well region in the second conductive type region by ion implantation each time a layer of the second conductive type region is formed; forming a deep well in the second conductive type layer; the doping concentration of each of the first conductive type well region and the deep well is greater than the doping concentration of the first conductive type region.

[0025] In one embodiment, after the step of forming the second conductive type layer on the first conductive type region, the step of forming a second well region is further included. The second well region is formed outside the first well region and has the second conductive type.

[0026] In one of the embodiments, the substrate has a second conductivity type.

[0027] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0029] Figure 1 is a schematic diagram of a cross-sectional structure of an exemplary NLDMOSFET;

[0030] Figure 2 is a schematic cross-sectional structural diagram of a semiconductor device with an isolation structure in one embodiment of the present application;

[0031] Figure 3a to Figure 3h Is adopted Figure 4 A schematic diagram of a cross-sectional structure of a device during the process of manufacturing an isolation structure by the method shown;

[0032] Figure 4 is a flow chart of a method for manufacturing an isolation structure in one embodiment of the present application;

[0033] Figure 5 It is a schematic cross-sectional structure diagram of a semiconductor device with an isolation structure in another embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0036] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0037] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0038] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0040] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0041] Figure 1 The cross-sectional structure diagram of an exemplary N-channel laterally diffused metal oxide semiconductor field effect transistor (NLDMOSFET) is shown. The Psub end (including the substrate lead-out region 129 and the P well 128), the ISO end (including the buried layer lead-out region 125 and the N well 126) and the Bulk end (including the body lead-out region 123 and the P well 124) of the device will parasitize a PNP structure distributed in both the horizontal and vertical directions. When the device is working normally, the two PN junctions of the PNP structure are reverse biased to form junction isolation. Due to the process limitation of the isolation ring implantation diffusion depth, the thickness of the P-type epitaxial layer 130 of the above-mentioned Fully isolated NLDMOS structure cannot be too thick, otherwise the implantation depth of the isolation ring cannot reach a sufficient depth (the depth of the N-type buried layer 122), which will affect the contact between the isolation ring and the N-type buried layer 122.

[0042] Figure 2 is a schematic cross-sectional structure diagram of a semiconductor device with an isolation structure in an embodiment of the present application, Figure 2The structure shown is bilaterally symmetrical, so only the structure on one side is labeled. The isolation structure includes a buried region 222, a super junction body, a first well region, and a second conductive type layer 230. The buried region 222 is located in the substrate 210 and has a first conductive type. The super junction body includes at least one layer of a second conductive type region 232 and at least one layer of a first conductive type region 234. The second conductive type regions 232 and the first conductive type regions 234 are vertically alternately arranged on the buried region 222, and the second conductive type region 232 is the closest to the buried region 222 in the super junction body. Figure 2 In the illustrated embodiment, the first well region includes a deep well 226 located in the second conductive type layer 230, and a plurality of first conductive type well regions 227 located above the buried region 222 and below the deep well 226. The first well region has a first conductive type and is located on the buried region 222. The bottom of the first well region is in direct contact with the buried region 222, thereby leading the buried region 222 to the device surface. The first well region is a closed loop structure in the lateral direction, thereby surrounding the super junction body in the lateral direction (the area surrounded by the first well region is the area surrounded by the first well region). Figure 2 The second conductive type layer 230 is located on the super junction body, and the area of ​​the second conductive type layer 230 surrounded by the first well region is used to form the device body. Figure 2 The structure shown also includes a second well region 228. The second well region 228 has a second conductivity type and is located on the substrate 210 and outside the first well region. The second well region 228 can lead out the substrate 210. In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type; in another embodiment of the present application, the first conductivity type is P-type and the second conductivity type is N-type.

[0043] The above isolation structure can obtain a higher isolation withstand voltage by forming a super junction structure in which the second conductive type regions 232 and the first conductive type regions 234 are alternately arranged between the buried region 222 and the second conductive type layer 230 .

[0044] In order to obtain a better isolation and leakage prevention effect, the doping concentration of the buried region 222 should be relatively high. In order to obtain a higher isolation withstand voltage, the doping concentration of each first conductive type region 234 should be relatively low. In one embodiment of the present application, the doping concentration of each first conductive type region 234 is much lower than the doping concentration of the buried region 222.

[0045] In one embodiment of the present application, the doping concentration of each of the first conductive type well regions 227 and the deep well 226 is greater than the doping concentration of the first conductive type region 234 .

[0046] In one embodiment of the present application, the super junction body is formed on the buried region 222 by multiple epitaxy, and each epitaxy forms a layer of the second conductive type region 232 or a layer of the first conductive type region 234. In one embodiment of the present application, the first conductive type well region 227 is formed by ion implantation in the epitaxial layer after each layer of epitaxial layer is formed, that is, after forming a layer of the first conductive type region 234 (or a layer of the second conductive type region 232) with a relatively light concentration, ion implantation is performed to form a more concentrated first conductive type well region 227 in the first conductive type region 234 (or the second conductive type region 232), and the well can be pushed after the ion implantation. Therefore, the number of the first conductive type well regions 227 is equal to the sum of the number of the first conductive type regions 234 and the second conductive type regions 232. In this way, the overall junction depth of the first well region can be very deep without using high-energy implantation ion implantation equipment. If the implantation of the first well region is not split into multiple implantations, the implantation energy requirements of the implantation machine will be extremely high. In one embodiment of the present application, the thickness of the deep well 226 is greater than the thickness of each first conductivity type well region 227. In one embodiment of the present application, the bottom of the first well region (i.e., the bottom of the bottommost first conductivity type well region 227) is in direct contact with the buried region 222.

[0047] In one embodiment of the present application, the substrate 210 is a semiconductor substrate, and its material may be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc. Figure 2 In the illustrated embodiment, the material of the substrate 210 is single crystal silicon of the second conductivity type.

[0048] In one embodiment of the present application, the semiconductor device is an NLDMOSFET, and the device body includes a source region 242, a drain region 244, and a drift region 231 of the NLDMOSFET. The semiconductor device also includes a gate 252 of the NNLDMOSFET, and the gate 252 is located above the region between the source region 242 and the drain region 244, and the source region 242, the drain region 244, and the drift region 231 are N-type regions. In one embodiment of the present application, the doping concentration of the source region 242 and the drain region 244 is greater than the doping concentration of the drift region 231.

[0049] In one embodiment of the present application, the gate 252 is made of polysilicon. In other embodiments, metal, metal nitride, metal silicide or similar compounds may be used as the gate material. In one embodiment of the present application, a gate dielectric layer ( Figure 2The gate dielectric layer may include conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in a vacuum), or the gate dielectric layer may include a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs). The gate 252 may extend to the top of the source region 242 or to the edge of the source region 242, i.e., overlap with a portion of the edge of the source region 242, or be tangent to the edge of the source region 242.

[0050] In one embodiment of the present application, the semiconductor device further includes a second conductive type well region 224 located between the first well region and the drift region 231. The source region 242 is located in the second conductive type well region 224, and the drain region 244 is located in the drift region 231. In one embodiment of the present application, the doping concentration of the second conductive type well region 224 is greater than the doping concentration of the second conductive type layer 230.

[0051] In one embodiment of the present application, the device body further includes a body lead region 223 located in the second conductivity type well region 224. The body lead region 223 has the second conductivity type, and its doping concentration is greater than that of the second conductivity type well region 224.

[0052] In one embodiment of the present application, the isolation structure further includes a substrate lead-out region 229 located in the second well region 228. The substrate lead-out region 229 has a second conductivity type, and the doping concentration is greater than the doping concentration of the second well region 228. In one embodiment of the present application, the isolation structure further includes a buried layer lead-out region 225 located in the deep well 226. The buried layer lead-out region 225 has a first conductivity type, and the doping concentration is greater than the doping concentration of the deep well 226. In one embodiment of the present application, the semiconductor device further includes an insulating isolation structure 272. Further, the insulating isolation structure 272 may be a shallow trench isolation structure (STI). The insulating isolation structure 272 may be disposed between the substrate lead-out region 229 and the buried layer lead-out region 225, between the buried layer lead-out region 225 and the body lead-out region 223, between the body lead-out region 223 and the source region 242, between the source region 242 and the drain region 244, and the like. A portion of the gate 252 is located above the insulating isolation structure 272 between the source region 242 and the drain region 244 .

[0053] when Figure 2When the semiconductor device in the structure shown is an NLDMOSFET, the substrate 210 is a P-type substrate, the buried region 222 is an N-type buried layer, the first well region composed of the first conductive type well region 227 and the deep well 226 is an N-well, the buried layer lead-out region 225 is an N+ region, the second well region 228 and the second conductive type well region 224 are deep P-wells, the substrate lead-out region 229 and the body lead-out region 223 are P+ regions, and the super junction body on the buried region 222 is a structure in which P-type epitaxial layers and N-type epitaxial layers are alternately arranged, that is, the first conductive type region 232 is an N-type epitaxial layer, the second conductive type layer 234 is a P-type epitaxial layer, the second conductive type layer 230 is a P-type epitaxial layer, the drift region 231 is an N-type drift region, and the source region 242 and the drain region 244 are N+ regions.

[0054] The present application accordingly provides a method for manufacturing an isolation structure, which can be used to manufacture the isolation structure described in any of the aforementioned embodiments. Figure 4 : is a flow chart of a method for manufacturing an isolation structure in an embodiment of the present application, comprising the following steps:

[0055] S410, obtaining a substrate with a buried region formed on the upper portion.

[0056] Reference Figure 3a , the buried region 322 has a first conductivity type. In one embodiment of the present application, the substrate 310 is a semiconductor substrate, and its material can be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI). Figure 3a In the embodiment shown, the constituent material of the substrate 310 is single crystal silicon of the second conductivity type. In one embodiment of the present application, the first conductivity type is N type and the second conductivity type is P type; in another embodiment of the present application, the first conductivity type is P type and the second conductivity type is N type.

[0057] In one embodiment of the present application, step S410 includes photolithography on the substrate 310 , and then ion implantation (implanting first conductive type ions) and well driving to form a buried region 322 .

[0058] S420, forming a second conductivity type region on the buried region.

[0059] Reference Figure 3b , perform the first epitaxial growth to form a second conductivity type region 332 .

[0060] S430 , forming a first conductive type region 332 on the second conductive type region.

[0061] Reference Figure 3c, a second epitaxial growth is performed to form a first conductive type region 334.

[0062] S440 , forming a second conductive type layer 334 on the first conductive type region.

[0063] The present application requires forming second conductive type regions 332 and first conductive type regions 334 alternately arranged vertically between the buried region 322 and the second conductive type layer 330 (above the buried region 322 and below the second conductive type layer 330) to form a PNPN-… super junction structure alternately arranged. At least one layer of second conductive type region 332 and one layer of first conductive type region 334 are formed between the buried region 322 and the second conductive type layer 330. The number of second conductive type regions 332 and first conductive type regions 334 can be set according to the specific withstand voltage requirements of the device. The higher the withstand voltage requirement, the corresponding increase in the number of epitaxy times (number of layers). Figure 3d to Figure 3g In the embodiment shown, the second conductive type region 332 is provided with 3 layers, and the first conductive type region 334 is provided with 2 layers. Then, the last second conductive type epitaxial layer, ie, the second conductive type layer 334, is grown.

[0064] S450, forming a first well region and a device body.

[0065] The first well region is formed on the buried region 322, and the device body is formed in the area surrounded by the first well region, and the first well region has a first conductivity type. In one embodiment of the present application, step S450 also includes forming a second well region 328. The second well region 328 is formed outside the first well region, and the second well region 328 has a second conductivity type. Figure 3g and Figure 3h In the illustrated embodiment, the first well region includes a deep well 326 located in the second conductivity type layer 330 , and a plurality of first conductivity type well regions 327 located above the buried region 322 and below the deep well 326 .

[0066] The manufacturing method of the isolation structure can obtain a higher isolation withstand voltage by forming a super junction structure in which the second conductive type region 332 and the first conductive type region 334 are alternately arranged between the buried region 322 and the second conductive type layer 330 .

[0067] In one embodiment of the present application, each time a first conductive type region 334 is formed, a first conductive type well region 327 is formed in the first conductive type region 334 by ion implantation (injection of first conductive type ions); each time a second conductive type region 332 is formed, a first conductive type well region 327 is formed in the second conductive type region 332 by ion implantation (injection of first conductive type ions). That is, a part of the structure of the first well region (each first conductive type well region 327) is formed before step S440, and then a deep well 326 is formed in the second conductive type layer 330 by ion implantation in step S450. Each epitaxy is correspondingly performed once for well implantation (injection of first conductive type ions), and finally the buried region 322 is led out to the device surface. When the device withstands a high voltage and the buried layer junction is deep, the solution of the present application can reduce the implantation energy required for each well implantation, which can not only meet the higher withstand voltage requirements, but also avoid the influence of high energy implantation on process fluctuations and the requirements for implantation machines (high energy implantation machines are more expensive). In one embodiment of the present application, well implantation may be performed again after forming two or more epitaxial layers. In one embodiment of the present application, well push may be performed after each implantation of the first conductive type well region 327. The doping concentration of each first conductive type well region 327 and the deep well 326 is greater than the doping concentration of the first conductive type region 334.

[0068] In one embodiment of the present application, the second well region 328 is formed by photolithography and ion implantation.

[0069] In one embodiment of the present application, step S450 of forming the device body includes forming a drift region 331. The drift region 331 has a first conductivity type and can be formed by photolithography and ion implantation.

[0070] In one embodiment of the present application, step S450 further includes the step of forming a second conductive type well region 324. The second conductive type well region 324 is formed between the first well region and the drift region 331 and may be formed by photolithography and ion implantation.

[0071] In one embodiment of the present application, step S450 further includes the step of forming an insulating isolation structure 372. In one embodiment of the present application, the insulating isolation structure 372 may be a STI.

[0072] In one embodiment of the present application, step S450 further includes forming a gate dielectric layer ( Figure 3h (not shown) and the gate 352.

[0073] In one embodiment of the present application, step S450 further includes the step of forming a P+ region and an N+ region by ion implantation, including forming a source region 342, a drain region 344, a buried layer lead-out region 325, a substrate lead-out region 329, and a body lead-out region 323. The source region 342 and the body lead-out region 323 are formed in the second conductivity type well region 324, the drain region 344 is formed in the drift region 331, the buried layer lead-out region 325 is formed in the deep well 326, and the substrate lead-out region 329 is formed in the second well region 328.

[0074] exist Figure 3h In the illustrated embodiment, the semiconductor device is an NLDMOSFET, the substrate 310 is a P-type substrate, the buried region 322 is an N-type buried layer, the first well region composed of the first conductive type well region 327 and the deep well 326 is an N-well, the buried layer lead-out region 325 is an N+ region, the second well region 328 is a P-well, the body lead-out region 323 and the substrate lead-out region 329 are P+ regions, and the super junction body on the buried region 322 is a structure in which P-type epitaxial layers and N-type epitaxial layers are alternately arranged, that is, the first conductive type region 332 is an N-type epitaxial layer, the second conductive type layer 334 is a P-type epitaxial layer, the second conductive type layer 330 is a P-type epitaxial layer, the second conductive type well region 324 is a P-well, the drift region 331 is an N-type drift region, and the source region 342 and the drain region 344 are N+ regions.

[0075] Figure 5 is a schematic diagram of a partial cross-sectional structure of a semiconductor device with an isolation structure in another embodiment of the present application, which is Figure 3h The main difference of the structure shown is that the device main region includes a body region 341 of the second conductivity type, the source region 342 is located in the body region 341, and the drain region 344 is arranged in the drift region 331 and is located between the deep well 326 and the body region 341 (also between the deep well 326 and the source region 342). Figure 5 The Fully isolated NLDMOS structure shown in the figure also forms a super junction structure by adding multiple layers of PNP-...alternatingly arranged epitaxial layers between the vertical drain port and the buried layer lead-out port (i.e., the area between the drain region 344 and the buried layer lead-out region 325 and located above the buried region 322), thereby improving the isolation withstand voltage from the drain port to the buried layer lead-out port, and providing the possibility for a fully isolated structure of a high-voltage device.

[0076] It should be understood that, although the various steps in the flowchart of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0077] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0078] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. An isolation structure, characterized in that: include: a buried region, located in the substrate, having a first conductivity type; A super junction body, comprising at least one layer of a second conductivity type region and at least one layer of a first conductivity type region, wherein the second conductivity type region and the first conductivity type region are alternately arranged vertically on the buried region, and the structure of the super junction body closest to the buried region is a second conductivity type region; the first conductivity type and the second conductivity type are opposite conductivity types; A first well region, having a first conductivity type, is located on the buried region, and the first well region surrounds the super junction body in a lateral direction; A second conductive type layer is located on the super junction body, and a region of the second conductive type layer surrounded by the first well region is used to form a device body.

2. The isolation structure according to claim 1, characterized in that: The doping concentration of each of the first conductive type regions is less than the doping concentration of the buried region.

3. The isolation structure according to claim 1, characterized in that: The first well region includes a deep well located in the second conductive type layer, and a plurality of first conductive type well regions located above the buried region and below the deep well, wherein the number of the first conductive type well regions is equal to the sum of the number of the first conductive type regions and the second conductive type regions; the doping concentration of each of the first conductive type well regions and the deep well is greater than the doping concentration of the first conductive type region.

4. The isolation structure according to claim 3, characterized in that: The thickness of the deep well is greater than the thickness of each of the first conductive type well regions.

5. The isolation structure according to any one of claims 1 to 4, characterized in that: The first conductivity type is N type, and the second conductivity type is P type.

6. A semiconductor device comprising a substrate, a device body and an isolation structure isolating the device body from the substrate, characterized in that: The isolation structure is the isolation structure according to any one of claims 1 to 5, and the substrate has a second conductivity type.

7. The semiconductor device according to claim 6, characterized in that The device body includes a source region, a drain region and a drift region of an N-channel laterally diffused metal oxide semiconductor field effect transistor, and the semiconductor device also includes a gate of the N-channel laterally diffused metal oxide semiconductor field effect transistor, wherein the gate is located above the region between the source region and the drain region, and the source region, the drain region and the drift region have a first conductivity type.

8. The semiconductor device according to claim 7, characterized in that It also includes a second conductive type well region located between the first well region and the drift region, the source region is located in the second conductive type well region, the drain region is located in the drift region, the device body also includes a body lead-out region located in the second conductive type well region, the body lead-out region has a second conductive type, and the doping concentration of the body lead-out region is greater than the doping concentration of the second conductive type well region; the semiconductor device also includes: a second well region, having a second conductive type, located on the substrate and outside the first well region.

9. A method for manufacturing an isolation structure, comprising: Obtaining a substrate having a buried region formed on an upper portion, wherein the buried region has a first conductivity type; forming a second conductivity type region on the buried region; The first conductivity type and the second conductivity type are opposite conductivity types; forming a first conductive type region on the second conductive type region; forming a second conductive type layer on the first conductive type region; A first well region and a device body are formed, wherein the first well region is formed on the buried region, the device body is formed in a region surrounded by the first well region, and the first well region has a first conductivity type.

10. The method for manufacturing an isolation structure according to claim 9, characterized in that: The step of forming a second conductive type region on the buried region and the step of forming a first conductive type region on the second conductive type region include forming at least one layer of second conductive type region and at least one layer of first conductive type region on the buried region, and the second conductive type region and the first conductive type region are alternately arranged vertically on the buried region to form a super junction structure; and / or The step of forming the first well region comprises: Each time a layer of the first conductive type region is formed, a first conductive type well region is formed in the layer of the first conductive type region by ion implantation; Each time a layer of the second conductive type region is formed, a first conductive type well region is formed in the layer of the second conductive type region by ion implantation; A deep well is formed in the second conductive type layer; and the doping concentration of each of the first conductive type well regions and the deep well is greater than the doping concentration of the first conductive type region.

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