Semiconductor MOS device

Abstract

The invention discloses a semiconductor MOS (Metal Oxide Semiconductor) device, which comprises an N-type drain region and a lightly doped N-type drift region which are positioned in a silicon wafer and are stacked, at least two device unit cells are arranged in the N-type drain region and the lightly doped N-type drift region at intervals, and each device unit cell further comprises a P-type left well region and a P-type right well region which are positioned at the left part and the right part of the upper part of the lightly doped N-type drift region respectively; the lightly doped N-type drift region is vertically provided with a middle doped N-type vertical strip part at the center between the P-type left well region and the P-type right well region, and the distance between the middle doped N-type vertical strip part and the P-type left well region is equal to the distance between the middle doped N-type vertical strip part and the P-type right well region in the horizontal direction; and a trench is arranged in the lightly doped N-type drift region between the P-type right well region of one device unit cell and the P-type left well region of the other device unit cell in two adjacent device unit cells. According to the invention, the reverse recovery time and loss of the device from conduction to cut-off are reduced while the on resistance of the device is prevented from being increased.

Description

Technical Field

[0001] The present invention relates to the technical field of MOS devices, and in particular to a semiconductor MOS device. Background Art

[0002] Lateral power LDMOS devices, namely lateral double diffused metal-oxide-semiconductor devices, are widely used in the field of power integration. Lateral high-voltage MOS devices have high withstand voltage and are easy to integrate. They are widely used in high-voltage integrated circuits and power integrated circuits. At present, the reverse recovery current of lateral MOS devices is large, which is not conducive to further reducing losses. Summary of the invention

[0003] The object of the present invention is to provide a semiconductor MOS device, which avoids reducing the breakdown voltage and reduces the reverse recovery current, thereby reducing the overall loss of the device.

[0004] To achieve the above object, the technical solution adopted by the present invention is: a semiconductor MOS device, comprising: an N-type drain region and a lightly doped N-type drift region located in a silicon wafer and stacked, at least two device cells are arranged in the N-type drain region and the lightly doped N-type drift region at intervals, the device cell further comprises a left part and a right part located on the upper part of the lightly doped N-type drift region, respectively, with a P-type left well region and a P-type right well region, and the upper parts of the P-type left well region and the P-type right well region respectively have a first source region and a second source region; A gate electrode is disposed directly above the lightly doped N-type drift region between the P-type left well region and the P-type right well region, the left end of the gate electrode extends to above the first source region and the lightly doped N-type drift region, and the right end of the gate electrode extends to above the second source region and the lightly doped N-type drift region; A gate oxide layer is provided between the gate electrode and the lightly doped N-type drift region, and a middle-doped N-type vertical stripe is vertically provided at the center between the P-type left well region and the P-type right well region in the lightly doped N-type drift region, and the middle-doped N-type vertical stripe is equidistant from the P-type left well region and the P-type right well region in the horizontal direction; A first upper metal layer is located on the upper surfaces of the first source region and the second source region, a second upper metal layer is located on the upper surface of the gate electrode, and a lower metal layer is located on the lower surface of the N-type drain region; a trench is provided in the lightly doped N-type drift region between the P-type right well region of one device cell and the P-type left well region of the other device cell in the two adjacent device cells, and an insulating dielectric column is filled in the trench.

[0005] The further improved scheme in the above technical scheme is as follows: 1. In the above solution, the depth of the trench is greater than the depth of the P-type left well region and the P-type right well region.

[0006] 2. In the above scheme, the insulating dielectric column is a low dielectric constant insulating dielectric column.

[0007] 3. In the above solution, the width between the P-type left well region and the P-type right well region is 4 to 8 times the width of the middle-doped N-type vertical stripe portion.

[0008] 4. In the above solution, the height of the middle-doped N-type vertical stripe portion is lower than the heights of the P-type left well region and the P-type right well region.

[0009] 5. In the above solution, the first upper metal layer covers the central area of ​​the first source region and the second source region respectively.

[0010] 6. In the above solution, an insulating dielectric layer is located around the first upper metal layer and covers the upper edge of the P-type left well region.

[0011] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art: The semiconductor MOS device of the present invention has a P-type left well region and a P-type right well region at the left and right parts of the upper part of the lightly doped N-type drift region respectively, and the lightly doped N-type drift region has a medium-doped N-type vertical stripe portion in the area between the P-type left well region and the P-type right well region, wherein the medium-doped N-type vertical stripe portion is equal to the width of the lightly doped N-type drift region between the P-type left well region and the P-type right well region respectively; the medium-doped N-type vertical stripe portion is added at the center of the current path, thereby avoiding reducing the breakdown voltage and reducing the reverse recovery current, thereby reducing the overall loss of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Attached Figure 1 It is a schematic structural diagram of the semiconductor MOS device of the present invention.

[0013] In the above figures: 1, silicon wafer; 2, N-type drain region; 3, lightly doped N-type drift region; 41, P-type left well region; 51, first source region; 52, second source region; 6, gate electrode; 7, gate oxide layer; 8, medium-doped N-type vertical stripe portion; 91, first upper metal layer; 92, second upper metal layer; 10, lower metal layer; 11, insulating dielectric layer; 12, device unit cell; 13, trench; 14, insulating dielectric column. DETAILED DESCRIPTION

[0014] The present invention can be further understood through the specific embodiments given below, but they are not intended to limit the present invention.

[0015] Embodiment 1: A semiconductor MOS device, as shown in the accompanying drawings, comprises: an N-type drain region 2 and a lightly doped N-type drift region 3 located in a silicon wafer 1 and stacked, at least two device cells 12 are arranged in the N-type drain region 2 and the lightly doped N-type drift region 3 at intervals, the device cell 13 further comprises a P-type left well region 41 and a P-type right well region 42 at the left and right parts located on the upper part of the lightly doped N-type drift region 3, and the upper parts of the P-type left well region 41 and the P-type right well region 42 respectively have a first source region 51 and a second source region 52; A gate electrode 6 is disposed directly above the lightly doped N-type drift region 3 located between the P-type left well region 41 and the P-type right well region 42. The left end of the gate electrode 6 extends to the area between the first source region 51 and the lightly doped N-type drift region 3, and the right end of the gate electrode 6 extends to the area between the second source region 52 and the lightly doped N-type drift region 3. A gate oxide layer 7 is provided between the gate electrode 6 and the lightly doped N-type drift region 3. The lightly doped N-type drift region 3 is vertically provided with a middle-doped N-type vertical stripe 8 at the center between the P-type left well region 41 and the P-type right well region 42. The middle-doped N-type vertical stripe 8 is horizontally equidistant from the P-type left well region 41 and the P-type right well region 42. A first upper metal layer 91 is located on the upper surfaces of the first source region 51 and the second source region 52, a second upper metal layer 92 is located on the upper surface of the gate electrode 6, and a lower metal layer 10 is located on the lower surface of the N-type drain region 2; a trench 13 is provided in the lightly doped N-type drift region 3 between the P-type right well region 42 of one device cell 12 and the P-type left well region 41 of the other device cell 12 in the two adjacent device cells 12, and an insulating dielectric column 14 is filled in the trench 13.

[0016] In the embodiment, the P-type base region 3 and the lightly doped N-type drift region 4 between adjacent device cells 13 have a deep groove portion 14, and the deep groove portion 14 extends from the upper surface of the P-type base region 3 to the lower portion of the lightly doped N-type drift region 4. The deep groove portion 14 is filled with an insulating medium portion 15, which effectively avoids leakage current between device cells, thereby improving the overall reliability of the device.

[0017] The depth of the trench 13 is greater than the depth of the P-type left well region 41 and the P-type right well region 42 .

[0018] The width between the P-type left well region 41 and the P-type right well region 42 is 5 times the width of the middle-doped N-type vertical stripe portion 8 .

[0019] The height of the middle-doped N-type vertical stripe portion 8 is lower than the heights of the P-type left well region 41 and the P-type right well region 42 .

[0020] An insulating dielectric layer 11 is located around the first upper metal layer 91 and covers the upper edge of the P-type left well region 41 .

[0021] The gate oxide layer 7 is a silicon dioxide layer.

[0022] Embodiment 2: A semiconductor MOS device, comprising: an N-type drain region 2 and a lightly doped N-type drift region 3 located in a silicon wafer 1 and stacked, at least two device cells 12 are arranged in the N-type drain region 2 and the lightly doped N-type drift region 3 at intervals, the device cell 13 further comprises a P-type left well region 41 and a P-type right well region 42 at the left and right parts located at the upper part of the lightly doped N-type drift region 3, and the upper parts of the P-type left well region 41 and the P-type right well region 42 respectively have a first source region 51 and a second source region 52; A gate electrode 6 is disposed directly above the lightly doped N-type drift region 3 located between the P-type left well region 41 and the P-type right well region 42. The left end of the gate electrode 6 extends to the area between the first source region 51 and the lightly doped N-type drift region 3, and the right end of the gate electrode 6 extends to the area between the second source region 52 and the lightly doped N-type drift region 3. A gate oxide layer 7 is provided between the gate electrode 6 and the lightly doped N-type drift region 3. The lightly doped N-type drift region 3 is vertically provided with a middle-doped N-type vertical stripe 8 at the center between the P-type left well region 41 and the P-type right well region 42. The middle-doped N-type vertical stripe 8 is horizontally equidistant from the P-type left well region 41 and the P-type right well region 42. A first upper metal layer 91 is located on the upper surfaces of the first source region 51 and the second source region 52, a second upper metal layer 92 is located on the upper surface of the gate electrode 6, and a lower metal layer 10 is located on the lower surface of the N-type drain region 2; a trench 13 is provided in the lightly doped N-type drift region 3 between the P-type right well region 42 of one device cell 12 and the P-type left well region 41 of the other device cell 12 in the two adjacent device cells 12, and an insulating dielectric column 14 is filled in the trench 13.

[0023] In the embodiment, the P-type base region 3 and the lightly doped N-type drift region 4 between adjacent device cells 13 have a deep groove portion 14, and the deep groove portion 14 extends from the upper surface of the P-type base region 3 to the lower portion of the lightly doped N-type drift region 4. The deep groove portion 14 is filled with an insulating medium portion 15, which effectively avoids leakage current between device cells, thereby improving the overall reliability of the device.

[0024] The depth of the trench 13 is greater than the depth of the P-type left well region 41 and the P-type right well region 42 .

[0025] The insulating dielectric column 14 is a low dielectric constant insulating dielectric column.

[0026] The width between the P-type left well region 41 and the P-type right well region 42 is 7 times the width of the middle-doped N-type vertical stripe portion 8 .

[0027] The height of the middle-doped N-type vertical stripe portion 8 is lower than the heights of the P-type left well region 41 and the P-type right well region 42 .

[0028] The first upper metal layer 91 covers the central regions of the first source region 51 and the second source region 52 .

[0029] The insulating dielectric layer 11 is a low dielectric constant insulating dielectric layer.

[0030] When the above-mentioned semiconductor MOS device is used, the left and right parts located on the upper part of the lightly doped N-type drift region 3 respectively have a P-type left well region 41 and a P-type right well region 42, and the lightly doped N-type drift region 3 has a medium-doped N-type vertical stripe portion 8 in the area between the P-type left well region 41 and the P-type right well region 42, wherein the medium-doped N-type vertical stripe portion 8 is respectively equal to the width of the lightly doped N-type drift region 3 between the P-type left well region 41 and the P-type right well region 42; adding the medium-doped N-type vertical stripe portion at the center of the current path avoids reducing the breakdown voltage while reducing the reverse recovery current, thereby reducing the overall loss of the device.

[0031] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor MOS device, characterized in that: include: An N-type drain region (2) and a lightly doped N-type drift region (3) are located in a silicon wafer (1) and overlapped, and at least two device cells (12) are arranged in the N-type drain region (2) and the lightly doped N-type drift region (3) at intervals, and the device cell (13) further comprises a P-type left well region (41) and a P-type right well region (42) at the left and right parts located above the lightly doped N-type drift region (3), respectively, and the upper parts of the P-type left well region (41) and the P-type right well region (42) respectively have a first source region (51) and a second source region (52); A gate electrode (6) is provided directly above the lightly doped N-type drift region (3) located between the P-type left well region (41) and the P-type right well region (42); the left end of the gate electrode (6) extends to above the first source region (51) and the lightly doped N-type drift region (3); and the right end of the gate electrode (6) extends to above the second source region (52) and the lightly doped N-type drift region (3); A gate oxide layer (7) is provided between the gate electrode (6) and the lightly doped N-type drift region (3); a middle-doped N-type vertical stripe (8) is vertically provided at the center between the P-type left well region (41) and the P-type right well region (42) of the lightly doped N-type drift region (3); the middle-doped N-type vertical stripe (8) is equidistant from the P-type left well region (41) and the P-type right well region (42) in the horizontal direction; A first upper metal layer (91) is located on the upper surfaces of the first source region (51) and the second source region (52), a second upper metal layer (92) is located on the upper surface of the gate electrode (6), and a lower metal layer (10) is located on the lower surface of the N-type drain region (2); a trench (13) is provided in the lightly doped N-type drift region (3) between the P-type right well region (42) of one device cell (12) and the P-type left well region (41) of the other device cell (12) of the two adjacent device cells (12), and an insulating dielectric column (14) is filled in the trench (13).

2. The semiconductor MOS device according to claim 1, characterized in that: The depth of the groove (13) is greater than the depth of each of the P-type left well region (41) and the P-type right well region (42).

3. The semiconductor MOS device according to claim 1, characterized in that: The insulating medium column (14) is a low dielectric constant insulating medium column.

4. The semiconductor MOS device according to claim 1, characterized in that: The width between the P-type left well region (41) and the P-type right well region (42) is 4 to 8 times the width of the middle-doped N-type vertical stripe portion (8).

5. The semiconductor MOS device according to claim 1, characterized in that: The height of the middle-doped N-type vertical stripe portion (8) is lower than the heights of the P-type left well region (41) and the P-type right well region (42).

6. The semiconductor MOS device according to claim 1, characterized in that: The first upper metal layer (91) covers the central regions of the first source region (51) and the second source region (52).

7. The semiconductor MOS device according to claim 1, characterized in that: An insulating dielectric layer (11) is located around the first upper metal layer (91) and covers the top of the edge of the P-type left well region (41).

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