Semiconductor device and integrated circuit and method of forming semiconductor device

Abstract

Various embodiments of the present invention provide a method for forming a recessed gate electrode having high thickness uniformity. A gate dielectric layer is deposited as a recessed liner, and a multi-layer thin film is deposited as a recessed liner over the gate dielectric layer. The multilayer thin film includes a gate electrode layer, a first sacrificial layer over the gate electrode layer, and a second sacrificial layer over the first sacrificial dielectric layer. Planarization is performed into the second sacrificial layer and stopped on the first sacrificial layer. A first etch is performed into the first sacrificial layer and the second sacrificial layer to remove the first sacrificial layer at the side of the recess. A second etch is performed into the gate electrode layer using the first sacrificial layer as a mask to form a recessed gate electrode. A third etch is performed after the second etch to remove the first sacrificial layer. According to the embodiment of the invention, a semiconductor device and an integrated circuit are also provided.

Description

[0001] This application is a divisional application of the invention patent application entitled “Semiconductor devices, integrated circuits and methods for forming semiconductor devices” with application number 202110086383.9 filed on January 22, 2021. Technical Field

[0002] Embodiments of the present application relate to semiconductor devices and integrated circuits and methods of forming semiconductor devices. Background Art

[0003] Integrated circuits (ICs) may include low voltage (LV) metal oxide semiconductor (MOS) devices and high voltage (HV) MOS devices. MOS devices include a gate electrode and a gate dielectric layer separating the gate electrode from a substrate. HV MOS devices typically have a thicker gate dielectric layer than LV MOS devices and therefore typically have a higher height than LV MOS devices. However, a higher height increases the difficulty of integrating the manufacturing process for the HV MOS device with the manufacturing process for the LV MOS device. Therefore, the gate electrode of the HV MOS device may be recessed into the substrate to minimize the effect of the increased height. Summary of the invention

[0004] According to an embodiment of the present application, a semiconductor device is provided, comprising: a substrate; a pair of source / drain regions located in the substrate; a gate dielectric layer located on the substrate; and a gate electrode recessed into the top of the gate dielectric layer and laterally located between the source / drain regions, wherein a top surface of the gate electrode has a first edge and a second edge on opposite sides of the gate electrode, respectively, wherein a thickness of the gate electrode is substantially uniform from the first edge to the second edge, and wherein the gate electrode has a pair of features located at the first edge and the second edge, respectively.

[0005] According to another embodiment of the present application, an integrated circuit is provided, comprising: a substrate; a pair of source / drain regions located in the substrate; a gate electrode located laterally between the source / drain regions, wherein the top of the gate electrode has a feature extending laterally along the periphery of the gate electrode in a closed path, wherein the feature has a first segment and a second segment located on opposite sides of the gate electrode, respectively, wherein the top of the gate electrode is substantially flat from the first segment to the second segment, and wherein the feature is a protrusion or a depression; and a gate dielectric layer surrounding the bottom of the gate electrode from the sidewall of the gate electrode to the bottom surface of the gate electrode.

[0006] According to another embodiment of the present application, a method for forming a semiconductor device is provided, the method comprising: forming a recess located above a substrate; depositing a gate dielectric layer, the gate dielectric layer serving as a liner of the recess and partially filling the recess; depositing a multilayer film, the multilayer film filling the remaining portion of the recess above the gate dielectric layer and comprising a gate electrode layer, a first sacrificial layer located above the gate electrode layer, and a second sacrificial layer located above the first sacrificial layer; performing planarization into the second sacrificial layer, the planarization stops on the first sacrificial layer, and the second sacrificial layer is removed at the side of the recess; performing a first etch into the first sacrificial layer and the second sacrificial layer to remove the first sacrificial layer at the side of the recess; and performing a second etch into the gate electrode layer, the second etch using the first sacrificial layer as a mask to remove the gate electrode layer at the side of the recess, and forming a gate electrode located below the first sacrificial layer in the recess.

[0007] Embodiments of the present application provide devices with recessed gate electrodes having high thickness uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0009] Figure 1 illustrates cross-sectional views of some embodiments of semiconductor devices including recessed gate electrodes having high thickness uniformity;

[0010] Figure 2A and Figure 2B Shows Figure 1 Top layouts of various embodiments of recessed gate electrodes;

[0011] Figure 3 Shown include Figure 1 Cross-sectional views of some embodiments of an integrated circuit (IC) of a semiconductor device;

[0012] Figure 4 Shows Figure 3 Cross-sectional views of some alternative embodiments of ICs wherein the trench isolation structures and the channel regions are varied;

[0013] Figure 5A-5F Shows Figure 4 Cross-sectional views of various alternative embodiments of an IC in which the recessed gate electrode is varied;

[0014] Figure 6 Shows Figure 3Cross-sectional views of some alternative embodiments of an IC, wherein the recessed gate electrode is recessed into the gate dielectric layer instead of the substrate;

[0015] Fig. 7A and Figure 7B Shows that along with Figure 6 The cross-sectional view is orthogonal to the direction Figure 6 Cross-sectional views of various embodiments of ICs;

[0016] Figure 8A-8C Shows Figure 6 Cross-sectional views of various alternative embodiments of an IC in which the recessed gate electrode is varied;

[0017] Fig. 9 Shows Figure 6 Cross-sectional views of some alternative embodiments of an IC, wherein the gate dielectric layer is located above the source / drain regions;

[0018] Fig.10 Shows Fig. 9 Cross-sectional views of some alternative embodiments of ICs wherein the recessed gate electrode is varied;

[0019] Figure 11-Figure 24 A series of cross-sectional views illustrating some embodiments of methods for forming a semiconductor device including a recessed gate electrode having high thickness uniformity;

[0020] Figure 25-Figure 29 Shows Figure 11-Figure 24 a series of cross-sectional views of some alternative embodiments of the method, wherein the gate electrode layer has a recessed surface that is recessed relative to a top surface of the gate dielectric layer;

[0021] Figure 30-Figure 34 Shows Figure 11-Figure 24 a series of cross-sectional views of some alternative embodiments of the method wherein the gate electrode layer has a recessed surface that is elevated by a greater amount above a top surface of the gate dielectric layer;

[0022] Fig.35 Shows Figure 11-Figure 34 Block diagram of some embodiments of the method;

[0023] Figure 36-Figure 43 Shows Figure 11-Figure 24 a series of cross-sectional views of some alternative embodiments of the method wherein a recessed gate electrode is formed as an alternative dummy structure;

[0024] Figure 44-Figure 49 Shows Figure 36-Figure 43 a series of cross-sectional views of some alternative embodiments of the method, wherein the gate electrode layer has a recessed surface that is recessed relative to a top surface of the gate dielectric layer;

[0025] Fig.50 Shows Figure 36-Figure 49 A block diagram of some embodiments of the method. DETAILED DESCRIPTION

[0026] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or structures discussed.

[0027] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0028] Various embodiments of the present invention are directed to methods for forming a semiconductor device including a recessed gate electrode with high thickness uniformity, and semiconductor devices produced by the method. In some embodiments, the recess is formed on a substrate. A gate dielectric layer is deposited as a liner for the recess and partially fills the recess, and a multilayer film is deposited to fill the remaining recess above the gate dielectric layer. The multilayer film includes a gate electrode layer, a first sacrificial layer located above the gate electrode layer, and a second sacrificial layer located above the first sacrificial dielectric layer. Planarization is implemented into the second sacrificial layer and stops on the first sacrificial layer. A first etch is implemented into the first sacrificial layer to remove a portion of the first sacrificial layer at the side of the recess. Using the first sacrificial layer as a mask, a second etch is implemented into the gate electrode layer to remove a portion of the gate electrode layer at the side of the recess, and a recessed gate electrode located below the first sacrificial layer is formed in the recess. The first etch and, in some embodiments, the second etch removes the second sacrificial layer. A third etch is implemented to remove the first sacrificial layer. In some embodiments, the first etch and the second etch are implemented by dry etching, and the third etch is implemented by wet etching. However, other etching types are acceptable.

[0029] In some embodiments, the multilayer film is deposited so that each individual layer of the multilayer film is recessed above the recess. In this way, after the planarization is completed, a portion of the second sacrificial layer remains directly above the recess. The remaining portion of the second sacrificial layer is used as a mask to protect the portion of the first sacrificial layer below during the first etch, so that the first sacrificial layer is not removed from directly above the recess. During the second etch, and until the second etch is completed, the first sacrificial layer is used as a mask to protect the portion of the gate electrode layer below that corresponds to the recessed gate electrode. In this way, throughout the second etch, the recessed gate electrode remains protected by the first sacrificial layer and can have the same thickness as the deposited gate electrode layer.

[0030] Since the deposition process can form a gate electrode layer with high thickness uniformity, the recessed gate electrode can have high thickness uniformity. In addition, since the recessed gate electrode remains protected by the first sacrificial layer throughout the second etching, the top surface of the recessed gate electrode can have high flatness. When batch manufacturing semiconductor devices, high thickness uniformity and high flatness can cause high uniformity of electrical characteristics of the recessed gate electrode and / or semiconductor devices. For example, the resistance of the recessed gate electrode and / or the work function of the recessed gate electrode can have high uniformity, so that the threshold voltage of the semiconductor device can have high uniformity.

[0031] refer to Figure 1 , a cross-sectional view 100 of some embodiments of a semiconductor device 102 including a recessed gate electrode 104 having high thickness uniformity is provided. The recessed gate electrode 104 is recessed into the top of a substrate 106. The recessed gate electrode 104 may be, for example, or include metal, doped polysilicon, some other suitable (some) conductive material, or any combination of the foregoing. The substrate 106 may be, for example, or include a single crystal silicon substrate, a silicon on insulator (SOI) substrate, or some other suitable semiconductor substrate.

[0032] The top surface 104t of the recessed gate electrode 104 has a high flatness (e.g., is flat or substantially flat) between the first feature 108a and the second feature 108b, which are respectively located on opposite sides of the recessed gate electrode 104 and at the periphery of the recessed gate electrode 104. In addition, the thickness T of the recessed gate electrode 104 is g There is high uniformity (eg, uniform or substantially uniform) between the first feature 108a and the second feature 108b. In at least some embodiments, since the recessed gate electrode 104 is formed according to the method of the present invention, the top surface 104t has high flatness and the thickness T g Has high uniformity.

[0033] As described below, at least some embodiments of the method may use both planarization and etching to form a recessed gate electrode 104 through a multi-layer thin film. In addition, planarization and etching may be performed in a manner that prevents exposure of the recessed gate electrode 104 to the planarization etchant and limits exposure of the recessed gate electrode 104 to the periphery of the recessed gate electrode 104. The limited exposure to the etchant may result in the first feature 108a and the second feature 108b. Since the recessed gate electrode 104 is limited to being exposed at the periphery of the recessed gate electrode 104, the thickness T g is as deposited at the rest of the recessed gate electrode 104. Since the deposition process can deposit materials with high thickness uniformity, the thickness T g The rest of the recessed gate electrode 104 may have high uniformity.

[0034] In some embodiments, if the difference between the highest height on the top surface 104t and the lowest height on the top surface 104t is less than about 1%, 2%, 5%, or some other suitable percentage of the highest height, the top surface 104t of the recessed gate electrode 104 has a high flatness. In addition, in some embodiments, if the difference between the minimum thickness value and the maximum thickness value is less than about 1%, 2%, 5%, or some other suitable percentage of the maximum thickness value, the thickness T g If the top surface 104t has too much variation (e.g., variation greater than about 5% of the highest height or some other suitable percentage), and / or the thickness T g With too large a variation (e.g., a variation greater than about 5% of the maximum thickness value or some other suitable percentage), the electrical characteristics of the recessed gate electrode 104 and / or the electrical characteristics of the semiconductor device 102 may deviate significantly and / or may deviate out of specification. The electrical characteristics may include, for example, gate resistance, gate work function, threshold voltage, other suitable characteristics, or any combination of the foregoing.

[0035] In some embodiments, the thickness T g is about 20 nm to 200 nm, about 20 nm to 110 nm, about 110 nm to 200 nm, about 100.16 nm, about 100.35 nm, or some other suitable value. g If the thickness T is too small (e.g., less than about 20 nanometers or some other suitable value), during the formation of the contact via on the recessed gate electrode 104, over-etching may extend through the recessed gate electrode 104 and damage the gate dielectric layer 110 located below the recessed gate electrode 104. Such damage may cause the operating parameters of the semiconductor device 102 to deviate from the specification range and / or reduce the performance of the semiconductor device 102. gIf the planarized surface is too large (e.g., greater than about 200 nanometers or some other suitable value), it may be difficult to integrate with other semiconductor devices on substrate 106. For example, the top surface of semiconductor device 102 may be elevated above the top surfaces of other semiconductor devices to such an extent that the load of chemical mechanical polishing (CMP) at semiconductor device 102 may be too high. As a result, the planarized surface may be angled and / or uneven, rather than substantially horizontal and / or substantially flat. This may result in overlay errors and / or other process difficulties.

[0036] The first feature 108a and the second feature 108b are concave indentations and / or depressions in the top of the recessed gate electrode 104. In alternative embodiments, the first feature 108a and the second feature 108b are upward protrusions, inverted fillets, or some other suitable features. The first feature 108a and the second feature 108b are characterized as features because the first feature 108a and the second feature 108b introduce non-uniformity into the thickness T of the recessed gate electrode 104. g As shown below and briefly mentioned above, the first features 108 a and the second features 108 b may be, for example, byproducts of a method for forming the recessed gate electrode 104 .

[0037] In some embodiments, first feature 108a is a mirror image of second feature 108b. Additionally, in some embodiments, first feature 108a and second feature 108b occupy a small percentage of the surface area in a two-dimensional (2D) projection of recessed gate electrode 104 on a top surface and / or a horizontal plane of substrate 106. The 2D projection of recessed gate electrode 104 may, for example, also be referred to as the footprint of recessed gate electrode 104. The small percentage may, for example, be a percentage less than about 5%, 10%, or 20%, or some other suitable percentage.

[0038] Since the first feature 108a and the second feature 108b introduce non-uniformity into the thickness T of the recessed gate electrode 104 g Therefore, the first feature 108a and the second feature 108b occupy a smaller surface area, and the thickness T g If the first features 108a and the second features 108b occupy too large a surface area (eg, greater than about 20% or some other suitable percentage), the electrical characteristics of the recessed gate electrode 104 may deviate significantly and / or may deviate out of specification.

[0039] The gate dielectric layer 110 embraces the lower side of the recessed gate electrode 104 and separates the recessed gate electrode 104 from the substrate 106. The gate dielectric layer 110 can be or include, for example, silicon oxide and / or some other suitable (some) dielectrics. In addition, a pair of source / drain regions 112 are located in the substrate 106. The source / drain regions 112 are respectively located on opposite sides of the recessed gate electrode 104. The source / drain regions 112 can be or include, for example, a doped semiconductor region of the substrate 106 and / or an epitaxial layer grown on the substrate 106.

[0040] The channel region 106c is located below the recessed gate electrode 104 in the substrate 106 and extends from one of the source / drain regions 112 to the other of the source / drain regions 112. The channel region 106c is configured to switch between a conductive state and a non-conductive state according to a bias voltage applied to the recessed gate electrode 104. For example, when the recessed gate electrode 104 is biased at a voltage higher than a threshold voltage, the channel region 106c can be switched to a conductive state. As another example, when the recessed gate electrode 104 is biased at a voltage lower than a threshold voltage, the channel region 106c can be switched to a non-conductive state.

[0041] In some embodiments, semiconductor device 102 is a field effect transistor (FET), some other suitable transistor, a memory cell, or some other suitable semiconductor device. In some embodiments, semiconductor device 102 is relatively large. When the width W of recessed gate electrode 104 is g The semiconductor device 102 may be, for example, larger than about 20 microns, 30 microns, or some other suitable value. Further, the semiconductor device 102 may, for example, have such a larger width when used in HV applications or some other suitable applications. High voltage (HV) applications may, for example, be applications in which the semiconductor device 102 operates at voltages exceeding 100 volts, 200 volts, 600 volts, 1200 volts, or some other suitable value.

[0042] refer to Figure 2A and Figure 2B , provides Figure 1 Top layouts 200A, 200B of various embodiments of the recessed gate electrode 104 are shown. Figure 1 The cross-sectional view 100 may be, for example, along Figure 2A and Figure 2B A is intercepted along any one of Figure 2A and Figure 2B any one of which may be intercepted by some other suitable line (not shown).

[0043] The first feature 108a and the second feature 108b correspond to the region of the ring-shaped feature 108 (shown in dashed lines) that extends along the edge of the recessed gate electrode 104 in a closed path. Figure 2A In FIG. 1 , the recessed gate electrode 104 is a square, and thus the annular feature 108 is a square annular. Figure 2B In FIG. 1 , the recessed gate electrode 104 is circular, and thus the annular member 108 is annular. Figure 2A and Figure 2B Specific shapes for the recessed gate electrode 104 and the ring-shaped feature 108 are provided in , but other shapes for the recessed gate electrode 104 and the ring-shaped feature 108 are acceptable.

[0044] refer to Figure 3 , provides Figure 1 1. A cross-sectional view 300 of some embodiments of an integrated circuit (IC) of a semiconductor device 102 of FIG. 1. The semiconductor device 102 is surrounded by a trench isolation structure 302. The trench isolation structure 302 extends into the top of the substrate 106 and provides electrical isolation between the semiconductor device 102 and other semiconductor devices (not shown). The trench isolation structure 302 is or includes silicon oxide and / or some other suitable (some) dielectric. In addition, the trench isolation structure 302 can be or include, for example, a shallow trench isolation (STI) structure or some other suitable trench isolation structure.

[0045] The interconnect structure 304 is located above the substrate 106 and the semiconductor device 102, and includes an interlayer dielectric (ILD) layer 306 and a plurality of contact vias 308. The contact vias 308 are located in the ILD layer 306 and extend to the source / drain regions 112 and the recessed gate electrode 104, respectively. In some embodiments, the interconnect structure 304 also includes a plurality of wires (not shown) and a plurality of inter-wire vias (not shown) alternately stacked above the contact vias 308 to define a conductive path leading out of the contact vias 308. The ILD layer 306 may be or include, for example, silicon oxide and / or some other suitable (some) dielectrics. The contact vias 308 may be or include, for example, metal and / or some other suitable (some) conductive material.

[0046] The silicide layer 310 is located on the recessed gate electrode 104 and provides an ohmic connection between the recessed gate electrode 104 and the corresponding contact via. In an alternative embodiment, the silicide layer 310 is omitted. In addition, in an alternative embodiment, a silicide layer (not shown) is located on the source / drain region 112 to provide an ohmic connection between the source / drain region 112 and the corresponding contact via. The silicide layer 310 can be or include, for example, nickel silicide and / or some other suitable metal silicide.

[0047] A hard mask 312 is located on the recessed gate electrode 104 and the gate dielectric layer 110. The hard mask 312 has a pair of sections adjacent to opposite edges of the silicide layer 310, respectively, and the sections extend from the source / drain region 112 to the opposite edges, respectively. As described below, the hard mask 312 can be used as a mask, for example, during the formation of the source / drain region 112 and / or the silicide layer 310. The hard mask 312 can be, for example, or include silicon nitride, silicon oxide, some other suitable dielectric(s), or any combination thereof.

[0048] A base dielectric layer 314 is located on the trench isolation structure 302 and the substrate 106, to the side of the gate dielectric layer 110, and between the hard mask 312 and the substrate 106. In addition, a contact etch stop layer (CESL) 316 is located on the base dielectric layer 314 and the hard mask 312. As described below, the CESL 316 can be used as an etch stop when forming contact vias corresponding to the source / drain regions 112 within the etch openings. The base dielectric layer 314 can be or include, for example, silicon oxide and / or some other suitable (some) dielectric. The CESL 316 can be or include, for example, silicon nitride and / or some other suitable (some) dielectric.

[0049] refer to Figure 4 , provides Figure 3 400 of some alternative embodiments of an IC, wherein a segment 302a of a trench isolation structure 302 separates an adjacent source / drain region 112a from a recessed gate electrode 304. As a result, the channel region 106c is routed around the bottom of the trench isolation segment 302a and has an increased length. In addition, the portion of the channel region 106c at the adjacent source / drain region 112a and the trench isolation segment 302a is further away from the recessed gate electrode 104 than the remainder of the channel region 106c. As a result, the portion of the channel region 106c relies on a stronger electric field to switch between a conductive state and a non-conductive state than the remainder of the channel region 106c. This, in turn, allows the semiconductor device 102 to operate at a higher voltage.

[0050] refer to Figure 5A-5F , provides Figure 4 500A-500F are cross-sectional views of various alternative embodiments of an IC in which the recessed gate electrode 104 is varied. Figure 5A In the embodiment, the first feature 108a and the second feature 108b are inverted circles and / or concave corners. In some embodiments, the inverted circles and / or concave corners are continuously curved downward with a decreasing slope from the top surface of the recessed gate electrode 104 to the sidewalls of the recessed gate electrode 104. Figure 5B In FIG. 1 , the first feature 108 a and the second feature 108 b are protrusions that protrude upward and have rounded tops. Figure 5C In the embodiment, the first feature 108a and the second feature 108b are protrusions that protrude upward and have a flat or substantially flat top. Figure 5D , the first feature 108a and the second feature 108b are protrusions that protrude upward and have top surfaces with concave recesses.

[0051] exist Figure 5E and Fig. 5F Of the two, the recessed gate electrode 104 and gate dielectric layer 110 are less straight and have, among other things, more rounded edges and more sloped sidewalls. Figure 5E In FIG. 1 , the first feature 108a and the second feature 108b are protrusions. Fig. 5F In the embodiment, the recessed gate electrode 104 is partially located above the section 302a of the trench isolation structure 302 and has an uneven bottom surface and a height change at the section 302a. In addition, the thickness T of the recessed gate electrode 104 is g The source / drain regions 112a increase toward the segment 302a adjacent to the trench isolation structure 302. Disposing the recessed gate electrode 104 above the trench isolation segment 302a may enable the semiconductor device 102 to operate at a high voltage because the trench isolation structure 302 dissipates the electric field generated by the recessed gate electrode 104.

[0052] Although about Figure 1 The recessed gate electrode 104 describes Figure 2A and Figure 2B , but it should be understood that Figure 2A and 2B Can be applied to Figure 3 , Figure 4 ,and Figure 5A-5F The recessed gate electrode 104 in any one of the above. For example, Figure 3 , Figure 4 ,and Figure 5A-5F Any of them can be along Figure 2A and 2B The line A in any one of the above is intercepted, or along Figure 2A and Figure 2B Some other suitable line (not shown) in any one of them is intercepted. Although 5A- Fig. 5F The trench isolation structure 302 and the channel region 106c are configured as follows Figure 4 As shown, however, the trench isolation structure 302 and the channel region 106c may alternatively be configured as follows Figure 1 and Figure 3 shown.

[0053] refer to Figure 6 , provides Figure 36 is a cross-sectional view of some alternative embodiments of an IC, wherein the recessed gate electrode 104 is recessed into the gate dielectric layer 110 instead of being recessed into the substrate 106. In addition, the source / drain regions 112 have top surfaces that are elevated above the top surface of the substrate 106, the base dielectric layer 314 and the hard mask 312 are omitted, and the CESL 316 is located on the sidewalls of the gate dielectric layer 110. In some alternative embodiments, the base dielectric layer 314 and / or the hard mask 312 are retained.

[0054] refer to Fig. 7A and Figure 7B , providing a Figure 6 The cross-sectional view 600 is orthogonal to the direction Figure 6 Cross-sectional views 700A, 700B of various embodiments of an IC. Fig. 7A and Figure 7B The cross-sectional views 700A and 700B are alternative embodiments to each other, and Figure 6 The cross-sectional view 600 may be, for example, along Fig. 7A and Figure 7B The line B in any one of the above is intercepted. Fig. 7A In FIG. 1 , the semiconductor device 102 is a planar FET, so that the bottom surface of the recessed gate electrode 104 is a planar or substantially planar surface. Figure 7B In FIG. 1 , the semiconductor device 102 is a finFET such that the bottom surface of the recessed gate electrode 104 wraps around the top of the fin defined by the substrate 106 . Fig. 7A and Figure 7B In both cases, the semiconductor device 102 is partially located above the trench isolation structure 302 .

[0055] refer to Figure 8A-8C , provides Figure 6 800A-800C are cross-sectional views of various alternative embodiments of an IC in which the recessed gate electrode 104 is varied. Fig. 8A In FIG. 1 , the first feature 108 a and the second feature 108 b are inverted fillets. Figure 8B In FIG. 1 , the first feature 108 a and the second feature 108 b are protrusions that protrude upward and have rounded tops. Figure 8C In the embodiment, the first feature 108a and the second feature 108b are protrusions that protrude upward and have a flat or substantially flat top. In an alternative embodiment, the recessed gate electrode 104 may be as follows: Figure 1 , Figure 3 , Figure 4 ,and Figure 5A-5F Any one of .

[0056] refer to Fig. 9 , provides Figure 6900 of some alternative embodiments of an IC, wherein the gate dielectric layer 110 is located above the source / drain region 112. In addition, the first feature 108a and the second feature 108b are more symmetrical, and the top surface of the recessed gate electrode 104 is elevated above the top surface of the gate dielectric layer 110. In alternative embodiments, the top surface of the recessed gate electrode 104 can be approximately flush with the top surface of the gate dielectric layer 110, or recessed below the top surface of the gate dielectric layer 110.

[0057] refer to Fig.10 , provides Fig. 9 1000 of some alternative embodiments of an IC, wherein the first feature 108a and the second feature 108b are protrusions that protrude upward and have a flat or substantially flat top. In addition, the top surface of the protrusion is approximately flush with the top surface of the gate dielectric layer 110. In alternative embodiments, the top surface of the protrusion can be raised above the top surface of the gate dielectric layer 110, or recessed below the top surface of the gate dielectric layer 110. In alternative embodiments, the recessed gate electrode 104 can be as shown in FIG. Figure 1 , Figure 3 , Figure 4 , Figure 5A-5F , Figure 6 , Fig. 7A , Figure 7B ,and Figure 8A-8C Any one of .

[0058] Although about Figure 1 The recessed gate electrode 104 describes Figure 2A and 2B , but it should be understood that Figure 2A and 2B Can be applied to Figure 6 , Fig. 7A , Figure 7B , Figure 8A-8C , Fig. 9 ,and Fig.10 The recessed gate electrode 104 in any one of the above. For example, Figure 6 , Fig. 7A , Figure 7B , Figure 8A-8C , Fig. 9 ,and Fig.10 Any of them can be along Figure 2A and 2B A is intercepted along any of the lines Figure 2A and Figure 2B Some other suitable line (not shown) in any one of them is intercepted. Although Figure 6 The semiconductor device 102 describes Fig. 7A and 7B , but it should be understood that Fig. 7A and Figure 7B Can be applied to Figure 8A-8C , Fig. 9 ,and Fig.10 A semiconductor device 102 in any one of the embodiments. For example, Figure 8A-8C , Fig. 9 ,and Fig.10 Any of them can be along Fig. 7A and Figure 7B The line B in any one of the above is intercepted, or along Fig. 7A and Figure 7B or some other suitable line (not shown) in any one of the above.

[0059] refer to Figure 11-Figure 24 , a series of cross-sectional views 1100-2400 of some embodiments of a method for forming a semiconductor device including a recessed gate electrode having high thickness uniformity are provided. The cross-sectional views 1100-2400 correspond to Figure 4 400, and thus shows Figure 4 However, the method shown in the cross-sectional view 1100-1100 may also be used to form the IC and the semiconductor device 102. Figure 1 , Figure 3 , Figure 4 ,and Figure 5A-5F An IC and / or semiconductor device 102 in any one of the embodiments.

[0060] like Fig.11 As shown in the cross-sectional view 1100 of , a substrate 106 is provided. The substrate 106 is covered by a first base dielectric layer 314 and a second base dielectric layer 1102. In addition, the trench isolation structure 302 extends to the top of the substrate 106 and is also covered by the first base dielectric layer 314 and the second base dielectric layer 1102. The second base dielectric layer 1102 can be or include, for example, silicon nitride and / or some other suitable (some) dielectric. In some embodiments, the first base dielectric layer 314 is or includes silicon oxide, and the second base dielectric layer 1102 is or includes silicon nitride.

[0061] Also through Fig.11 1100, the substrate 106 is patterned to form a recess 1104 extending to a depth D1 in the substrate 106. The depth D1 may be, for example, about 500 angstroms to 1500 angstroms, about 500 angstroms to 1000 angstroms, about 1000 angstroms to 1500 angstroms, about 1000 angstroms, or some other suitable value. The patterning may be implemented, for example, by a photolithography / etching process or some other suitable process. The photolithography / etching process may, for example, employ a photoresist mask 1106 and / or some other suitable mask located above the second base dielectric layer 1102.

[0062] like Fig.12 As shown in the cross-sectional view 1200 of , the gate dielectric layer 110 is deposited on the second base dielectric layer 1102 and serves as a liner for the recess 1104. The gate dielectric layer 110 is recessed at the recess 1104 and may be or include, for example, silicon oxide and / or some other suitable dielectric(s).

[0063] Also through Fig.12 1200 shows that a multilayer film 1202 is deposited over the gate dielectric layer 110 and acts as a liner for the recess 1104. The multilayer film 1202 includes a gate electrode layer 1204, a first sacrificial layer 1206, and a second sacrificial layer 1208, each of which is recessed at the recess 1104. The gate electrode layer 1204 is conductive and can be or include, for example, doped polysilicon, a metal, some other suitable (some) conductive material, or any combination of the foregoing. The first sacrificial layer 1206 is located above the gate electrode layer 1204 and can be or include, for example, silicon nitride, silicon oxide, silicon oxynitride, some other suitable (some) dielectric, or any combination of the foregoing. The second sacrificial layer 1208 is located above the first sacrificial layer 1206 and is a different material from the first sacrificial layer 1206. The second sacrificial layer 1208 can be silicon oxide and / or some other suitable (some) dielectric. Alternatively, the second sacrificial layer 1208 may be a metal, doped polysilicon, some other suitable conductive material(s), or any combination thereof. In some embodiments, the gate electrode layer 1204 and the second sacrificial layer 1208 are or include the same material. Additionally, in some embodiments, the gate electrode layer 1204 is or includes doped polysilicon, the first sacrificial layer 1206 is or includes silicon nitride, and the second sacrificial layer 1208 is or includes silicon oxide.

[0064] In some embodiments, the gate dielectric layer 110 and the various layers of the multilayer thin film 1202 are conformally deposited. In addition, in some embodiments, the gate dielectric layer 110 and the various layers of the multilayer thin film 1202 are deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), some other suitable deposition process(es), or any combination thereof.

[0065] The thickness T of the gate electrode layer 1204 is deposited gCorresponding to the final thickness of the recessed gate electrode formed by the gate electrode layer 1204 hereinafter. Since CVD, PVD, and other suitable deposition processes can form the gate electrode layer 1204 with high thickness uniformity, the recessed gate electrode can have high thickness uniformity. When semiconductor devices are manufactured in batches, high thickness uniformity can obtain high uniformity of electrical characteristics of the recessed gate electrode and / or the semiconductor device. For example, the resistance of the recessed gate electrode and / or the work function of the recessed gate electrode can have high uniformity, so that the threshold voltage of the semiconductor device can have high uniformity.

[0066] In addition, the thickness T g The recessed surface 1204r of the gate electrode layer 1204 is raised above the top surface of the gate dielectric layer 110 by a distance D2. In an alternative embodiment, the thickness T g The recessed surface 1204r of the gate electrode layer 1204 is approximately flush with the top surface of the gate dielectric layer 110 (eg, the distance D2 is approximately zero). As will be shown below, the thickness T g Variations of can obtain recessed gate electrodes with different profiles.

[0067] like Fig.13 As shown in the cross-sectional view 1300 of , the first planarization is performed into the second sacrificial layer 1208 and stops on the first sacrificial layer 1206. The first planarization can be performed, for example, by CMP and / or some other suitable planarization process. Since the first planarization stops on the first sacrificial layer 1206 and the first sacrificial layer 1206 is recessed at the recess 1104, the second sacrificial layer 1208 remains at the recess 1104. In addition, in at least one embodiment in which the first planarization is performed by CMP, different CMP removal rates may cause the second sacrificial layer 1208 to be recessed. In this way, the top surface 1208t of the second sacrificial layer 1208 may be concave and / or the thickness T of the second sacrificial layer 1208 may be greater than or equal to 0. s May be uneven.

[0068] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 1 , the first etching is performed into the multilayer thin film 1202. The first etching removes the portion of the first sacrificial layer 1206 at the side of the recess 1104, and the portion not covered by the second sacrificial layer 1208 (see, for example, Fig.13 As a result, the first sacrificial layer 1206 has a pair of protrusions 1402 at the periphery of the first sacrificial layer 1206 and on opposite sides of the first sacrificial layer 1206. In addition, the first etching thins the gate electrode layer 1204 and removes the second sacrificial layer 1208 (see, for example Fig.13). In an alternative embodiment, the first etch does not remove the second sacrificial layer 1208, but rather thins the second sacrificial layer 1208. Regardless of whether the second sacrificial layer 1208 is removed by the first etch or only thinned by the first etch, the second sacrificial layer 1208 acts as a mask to protect the underlying portion of the first sacrificial layer 1206. However, for the second sacrificial layer 1208, the portion of the first sacrificial layer 1206 located above the recess 1104 will be removed or substantially thinned.

[0069] In some embodiments, the first etch is performed using a non-selective etchant. The non-selective etchant may, for example, be non-selective in that it has the same or substantially the same etching rate for the first sacrificial layer 1206 as for the second sacrificial layer 1208 and / or the gate electrode layer 1204. In alternative embodiments, the first etch is performed using a selective etchant that has high selectivity (e.g., high etching rate) for the first sacrificial layer 1206 relative to the second sacrificial layer 1208 and / or the gate electrode layer 1204. In some embodiments, the first etch is performed by dry etching. In alternative embodiments, the first etch is performed by wet etching and / or some other suitable type of etching.

[0070] like Fig.15 As shown in the cross-sectional view 1500 of , the second etch is performed into the gate electrode layer 1204 and stops on the first sacrificial layer 1206 and the gate dielectric layer 110. The second etch removes the portion of the gate electrode layer 1204 at the side of the recess 1104 and the portion not covered by the first sacrificial layer 1206. As a result, the second etch forms a recessed gate electrode 104 in the recess 1104. In addition, the second etch removes any remaining portion of the second sacrificial layer 1208 (see, e.g., Fig.13 ).

[0071] The first sacrificial layer 1206 is used as a mask to protect the portion of the underlying gate electrode layer 1204. Since the first sacrificial layer 1206 protects the gate electrode layer 1204 and the second etch stops on the first sacrificial layer 1206, the thickness T of the recessed gate electrode 104 is g The gate electrode layer 1204 deposited where the recessed gate electrode 104 is covered by the first sacrificial layer 1206 (see, for example, Fig.12 ) are the same thickness. Since the gate electrode layer 1204 can be deposited to have high thickness uniformity, the recessed gate electrode 104 can have high thickness uniformity. When the recessed gate electrodes 104 are manufactured in batches, the high thickness uniformity can obtain high uniformity of the electrical characteristics of the recessed gate electrodes 104.

[0072] Since the recessed gate electrode 104 is not covered by the first sacrificial layer 1206 at the periphery of the recessed gate electrode 104, the second etching over-etches into the recessed gate electrode 104 at the periphery of the recessed gate electrode 104. As a result, the first feature 108a and the second feature 108b are formed at the periphery of the recessed gate electrode 104, respectively, on opposite sides of the recessed gate electrode 104. The top layout of the recessed gate electrode 104 may be, for example, Figure 2A and Figure 2B Any of, and / or, Fig.15 The cross-sectional view 1500 may be, for example, along Figure 2A and Figure 2B However, other top layouts are acceptable.

[0073] The second etch is performed using a selective etchant having a high etch rate for the gate electrode layer 1204 relative to the first sacrificial layer 1206 and / or the gate dielectric layer 110. In some embodiments, the second etch is performed by dry etching. In alternative embodiments, the second etch is performed by wet etching and / or some other suitable etching type. However, dry etching can achieve higher selectivity than wet etching. Due to the higher selectivity, dry etching is less likely to etch through the first sacrificial layer 1206 at the recessed gate electrode 104 than wet etching. Therefore, compared with wet etching, dry etching is less likely to cause damage to the recessed gate electrode 104.

[0074] In some embodiments, the first etching and the second etching are implemented in a common process chamber, so that from the beginning of the first etching to the end of the second etching, the substrate 106 remains in the common process chamber. In an alternative embodiment, the first etching and the second etching are implemented in separate process chambers. In some embodiments, the first etching and the second etching are implemented by the same etching type. For example, the first etching and the second etching can be implemented by dry etching. In an alternative embodiment, the first etching and the second etching are implemented by different etching types. For example, the first etching can be implemented by wet etching, and the second etching can be implemented by dry etching, and vice versa.

[0075] In some embodiments, the first etching and the second etching are performed by dry etching in a common process chamber, and a common dry etching process is defined. The common dry etching process may, for example, include performing the first etching with a first set of process gases in the common process chamber, transitioning from the first set of process gases to a second set of process gases in the common process chamber, and performing the second etching with the second set of process gases in the common process chamber.

[0076] like Fig.16As shown in the cross-sectional view 1600 of FIG. 16 , the third etching is performed to the first sacrificial layer 1206 (see, for example, Fig.15 ). The third etch removes the first sacrificial layer 1206. In addition, in some embodiments, the third etch rounds corners of the recessed gate electrode 104 and / or rounds corners of the gate dielectric layer 110. The third etch is performed using an etchant having a high selectivity (e.g., a high etch rate) to the first sacrificial layer 1206 relative to the recessed gate electrode 104, so that the recessed gate electrode 104 is not etched and / or is minimally etched.

[0077] In some embodiments, the third etching is implemented by wet etching. For example, the third etching is implemented by wet etching using an etchant including phosphoric acid (e.g., H3PO4) in at least some embodiments in which the first sacrificial layer 1206 is or includes silicon nitride. As another example, the third etching is implemented by wet etching using an etchant including dilute hydrofluoric acid (DHF) in at least some embodiments in which the first sacrificial layer 1206 is or includes silicon oxide. However, other suitable etchants for the third etching are acceptable. In an alternative embodiment, the second etching process is implemented by dry etching and / or some other suitable etching type. However, compared with wet etching, physical ion bombardment performed by dry etching is more likely to cause damage to the recessed gate electrode 104. Therefore, dry etching is more likely to cause the thickness T of the recessed gate electrode 104 to be greater than 0.04. g As described above, when the recessed gate electrodes 104 are manufactured in batches, such a thickness T g The non-uniformity may cause non-uniform electrical properties of the recessed gate electrode.

[0078] like Fig.17 As shown in the cross-sectional view 1700 of FIG. 1 , the fourth etch is performed into the gate dielectric layer 110. The fourth etch removes a portion of the gate dielectric layer 110 located above the second base dielectric layer 1102. In addition, at the first feature 108a and the second feature 108b, the fourth etch rounds the corners 1702 of the recessed gate electrode 104. The fourth etch is performed using an etchant having a high selectivity (e.g., a high etching rate) to the gate dielectric layer 110 relative to the recessed gate electrode 104, so the recessed gate electrode 104 is not etched and / or is minimally etched.

[0079] In some embodiments, the fourth etching is implemented by wet etching. For example, the fourth etching is implemented by wet etching using an etchant including DHF in at least some embodiments where the gate dielectric layer 110 is or includes silicon oxide. Other suitable etchants for the fourth etching are acceptable. In alternative embodiments, the fourth etching is implemented by dry etching and / or some other suitable etching types. However, compared with wet etching, the ion bombardment performed by dry etching is more likely to cause damage to the recessed gate electrode 104.

[0080] In some embodiments, the gate dielectric layer 110 and the first sacrificial layer 1206 (see, e.g., Fig.15 ) are or include the same material. For example, the gate dielectric layer 110 and the first sacrificial layer 1206 can be or include silicon oxide. In at least some embodiments in which the gate dielectric layer 110 and the first sacrificial layer 1206 are or include the same material, the third etch and the fourth etch are performed together by the same etching action. For example, in at least some embodiments in which the gate dielectric layer 110 and the first sacrificial layer 1206 are or include silicon oxide, the third etch and the fourth etch are performed together by wet etching using DHF. Therefore, in some embodiments, the gate dielectric layer 110 and the first sacrificial layer 1206 are removed simultaneously.

[0081] like Fig.18 As shown in the cross-sectional view 1800 of FIG. 1 , the fifth etch is performed into the second base dielectric layer 1102. The fifth etch removes the second base dielectric layer 1102. In addition, the fifth etch further rounds the corners 1702 of the recessed gate electrode 104 at the first feature 108a and the second feature 108b. The fifth etch is performed using an etchant having a high selectivity (e.g., a high etching rate) to the second base dielectric layer 1102 relative to the recessed gate electrode 104, so the recessed gate electrode 104 is not etched and / or is minimally etched.

[0082] In some embodiments, the fifth etching is implemented by wet etching. For example, the fifth etching is implemented by wet etching using an etchant including phosphoric acid (e.g., H3PO4) in at least some embodiments in which the second base dielectric layer 1102 is or includes silicon nitride. However, other suitable etchants for the fifth etching are acceptable. In alternative embodiments, the fifth etching is implemented by dry etching and / or some other suitable etching type. However, compared with wet etching, ion bombardment performed by dry etching is more likely to cause damage to the recessed gate electrode 104.

[0083] In some embodiments, the first etching and the second etching are performed by dry etching and / or define a multi-step dry etching process, and the third etching, the fourth etching, and the fifth etching are performed by wet etching and / or define a multi-step wet etching process. In some embodiments, the second base dielectric layer 1102 (see, for example, Fig.17 ) and a first sacrificial layer 1206 (see e.g. Fig.15 ) is or includes silicon nitride, and the gate dielectric layer 110 is or includes oxide. In at least some of these embodiments, the third etching and the fifth etching are performed by wet etching using an etchant including phosphoric acid, and the fourth etching is performed by wet etching using an etchant including DHF.

[0084] like Fig.19 As shown in cross-sectional view 1900 of , a hard mask layer 1902 is deposited over the recessed gate electrode 104 and the substrate 106. The hard mask layer 1902 may be or include, for example, silicon nitride, silicon oxide, some other suitable dielectric(s), or any combination thereof.

[0085] like Fig. 20 As shown in the cross-sectional view 2000, the hard mask layer 1902 (see for example Fig.19 ) is patterned to remove the hard mask layer 1902 from the side of the recessed gate electrode 104 and form a hard mask 312 located above the recessed gate electrode 104. The patterning can be implemented, for example, by photolithography / etching or some other suitable patterning process. The photolithography / etching process can, for example, use a photoresist mask 2002 and / or some other suitable mask located above the hard mask layer 1902.

[0086] like Fig.21 As shown in the cross-sectional view 2100 of FIG. 1 , a pair of source / drain regions 112 are formed in the substrate 106. The source / drain regions 112 are respectively formed on opposite sides of the recessed gate electrode 104. The source / drain regions 112 can be formed, for example, by ion implantation into the substrate 106, an epitaxial deposition process, some other suitable process, or any combination of the foregoing. The recessed gate electrode 104, the gate dielectric layer 110, and the source / drain regions 112 partially or completely define the semiconductor device 102. The semiconductor device 102 can be, for example, a FET, some other suitable transistor, a memory cell, or some other suitable semiconductor device.

[0087] Also through Fig.21 The cross-sectional view 2100 shows that the CESL 316 and the first ILD layer 306a are deposited over the hard mask 312 and the substrate 106. The first ILD layer 306a may be or include, for example, silicon oxide and / or some other suitable dielectric(s).

[0088] like Fig. 22 As shown in the cross-sectional view 2200 of FIG. 2 , the second planarization is performed into the first ILD layer 306 a and the CESL 316 to expose the hard mask 312. In addition, the second planarization makes the top surface of the first ILD layer 306 a coplanar with the top surface of the CESL 316 and the top surface of the hard mask 312. The second planarization can be performed, for example, by CMP and / or some other suitable planarization process.

[0089] like Fig.23 As shown in the cross-sectional view 2300 of , the hard mask 312 is patterned to form an opening 2302 exposing the recessed gate electrode 104. The patterning can be implemented, for example, by photolithography / etching or some other suitable patterning process. The photolithography / etching process can, for example, use a photoresist mask 2304 and / or some other suitable mask located above the hard mask 312.

[0090] Also through Fig.23 The cross-sectional view 2300 of FIG. 23 shows that in the opening 2302, the silicide layer 310 is formed on the recessed gate electrode 104. The silicide layer 310 may be formed, for example, by a self-aligned silicide process and / or some other suitable silicide formation process.

[0091] like Fig.24 As shown in the cross-sectional view 2400 of FIG. 24, the second ILD layer 306b is formed to fill the opening 2302 (see, for example, Fig.23 ), and is also located above the first ILD layer 306a and the silicide layer 310. The second ILD layer 306b may, for example, be or include silicon oxide and / or some other suitable (some) dielectrics. The process for forming the second ILD layer 306b may, for example, include depositing the second ILD layer 306b, and then performing planarization into the top surface of the second ILD layer 306b.

[0092] Also through Fig.24 The cross-sectional view 2400 shows that the contact via 308 is formed in the second ILD layer 306b, extending from the source / drain region 112 and the silicide layer 310, respectively. The process for forming the contact via 308 may, for example, include selectively etching the first ILD layer 306a and the second ILD layer 306b to form a contact opening, depositing a conductive material in the contact opening, and planarizing the conductive material. However, other processes are acceptable.

[0093] Since the recessed gate electrode 104 is formed according to the method of the present invention, the thickness T of the recessed gate electrode 104 is gThe uniformity is high, and the recessed gate electrode 104 is less likely to be too thin at the center of the recessed gate electrode 104. If the recessed gate electrode 104 becomes too thin at the center of the recessed gate electrode 104, the formation of the contact via 308 may over-etch through the recessed gate electrode 104 and damage the gate dielectric layer 110. Such damage may degrade the performance of the semiconductor device 102 and / or cause failure of the semiconductor device 102.

[0094] Although various embodiments of the reference method are described Figure 11-Figure 24 , but it should be understood that Figure 11-Figure 24 The structure shown is not limited to this method but can be independent of this method. Figure 11-Figure 24 Although described as a series of actions, it should be understood that in other embodiments, the order of the actions may be changed. Figure 11-Figure 24 What is shown and described is a set of specific actions, but some actions shown and / or described may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments.

[0095] refer to Figure 25-Figure 29 , provides Figure 11-Figure 24 A series of cross-sectional views 2500-2900 of some alternative embodiments of the method of wherein the gate electrode layer has a recessed surface that is recessed relative to a top surface of the gate oxide layer. The cross-sectional views 2500-2900 correspond to Figure 5B The cross-sectional view 500B shows Figure 5B However, the method shown in the cross-sectional views 2500-2900 may also be used to form the IC and the semiconductor device 102. Figure 1 , Figure 3 , Figure 4 ,and Figure 5A-5F An IC and / or semiconductor device 102 in any one of the embodiments.

[0096] like Fig.25 As shown in the cross-sectional view 2500 of FIG. 1 , a recess 1104 is formed in the substrate 106. In addition, the gate dielectric layer 110 and the multilayer thin film 1202 are deposited to line the recess 1104. The recess 1104, the gate dielectric layer 110, and the multilayer thin film 1202 are respectively described with reference to FIG. Fig.11 and Fig.12 12 is formed as shown and described, except that the recessed surface 1204r of the gate electrode layer 1204 is recessed below the top surface of the gate dielectric layer 110 by a distance D2.

[0097] like Fig.26 As shown in the cross-sectional view 2600 of FIG. 1 , the first planarization is performed into the second sacrificial layer 1208, as described with reference to FIG. Fig.13 as described.

[0098] like Fig. 27 As shown in the cross-sectional view 2700, the first etching and the second etching are respectively as described with respect to Fig.14 and Fig.15 The gate electrode 104 is formed by performing the above-described operations to form a recessed gate electrode 104. Since the recessed surface 1204r of the gate electrode layer 1204 is recessed below the top surface of the gate dielectric layer 110, the first feature 108a and the second feature 108b are protrusions that protrude upward and have a flat or substantially flat top surface. In alternative embodiments, the top surface is curved and / or has some other suitable profile.

[0099] like Fig.28 As shown in the cross-sectional view 2800 of FIG. 1 , the third etching, the fourth etching, and the fifth etching are performed to respectively remove: 1) the first sacrificial layer 1206 (see, for example Fig. 27 ); 2) a gate dielectric layer 110 located on the side of the recessed gate electrode 104; and 3) a second base dielectric layer 1102 (see, for example Fig. 27 ). The third etching, the fourth etching, and the fifth etching may be, for example, as respectively related to Figure 16-18 As discussed above, in at least some embodiments where the gate dielectric layer 110 and the first sacrificial layer 1206 are or include the same material, the third etch and the fourth etch are performed together by the same etching action. Therefore, in some embodiments, the gate dielectric layer 110 and the first sacrificial layer 1206 are removed simultaneously.

[0100] like Fig.29 As shown in the cross-sectional view 2900, the first ILD layer 306a and the second ILD layer 306b, the CESL 316, the silicide layer 310, the source / drain region 112, the contact via 308, and the hard mask 312 are as shown in FIG. Figure 19-Figure 24 Formed as described.

[0101] Although various embodiments of the reference method are described Figure 25-Figure 29 , but it should be understood that Figure 25-Figure 29 The structure shown is not limited to this method but can be independent of this method. Figure 25-Figure 29 Although described as a series of actions, it should be understood that in other embodiments, the order of the actions may be changed. Figure 25-Figure 29 What is shown and described is a set of specific actions, but some actions shown and / or described may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments.

[0102] refer to Figure 30-Figure 34 , provides Figure 11-Figure 24A series of cross-sectional views 3000-3400 of some alternative embodiments of the method of wherein the gate electrode layer has a recessed surface that is elevated above the top surface of the gate dielectric layer by a greater amount. The cross-sectional views 3000-3400 correspond to Figure 5A The cross-sectional view 500A shows Figure 5A However, the method shown in the cross-sectional views 3000-3400 may also be used to form the IC and the semiconductor device 102. Figure 1 , Figure 3 , Figure 4 ,and Figure 5A-5F An IC and / or semiconductor device 102 in any one of the embodiments.

[0103] like Fig.30 As shown in the cross-sectional view 3000 of FIG. 1 , a recess 1104 is formed in the substrate 106. In addition, the gate dielectric layer 110 and the multilayer thin film 1202 are deposited to line the recess 1104. The recess 1104, the gate dielectric layer 110, and the multilayer thin film 1202 are respectively described with reference to FIG. Fig.11 and Fig.12 1 and 12 are formed as shown and described, except that the thickness T of the gate electrode layer 1204 is g Greater than Fig.12 The thickness T g .

[0104] like Fig.31 As shown in the cross-sectional view 3100 of FIG. 1 , the first planarization is performed into the second sacrificial layer 1208, as described with reference to FIG. Fig.13 as described.

[0105] like Fig.32 As shown in the cross-sectional view 3200, the first etching and the second etching are respectively as described with respect to Fig.14 and Fig.15 The gate electrode 104 is formed by performing the above-described process. g Greater than Fig.15 The thickness T g , so the first feature 108a and the second feature 108b are Fig.15 More asymmetric.

[0106] like Fig.33 As shown in the cross-sectional view 3300 of FIG. 1 , the third etching, the fourth etching, and the fifth etching are performed to respectively remove: 1) the first sacrificial layer 1206 (see, for example Fig.32 ); 2) a gate dielectric layer 110 located on the side of the recessed gate electrode 104; and 3) a second base dielectric layer 1102 (see, for example Fig.32 ). The third etching, the fourth etching, and the fifth etching may be, for example, as respectively related to Figure 16-18As discussed above, in at least some embodiments where the gate dielectric layer 110 and the first sacrificial layer 1206 are or include the same material, the third etch and the fourth etch are performed together by the same etching action. Therefore, in some embodiments, the gate dielectric layer 110 and the first sacrificial layer 1206 are removed simultaneously.

[0107] like Fig.34 As shown in the cross-sectional view 3400, the first ILD layer 306a and the second ILD layer 306b, the CESL 316, the silicide layer 310, the source / drain region 112, the contact via 308, and the hard mask 312 are as shown in FIG. Figure 19-Figure 24 Formed as described.

[0108] Although various embodiments of the reference method are described Figure 30-Figure 34 , but it should be understood that Figure 30-Figure 34 The structure shown in is not limited to this method, but can be independent of this method. Figure 30-Figure 34 Although described as a series of actions, it should be understood that in other embodiments, the order of the actions may be changed. Figure 30-Figure 34 What is shown and described is a set of specific actions, but some actions shown and / or described may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments.

[0109] refer to Fig.35 , provides Figure 11-Figure 34 Block diagram 3500 of some embodiments of the method.

[0110] At 3502, a recess is formed in a substrate and a base dielectric layer. See e.g. Fig.11 , Fig.25 ,or Fig.30 .

[0111] At 3504, a gate dielectric layer is deposited to line and partially fill the recess. See e.g. Fig.12 , Fig.25 ,or Fig.30 .

[0112] At 3506, a multi-layer film is deposited to fill the remaining recess above the gate dielectric layer and include a gate electrode layer, a first sacrificial layer above the gate electrode layer, and a second sacrificial layer above the first sacrificial layer. See, e.g. Fig.12 , Fig.25 ,or Fig.30 .

[0113] At 3508, planarization is performed into the second sacrificial layer, wherein the planarization stops on the first sacrificial layer and removes the second sacrificial layer at the sides of the recess. See, e.g. Fig.13, Fig.26 ,or Fig.31 .

[0114] At 3510, a first etch is performed into the first sacrificial layer and the second sacrificial layer to remove the first sacrificial layer at the sides of the recess and to remove or thin the second sacrificial layer above the recess, wherein the second sacrificial layer serves as a mask to protect portions of the underlying first sacrificial layer. See, e.g. Fig.14 , Fig. 27 ,or Fig.32 .

[0115] At 3512, a second etch is performed into the gate electrode layer to form a gate electrode in the recess, wherein the second etch stops on the first sacrificial layer and the gate dielectric layer, and wherein the first sacrificial layer is used as a mask to protect portions of the underlying gate electrode layer. See, e.g. Fig.15 , Fig. 27 ,or Fig.32 In some embodiments, the first etching and / or the second etching are performed by dry etching. In some embodiments, the first etching and the second etching are performed by a common dry etching process in a common process chamber.

[0116] At 3514, a series of additional etches are performed to remove the first sacrificial layer located above the gate electrode, the gate dielectric layer at the sides of the gate electrode, and the base dielectric layer. See, e.g. Figure 16-18 , Fig.28 ,or Fig.33 In some embodiments, the series of etches are performed by wet etching.

[0117] At 3516, a hard mask is formed over the gate electrode. See e.g. Fig.19 , Fig. 20 , Fig.29 ,or Fig.34 .

[0118] At 3518, source / drain regions are formed in the substrate and are located on opposite sides of the gate electrode. See, e.g. Fig.21 , Fig.29 ,or Fig.34 .

[0119] At 3520, a silicide layer is formed on the gate electrode and in the opening of the hard mask. See, e.g. Figure 21-23 , Fig.29 ,or Fig.34 .

[0120] At 3522, contact vias are formed on the silicide layer and the source / drain regions, respectively. See, e.g. Fig.24 , Fig.29 ,or Fig.34 .

[0121] Although Fig.35 The block diagram 3500 is shown and described as a series of actions or events, but it should be understood that the order of showing such actions or events should not be interpreted in a restrictive sense. For example, in addition to those actions or events shown and / or described herein, some actions may occur in different orders and / or occur simultaneously with other actions or events. In addition, it may not be necessary to implement one or more aspects or embodiments described herein with all the actions shown, and one or more actions described herein may be performed in one or more separate actions and / or stages.

[0122] refer to Figure 36-Figure 43 , provides Figure 11-Figure 24 A series of cross-sectional views 3600-4300 of some alternative embodiments of the method of wherein the recessed gate electrode is formed as an alternative dummy structure. The cross-sectional views 3600-4300 correspond to Figure 6 600, and thus shows Figure 6 However, the method shown in the cross-sectional view 3600-3600 may also be used to form the IC and semiconductor device 102. Fig. 7A , Figure 7B , Figure 8A-8C , Fig. 9 ,and Fig.10 An IC and / or semiconductor device 102 in any one of the embodiments.

[0123] like Fig.36 As shown in the cross-sectional view 3600 of , a substrate 106 is provided. The substrate 106 is located below a pair of source / drain regions 112, a dummy structure 3602, a CESL 316, and a first ILD layer 306a, and supports a pair of source / drain regions 112, a dummy structure 3602, a CESL 316, and a first ILD layer 306a. The dummy structure 3602 is laterally located between the source / drain regions 112 and is laterally surrounded by the CESL 316 and the first ILD layer 306a. The first ILD layer 306a is located above the source / drain regions 112 and is separated from the source / drain regions 112 by the CESL 316.

[0124] like Fig.37 As shown in the cross-sectional view 3700 of FIG. 3700 , the dummy structure 3602 is removed (see, for example, Fig.36), to expose or otherwise form a recess 1104 having a depth D1. The depth D1 may be, for example, about 500 angstroms-1500 angstroms, about 500 angstroms-1000 angstroms, about 1000 angstroms-1500 angstroms, about 1000 angstroms, or some other suitable value. The removal may be performed, for example, by a photolithography / etching process or some other suitable process. The photolithography / etching process may, for example, employ a photoresist mask 3702 and / or some other suitable mask located above the first ILD layer 306a.

[0125] like Fig.38 As shown in the cross-sectional view 3800 of FIG. 1 , the gate dielectric layer 110 and the multilayer thin film 1202 are deposited to line the recess 1104. The gate dielectric layer 110 and the multilayer thin film 1202 are deposited to line the recess 1104. Fig.12 as shown and described.

[0126] like Fig.39 As shown in the cross-sectional view 3900 of FIG. 1 , the first planarization is performed into the second sacrificial layer 1208, as described with reference to FIG. Fig.13 as described.

[0127] like Fig.40 As shown in the cross-sectional view 4000, the first etching and the second etching are performed to the multilayer film 1202 (see, for example Fig.39 ) to form a recessed gate electrode 104, as described with respect to Fig.14 and Fig.15 as described.

[0128] like Fig.41 As shown in the cross-sectional view 4100 of FIG. 4 , the third etching and the fourth etching are performed to remove: 1) the first sacrificial layer 1206 (see, for example Fig.40 ); and 2) the gate dielectric layer 110 at the side of the recessed gate electrode 104. The third etch and the fourth etch may be, for example, as described with respect to Fig.16 and Fig.17 Implement as described.

[0129] like Fig.42 As shown in the cross-sectional view 4200 of , the silicide layer 310 is formed on the recessed gate electrode 104. The silicide layer 310 may be formed, for example, by a self-aligned silicide process and / or some other suitable silicide formation process.

[0130] like Fig.43 As shown in the cross-sectional view 4300, the second ILD layer 306b and the contact through hole 308 are as shown in FIG. Fig.24 Formed as described.

[0131] Although various embodiments of the reference method are described Figure 36-Figure 43 , but it should be understood that Figure 36-Figure 43The structure shown in is not limited to this method, but can be independent of this method. Figure 36-Figure 43 Although described as a series of actions, it should be understood that in other embodiments, the order of the actions may be changed. Figure 36-Figure 43 What is shown and described is a set of specific actions, but some actions shown and / or described may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments.

[0132] refer to Figure 44-Figure 49 , provides Figure 36-Figure 43 A series of cross-sectional views 4400-4900 of some alternative embodiments of the method of wherein the gate electrode layer has a recessed surface that is recessed relative to a top surface of the gate oxide layer. The cross-sectional views 4400-4900 correspond to Figure 8B The cross-sectional view 800B shows Figure 8B However, the method shown in the cross-sectional views 4400-4900 may also be used to form the IC and the semiconductor device 102. Figure 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8C , Fig. 9 ,and Fig.10 An IC and / or semiconductor device 102 in any one of the embodiments.

[0133] like Fig.44 As shown in the cross-sectional view 4400 of FIG. 4, a recess 1104 is formed. In addition, the gate dielectric layer 110 and the multilayer thin film 1202 are deposited to liner the recess 1104. The recess 1104 may be formed as described in detail with reference to FIG. Fig.36 and Fig.37 The gate dielectric layer 110 and the multilayer thin film 1202 may be formed as described in relation to Fig.11 and Fig.12 The gate electrode layer 1204 is formed as described above, except that the recessed surface 1204r of the gate electrode layer 1204 is recessed below the top surface of the gate dielectric layer 110 by a distance D2.

[0134] like Fig.45 As shown in the cross-sectional view 4500 of FIG. 1 , the first planarization is performed into the second sacrificial layer 1208, as described with reference to FIG. Fig.13 as described.

[0135] like Fig.46 As shown in the cross-sectional view 4600, the first etching and the second etching are respectively as described with respect to Fig.14 and Fig.15The process is performed as described to form a recessed gate electrode 104. Since the recessed surface 1204r of the gate electrode layer 1204 is recessed below the top surface of the gate dielectric layer 110, the first feature 108a and the second feature 108b are raised rather than recessed.

[0136] like Fig.47 As shown in the cross-sectional view 4700 of FIG. 4 , the third etching and the fourth etching are performed to remove: 1) the first sacrificial layer 1206 (see, for example, Fig.46 ); and 2) the gate dielectric layer 110 at the side of the recessed gate electrode 104. The third etch and the fourth etch may be, for example, as described with respect to Fig.16 and Fig.17 Implement as described.

[0137] like Fig.48 As shown in the cross-sectional view 4800 of FIG. 48 , the silicide layer 310 is formed on the recessed gate electrode 104. The silicide layer 310 may be formed, for example, by a self-aligned silicide process and / or some other suitable silicide formation process.

[0138] like Fig.49 As shown in the cross-sectional view 4900, the second ILD layer 306b and the contact through hole 308 are as shown in FIG. Fig.24 Formed as described.

[0139] Although various embodiments of the reference method are described Figure 44-Figure 49 , but it should be understood that Figure 44-Figure 49 The structure shown is not limited to this method but can be independent of this method. Figure 44-Figure 49 Although described as a series of actions, it should be understood that in other embodiments, the order of the actions may be changed. Figure 44-Figure 49 What is shown and described is a set of specific actions, but some actions shown and / or described may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments.

[0140] refer to Fig.50 , provides Figure 36-Figure 49 A block diagram of some embodiments of the method.

[0141] At 5002, a dummy structure located on the substrate is removed to form a recess, wherein the recess is located between the source / drain regions. Fig.36 and Fig.37 or Fig.44 .

[0142] At 5004, a gate dielectric layer is deposited to line and partially fill the recess. See e.g. Fig.38 or Fig.44 .

[0143] At 5006, a multi-layer film is deposited to fill the remaining recess above the gate dielectric layer and include a gate electrode layer, a first sacrificial layer located above the gate electrode layer, and a second sacrificial layer located above the first sacrificial layer. See, e.g. Fig.38 or Fig.44 .

[0144] At 5008, planarization is performed on the multilayer film, where the planarization stops at the first sacrificial layer and the second sacrificial layer at the sides of the recess is removed. See, e.g. Fig.39 or Fig.45 .

[0145] At 5010, a first etch is performed into the first sacrificial layer and the second sacrificial layer to remove the first sacrificial layer at the sides of the recess and to remove or thin the second sacrificial layer above the recess, wherein the second sacrificial layer serves as a mask to protect portions of the underlying first sacrificial layer. See, e.g. Fig.40 or Fig.46 .

[0146] At 5012, a second etch is performed into the gate electrode layer to form a gate electrode in the recess, wherein the second etch stops on the first sacrificial layer and the gate dielectric layer, and wherein the first sacrificial layer is used as a mask to protect portions of the underlying gate electrode layer. See, e.g. Fig.40 or Fig.46 In some embodiments, the first etching and / or the second etching are performed by dry etching. In some embodiments, the first etching and the second etching are performed by a common dry etching process in a common process chamber.

[0147] At 5014, a series of additional etches are performed to remove the first sacrificial layer located above the gate electrode and the gate dielectric layer at the sides of the gate electrode. See, e.g. Fig.41 or Fig.47 In some embodiments, the series of etches are performed by wet etching.

[0148] At 5016, a silicide layer is formed on the gate electrode. See, e.g. Fig.42 or Fig.48 .

[0149] At 5018, contact vias are formed on the silicide layer and the source / drain regions, respectively. Fig.43 or Fig.49 .

[0150] Although Fig.50The block diagram 5000 is shown and described as a series of actions or events, but it should be understood that the order of showing such actions or events should not be interpreted in a restrictive sense. For example, in addition to those actions or events shown and / or described herein, some actions can occur in different orders and / or occur simultaneously with other actions or events. In addition, it may not be necessary to realize one or more aspects or embodiments described herein with all the actions shown, and one or more actions described herein can be performed in one or more separate actions and / or stages.

[0151] In some embodiments, the present invention provides a semiconductor device, comprising: a substrate; a pair of source / drain regions located in the substrate; a gate dielectric layer located on the substrate; and a gate electrode recessed into the top of the gate dielectric layer and laterally located between the source / drain regions, wherein the top surface of the gate electrode has a first edge and a second edge on opposite sides of the gate electrode, respectively, wherein the thickness of the gate electrode is substantially uniform from the first edge to the second edge, and wherein the gate electrode has a pair of features at the first edge and the second edge, respectively. In some embodiments, the feature is an inverted fillet. In some embodiments, the feature is an upward protrusion. In some embodiments, the feature is a concave recess. In some embodiments, the pair of features includes a first feature and a second feature having a first cross-sectional profile and a second cross-sectional profile, respectively, wherein the first cross-sectional profile is a mirror image of the second cross-sectional profile. In some embodiments, the feature is a different region of a common feature extending laterally around the top surface of the gate electrode in a closed path. In some embodiments, the gate electrode is recessed into the top of the substrate and is separated from the substrate by the gate dielectric layer. In some embodiments, the substrate defines an upwardly protruding fin, wherein the gate electrode surrounds the top of the fin.

[0152] In some embodiments, the present invention provides an IC, comprising: a substrate; a pair of source / drain regions located in the substrate; a gate electrode located laterally between the source / drain regions, wherein the top of the gate electrode has a feature extending laterally along the periphery of the gate electrode in a closed path, wherein the feature has a first section and a second section located on opposite sides of the gate electrode, respectively, wherein the top of the gate electrode is substantially flat from the first section to the second section, and wherein the feature is a protrusion or a recess; and a gate dielectric layer surrounding the bottom of the gate electrode from the sidewall of the gate electrode to the bottom surface of the gate electrode. In some embodiments, the feature is a protrusion that protrudes upward. In some embodiments, the feature is an inverted corner that bends downward with a decreasing slope from the top surface of the gate electrode to the sidewall of the gate electrode. In some embodiments, the feature is a recess. In some embodiments, the IC further comprises: an ILD layer located above the substrate and the source / drain regions, wherein the gate electrode is recessed into the top of the ILD layer, wherein the gate dielectric layer separates the gate electrode from the substrate and the sidewall of the ILD layer. In some embodiments, the gate electrode is recessed into the top of the substrate such that a bottom surface of the gate electrode is below a top surface of the substrate.

[0153] In some embodiments, the present invention provides a method for forming a semiconductor device, comprising: forming a recess located above a substrate; depositing a gate dielectric layer, the gate dielectric layer acting as a liner of the recess and partially filling the recess; depositing a multi-layer film, the multi-layer film filling the rest of the recess above the gate dielectric layer, and including a gate electrode layer, a first sacrificial layer located above the gate electrode layer, and a second sacrificial layer located above the first sacrificial layer; performing planarization into the second sacrificial layer, the planarization stops on the first sacrificial layer, and the second sacrificial layer at the side of the recess is removed; performing a first etch into the first sacrificial layer and the second sacrificial layer to remove the first sacrificial layer at the side of the recess; and performing a second etch into the gate electrode layer, the second etch using the first sacrificial layer as a mask to remove the gate electrode layer at the side of the recess, and forming a gate electrode located below the first sacrificial layer in the recess. In some embodiments, the first etch and the second etch are performed by a common dry etching process. In some embodiments, the first etch is a non-selective etch having substantially the same etch rate for the first sacrificial layer and the second sacrificial layer, and wherein the second etch is a selective etch having a high etch rate for the gate electrode layer relative to the first sacrificial layer. In some embodiments, the method further includes: performing a third etching into the first sacrificial layer after the second etching to remove the first sacrificial layer from the top of the gate electrode; and performing a fourth etching to remove the gate dielectric layer at the side of the recess. In some embodiments, the third etching and the fourth etching are performed by a common wet etching process using the same etchant. In some embodiments, the formation of the recess includes performing etching into the substrate to form a recess in the substrate.

[0154] According to an embodiment of the present application, a semiconductor device is provided, comprising: a substrate; a pair of source / drain regions located in the substrate; a gate dielectric layer located on the substrate; and a gate electrode recessed into the top of the gate dielectric layer and laterally located between the source / drain regions, wherein the top surface of the gate electrode has a first edge and a second edge on opposite sides of the gate electrode, respectively, wherein the thickness of the gate electrode is substantially uniform from the first edge to the second edge, and wherein the gate electrode has a pair of features at the first edge and the second edge, respectively. In some embodiments, wherein the feature is an inverted fillet. In some embodiments, wherein the feature is an upward protrusion. In some embodiments, wherein the feature is a concave recess. In some embodiments, wherein a pair of features includes a first feature and a second feature having a first cross-sectional profile and a second cross-sectional profile, respectively, and wherein the first cross-sectional profile is a mirror image of the second cross-sectional profile. In some embodiments, wherein the feature is a different region of a common feature extending laterally around the top surface of the gate electrode in a closed path. In some embodiments, wherein the gate electrode is recessed into the top of the substrate and is separated from the substrate by the gate dielectric layer. In some embodiments, the substrate defines an upwardly protruding fin, and wherein the gate electrode surrounds a top portion of the fin.

[0155] According to another embodiment of the present application, an integrated circuit is provided, comprising: a substrate; a pair of source / drain regions located in the substrate; a gate electrode located laterally between the source / drain regions, wherein the top of the gate electrode has a feature extending laterally along the periphery of the gate electrode in a closed path, wherein the feature has a first section and a second section located on opposite sides of the gate electrode, respectively, wherein the top of the gate electrode is substantially flat from the first section to the second section, and wherein the feature is a protrusion or a recess; and a gate dielectric layer surrounding the bottom of the gate electrode from the sidewall of the gate electrode to the bottom surface of the gate electrode. In some embodiments, wherein the feature is a protrusion protruding upward. In some embodiments, wherein the feature is an inverted corner that bends downward with a decreasing slope from the top surface of the gate electrode to the sidewall of the gate electrode. In some embodiments, wherein the feature is a recess. In some embodiments, the integrated circuit further comprises: an interlayer dielectric (ILD) layer located above the substrate and the source / drain regions, wherein the gate electrode is recessed into a top portion of the interlayer dielectric layer, and wherein the gate dielectric layer separates the gate electrode from the substrate and a sidewall of the interlayer dielectric layer. In some embodiments, the gate electrode is recessed into a top portion of the substrate such that a bottom surface of the gate electrode is below a top surface of the substrate.

[0156] According to another embodiment of the present application, a method for forming a semiconductor device is provided, the method comprising: forming a recess located above a substrate; depositing a gate dielectric layer, the gate dielectric layer acting as a liner of the recess and partially filling the recess; depositing a multi-layer film, the multi-layer film filling the rest of the recess above the gate dielectric layer, and including a gate electrode layer, a first sacrificial layer located above the gate electrode layer, and a second sacrificial layer located above the first sacrificial layer; performing planarization into the second sacrificial layer, the planarization stops on the first sacrificial layer, and the second sacrificial layer at the side of the recess is removed; performing a first etch into the first sacrificial layer and the second sacrificial layer to remove the first sacrificial layer at the side of the recess; and performing a second etch into the gate electrode layer, the second etch using the first sacrificial layer as a mask to remove the gate electrode layer at the side of the recess, and forming a gate electrode located below the first sacrificial layer in the recess. In some embodiments, the first etch and the second etch are performed by a common dry etching process. In some embodiments, the first etch is a non-selective etch having substantially the same etch rate for the first sacrificial layer and the second sacrificial layer, and wherein the second etch is a selective etch having a high etch rate for the gate electrode layer relative to the first sacrificial layer. In some embodiments, the method for forming a semiconductor device further comprises: performing a third etch into the first sacrificial layer after the second etch to remove the first sacrificial layer from the top of the gate electrode; and performing a fourth etch to remove the gate dielectric layer at the side of the recess. In some embodiments, the third etch and the fourth etch are performed by a common wet etching process using the same etchant. In some embodiments, the formation of the recess comprises performing an etch into the substrate to form the recess in the substrate.

[0157] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: substrate; a pair of source / drain regions located in the substrate; A gate dielectric layer, located on the substrate; as well as A gate electrode is recessed into the top of the gate dielectric layer and is laterally located between the source / drain regions, wherein the top surface of the gate electrode has a first edge and a second edge on opposite sides of the gate electrode, respectively, wherein the thickness of the gate electrode is substantially uniform from the first edge to the second edge, and wherein the gate electrode has a pair of features at the first edge and the second edge, respectively, wherein the thickness of the gate electrode at the pair of features is different from the thickness of the gate electrode from the first edge to the second edge, wherein the features are recessed from the top surface of the gate electrode and then protrude from the recess to the outermost sidewall of the gate electrode.

2. The semiconductor device according to claim 1, wherein The feature is an inverted fillet.

3. The semiconductor device according to claim 1, further comprising: A silicide is located on the gate electrode.

4. The semiconductor device according to claim 3, further comprising: A contact via is located above the silicide.

5. The semiconductor device according to claim 1, wherein The pair of features includes a first feature and a second feature having first and second cross-sectional profiles, respectively, and wherein the first cross-sectional profile is a mirror image of the second cross-sectional profile.

6. The semiconductor device according to claim 1, wherein The features are different regions of a common feature that extend laterally around the top surface of the gate electrode in a closed path.

7. The semiconductor device according to claim 1, wherein The gate electrode is recessed into the top of the substrate and is separated from the substrate by the gate dielectric layer.

8. The semiconductor device according to claim 1, wherein The substrate defines an upwardly protruding fin, and wherein the gate electrode surrounds a top portion of the fin.

9. An integrated circuit comprising: substrate; a pair of source / drain regions located in the substrate; a gate electrode laterally located between the source / drain regions, wherein a top portion of the gate electrode has a feature extending laterally along a periphery of the gate electrode in a closed path, wherein the feature has a first segment and a second segment respectively located on opposite sides of the gate electrode, wherein the top portion of the gate electrode is substantially flat from the first segment to the second segment, wherein a thickness of the gate electrode at the feature is different from a thickness of the gate electrode from the first segment to the second segment, and wherein the feature is a protrusion or a depression; and A gate dielectric layer surrounds the bottom of the gate electrode from the sidewall of the gate electrode to the bottom surface of the gate electrode, wherein the feature is an inverted corner that bends downward with a decreasing slope from the top surface of the gate electrode to the sidewall of the gate electrode.

10. A semiconductor device comprising: substrate; a pair of source / drain regions located in the substrate; A gate electrode is laterally located between the source / drain regions, wherein a top portion of the gate electrode has a feature extending laterally along a periphery of the gate electrode in a closed path, and a thickness of the gate electrode at the feature first decreases and then increases.

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