Method for forming semiconductor device structure

Abstract

The embodiment of the invention provides a forming method of a semiconductor device structure. The method includes forming a fin structure over a substrate; forming an insulating material near the fin structure; depositing a gate dielectric layer over the fin structure and the insulating material; depositing a gate electrode layer on the gate dielectric layer; forming an opening through the gate electrode layer and the gate dielectric layer into the insulating material; subsequently performing an etching process that etches the gate dielectric layer at a faster rate than the gate electrode layer; and filling the opening with a dielectric material.

Description

Technical Field

[0001] The present disclosure relates to a method for forming a semiconductor device structure. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generation after generation of ICs, each with smaller and more complex circuits than the previous generation. During the evolution of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometric size (i.e., the smallest component (or circuit) that can be created using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing ICs.

[0003] Therefore, there is a need for improved processing and manufacturing of ICs. Summary of the invention

[0004] According to some embodiments of the present disclosure, a method of forming a semiconductor device structure includes the following steps: forming a fin structure above a substrate; forming an insulating material near the fin structure; depositing a gate dielectric layer above the fin structure and the insulating material; depositing a gate electrode layer on the gate dielectric layer; forming an opening through the gate electrode layer and the gate dielectric layer into the insulating material; then performing an etching process that etches the gate dielectric layer at a faster rate than etching the gate electrode layer; and filling the opening with a dielectric material.

[0005] According to some embodiments of the present disclosure, a method of forming a semiconductor device structure includes the following steps. An insulating material is formed over a substrate. A gate dielectric layer is deposited on the insulating material. A gate electrode layer is deposited on the gate dielectric layer. A cyclic process is performed to form an opening through the gate electrode layer and the gate dielectric layer into the insulating material, wherein the cyclic process includes a plurality of cycles, and each cycle includes: depositing a layer on the gate electrode layer; oxidizing the layer to form an oxide layer; removing a portion of the oxide layer; and performing a main etching process to remove a portion of the gate electrode layer. Subsequently, an additional etching process is performed, wherein the additional etching process etches the gate dielectric layer at a faster rate than etching the gate electrode layer. The opening is filled with a dielectric material.

[0006] According to some embodiments of the present disclosure, a method for forming a semiconductor device structure includes the following steps. An insulating material is formed above a substrate. A gate dielectric layer is deposited on the insulating material. A gate electrode layer is deposited on the gate dielectric layer. A cyclic process is performed to form an opening through the gate electrode layer and the gate dielectric layer into the insulating material, wherein the cyclic process includes a plurality of cycles, and each cycle includes: performing a main etching process to remove a portion of the gate electrode layer, wherein the main etching process includes: introducing a first chlorine-containing etchant at a first flow rate and introducing a second chlorine-containing etchant at a second flow rate, and the ratio of the first flow rate to the second flow rate is in the range of 1:2 to 1:6. Subsequently, an additional etching process is performed, wherein the additional etching process etches the gate dielectric layer at a faster rate than etching the gate electrode layer, wherein the additional etching process includes introducing the first chlorine-containing etchant at a third flow rate and introducing the second chlorine-containing etchant at a fourth flow rate, and the ratio of the third flow rate to the fourth flow rate is in the range of 5:1 to 15:1. Fill the opening with a dielectric material. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In practice, the sizes of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1 to 6 are perspective views of various stages of fabricating a semiconductor device structure according to some embodiments;

[0009] 7A to 11A According to some embodiments, Figure 6 A cross-sectional side view of various stages of manufacturing a semiconductor device structure taken along line AA;

[0010] FIG. 7B to FIG. 11B According to some embodiments, Figure 6 A cross-sectional side view of various stages of manufacturing a semiconductor device structure taken along line BB;

[0011] FIG. 7C to FIG. 11C According to some embodiments, Figure 6 Cross-sectional side views of various stages of manufacturing a semiconductor device structure taken along line CC;

[0012] FIG. 12A to FIG. 12D According to some embodiments, Figure 6 A cross-sectional side view of various stages of manufacturing a semiconductor device structure taken along line BB;

[0013] Fig.13A and Fig. 13Bis a top view of various stages of forming an opening in a gate electrode layer of a semiconductor device structure according to some embodiments;

[0014] FIG. 14A to FIG. 14C are various views of one of the various stages of manufacturing a semiconductor device structure according to some embodiments;

[0015] FIG. 15A to FIG. 15C According to some embodiments FIG. 14A to FIG. 14C A top view of a semiconductor device structure.

[0016]

Explanation of symbols

[0017] 100:Semiconductor device structure

[0018] 101:Substrate

[0019] 104: Semiconductor layer stack

[0020] 106: first semiconductor layer

[0021] 108: Second semiconductor layer

[0022] 112: Fin structure

[0023] 114: Groove

[0024] 116: Well Section

[0025] 118: Insulation material

[0026] 120: Isolation Area

[0027] 130: Sacrificial gate structure

[0028] 132: Sacrificial gate dielectric layer

[0029] 134: Sacrificial gate electrode layer

[0030] 136: Mask layer

[0031] 138: Gate spacer

[0032] 144: Dielectric spacer

[0033] 146: Source / drain region

[0034] 162: Contact etching stop layer

[0035] 164: Interlayer dielectric layer

[0036] 170: Gate dielectric layer

[0037] 172: Gate electrode layer

[0038] 174: Gate structure

[0039] 180: Mask structure

[0040] 181: Opening

[0041] 182: first dielectric layer

[0042] 184: Semiconductor layer

[0043] 186: Second dielectric layer

[0044] 189, 197, 199: midpoint

[0045] 190: Resist structure

[0046] 191: Dielectric Materials

[0047] 192: Bottom

[0048] 193: Conductive characteristics

[0049] 194: Middle layer

[0050] 195: Silicide layer

[0051] 196: Photoresist layer

[0052] 200, 202: Enlarged part

[0053] A1: First Angle

[0054] A2: Second Angle

[0055] A3: The third angle

[0056] A4: The fourth angle

[0057] A5: The fifth angle

[0058] A6: The sixth angle

[0059] A7: The seventh angle

[0060] A8: The eighth angle

[0061] AA, BB, CC: Line

[0062] D1: Dimensions

[0063] D2, D3: Distance

[0064] L1, L2: length DETAILED DESCRIPTION

[0065] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these specific embodiments or examples are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0066] Additionally, for ease of description, spatially relative terms (such as "below," "beneath," "lower," "above," "over," "on," "top," "upper," and the like) may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the accompanying figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0067] Although the embodiments of the present disclosure are discussed with respect to nanostructure channel FETs, such as gate all around (GAA) FETs, for example, horizontal gate all around (HGAA) FETs or vertical gate all around (VGAA) FETs, implementations of some aspects of the present disclosure may be used for other processes and / or other devices, such as planar FETs, Fin-FETs, and other suitable devices. A person of ordinary skill will readily appreciate other modifications that may be made within the scope of the present disclosure. In the case of a gate all around (GAA) transistor structure, the GAA transistor structure may be patterned using any suitable method. For example, the structure may be patterned using one or more photolithography processes including a double patterning or multi-patterning process. Typically, the double patterning or multi-patterning process combines photolithography with a self-alignment process, allowing the creation of a pattern having, for example, a pitch that is smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is subsequently removed and the remaining spacers can then be used to pattern the GAA structure.

[0068] Figures 1 to 15C 1 shows an exemplary process for manufacturing a semiconductor device structure 100 according to an embodiment of the present disclosure. It should be understood that Figures 1 to 15C Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes is not limited and may be interchanged.

[0069] Figures 1 to 6 1 is a perspective view of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 1As shown, the semiconductor device structure 100 includes a stack of semiconductor layers 104 formed above the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include a crystalline semiconductor material, such as but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonate (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb) and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for enhancement. In one embodiment, the insulating layer is an oxygen-containing layer.

[0070] The substrate 101 may include various regions doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for n-type field effect transistors (NFETs) and boron for p-type field effect transistors (PFETs).

[0071] The semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructure channels in multi-gate devices, such as nanostructure channel FETs. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etching selectivities and / or oxidation rates. For example, the first semiconductor layer 106 can be made of Si, and the second semiconductor layer 108 can be made of SiGe. In some examples, the first semiconductor layer 106 can be made of SiGe, and the second semiconductor layer 108 can be made of Si. Alternatively, in some embodiments, any of the semiconductor layers 106, 108 can be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0072] The first semiconductor layer 106 and the second semiconductor layer 108 are formed using any suitable deposition process such as epitaxy. For example, the epitaxial growth of the layers of the semiconductor layer stack 104 may be performed using a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0073] The first semiconductor layer 106 or a portion thereof may form a nanostructure channel of the semiconductor device structure 100 in a later manufacturing stage. The term nanostructure is used herein to refer to any material portion having nanometer-scale or even micrometer-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to both elongated material portions of circular and substantially circular cross-sections and beam-shaped or strip-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. The nanostructure channel of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanostructure transistor. The nanostructure transistor may be referred to as a nanosheet transistor, a nanowire transistor, a gate-all-around (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding a channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0074] Each first semiconductor layer 106 may have a thickness in a range between about 5 nm and about 30 nm. Each second semiconductor layer 108 may have a thickness that is equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness in a range between about 2 nm and about 50 nm. Figure 1 As shown, three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately, which is for the purpose of illustration and is not intended to limit the content beyond the specific enumeration in the claims. It can be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels of the semiconductor device structure 100.

[0075] exist Figure 2, fin structures 112 are formed by a semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a well portion 116 formed by a substrate 101. The fin structure 112 may be formed by patterning a hard mask layer (not shown) formed on the semiconductor layer stack 104 using a multi-patterning operation including photolithography and etching processes. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process may include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure bake process, and developing the photoresist layer to form a mask component including the photoresist layer. In some embodiments, patterning the photoresist layer to form the mask component may be performed using an electron beam (e-beam) lithography process. The etching process forms trenches 114 through the hard mask layer, through the semiconductor layer stack 104, and into the substrate 101 in the unprotected areas, leaving a plurality of extended fin structures 112. The trenches 114 extend along the X direction. The trenches 114 may be etched using dry etching (e.g., RIE), wet etching, and / or a combination thereof.

[0076] exist Figure 3 In the embodiment, after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trench 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Subsequently, a planarization operation, such as a chemical mechanical polishing (CMP) method and / or an etch-back method, is performed to expose the top of the fin structure 112. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-K dielectric material, or any suitable dielectric material. The insulating material 118 can be formed using any suitable method such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), or flowable CVD (FCVD).

[0077] exist Figure 4In the embodiment of the present invention, the insulating material 118 is recessed to form the isolation region 120. The recess of the insulating material 118 exposes a portion of the fin structure 112, such as the semiconductor layer stack 104. The recess of the insulating material 118 exposes the trench 114 between adjacent fin structures 112. The isolation region 120 can be formed using a suitable process such as a dry etching process, a wet etching process, or a combination thereof. The top surface of the insulating material 118 can be flush with or below the surface of the second semiconductor layer 108 that contacts the well portion 116 formed by the substrate 101.

[0078] exist Figure 5 , one or more sacrificial gate structures 130 (only one of which is shown) are formed above the semiconductor device structure 100. The sacrificial gate structure 130 is formed above a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 may be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 and then patterning the layers into the sacrificial gate structure 130. Subsequently, a gate spacer 138 is formed on the sidewalls of the sacrificial gate structure 130. For example, the gate spacer 138 may be formed by conformally depositing one or more layers of the gate spacer 138 and anisotropically etching the one or more layers. In some embodiments, the gate spacer 138 is also formed on the sidewalls of the exposed portion of the fin structure 112. Although one sacrificial gate structure 130 is shown, in some embodiments, two or more sacrificial gate structures 130 may be configured along the X direction.

[0079] The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as silicon oxide-based materials. The sacrificial gate electrode layer 134 may include silicon, such as polysilicon or amorphous silicon. The mask layer 136 may include more than one layer, such as an oxide layer and a nitride layer. The gate spacer 138 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof.

[0080] The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as a channel region of the semiconductor device structure 100 .

[0081] exist Figure 6In the embodiment of the present invention, the portion of the fin structure 112 not covered by the sacrificial gate structure 130 and the gate spacer 138 is recessed to a level above, at, or below the top surface of the isolation region 120. The recessing of the portion of the fin structure 112 can be accomplished using an etching process that is an isotropic or anisotropic etching process, and the etching process can be selective with respect to one or more crystal planes of the substrate 101. The etching process can be a dry etch, such as RIE, NBE, or the like, or a wet etch, such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant.

[0082] Fig. 7A , Figure 7B and Figure 7C Along the Figure 6 1 is a cross-sectional side view of the semiconductor device structure 100 taken along lines AA, BB, and CC.

[0083] Fig. 8A , Figure 8B and Figure 8C According to some embodiments, respectively Figure 6 FIG. 1 is a cross-sectional side view of one of the various stages of manufacturing the semiconductor device structure 100, taken along lines AA, BB, and CC. Fig. 8A As shown, edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are horizontally removed along the X direction. The removal of the edge portions of the second semiconductor layer 108 forms a cavity. In some embodiments, portions of the second semiconductor layer 108 are removed using a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant, such as but not limited to ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediaminepyrocatechol (EDP) or potassium hydroxide (KOH) solution.

[0084] After removing the edge portion of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form a dielectric spacer 144. The dielectric spacer 144 can be made of a low-K dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The dielectric spacer 144 can be formed by first forming a conformal dielectric layer using a conformal deposition process such as ALD, and then performing anisotropic etching to remove portions of the conformal dielectric layer except the dielectric spacer 144. During the anisotropic etching process, the dielectric spacer 144 is protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 covers between the dielectric spacers 144 along the X direction.

[0085] Fig.9A , Fig. 9B and Fig. 9C According to some embodiments, respectively Figure 6 FIG. 1 is a cross-sectional side view of one of the various stages of manufacturing the semiconductor device structure 100, taken along lines AA, BB, and CC. Fig. 9A and Fig. 9C As shown, source / drain (S / D) regions 146 are formed by well portion 116. S / D regions 146 may be grown vertically and horizontally to form facets that may correspond to crystal planes of the material used for well portion 116. In the present disclosure, source region and drain region may be used interchangeably and their structures are substantially the same. In addition, source / drain region may refer to a source or drain individually or collectively depending on the context. S / D region 146 may be made of one or more layers of Si, SiP, SiC, and SiCP for n-channel FETs or Si, SiGe, Ge for p-channel FETs. For p-channel FETs, p-type dopants such as boron (B) may also be included in S / D region 146. S / D region 146 may be formed using epitaxial growth methods using CVD, ALD, or MBE.

[0086] Fig. 10A , Fig. 10B and Fig. 10C According to some embodiments, respectively Figure 6 A cross-sectional side view of one of the various stages of manufacturing the semiconductor device structure 100 taken along lines AA, BB, and CC. Fig. 10A , Fig. 10B and Fig. 10CIn the embodiment of the present invention, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the sidewalls of the sacrificial gate structure 130, the insulating material 118, and the S / D regions 146. The CESL 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, or the like or a combination thereof, and may be formed using CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162 over the semiconductor device structure 100. The material for the ILD layer 164 may include a compound including Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials such as polymers may also be used for the ILD layer 164. The ILD layer 164 may be deposited using a PECVD process or other suitable deposition techniques. In some embodiments, after forming the ILD layer 164 , the semiconductor device structure 100 may be subjected to a thermal process to anneal the ILD layer 164 .

[0087] like Fig. 10A and Fig. 10B As shown, after forming the ILD layer 164 , a planarization operation, such as CMP, is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed.

[0088] Fig.11A , Fig. 11B and Fig. 11C According to some embodiments, respectively Figure 6 FIG. 1 is a cross-sectional side view of one of the various stages of manufacturing the semiconductor device structure 100, taken along lines AA, BB, and CC. Fig.11A and Fig. 11B As shown, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. The removal of the sacrificial gate structure 130 and the semiconductor layer 108 forms openings between the gate spacers 138 and between the first semiconductor layer 106. The ILD layer 164 protects the S / D region 146 during the removal process. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 can be first removed using any suitable process such as dry etching, wet etching, or a combination thereof, followed by the removal of the sacrificial gate dielectric layer 132, which can also be performed using any suitable process such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer 134 without removing the gate spacers 138, the ILD layer 164, and the CESL 162.

[0089] A selective wet etching process may be used to remove portions of the second semiconductor layer 108. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemistry used in the selective wet etching process removes the SiGe while substantially not affecting the Si, the dielectric material of the gate spacer 138, and the dielectric spacer 144. In one embodiment, the second semiconductor layer 108 may be removed using a wet etchant such as, but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4), a dry etchant such as a fluorine-based (e.g., F2) or chlorine-based gas (e.g., Cl2), or any suitable isotropic etchant.

[0090] After forming the nanostructure channel (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed to surround the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as a gate structure 174. In some embodiments, an interfacial layer (IL) (not shown) is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. In some embodiments, the gate dielectric layer 170 includes one or more layers of a dielectric material such as silicon oxide, silicon nitride or a high-K dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-K dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-K dielectric materials, and / or combinations thereof. The gate dielectric layer 170 may be formed using CVD, ALD, or any suitable deposition technique. The gate electrode layer 172 may include one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or any combination thereof. The gate electrode layer 172 may be formed using CVD, ALD, electroplating, or other suitable deposition techniques. The gate electrode layer 172 may also be deposited over the upper surface of the ILD layer 164. The gate dielectric layer 170 and the gate electrode layer 172 formed over the ILD layer 164 are then removed by using, for example, CMP until the top surface of the ILD layer 164 is exposed.

[0091] FIG. 12A to FIG. 12D According to some embodiments, Figure 6 The cross-sectional side views of various stages of manufacturing the semiconductor device structure 100 are taken along line BB. Fig. 12A As shown, a mask structure 180 is formed on the gate electrode layer 172 and the ILD layer 164, and a resist structure 190 is formed on the mask structure 180. In some embodiments, the mask structure 180 includes a first dielectric layer 182, a semiconductor layer 184 deposited on the first dielectric layer, and a second dielectric layer 186 deposited on the semiconductor layer 184. The first dielectric layer 182 and the second dielectric layer 186 may include any suitable dielectric material. In some embodiments, the first dielectric layer 182 and the second dielectric layer 186 are SiN layers. The semiconductor layer 184 may be any suitable semiconductor layer. In some embodiments, the semiconductor layer 184 is an amorphous silicon layer. In some embodiments, the resist structure 190 is a three-layer photoresist. For example, the resist structure 190 may include a bottom layer 192 deposited on the mask structure 180, an intermediate layer 194 deposited on the bottom layer 192, and a photoresist layer 196 deposited on the intermediate layer 194. The bottom layer 192 and the intermediate layer 194 are made of different materials, so that the optical properties and / or etching properties of the bottom layer 192 and the intermediate layer 194 are different from each other. In some embodiments, the bottom layer 192 can be a carbon layer, and the intermediate layer 194 can be a silicon-rich layer designed to provide etching selectivity between the intermediate layer 194 and the bottom layer 192. The photoresist layer 196 can be a chemically amplified photoresist layer, and can be a positive photoresist or a negative photoresist. The photoresist layer 196 can include a polymer, such as a phenolic resin, a poly (norbornene) -co-maleic anhydride (COMA) polymer, a poly (4-hydroxystyrene) (PHS) polymer, a phenolic (phenolic plastic) polymer, a polyethylene (PE) polymer, a polypropylene (PP) polymer, a polycarbonate polymer, a polyester polymer or an acrylate-based polymer, such as a poly (methyl methacrylate) (PMMA) polymer or a poly (methacrylic acid) (PMAA). The photoresist layer 196 can be formed by spin coating. The photoresist layer 196 can be patterned to form an opening 181 therein.

[0092] like Fig. 12B As shown, the opening 181 extends into the middle layer 194, the bottom layer 192, and the mask structure 180. The opening 181 can be extended into the middle layer 194, the bottom layer 192, and the mask structure 180 using one or more etching processes. In some embodiments, the resist structure 190 is removed during the one or more etching processes to extend the opening 181 into the mask structure 180. In some embodiments, after the opening 181 extends into the mask structure 180, the resist structure 190 is removed. A portion of the gate electrode layer 172 is exposed in the opening 181.

[0093] like Fig. 12C and Fig.12DAs shown, the exposed portion of the gate electrode layer 172 is removed. The exposed portion of the gate electrode layer 172 can be removed using any suitable method. In some embodiments, a cyclic process is performed to remove the exposed portion of the gate electrode layer 172. The cyclic process includes a plurality of cycles, and each cycle includes depositing a layer on the exposed portion of the gate electrode layer 172, oxidizing the layer to form an oxide layer, removing a portion of the oxide layer, and removing a portion of the exposed portion of the gate electrode layer 172. In some embodiments, the layer can be a silicon-containing layer and can be formed using any suitable process such as CVD or PECVD. A silicon-containing precursor such as SiCl4 can be introduced into a processing chamber in which the semiconductor device structure 100 is disposed, and a silicon-containing layer is formed on the exposed surface of the semiconductor device structure 100. In some embodiments, the silicon-containing layer is formed on the sidewalls of the second dielectric layer 186, the first dielectric layer 182 in the opening 181, the semiconductor layer 184, and the second dielectric layer 186, and the exposed surface of the gate electrode layer 172. Next, an oxidation process is performed to oxidize the silicon-containing layer to form an oxide layer, such as a silicon oxide layer. The oxidation process may be any suitable oxidation process, such as a thermal oxidation process. Next, a breakthrough etching process is performed to remove portions of the oxide layer formed on the horizontal surface of the semiconductor device structure 100, such as portions of the oxide layer formed on the exposed surfaces of the second dielectric layer 186 and the gate electrode layer 172. The breakthrough etching process may be an anisotropic dry etching process, such as a plasma etching process. In some embodiments, a fluorine-containing etchant such as C4F6 may be used for the anisotropic dry etching process. After the breakthrough etching process, a portion of the gate electrode layer 172 located at the bottom of the opening 181 is exposed, and a main etching process is performed to remove a portion of the gate electrode layer 172. In some embodiments, the main etching process is a dry etching process, such as an anisotropic plasma etching process. One or more etchants may be used in the main etching process. In some embodiments, one or more chlorine-containing etchants, such as boron trichloride (BCl3) and / or chlorine (Cl2), may be used. For example, BCl3 and Cl2 are simultaneously introduced into a processing chamber in which the semiconductor device structure 100 is disposed. BCl3 etches dielectrics at a much faster rate than metals, while Cl2 etches metals at a much faster rate than dielectrics. In some embodiments, BCl3 is introduced into the processing chamber at a first flow rate, Cl2 is introduced into the processing chamber at a second flow rate, and the first flow rate is significantly less than the second flow rate. The ratio of the first flow rate to the second flow rate can range from about 1:2 to about 1:6. Therefore, the gate electrode layer 172 is etched at a much faster rate than the gate dielectric layer 170. The oxide layer formed on the sidewalls in the opening 181 can also be removed using one or more chlorine-containing etchants. In some embodiments, a deposition gas, such as a silicon-containing gas, for example SiCl4, can be introduced into the processing chamber together with the etchant.As the opening 181 extends into the gate electrode layer 172, the deposition gas may form a layer on the sidewalls of the gate electrode layer 172 in the opening 181. The layer protects the sidewalls of the gate electrode layer 172 during the main etching process to protect the sidewalls of the gate electrode layer 172. In other words, the oxide layer formed on the sidewalls in the opening 181 may be removed using an etchant of the main etching process, while the deposition gas of the main etching process forms a layer on the sidewalls in the opening 181, which layer may be a silicon layer. In some embodiments, the duration of the main etching process may be quite short, such as about 10 seconds to about 20 seconds, and removes a small portion of the gate electrode layer 172, such as. Fig. 12C shown.

[0094] like Fig.12D As shown, the cycle of depositing a layer on the exposed portion of the gate electrode layer 172, oxidizing the layer to form an oxide layer, removing a portion of the oxide layer, and removing a portion of the exposed portion of the gate electrode layer 172 is repeated multiple times so that the opening 181 extends through the gate electrode layer 172 and into the insulating material 118. Fig. 12C As shown, after the opening 181 first extends into the gate electrode layer 172, a cyclic process of depositing a layer on the exposed portion of the gate electrode layer 172, oxidizing the layer to form an oxide layer, and removing a portion of the oxide layer forms an oxide layer on the sidewalls of the gate electrode layer 172 in the opening 181 to protect the sidewalls of the gate electrode layer 172. In some embodiments, the number of cycles ranges from about 8 to about 15 (such as 12). In some embodiments, one or more wet cleaning processes may be performed between multiple cycles to remove byproducts formed by the etching process. For example, in some embodiments, a wet cleaning process is performed after seven cycles. The wet cleaning process does not substantially affect the materials of the semiconductor device structure 100, such as the gate electrode layer 172 and the gate dielectric layer 170.

[0095] Fig.13A and Fig. 13B FIG. 1 is a top view of various stages of forming an opening 181 in a gate electrode layer 172 of a semiconductor device structure 100 according to some embodiments. Fig.13A and Fig. 13B Various elements of the semiconductor device structure 100, such as the CESL 162, the ILD layer 164, and the gate spacer 138, are omitted. Fig.13A As shown, the opening 181 may extend through one or more gate electrode layers 172, such as two gate electrode layers 172. The opening 181 may also be formed in the ILD layer 164 between adjacent gate electrode layers 172. Fig.13AAs shown, after performing a cyclic process to extend the opening 181 through the gate electrode layer 172 and into the insulating material 118, the opening 181 may extend under the mask structure 180 (shown in dotted lines for better illustration). In other words, lateral undercutting of the gate electrode layer 172 under the mask structure 180 may occur. One of the reasons for the lateral undercut is that the etching rate of the gate electrode layer 172 is significantly faster than the etching rate of the gate dielectric layer 170. In addition, the portion of the gate electrode layer 172 in contact with the gate dielectric layer 170 is also etched at a slower rate than the portion of the gate electrode layer 172 away from the gate dielectric layer 170. In some embodiments, the gate electrode layer 172 includes a central portion having a length L1 and an edge portion having a length L2, and the length L2 is substantially greater than the length L1. Since the length L2 is closely related to the subsequently formed conductive feature 193 ( Fig.15A ) adjacent to each other, the effective capacitance (Ceff) may increase. As Ceff increases, the speed of devices such as ring oscillators may decrease, and the efficiency of AC devices may decrease.

[0096] In some embodiments, to reduce the length L2 without significantly affecting the length L1, an additional etching process may be performed after the cyclic process that extends the opening 181 into the insulating material 118. The additional etching process may utilize one or more etchants that etch dielectrics at a much faster rate than metals. Thus, the additional etching process etches the gate dielectric layer 170 at a much faster rate than the gate electrode layer 172. In addition, portions of the gate electrode layer 172 that are in contact with the gate dielectric layer 170 may be etched at a faster rate than portions of the gate electrode layer 172 that are away from the gate dielectric layer 170. Fig. 13B FIG. 1 shows the opening 181 after the additional etching process. Fig. 13B As shown, the difference between the length L1 and the length L2 is substantially reduced. In some embodiments, the length L1 and the length L2 are substantially the same. As the length L2 of the edge portion of the gate electrode layer 172 decreases, Ceff decreases.

[0097] In some embodiments, the ILD layer 164 ( Fig.11A ) may occur due to the additional etching process, because the additional etching process removes the dielectric at a faster rate. Fig.13A and Fig. 13B As shown, after the cyclic process and before the additional etching process, the size D1 of the opening 181 in the ILD layer 164 along the Y direction may be substantially constant, and the size D1 changes after the additional etching process. Fig. 13BAs shown, after the additional etching process, the portion of the opening 181 in the ILD layer 164 located between adjacent gate electrode layers 172 may have a dimension D1 that increases from the gate electrode layer 172 to the midpoint between the adjacent gate electrode layers 172. In other words, the dimension D1 increases in a direction away from the first gate electrode layer 172, and at about the midpoint between the first gate electrode layer 172 and the second gate electrode layer 172 adjacent to the first gate electrode layer 172, the dimension D1 decreases in a direction toward the second gate electrode layer 172. In some embodiments, as Fig. 13B As shown, dimension D1 has a maximum value at approximately the midpoint between the first gate electrode 172 and the second gate electrode 172 .

[0098] In some embodiments, the additional etching process is an isotropic plasma etching process using one or more chlorine-containing etchants. For example, BCl3 and Cl2 are simultaneously introduced into a processing chamber in which the semiconductor device structure 100 is disposed. As described above, BCl3 etches dielectrics at a much faster rate than metals, and Cl2 etches metals at a much faster rate than dielectrics. In some embodiments, BCl3 is introduced into the processing chamber at a first flow rate, and Cl2 is introduced into the processing chamber at a second flow rate, and the first flow rate is substantially greater than the second flow rate. The ratio of the first flow rate to the second flow rate can be between about 5:1 and about 15:1, such as about 8:1 to about 12:1, for example 10:1. In some embodiments, the first flow rate is between about 250 standard cubic centimeters per minute (standard cubic centimeter per minute, sccm) and about 350sccm, such as about 300sccm, and the second flow rate is between about 25sccm and about 35sccm, such as about 30sccm. In some embodiments, the duration of the additional etching process may be substantially longer than the duration of one cycle of the cyclic process because the etchant that etches the metal at a faster rate has a substantially slower flow rate. For example, the duration of the additional etching process may be about twice the duration of one cycle of the cyclic process. In addition, during the isotropic plasma etching process, no deposition gas is introduced into the processing chamber together with the etchant. In some embodiments, the chamber pressure of the isotropic plasma etching process is less than about 100 mTorr, such as about 50 mTorr to about 90 mTorr. The isotropic plasma etching process may utilize a transformer coupled plasma (TCP) with a plasma power in the range of about 1000W to about 1500W (such as about 1200W). The transformer coupled capacitance tuning (TCCT) ratio may be about 1.5. A bias voltage of about 50V to about 150V at about 13MHz, such as about 100V, may be applied. The plasma power may be pulsed with a duty cycle ranging from about 20% to about 80% and a duty cycle frequency of about 50 Hz to about 100 Hz, such as about 100 Hz. The duration of the additional etching process may range from about 20 seconds to about 40 seconds, such as about 30 seconds.

[0099] In some embodiments, the additional etching process is a wet etching process due to its generally isotropic nature. In some embodiments, the wet etching process utilizes a fluorine-containing etchant, such as an HF solution. In some embodiments, the additional etching process is performed after the cyclic process of extending the opening 181 through the gate electrode layer 172 is completed. If the additional etching process is performed between cycles of the cyclic process or before the cyclic process, the undercut of the gate electrode layer 172 and the ILD layer 164 under the photomask structure 180 may be degraded due to the subsequently performed cycles of the cyclic process.

[0100] After the additional etching process, an optional trimming process may be performed to trim the mask structure 180 so that the opening 181 in the mask structure 180 is widened. In some embodiments, a plasma etching process is performed to trim the mask structure 180. The plasma etching process may utilize a fluorine-containing etchant, such as C4F6. After the optional trimming process, a wet cleaning process may be performed to remove any byproducts of the etching process.

[0101] FIG. 14A to FIG. 14C 1 is a diagram showing various views of one of various stages in fabricating a semiconductor device structure 100 according to some embodiments. FIG. 14A to FIG. 14C As shown, a dielectric material 191 is formed in the opening 181, the mask structure 180 is removed, and a conductive feature 193 is formed in the ILD layer 164. A silicide layer 195 may be formed between the S / D region 146 and the conductive feature 193. The dielectric material 191 may include any suitable dielectric material, such as SiN. The conductive feature 193 may include any suitable conductive material, such as a metal. The silicide layer 195 may be a metal silicide layer, which is the result of a reaction between the metal of the conductive feature 193 and the semiconductor material of the S / D region 146.

[0102] FIG. 15A to FIG. 15C According to some embodiments FIG. 14A to FIG. 14C FIG. 1 is a top view of a semiconductor device structure 100. Fig.15A As shown, dielectric material 191 is formed in opening 181 ( Fig.13A ), and the dielectric material 191 may have the shape of the opening 181. In some embodiments, the distance D2 between adjacent gate electrode layers 172 may be in the range of about 72 nm to about 82 nm. The distance D3 between the gate electrode layer 172 and the midpoint 199 between adjacent gate electrode layers 172 may be in the range of about 36 nm to about 41 nm. Fig. 15B illustrate Fig.15A The enlarged part is 200, and Fig. 15C illustrate Fig.15A The enlarged portion 202. Fig. 15BAs shown, the dielectric material 191 includes: a first angle A1 formed between a first surface of the dielectric material 191 extending from a midpoint 189 of the gate electrode layer 172 to a first sidewall of the gate electrode layer 172 and a longitudinal axis of the gate electrode layer 172; a second angle A2 formed between a second surface of the dielectric material 191 extending from a midpoint 189 of the gate electrode layer 172 to a second sidewall of the gate electrode layer 172 opposite to the first sidewall and the longitudinal axis of the gate electrode layer 172; a third angle A3 formed between a third surface of the dielectric material 191 opposite to the first surface; and a fourth angle A4 formed between a fourth surface of the dielectric material 191 opposite to the second surface. In some embodiments, due to additional etching processes, the angles A1, A2, A3, and A4 are substantially greater than about 70 degrees, such as greater than about 75 degrees. In some embodiments, the angles A1, A2, A3, and A4 range from about 74 degrees to about 80 degrees.

[0103] like Fig. 15C As shown, dielectric material 191 includes: a fifth angle A5 formed between a fifth surface of dielectric material 191 extending from midpoint 197 of conductive feature 193 to a first sidewall of conductive feature 193 and a longitudinal axis of conductive feature 193; a sixth angle A6 formed between a sixth surface of dielectric material 191 extending from midpoint 197 of conductive feature 193 to a second sidewall of conductive feature 193 opposite to the first sidewall and the longitudinal axis of conductive feature 193; a seventh angle A7 formed between a seventh surface of dielectric material 191 opposite to the fifth surface; and an eighth angle A8 formed between an eighth surface of dielectric material 191 opposite to the sixth surface. In some embodiments, angles A5, A6, A7, and A8 are substantially less than about 90 degrees, such as about 78 degrees to about 81 degrees, due to additional etching processes.

[0104] Embodiments of the present disclosure provide a method of forming a semiconductor device structure 100. The method includes forming an opening through a gate electrode layer 172 using a cyclic process and performing an additional etching process to remove an edge portion of the gate electrode layer 172. Some embodiments may achieve advantages. For example, as the reduced length L2 of the edge portion of the gate electrode layer 172 is adjacent to the conductive feature 193, Ceff is reduced.

[0105] An embodiment is a method. The method includes: forming a fin structure over a substrate; forming an insulating material near the fin structure; depositing a gate dielectric layer over the fin structure and the insulating material; depositing a gate electrode layer over the gate dielectric layer; forming an opening through the gate electrode layer and the gate dielectric layer into the insulating material; then performing an etching process that etches the gate dielectric layer at a faster rate than the gate electrode layer; and filling the opening with a dielectric material.

[0106] In one or more embodiments, the fin structure includes a plurality of semiconductor layers, and a gate dielectric layer and a gate electrode layer surround a portion of each semiconductor layer of these semiconductor layers. In one or more embodiments, the etching process is a plasma etching process. In one or more embodiments, a first chlorine-containing etchant and a second chlorine-containing etchant are used in the plasma etching process. In one or more embodiments, the first chlorine-containing etchant etches the gate dielectric layer at a faster rate than etching the gate electrode layer, and the second chlorine-containing etchant etches the gate dielectric layer at a slower rate than etching the gate electrode layer. In one or more embodiments, the first chlorine-containing etchant is introduced at a first flow rate, and the second chlorine-containing etchant is introduced at a second flow rate significantly lower than the first flow rate. In one or more embodiments, the first chlorine-containing etchant includes BCl3, and the second chlorine-containing etchant includes Cl2. In one or more embodiments, the etching process is a wet etching process.

[0107] Another embodiment is a method. The method includes: forming an insulating material over a substrate; depositing a gate dielectric layer on the insulating material; depositing a gate electrode layer on the gate dielectric layer; and performing a cyclic process to form an opening through the gate electrode layer and the gate dielectric layer into the insulating material. The cyclic process includes a plurality of cycles, and each cycle includes: depositing a layer on the gate electrode layer; oxidizing the layer to form an oxide layer; removing a portion of the oxide layer; and performing a main etching process to remove a portion of the gate electrode layer. The method further includes: after the cyclic process, performing an additional etching process that etches the gate dielectric layer at a faster rate than the gate electrode layer; and filling the opening with a dielectric material.

[0108] In one or more embodiments, the layer is a silicon-containing layer, and the oxide layer is a silicon oxide layer. In one or more embodiments, the portion of the oxide layer is formed on a horizontal surface. In one or more embodiments, the main etching process includes simultaneously introducing a first chlorine-containing etchant and a second chlorine-containing etchant. In one or more embodiments, the first chlorine-containing etchant includes BCl3, and the second chlorine-containing etchant includes Cl2. In one or more embodiments, the first chlorine-containing etchant is introduced at a first flow rate, and the second chlorine-containing etchant is introduced at a second flow rate significantly higher than the first flow rate. In one or more embodiments, the ratio of the first flow rate to the second flow rate is between about 1:2 and about 1:6. In one or more embodiments, the additional etching process includes simultaneously introducing a first chlorine-containing etchant and a second chlorine-containing etchant, wherein the first chlorine-containing etchant is introduced at a third flow rate, and the second chlorine-containing etchant is introduced at a fourth flow rate significantly lower than the third flow rate. In one or more embodiments, the ratio of the third flow rate to the fourth flow rate is between about 5:1 and about 15:1.

[0109] Yet another embodiment is a method. The method includes: forming an insulating material over a substrate; depositing a gate dielectric layer on the insulating material; depositing a gate electrode layer on the gate dielectric layer; and performing a cyclic process to form an opening through the gate electrode layer and the gate dielectric layer into the insulating material. The cyclic process includes a plurality of cycles, and each cycle includes performing a main etching process to remove a portion of the gate electrode layer. The main etching process includes: introducing a first chlorine-containing etchant at a first flow rate and introducing a second chlorine-containing etchant at a second flow rate, and the ratio of the first flow rate to the second flow rate is in the range of about 1:2 to about 1:6. Subsequently, the method further includes: performing an additional etching process, which etches the gate dielectric layer at a faster rate than the gate electrode layer. The additional etching process includes: introducing the first chlorine-containing etchant at a third flow rate and introducing the second chlorine-containing etchant at a fourth flow rate, and the ratio of the third flow rate to the fourth flow rate is in the range of about 5:1 to about 15:1. The method further includes filling the opening with a dielectric material.

[0110] In one or more embodiments, each cycle of the cyclic process has a first duration, and the additional etching process has a second duration substantially longer than the first duration. In one or more embodiments, the second duration is approximately twice as long as the first duration.

[0111] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that those skilled in the art can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device structure, characterized in that: include: forming a fin structure above a substrate; forming an insulating material near the fin structure; depositing a gate dielectric layer over the fin structure and the insulating material; depositing a gate electrode layer on the gate dielectric layer; forming an opening through the gate electrode layer and the gate dielectric layer into the insulating material; Then performing an etching process, wherein the etching process etches the gate dielectric layer at a faster rate than etching the gate electrode layer; as well as The opening is filled with a dielectric material.

2. A method for forming a semiconductor device structure, characterized in that: include: forming an insulating material on a substrate; depositing a gate dielectric layer on the insulating material; depositing a gate electrode layer on the gate dielectric layer; Performing a cyclic process to form an opening through the gate electrode layer and the gate dielectric layer into the insulating material, wherein the cyclic process includes a plurality of cycles, and each cycle includes: depositing a layer on the gate electrode layer; oxidizing the layer to form an oxide layer; removing a portion of the oxide layer; and Performing a main etching process to remove a portion of the gate electrode layer; then performing an additional etching process that etches the gate dielectric layer at a faster rate than etching the gate electrode layer; and The opening is filled with a dielectric material.

3. The method for forming a semiconductor device structure according to claim 2, wherein: The main etching process includes simultaneously introducing a first chlorine-containing etchant and a second chlorine-containing etchant.

4. The method for forming a semiconductor device structure according to claim 3, wherein: The first chlorine-containing etchant is introduced at a first flow rate, and the second chlorine-containing etchant is introduced at a second flow rate significantly higher than the first flow rate.

5. The method for forming a semiconductor device structure according to claim 4, wherein: The ratio of the first flow rate to the second flow rate is in the range of 1:2 to 1:

6.

6. The method for forming a semiconductor device structure according to claim 5, wherein: The additional etching process includes simultaneously introducing the first chlorine-containing etchant and the second chlorine-containing etchant, wherein the first chlorine-containing etchant is introduced at a third flow rate, and the second chlorine-containing etchant is introduced at a fourth flow rate significantly lower than the third flow rate.

7. The method for forming a semiconductor device structure according to claim 6, wherein: The ratio of the third flow rate to the fourth flow rate is in a range of 5:1 to 15:

1.

8. A method for forming a semiconductor device structure, characterized in that: include: forming an insulating material on a substrate; depositing a gate dielectric layer on the insulating material; depositing a gate electrode layer on the gate dielectric layer; Performing a cyclic process to form an opening through the gate electrode layer and the gate dielectric layer into the insulating material, wherein the cyclic process includes a plurality of cycles, and each cycle includes: Performing a main etching process to remove a portion of the gate electrode layer, wherein the main etching process includes: introducing a first chlorine-containing etchant at a first flow rate and introducing a second chlorine-containing etchant at a second flow rate, and a ratio of the first flow rate to the second flow rate is in a range of 1:2 to 1:6; then performing an additional etching process that etches the gate dielectric layer at a faster rate than etching the gate electrode layer, wherein the additional etching process includes introducing the first chlorine-containing etchant at a third flow rate and introducing the second chlorine-containing etchant at a fourth flow rate, and a ratio of the third flow rate to the fourth flow rate is in a range of 5:1 to 15:1; and The opening is filled with a dielectric material.

9. The method for forming a semiconductor device structure according to claim 8, wherein: Each cycle of the cyclic process has a first duration, and the additional etching process has a second duration substantially longer than the first duration.

10. The method for forming a semiconductor device structure according to claim 9, wherein: The second duration is twice as long as the first duration.

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