Method of fabricating a semiconductor structure, semiconductor structure, device and apparatus

Abstract

The application provides a semiconductor structure preparation method, a semiconductor structure, a device and equipment. The preparation method comprises: forming a first electrode structure on a first region of a substrate, and forming a first transistor in a flip-chip stacked transistor on a second region of the substrate; flipping and removing the substrate; forming a second electrode structure on the first region, and forming a second transistor in the flip-chip stacked transistor on the second region, wherein the ion doping type of the second electrode structure is different from the ion doping type of the first electrode structure; and wherein, in the case that the first electrode structure or the second electrode structure is a base electrode structure, an emitter electrode structure is formed on a third region of the base electrode structure by ion doping, and the ion doping type of the emitter electrode structure is different from the ion doping type of the base electrode structure. By preparing a punch-through bipolar junction transistor compatible with the flip-chip stacked transistor process, the process steps are saved, and the flexibility of the semiconductor device circuit design is enhanced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated semiconductors, and in particular to a method for manufacturing a semiconductor structure, a semiconductor structure, a device and an apparatus. BACKGROUND

[0002] With the deepening of Moore's Law, it is a hot issue in the current industry to continue to promote the miniaturization of transistors. Stacked transistors integrate two or more transistors in vertical space to further improve the integration density of transistors, and become one of the important technologies to continue the miniaturization of integrated circuits. Under the preparation process of flip stacked transistors, a method for preparing a bipolar junction transistor is urgently needed. SUMMARY

[0003] The present application provides a method for manufacturing a semiconductor structure, a semiconductor structure, a device and an apparatus, which prepares a through bipolar junction transistor compatible with the flip stacked transistor process, not only saving the process steps, but also enhancing the flexibility of circuit design in semiconductor devices.

[0004] In a first aspect, the embodiments of the present application provide a method for manufacturing a semiconductor structure, which includes: forming a first electrode structure on a first region of a substrate, and forming a first transistor in a flip stacked transistor on a second region of the substrate, the first region and the second region being different regions of the substrate in a first direction; flipping the first electrode structure and the first transistor, and removing the substrate; forming a second electrode structure on the first region, and forming a second transistor in the flip stacked transistor on the second region, the ion doping type of the second electrode structure being different from the ion doping type of the first electrode structure; wherein the first electrode structure is a base electrode structure, and the second electrode structure is a collector electrode structure, or the first electrode structure is a collector electrode structure, and the second electrode structure is a base electrode structure; forming an emitter electrode structure on a third region of the base electrode structure by ion doping, the ion doping type of the emitter electrode structure being different from the ion doping type of the base electrode structure.

[0005] In a possible implementation, forming a first electrode structure on a first region of a substrate, and forming a first transistor in a flip stacked transistor on a second region of the substrate includes: forming a first mask on the second region; forming a first electrode on the first region by ion doping; removing the first mask; forming a first electrode contact metal on the first electrode in the case of forming the first transistor based on the second region, the first electrode and the first electrode contact metal constituting the first electrode structure.

[0006] In a possible implementation, forming a second electrode structure on the first region and forming a second transistor in the flip-chip stacked transistor on the second region comprises: forming a second mask on the second region; forming a second electrode on the first region by ion doping, the ion doping type of the second electrode being different from the ion doping type of the first electrode; removing the second mask; forming a second electrode contact metal on the second electrode in the case of forming the second transistor based on the second region, the second electrode and the second electrode contact metal constituting the second electrode structure.

[0007] In a possible implementation, in the case of the first electrode being a collector, forming a first electrode contact metal on the first electrode in the case of forming a first transistor in the flip-chip stacked transistor based on the second region comprises: forming a third mask on the first region, and etching the substrate in the second region to form an active structure, the active structure comprising a first active structure away from the substrate and a second active structure close to the substrate; forming a first semiconductor structure based on the first active structure; removing the third mask; forming a first source-drain structure on the second region by ion implantation and forming a collector contact structure on the collector of the first region, the first source-drain structure being formed after ion implantation of the first semiconductor structure, and the ion concentration of the collector contact structure being higher than that of the collector structure; forming a first gate structure in the first transistor and a first source-drain metal on the second region in sequence while forming a collector contact metal on the collector contact structure of the first region.

[0008] In a possible implementation, forming a first gate structure in the first transistor and a first source-drain metal on the second region in sequence while forming a collector contact metal on the collector contact structure of the first region comprises: forming a first dielectric layer on the first source-drain structure and the collector contact structure; forming a first gate structure based on the first active structure; etching the first dielectric layer to form a first source-drain metal on the first source-drain structure and a collector contact metal on the collector contact structure.

[0009] In a possible implementation, in the case of the second electrode being a base, forming a second electrode contact metal on the second electrode in the case of forming a second transistor based on the second region comprises: forming a second source-drain structure based on a second active structure on the second region; forming a fourth mask on the first region and the second region, the fourth mask on the first region exposing a region where the emitter is located; forming an emitter on the first region by ion implantation; removing the fourth mask; forming a second gate structure in the second transistor and a second source-drain metal on the second region in sequence while forming a base contact metal on the base of the first region and an emitter contact metal on the emitter.

[0010] In a possible implementation, the second gate structure and the second source-drain metal in the second transistor are sequentially formed on the second region, and the base contact metal is formed on the base of the first region, and the emitter contact metal is formed on the emitter, including: forming a second dielectric layer on the second source-drain structure, the base and the emitter; forming the second gate structure based on the second active structure; etching the second dielectric layer to form the second source-drain metal on the second source-drain structure, and form the base contact metal on the base and the emitter contact metal on the emitter.

[0011] In a possible implementation, in the case that the first pole structure is the base structure, the first pole is formed on the first region by ion doping, including: forming the collector by ion doping on the first region; forming the base by ion doping on the collector, the ion doping type of the base being different from the ion doping type of the collector.

[0012] In a possible implementation, in the case that the first pole is the base, the first transistor in the flip stacked transistor is formed based on the second region, and the first pole contact metal is formed on the first pole, including: forming a fifth mask on the first region, and etching the substrate in the second region to form an active structure, the active structure including a first active structure away from the substrate and a second active structure close to the substrate; forming a first source-drain structure based on the first active structure, the ion doping type in the first source-drain structure being the same as the ion doping type of the base structure; forming a fifth mask on the second region, and etching the fifth mask on the first region to expose the region where the emitter is located; forming an emitter structure on the first region by ion implantation; removing the fifth mask; sequentially forming the first gate structure and the first source-drain metal in the first transistor on the first region, and forming the base contact metal on the base of the first region and the emitter contact metal on the emitter.

[0013] In a possible implementation, in the case that the second pole is the collector, the second transistor is formed based on the second region, and the second pole contact metal is formed on the second pole, including: forming a sixth mask on the first region, and forming a second semiconductor structure based on the second active structure on the second region; removing the sixth mask; forming a second source-drain structure on the second region by ion implantation, and forming a collector contact structure on the collector of the first region, the second source-drain structure being formed after ion implantation of the second semiconductor structure, and the ion concentration of the collector contact structure being higher than the ion concentration of the collector; sequentially forming the second gate structure and the second source-drain metal in the second transistor on the second region, and forming the collector contact metal on the collector contact structure of the first region.

[0014] In a second aspect, the embodiments of the present application provide a semiconductor structure, which is prepared by the preparation method in the first aspect and any of the embodiments thereof, and includes: flip-chip stacked transistors and bipolar junction transistors in different regions, the flip-chip stacked transistors and the bipolar junction transistors being formed simultaneously; wherein the flip-chip stacked transistors include first and second transistors arranged oppositely, and the bipolar junction transistors include collector structures, base structures and emitter structures, the collector structures being arranged oppositely to the base structures and the emitter structures.

[0015] In a third aspect, the embodiments of the present application provide a semiconductor device, which includes the semiconductor structure in the second aspect.

[0016] In a fourth aspect, the embodiments of the present application provide an electronic device, which includes a circuit board and the semiconductor device in the third aspect, and the semiconductor device is arranged on the circuit board.

[0017] The technical solutions provided by the present application can have the following beneficial effects:

[0018] In the embodiments of the present application, the first electrode structure is formed on the first region of the substrate, and the first transistor in the flip-chip stacked transistors is formed on the second region of the substrate; the substrate is flipped and removed; the second electrode structure different from the ion doping type of the first electrode structure is formed on the first region, and the second transistor in the flip-chip stacked transistors is formed on the second region. The present application prepares the through bipolar junction transistor compatible with the flip-chip stacked transistor process, saves the process steps, and enhances the flexibility of the semiconductor device circuit design.

[0019] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present application and, together with the specification, serve to explain the principles of the present application.

[0021] Figure 1 An implementation flowchart of the preparation method of the semiconductor structure in the embodiments of the present application;

[0022] Figure 2 A first top view schematic diagram of the semiconductor structure in the embodiments of the present application;

[0023] Figures 3 to 14 A first preparation process schematic diagram of the semiconductor structure in the embodiments of the present application;

[0024] Figure 15 A first structure schematic diagram of the semiconductor structure in the embodiments of the present application;

[0025] Figure 16 Fig. 2 is a second top view of a semiconductor structure in an embodiment of the present application;

[0026] Figure 17 Fig. 3 is a second structural view of a semiconductor structure in an embodiment of the present application;

[0027] Figure 18 Fig. 4 is a third structural view of a semiconductor structure in an embodiment of the present application;

[0028] Figure 19 Fig. 5 is a fourth structural view of a semiconductor structure in an embodiment of the present application.

[0029] Figs. 1-5:

[0030] 10, flip-chip stacked transistor; 11, first transistor (front-side transistor); 111, first fin structure; 112, first source-drain structure; 113, first interlayer dielectric layer; 114, first gate structure; 115, first source-drain metal; 12, second transistor (back-side transistor); 121, first fin structure; 122, second source-drain structure; 123, second interlayer dielectric layer; 124, second gate structure; 125, second source-drain metal; 20, BJT; 21, substrate; 22, first photoresist layer; 23, collector region; 24, second photoresist layer; 25, fin structure; 26, isolation structure; 27, first dummy gate structure; 28, first sidewall; 29, first semiconductor structure; 30, collector contact region; 31, first dielectric layer; 32, collector contact metal; 33, first insulating layer; 34, first oxide layer; 35, second oxide layer; 36, second insulating layer; 37, carrier wafer; 38, base region; 39, third photoresist layer; 40, second dummy gate structure; 41, second sidewall; 42, fourth photoresist layer; 43, emitter region; 44, second dielectric layer; 45, base contact metal; 46, emitter contact metal; 47, third insulating layer; 48, third oxide layer. DETAILED DESCRIPTION

[0031] The exemplary embodiments will be described in detail herein with reference to the attached drawings. In the following description, unless otherwise indicated, like numbers refer to like elements throughout the several drawings. The following exemplary embodiments are described with reference to the accompanying drawings.

[0032] In the context of Moore's Law, continuing to push the scaling of transistor size is a hot issue in the current industry. Stacked transistors, by stacking three-dimensional transistors, can integrate two or more layers of transistors in vertical space, helping to further improve transistor integration density and circuit performance, and is considered one of the important technologies to continue the scaling of integrated circuit size.

[0033] In an embodiment, there are two options for the preparation process of the stacked transistors, one is a monolithic option and the other is a sequential option.

[0034] In the first option, N field effect transistors (NFET) and P field effect transistors (PFET) are fabricated on the same substrate without using substrate bonding technology. This determines that the transistors in the same layer must be of the same type, i.e., NFET or PFET. Moreover, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this option is better integration density. The disadvantages of this option include the following two points: (1) complex process, a large amount of process technology development and optimization are required; (2) the polarity of each layer of transistors is fixed, and the basic complementary metal-oxide-semiconductor (CMOS) circuit must be composed of two layers of transistors, which has poor design flexibility.

[0035] In the second option, the substrate is bonded and processed layer by layer. Specifically, the two transistors are vertically stacked by bonding the substrate on the top of the lower layer of transistors to prepare the upper layer of transistors. However, the temperature needs to be strictly controlled during the thermal process of preparing the upper layer of transistors to avoid affecting the lower layer of transistors and the interconnection lines. The advantage of this option is that due to the substrate bonding, the device structure, channel crystal direction and even channel material of the upper and lower layers of transistors can be optimized accordingly to obtain better and more matched device performance. The current technical challenges of this option include the following: (1) preparation of high-quality upper layer of transistors; (2) thinning and defect control of the upper bonding substrate; (3) alignment error exists between the upper and lower layers of transistors, which requires high precision of photolithography.

[0036] However, some preparation options for flip-chip stacked transistors do not involve the preparation of bipolar junction transistors (BJT) in the flip-chip stacked transistor process.

[0037] Therefore, the embodiments of the present application provide a preparation method of a semiconductor structure, which saves process steps and enhances the flexibility of semiconductor device circuit design by preparing a punch-through bipolar junction transistor compatible with the flip-chip stacked transistor process.

[0038] In the embodiments of the present application, the semiconductor structure described above can be applied to semiconductor devices such as memories and processors.

[0039] In some embodiments, the semiconductor structure can include flip-chip stacked transistors and bipolar junction transistors located in different regions, the flip-chip stacked transistors and the bipolar junction transistors being formed simultaneously; wherein the flip-chip stacked transistors include first and second transistors arranged oppositely, and the bipolar junction transistor includes a collector structure, a base structure, and an emitter structure, the collector structure being arranged oppositely to the base structure and the emitter structure.

[0040] In the embodiments of the present application, the first and second transistors in the flip-chip stacked transistors are the same type of transistors, which can include but are not limited to fin field effect transistors (FinFETs), gate-all-around field effect transistors (GAAFETs), planar transistors, vertical field effect transistors (VFETs), etc.

[0041] Figure 1 An implementation flowchart of a method for manufacturing a semiconductor structure in the embodiments of the present application is shown in FIG. 1. Figure 1 As shown in FIG. 1, the method for manufacturing a semiconductor structure includes the following steps.

[0042] Step S101: forming a first electrode structure on a first region of a substrate, and forming a first transistor in flip-chip stacked transistors on a second region of the substrate.

[0043] In some embodiments, the first and second regions are different regions of the substrate in a first direction.

[0044] In some embodiments, the implementation process of step S101 can be: forming a first mask on the second region; forming a first electrode on the first region by ion doping; removing the first mask; forming a first electrode contact metal on the first electrode in the case of forming the first transistor based on the second region, the first electrode and the first electrode contact metal constituting the first electrode structure.

[0045] In some embodiments, the collector structure in the punch-through BJT can be located on the front surface, and the base structure and the emitter structure can be located on the back surface, or the base structure and the emitter structure can be located on the front surface, and the collector structure can be located on the back surface. In the present application, the scheme in which the collector structure is located on the front surface, and the base structure and the emitter structure are located on the back surface is referred to as the first scheme, and the scheme in which the base structure and the emitter structure are located on the front surface, and the collector structure is located on the back surface is referred to as the second scheme.

[0046] In some embodiments, in the case that the first electrode structure of the front side is a collector structure (corresponding to the first scheme), a substrate is first provided, the substrate including a first region for preparing a BJT and a second region for preparing a flip-chip stacked transistor; a first mask is then formed on the second region of the substrate; and a collector is formed on the first region of the substrate by ion doping. The collector can also be referred to as a collector region.

[0047] In some embodiments, the substrate can be any semiconductor substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, etc.

[0048] In some embodiments, the ion doping type can be N-type ions or P-type ions. The P-type ions can be any of boron (B), gallium (Ga), and aluminum (Al). The N-type ions can be any of phosphorus (P), arsenic (As), and antimony (Sb).

[0049] It can be understood that the BJT device region (i.e., the first region) and the flip-chip stacked transistor device region (i.e., the second region) are defined by photolithography, a first mask is formed on the second region, and then a collector region is formed on the first region by ion doping. Since the second region has a first mask as a protective layer when ion doping is performed, the substrate on the second region is not ion doped.

[0050] In some embodiments, the collector region can be formed by low-doped deep well implantation, so that the ion doping concentration of the collector region is low, and the thickness of the collector region is high. For example, the ion doping type of the collector region can be P-type ions.

[0051] In some embodiments, in the case that the first electrode structure is a base structure (corresponding to the second scheme), a substrate is first provided, the substrate including a first region for preparing a BJT and a second region for preparing a flip-chip stacked transistor; a first mask is formed on the second region of the substrate; a collector is formed on the first region of the substrate by ion doping; and a base is formed on the collector by ion doping, the ion doping type of the base being different from the ion doping type of the collector. The collector can also be referred to as a collector region, and the base can also be referred to as a base region.

[0052] It can be understood that the collector region is first formed on the first region, and then the base region of the BJT is defined by photolithography and ion doping to form the base region. The thickness of the base region is less than the thickness of the collector region.

[0053] In some embodiments, in the case that the ion doping type of the collector region is P-type ions, the ion doping type of the base region is N-type ions.

[0054] In some embodiments, the base region can be formed by shallow well implantation, so that the base region formed has a low thickness.

[0055] It can be understood that the first mask is used as a protective layer to form the collector region or the base region of the BJT, and then the first mask can be removed, and the front surface transistor (i.e., the first transistor) of the flip-chip stacked transistor and the front surface structure of the BJT are formed at the same time.

[0056] In some embodiments, in the case of forming the first transistor in the flip-chip stacked transistor based on the second region, the first electrode contact metal is formed on the first electrode structure.

[0057] In some embodiments, in the case of the first electrode being a collector electrode on the front surface (corresponding to the first scheme), in the case of forming the first transistor in the flip-chip stacked transistor based on the second region, the implementation process of forming the first electrode contact metal on the first electrode structure can be: forming a third mask on the first region, and etching the substrate in the second region to form an active structure, the active structure including a first active structure away from the substrate and a second active structure close to the substrate; based on the first active structure, forming a first semiconductor structure; removing the third mask; forming a first source-drain structure in the second region by ion implantation, and forming a collector electrode contact structure in the first region, the first source-drain structure being formed after ion implantation of the first semiconductor structure, and the ion concentration of the collector electrode contact structure being higher than the ion concentration of the collector electrode; and forming a first gate structure and a first source-drain metal of the first transistor in the second region in sequence, while forming a collector electrode contact metal on the collector electrode contact structure in the first region. The collector electrode contact structure can also be referred to as a collector electrode contact region.

[0058] It can be understood that the third mask is first formed on the first region, and then the substrate in the second region is etched to form a plurality of active structures standing on the substrate, and based on the first active structure in the active structure, the first semiconductor structure is formed. Then the third mask is removed, and the first semiconductor structure in the second region is formed into a first source-drain structure by ion implantation, and a part of the collector region in the first region is formed into a collector electrode contact region. Thereafter, the front surface transistor in the flip-chip stacked transistor and the collector electrode contact metal in the front surface of the BJT can be formed respectively. For example, the etching process can be at least one of dry etching, wet etching, and reactive ion etching.

[0059] In the case of the flip-chip stacked transistor being a fin field effect transistor, the active structure is a fin structure (fin). In the case of the flip-chip stacked transistor being a fully wrapped gate transistor, the active structure is a nanosheet. In the case of the flip-chip stacked transistor being a planar transistor, the active structure is a block planar structure.

[0060] In some embodiments, after the active structure is formed, an insulating material can be deposited on the substrate to form an isolation structure wrapping the second active structure.

[0061] It can be understood that, after the active structure is formed, an insulating material can be deposited on the substrate and the surface of the active structure and thinned, so that the formed isolation structure wraps the second active structure to expose the first active structure.

[0062] In an example, the isolation structure can be in the form of a shallow trench isolation (STI). For example, the insulating material forming the isolation structure can be any one of silicon nitride (SiN, Si3N4), silicon dioxide (SiO2), or silicon carbon oxide (SiCO), etc. The thinning process can be a chemical-mechanical planarization (CMP) process, etc.

[0063] In some embodiments, before the first semiconductor structure is formed based on the first active structure, a semiconductor material can also be deposited in the gate region of the first transistor to form a first dummy gate structure surrounding the first active structure; and a first side wall is formed on both sides of the first dummy gate structure.

[0064] For example, the semiconductor material can be poly-Si, amorphous silicon, etc.

[0065] It can be understood that, after the isolation structure is formed, the gate region can be opened by lithography, and a semiconductor material such as poly-Si is deposited in the gate region as a dummy gate structure (i.e., the first dummy gate structure) of the front surface transistor. Then a dielectric material is deposited on both sides of the first dummy gate structure to form a first side wall. The first spacer is used to isolate the first source / drain structure from the first gate structure. The structure of the first spacer can be set according to actual needs, and the embodiments of the present application are not limited thereto. For example, the first spacer can have a single-layer structure and be made of the same material, such as porous silicon carbon oxide hydride (SiCOH).

[0066] In some embodiments, after the first side wall is formed, the first semiconductor structure can be formed on the first active structure on both sides of the first dummy gate structure and the first side wall. That is, the first source / drain structure without ion implantation is formed.

[0067] In an example, the first active structure in the source / drain region of the first transistor is etched to form a source / drain recess, and then a strain material such as silicon germanium or silicon carbide is formed by selective epitaxial growth to fill the source / drain recess to form the first semiconductor structure.

[0068] After the first semiconductor structure is formed, the third mask is removed, the collector contact region of the BJT is defined by lithography, and then ion implantation is performed on both regions to form the collector contact structure on the first region and the first source-drain structure on the second region. The thickness of the collector contact structure is less than the thickness of the collector region, and the ion concentration of the collector contact structure is higher than the ion concentration of the collector region.

[0069] It should be noted that the type of ion implanted here is the same as the type of ion doped in the collector region in step S101. For example, when the type of ion doped in the collector region is P-type, the type of ion implanted here is also P-type.

[0070] It can be understood that after the third mask is removed, the first source-drain structure can be formed by ion implantation of the strained material of the first semiconductor structure in the second region, and the collector contact structure can be formed by defining the collector contact region by lithography and then performing high-concentration ion implantation on the region.

[0071] After the first source-drain structure and the collector contact structure are formed, the first gate structure in the first transistor and the first source-drain metal can be formed on the second region at the same time, and the collector contact metal can be formed on the collector contact structure of the first region.

[0072] In some embodiments, the implementation process of forming the first gate structure in the first transistor and the first source-drain metal on the second region at the same time, and forming the collector contact metal on the collector contact structure of the first region can be: forming a first dielectric layer on the first source-drain structure and the collector contact structure; based on the first active structure, forming the first gate structure; etching the first dielectric layer to form the first source-drain metal on the first source-drain structure and the collector contact metal on the collector contact structure.

[0073] It can be understood that after the collector contact structure and the first source-drain structure are formed at the same time, an insulating material (such as SiO2) can be deposited on the collector contact structure and the first source-drain structure and planarized to form a first interlayer dielectric layer (which can also be referred to as a first dielectric layer), which can cover the collector contact structure and the first source-drain structure. Then the first dummy gate structure in the second region can be removed to form the first gate structure. Then the first dielectric layer can be etched to expose the collector contact structure in the first region and the first source-drain structure in the second region, and a metal material can be deposited on the exposed collector contact structure and first source-drain structure to form the collector contact metal in the first region and the first source-drain metal in the second region. The collector contact metal occupies a small part of the area on the collector contact structure.

[0074] It should be noted that the first gate structure does not exist in the first region because there is no active structure and dummy gate structure in the first region.

[0075] In some embodiments, the first dummy gate structure formed above is removed by an etching process to form a first gate recess, an insulating material is deposited at the first gate recess to form a first gate dielectric layer, and a metal material is deposited on the first gate dielectric layer to form a first gate electrode layer. The first gate dielectric layer and the first gate electrode layer together constitute the first gate structure.

[0076] For example, the first gate dielectric layer can be composed of a silicon oxide layer and a high-K hafnium oxide layer, and the thickness of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the transistor. For example, the first gate electrode layer can be composed of multiple layers of electrode materials, each layer of electrode material including but not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0077] In addition, in some embodiments, after the first gate structure is formed, an insulating material can be deposited on the first gate structure in the second region and the collector contact structure in the first region to form a first insulating layer, and then a first oxide layer is formed on the first insulating layer to protect the collector contact structure in the first region and the first gate structure in the second region. When the first source / drain metal and the collector contact metal are formed by photolithography, if the photolithography punch is offset, it will also be punched on the insulating layer, preventing the gate metal from directly contacting the source / drain metal and reducing the requirements for photolithography.

[0078] In some embodiments, after the collector contact metal is formed in the first region and the first source / drain metal is formed in the second region, a first metal interconnection layer can be formed by subsequent processes (such as interconnection line medium deposition, metal line formation, lead-out pad formation, etc.). Thus, the front surface structure of the BJT in the first region and the front surface transistor of the flip-chip stacked transistor in the second region are prepared.

[0079] The above is the preparation process of forming the collector structure on the front surface in the first scheme. The following describes the preparation process of forming the base structure and the emitter structure on the front surface in the second scheme.

[0080] In some embodiments, in the case of the first pole of the front side being the base (corresponding to the second scheme), in the case of forming the first transistor in the flip-chip stacked transistor based on the second region, the implementation process of forming the first pole contact metal on the first pole structure can be: forming a fifth mask on the first region, and etching the substrate in the second region to form the active structure, the active structure including the first active structure away from the substrate and the second active structure close to the substrate; based on the first active structure, forming the first source-drain structure, the ion doping type of the first source-drain structure being the same as the ion doping type of the base structure; forming a fifth mask on the second region, and etching the fifth mask on the first region to expose the region where the emitter is located; forming the emitter on the first region by ion implantation; removing the fifth mask; and forming the first gate structure and the first source-drain metal in the first transistor on the first region in sequence, while forming the base contact metal on the base of the first region and forming the emitter contact metal on the emitter. The emitter can also be referred to as the emission region.

[0081] It can be understood that first, the fifth mask is formed on the first region, and then the substrate in the second region is etched to form a plurality of active structures standing on the substrate, and based on the first active structure in the active structure, the first source-drain structure with the same ion doping type as the ion doping type of the base region is formed. Then the emitter region can be defined on the first region by lithography, and then the emission region is formed on the third region of the base region by ion doping, and finally the front side transistor in the flip-chip stacked transistor and the base contact metal and the emitter contact metal of the front side in the BJT are formed respectively. The third region is a part of the base region.

[0082] In some embodiments, after the active structure is formed, an insulating material can be deposited on the substrate to form an isolation structure wrapping the second active structure.

[0083] In some embodiments, before the first source-drain structure is formed based on the first active structure, a semiconductor material can also be deposited in the gate region of the first transistor to form a first pseudo-gate structure surrounding the first active structure; and first side walls are formed on both sides of the first pseudo-gate structure.

[0084] It can be understood that in the second scheme, after the base region with an ion doping type different from that of the collector region is formed in the above step S101, a first source-drain structure with the same ion doping type as that of the base region can be formed here. For example, in the case where the ion doping type of the collector region is P-type and the ion doping type of the base region is N-type, an N-type first source-drain structure can be formed here.

[0085] After the first source-drain structure is formed, a fifth mask can be formed on the second region, and an emitter region in the first region is defined by lithography. Thus, the fifth mask in the first region can be etched to expose the region where the emitter region is located, and then the emitter region is formed by ion implantation in the exposed region of the first region. After the emitter region is formed, the fifth mask can be removed. The ion implantation (also referred to as doping) concentration of the emitter region is higher than that of the collector region, the ion doping type of the emitter region is the same as that of the collector region, and different from that of the base region. For example, in the case where the ion doping type of the collector region is P type and the ion doping type of the base region is N type, the ion doping type of the emitter region is P type.

[0086] In some embodiments, the emitter region can be formed by high-doped shallow well implantation, so that the ion doping concentration of the emitter region is high, and the thickness of the emitter region is low.

[0087] After the base and the emitter are formed, the first gate structure in the first transistor and the first source-drain metal can be formed on the second region in sequence, and the base contact metal is formed on the base of the first region and the emitter contact metal is formed on the emitter.

[0088] In some embodiments, the implementation process of forming the base contact metal on the base of the first region and the emitter contact metal on the emitter while forming the first gate structure in the first transistor and the first source-drain metal on the second region can be: forming a first dielectric layer on the first source-drain structure, the base and the collector; forming the first gate structure based on the first active structure; etching the first dielectric layer to form the first source-drain metal on the first source-drain, and to form the base contact metal on the base and the emitter contact metal on the emitter.

[0089] It can be understood that after the base and the emitter are formed, an insulating material (such as SiO2) can be deposited on the base, the emitter and the first source-drain structure, and planarization processing is performed to form a first interlayer dielectric layer (also referred to as a first dielectric layer), which can cover the base, the emitter and the first source-drain structure. Then the first dummy gate structure in the second region can be removed to form the first gate structure. Then the first dielectric layer can be etched to expose the base, the emitter in the first region and the first source-drain structure in the second region, and a metal material can be deposited on the exposed base, the emitter and the first source-drain structure to form the base contact metal, the emitter contact metal in the first region and the first source-drain metal in the second region.

[0090] In some embodiments, after forming the base contact metal, the emitter contact metal in the first region and the first source / drain metal in the second region, a first metal interconnection layer can be formed by a back-end-of-line process (e.g., interconnection line medium deposition, metal line formation, lead pad formation, etc.). Thus, the front surface structure of the BJT in the first region and the front surface transistor of the flip-chip stacked transistor in the second region are prepared.

[0091] Step S102: flip the first polar structure and the first transistor, and remove the substrate.

[0092] It can be understood that, after the front surface structure of the BJT in the first region and the front surface transistor of the flip-chip stacked transistor in the second region are prepared, the front surface structure of the BJT and the front surface transistor can be flipped, the back surface structure of the BJT is prepared on the front surface structure of the BJT, and the back surface transistor is prepared on the front surface transistor.

[0093] In some embodiments, an insulating material (e.g., silicon oxide) can be deposited on the first metal interconnection layer to form a second insulating layer, and the second insulating layer is bonded with a wafer carrier, followed by flipping and removing the substrate.

[0094] In some embodiments, after removing the substrate, the isolation structure on the second region can be thinned to expose the second active structure, so as to subsequently prepare the back surface transistor based on the exposed second active structure.

[0095] Step S103: form a second polar structure on the first region, and form a second transistor in the flip-chip stacked transistor on the second region.

[0096] In some embodiments, the ion doping type of the second polar structure is different from the ion doping type of the first polar structure.

[0097] In some embodiments, the implementation process of step S103 can be: forming a second mask on the second region; forming a second polar on the first region by ion doping, the ion doping type of the second polar being different from the ion doping type of the first polar; removing the second mask; forming a second polar contact metal on the second polar in the case of forming a second transistor based on the second region, the second polar and the second polar contact metal constituting the second polar structure.

[0098] In some embodiments, in the case that the second polar structure on the back surface is a base structure (corresponding to the first scheme), a second mask can be formed on the second region, the base region of the BJT is defined by photolithography, and the base polar is formed by ion doping. The ion doping type of the base polar is different from the ion doping type of the collector.

[0099] In some embodiments, in the case that the second electrode on the back side is a collector (corresponding to the second scheme), since the first step of the second scheme has formed a collector in the foregoing step S101, no operation can be performed here.

[0100] It can be understood that the first scheme forms the base region of the BJT with the second mask as the protective layer, and then the second mask can be removed, and the back side transistor of the flip-chip stacked transistor and the back side structure of the BJT are formed at the same time.

[0101] In some embodiments, in the case that the second transistor in the flip-chip stacked transistor is formed based on the second region, the second electrode contact metal is formed on the second electrode structure.

[0102] In some embodiments, in the case that the second electrode on the back side is a base (corresponding to the first scheme), in the case that the second transistor in the flip-chip stacked transistor is formed based on the second region, the implementation process of forming the second electrode contact metal on the second electrode structure can be: forming a fourth mask on the first region, and forming a second source-drain structure based on the second active structure on the second region; forming a fourth mask on the second region, and the fourth mask on the first region exposes the region where the emitter is located; forming the emitter on the first region by ion implantation; removing the fourth mask; forming the second gate structure and the second source-drain metal in the second transistor on the second region in sequence, and forming the base contact metal on the base of the first region and the emitter contact metal on the emitter at the same time.

[0103] It can be understood that the fourth mask is first formed on the first region, and then the second source-drain structure of the same ion doping type as the base region is formed based on the second active structure in the active structure of the second region. Then the emitter region can be defined on the first region by lithography, and then the emitter region is formed by ion doping on the third region of the base region, and finally the back side transistor (i.e. the second transistor) in the flip-chip stacked transistor and the base contact metal and the emitter contact metal on the back side in the BJT are formed respectively.

[0104] In some embodiments, before forming the second source-drain structure based on the second active structure on the second region, a mask can also be formed on the first region, and then a semiconductor material is deposited in the gate region of the second transistor in the second region to form a second pseudo-gate structure surrounding the second active structure; the second side wall is formed on both sides of the second pseudo-gate structure. After forming the second side wall, the second source-drain structure can be formed on the second active structure on both sides of the second pseudo-gate structure and the second side wall. Then the mask can be removed.

[0105] After the second source-drain structure is formed, a fourth mask can be formed on the second region, and the area where the emitter is located in the second region is defined by lithography. Thus, the fourth mask in the first region can be etched to expose the area where the emitter is located, and then the emitter region is formed by ion implantation in the exposed area of the first region. After the emitter region is formed, the fourth mask can be removed.

[0106] After the base and the emitter are formed, the second gate structure in the second transistor and the second source-drain metal can be formed on the second region in sequence, while the base contact metal is formed on the base in the first region and the emitter contact metal is formed on the emitter.

[0107] In some embodiments, the implementation process of forming the base contact metal on the base in the first region and the emitter contact metal on the emitter while forming the second gate structure in the second transistor and the second source-drain metal on the second region in sequence can be: forming a second dielectric layer on the second source-drain structure, the base and the collector; forming the second gate structure based on the second active structure; etching the second dielectric layer to form the second source-drain metal on the second source-drain structure, and to form the base contact metal on the base and the emitter contact metal on the emitter.

[0108] It can be understood that after the base and the emitter are formed, an insulating material (such as SiO2) can be deposited on the base, the emitter and the second source-drain structure, and a planarization process can be performed to form a second interlayer dielectric layer (which can also be referred to as a second dielectric layer), which can cover the base, the emitter and the second source-drain structure. Then the second dummy gate structure in the second region can be removed to form the second gate structure. Then the second dielectric layer can be etched to expose the base, the emitter in the first region and the second source-drain structure in the second region, and a metal material can be deposited on the exposed base, the emitter and the second source-drain structure to form the base contact metal, the emitter contact metal in the first region and the second source-drain metal in the second region.

[0109] In some embodiments, after the base contact metal, the emitter contact metal in the first region and the second source-drain metal in the second region are formed, a second metal interconnection layer can be formed by a back-end-of-line process (such as interconnection line interlayer dielectric deposition, metal line formation, lead pad formation, etc.). Thus, the back surface structure of the BJT in the first region and the back surface transistor of the flip-chip stacked transistor in the second region are prepared.

[0110] In some embodiments, after forming the second gate structure and before forming the second source-drain, an insulating material can be deposited on the second gate structure of the second region and the base and emitter of the first region to form a third insulating layer, and then a second oxide layer can be formed on the third insulating layer to protect the base and emitter in the first region and the second gate structure in the second region. When the second source-drain metal and the base contact metal and the emitter contact metal are formed by photolithography, if the photolithography punch is offset, it will also be punched on the insulating layer, preventing the gate metal from directly contacting the source-drain metal and reducing the requirements for photolithography.

[0111] In some embodiments, after forming the base contact metal and the emitter contact metal in the first region and the second source-drain metal in the second region, a second metal interconnection layer can be formed by subsequent processes such as interconnection line medium deposition, metal line formation, and lead-out pad formation. In this way, the back surface structure of the BJT in the first region and the back surface transistor of the flip-chip stacked transistor in the second region are prepared.

[0112] The above is the preparation process of forming the base structure and the emitter structure on the back surface in the first scheme. The preparation process of forming the collector structure on the back surface in the second scheme is introduced below.

[0113] In some embodiments, in the case where the second pole on the back surface is the collector (corresponding to the second scheme) and the second transistor in the flip-chip stacked transistor is formed based on the second region, the implementation process of forming the second pole contact metal on the second pole structure can be: forming a sixth mask on the first region, and forming a second semiconductor structure based on the second active structure on the second region; removing the sixth mask; forming a second source-drain structure in the second region by ion implantation, and forming a collector contact structure on the collector of the first region, the second source-drain structure being formed after ion implantation of the second semiconductor structure, and the ion concentration of the collector contact structure being higher than that of the collector; simultaneously forming a second gate structure and a second source-drain metal in the second transistor on the second region, and forming a collector contact metal on the collector contact structure of the first region.

[0114] In some embodiments, before forming the second semiconductor structure based on the second active structure, a semiconductor material can also be deposited in the gate region of the second transistor to form a second dummy gate structure surrounding the second active structure; and a second side wall can be formed on both sides of the second dummy gate structure.

[0115] In some embodiments, after forming the second side wall, the second semiconductor structure can be formed on the second active structure on both sides of the second dummy gate structure and the second side wall. That is, the second source-drain structure that has not undergone ion implantation is formed.

[0116] After the second semiconductor structure is formed, the sixth mask is removed, the collector contact region of the BJT is defined by lithography, and then ion implantation is performed on both regions to form the collector contact region on the first region and the second source-drain structure on the second region.

[0117] It can be understood that after the sixth mask is removed, the second source-drain structure can be formed by ion implantation of the strained material of the second semiconductor structure in the second region, and the collector contact structure can be formed by defining the collector contact region by lithography and then performing high-concentration ion implantation on the region.

[0118] After the second source-drain structure and the collector contact structure are formed, the second gate structure in the second transistor and the second source-drain metal can be formed on the second region in sequence, and the collector contact metal can be formed on the collector contact structure of the first region.

[0119] In some embodiments, the implementation process of forming the second gate structure in the second transistor and the second source-drain metal on the second region in sequence and forming the collector contact metal on the collector contact structure of the first region can be: forming a second dielectric layer on the second source-drain structure and the collector contact structure; forming the second gate structure based on the second active structure; etching the second dielectric layer to form the second source-drain metal on the second source-drain structure and the collector contact metal on the collector contact structure.

[0120] It can be understood that after the collector contact structure and the second source-drain structure are formed at the same time, an insulating material (such as SiO2) can be deposited on the collector contact structure and the second source-drain structure and planarized to form a second interlayer dielectric layer (which can also be referred to as a second dielectric layer), which can cover the collector contact structure and the second source-drain structure. Then the second dummy gate structure in the second region can be removed to form the second gate structure. Then the second dielectric layer can be etched to expose the collector contact structure in the first region and the second source-drain structure in the second region, and a metal material can be deposited on the exposed collector contact structure and second source-drain structure to form the collector contact metal in the first region and the second source-drain metal in the second region.

[0121] In addition, in some embodiments, after the second gate structure is formed, an insulating material can be deposited on the second gate structure of the second region and the collector contact structure of the first region to form a third insulating layer, and then a second oxide layer can be formed on the third insulating layer to protect the collector contact structure in the first region and the second gate structure in the second region. When the second source-drain metal and the collector contact metal are formed by lithography, if there is a shift when the lithography is punched, it will also be punched on the insulating layer, preventing the gate metal from directly contacting the source-drain metal and reducing the requirements for lithography.

[0122] In some embodiments, after forming the collector contact metal in the first region and the second source / drain metal in the second region, a second metal interconnection layer can be formed by subsequent processes (such as interconnection line medium deposition, metal line formation, lead-out pad formation, etc.). Thus, the back surface structure of the BJT in the first region and the back surface transistor of the flip-chip stacked transistor in the second region are prepared.

[0123] In the embodiments of the present application, a first electrode structure is formed on the first region of the substrate, and a first transistor in the flip-chip stacked transistor is formed on the second region; the substrate is flipped and removed; a second electrode structure different from the ion doping type of the first electrode structure is formed on the first region, and a second transistor in the flip-chip stacked transistor is formed on the second region. The present application saves process steps and enhances the flexibility of semiconductor device circuit design by preparing a through-biased junction transistor compatible with the flip-chip stacked transistor process.

[0124] Further, the embodiments of the present application can improve the performance of the BJT in the following ways. For example, the area and doping concentration of the collector high-doped region can be increased to increase the effective collection area width, reduce the series resistance, and increase the maximum current density, but the breakdown voltage will be reduced. Alternatively, the doping concentration of the collector region around the base region can be reduced to reduce the collector junction parasitic capacitance and increase the early voltage (VA). Alternatively, the base region thickness can be reduced to reduce the base region transit time and improve the frequency of the device, but the base region doping concentration needs to be increased to prevent punch-through, which will reduce the VA and current gain. Therefore, a trade-off can be made among the frequency, VA, and current gain.

[0125] The preparation method of the semiconductor structure provided by the embodiments of the present application will be described below taking the fin-shaped structure as an example. Figure 2 FIG. 1 is a first top view of the semiconductor structure in the embodiments of the present application. Figure 2 (a) in FIG. 1 is a top view of the BJT, Figure 2 (b) in FIG. 1 is a top view of the flip-chip stacked transistor. For ease of understanding, the top view in (a) only shows the base region, the front surface structure of the BJT, the back surface structure of the BJT, the collector region, and the BJT region, and the top view in (b) only shows the fin-shaped structure, the gate structure, and the source / drain structure. Among them, the A-A' direction is the section direction of the BJT along the front surface structure of the BJT; the B-B' direction is the section direction of the BJT along the lateral BJT; the A1-A1' direction is the section direction of the stacked transistor along the source / drain structure; and the B1-B1' direction is the section direction of the flip-chip stacked transistor along the fin-shaped structure.

[0126] The first preparation process will be introduced first. Figures 3 to 14 FIG. 2 is a schematic diagram of the semiconductor structure in the first preparation process in the embodiments of the present application, Figures 3 to 14(a) in FIG. 1 is a structural schematic diagram of a BJT in a semiconductor structure in a first preparation process, Figures 3 to 14 (b) in FIG. 1 is a structural schematic diagram of a flip-chip stacked transistor in a semiconductor structure in a first preparation process, Figure 15 FIG. 1 is a first structural schematic diagram of a semiconductor structure in an embodiment of the present application, Figure 15 (a) in FIG. 1 is a first structural schematic diagram of a BJT in a semiconductor structure, Figure 15 (b) in FIG. 1 is a first structural schematic diagram of a flip-chip stacked transistor in a semiconductor structure.

[0127] In an example, the first preparation process of the semiconductor structure can include the following steps:

[0128] Step 1: Form a first photoresist layer 22 on the second region of the substrate 21, and perform ion doping with the first photoresist layer 22 as a mask, to obtain a structure as shown in FIG. 2. Figure 3

[0129] It can be understood that the first region of the substrate 21 is used to prepare the BJT, and the second region is used to prepare the flip-chip stacked transistor. First, the photoresist can be covered on the second region of the substrate 21 to form the first photoresist layer 22, and then the substrate 21 is ion doped with the first photoresist layer 22 as a mask. Since the first region is not covered with photoresist, a collector region 23 can be formed by low-doped deep well doping in the planar BJT region. For example, the type of ion doped in the collector region 23 can be P-type ion.

[0130] Step 2: Remove the first photoresist layer 22, and form a second photoresist layer 24 on the collector region, then etch the substrate 21 in the second region by using a standard process to form a fin structure 25, and then deposit an insulating material on the substrate 21 to form an isolation structure 26; deposit a semiconductor material on the isolation structure 26 to form a first pseudo-gate structure 27; form a first side wall 28 on both sides of the first pseudo-gate structure 27 and the first fin structure, to obtain a structure as shown in FIG. 3. Figure 4

[0131] It can be understood that the fin structure 25 includes a first fin structure 111 close to the substrate and a second fin structure 121 away from the substrate, and the isolation structure 26 wraps the second fin structure 121 and exposes the first fin structure 111.

[0132] Step 3: Form a first semiconductor structure 29 on the second region, to obtain a structure as shown in FIG. 4. Figure 5

[0133] ​​​It can be understood that the first fin structure in the source-drain region is etched to a preset height to form a first source-drain groove in the source-drain region, and then a strain material such as selectively epitaxially grown silicon germanium or silicon carbide is filled in the first source-drain groove to form the first semiconductor structure 29.

[0134] Step 4: remove the second photoresist layer 24, and form a collector contact region 30 in the first region and a first source-drain structure 112 in the first region by a heavy doping process, to obtain a structure as shown in Figure 6 .

[0135] It can be understood that after the second photoresist layer is removed, the collector contact region of the BJT is defined by lithography, and then ion doping is performed. For example, the type of ion doping can be P-type ions. Since the first region and the second region are simultaneously subjected to the doping process, the ion type of the collector contact region 30 and the first source-drain structure 112 in the first region is the same.

[0136] It should be noted that the ion type of the collector contact region 30 is the same as the ion type of the collector region 23 formed in the first step, and the ion concentration is different. The ion concentration of the collector contact region is higher than the ion concentration of the collector region.

[0137] Step 5: prepare the front surface transistor of the flip-chip stacked transistor in the second region and the first dielectric layer 31 and the collector contact metal 32 in the collector region of the BJT in the first region according to the standard process, to obtain a structure as shown in Figure 7 .

[0138] It can be understood that by depositing an interlayer dielectric on the first source-drain structure 112 and the collector contact region 30 formed in the previous step, a first interlayer dielectric layer 113 in the second region and a first dielectric layer 31 in the first region are formed, then the first dummy gate structure 27 in the second region is removed and a first gate structure 114 is formed, the first interlayer dielectric layer is etched and a metal material is deposited on the exposed first source-drain structure 112 to form a first source-drain metal 115, a part of the first dielectric layer 31 in the first region is lithographed, and a metal material is deposited at the position where the first dielectric layer 31 is etched to form a collector contact metal 32.

[0139] In addition, after the first gate structure is formed, the first gate structure 114 can be selectively etched to a preset height, and an insulating material is deposited on the etched first gate structure 114 to form a first insulating layer 33, and then a first oxide layer 34 is formed on the first insulating layer 33.

[0140] It should be noted that since the first dummy gate structure does not exist in the first region, the first gate structure does not exist in the first region at this step.

[0141] Step 6: Perform subsequent processes and deposit SiO2 to form a second oxide layer 35. Then, deposit SiCN on the second oxide layer 35 to form a second insulating layer 36, resulting in the desired product. Figure 8 The structure shown.

[0142] Figure 8 The first metal interconnect layer formed by subsequent processes is not shown in the figure.

[0143] Step 7: Above the second insulating layer 36, bond the carrier wafer 37 to the second insulating layer 36, then flip the wafer to obtain the following: Figure 9 The structure shown.

[0144] Step 8: Remove substrate 21 and thin the isolation structure 26 in the second region to expose the second fin structure, resulting in... Figure 10 The structure shown.

[0145] Step 9: Define the base region of the BJT on the second region using photolithography and perform ion doping to form base region 38, resulting in... Figure 11 The structure shown.

[0146] It is understandable that the doping concentration in the base region is higher than that in the collector region, and the ion types doped in the base region are opposite to those doped in the collector region.

[0147] Step 10: A third photoresist layer 39 is formed on the base region 38 of the first region, and then semiconductor material is deposited on the thinned isolation structure 26 to form a second dummy gate structure 40; second sidewalls 41 are formed on both sides of the second dummy gate structure 40 and the second fin structure, resulting in... Figure 12 The structure shown.

[0148] Step 11: Form the second source / drain structure 122 in the second region, to obtain... Figure 13 The structure shown.

[0149] Understandably, a first source / drain groove is formed in the source / drain region by etching the first fin-like structure within the source / drain region to a predetermined height. Then, a strain material such as silicon-germanium or silicon carbide is selectively epitaxially grown in the first source / drain groove, and a second source / drain structure 122 is formed on the strain material through a heavy doping process. The type of ions doped in the second source / drain structure 122 is opposite to the type of ions doped in the first source / drain structure 112.

[0150] Step 12: Remove the third photoresist layer 39, then form a fourth photoresist layer 42 on both the first and second regions. Define the emission region in the first region using photolithography, and remove the fourth photoresist layer on the emission region. Then form the emission region 43 by ion implantation, resulting in... Figure 14 The structure shown.

[0151] It can be understood that the emitter region is a small part of the base region, the ion type doped in the emitter region is opposite to the ion type doped in the base region, and the ion concentration is different, wherein the ion concentration doped in the emitter region is higher than the ion concentration doped in the base region.

[0152] Thirteenth step: removing the fourth photoresist layer 42, and then preparing the back surface transistor of the flip-chip stacked transistor in the second region according to the standard process, and preparing the second dielectric layer 44, the base contact metal 45, and the emitter contact metal 46 of the BJT in the first region, to obtain a structure as shown in FIG. 8. Figure 15

[0153] It can be understood that after removing the fifth photoresist layer, the second interlayer dielectric layer 123 in the first region and the second dielectric layer 44 in the first region are formed by depositing an interlayer dielectric on the second source-drain structure 122, the base region 38, and the emitter region 43, then the second dummy gate structure 40 in the second region is removed and the second gate structure 124 is formed, the second interlayer dielectric layer is etched and the metal material is deposited on the exposed second source-drain structure 122 to form the second source-drain metal 125. In the base region and the emitter region in the first region, a part of the first dielectric layer is photoetched, and the metal material is deposited at the position where the first dielectric layer is etched to form the base contact metal 45 and the emitter contact metal 46 of the base region, respectively.

[0154] In addition, after the second gate structure is formed, the second gate structure 124 can be selectively etched to a preset height, and an insulating material is deposited on the etched second gate structure 124 to form a third insulating layer 47, and then a third oxide layer 48 is formed on the third insulating layer 47.

[0155] In addition, after the third oxide layer is formed, a second metal interconnection layer can also be formed by subsequent processes, Figure 15 which is not shown in FIG. 8.

[0156] It should be noted that since the second dummy gate structure does not exist in the first region, the second gate structure also does not exist in the first region in this step.

[0157] For the Figure 15 ​(a), the emitter region 43 forms a PN junction with the base region 38, and the base region 38 forms a PN junction with the collector region 23. Moreover, the collector region includes a base region, and the base region includes two high-doped regions of different conductive types, i.e., a region of the base region connected with the base contact metal and a region of the emitter region connected with the emitter contact metal. The emitter contact metal in the back surface structure is connected with a high-doped region surrounded by the base region and having an ion doping type different from that of the base region. The base contact metal can be directly connected with the base region, or can be connected with a high-doped region surrounded by the base region and having an ion doping type same as that of the base region.

[0158] Figure 16 Fig. 4 is a second top view of a semiconductor structure according to an embodiment of the present application. Figure 16 Fig. 4(a) is a top view of a BJT according to an embodiment of the present application, Figure 16 Fig. 4(b) is a top view of a flip-chip stacked transistor according to an embodiment of the present application. Figure 17 Fig. 5 is a second structure diagram of a semiconductor structure according to an embodiment of the present application, Figure 17 Fig. 5(a) is a second structure diagram of a BJT in a semiconductor structure according to an embodiment of the present application, Figure 17 Fig. 5(b) is a second structure diagram of a flip-chip stacked transistor in a semiconductor structure according to an embodiment of the present application. Referring to the first preparation method, the preparation can be performed on a multi-fin device.

[0159] Figure 18 Fig. 6 is a third structure diagram of a semiconductor structure according to an embodiment of the present application, Figure 18 Fig. 6(a) is a third structure diagram of a BJT in a semiconductor structure according to an embodiment of the present application, Figure 18 Fig. 6(b) is a third structure diagram of a flip-chip stacked transistor in a semiconductor structure according to an embodiment of the present application. Referring to the first preparation method, the third preparation method is different from the first preparation method, i.e., the third preparation method is to first manufacture an N-type device and an N-type collector region on the front surface, and then manufacture a P-type device and a P-type base region and an N-type emitter region on the back surface. It should be noted that the ion type doped in the first step is N-type ion.

[0160] Figure 19 Fig. 7 is a fourth structure diagram of a semiconductor structure according to an embodiment of the present application, Figure 19 Fig. 7(a) is a fourth structure diagram of a BJT in a semiconductor structure according to an embodiment of the present application, Figure 16(b) in FIG. 1 is a fourth structure schematic diagram of the flip-chip stacked transistor in the semiconductor structure. In the preparation of the BJT, the base region and the emitter region are prepared on the front surface, and the collector region is prepared on the back surface. Referring to the first preparation method, different from the first preparation method, in the fourth preparation method, after the collector region is formed in the first step, the base region of the BJT is defined on the collector region by photolithography, and ion doping is performed to form the base region, then in the third step, the first source-drain structure after ion doping is formed at one time in the second region, according to step eleven, the emitter region is defined by photolithography, and the emitter region is formed by ion implantation, and then the base contact metal and the emitter contact metal are formed respectively. The second source-drain structure without ion doping is formed in the second region by redeveloping, and the collector contact region and the second source-drain structure are formed in the first region and the second region by ion implantation, and finally the collector contact metal is formed in the first region, and the back transistor is formed in the second region.

[0161] The embodiments of the present application can further propose a through BJT preparation scheme compatible with the process of the self-aligned flip-chip stacked transistor, which not only saves the process steps, but also enhances the flexibility of the FFET device circuit design.

[0162] It should be noted that the above is an example of a fin field effect transistor to introduce the structure of the semiconductor structure provided by the present application. The preparation method in the embodiments of the present application can also be applied to the stacking of various forms of transistors such as full-encircling gate transistors, planar transistors, vertical field effect transistors, and fork transistors, and the embodiments of the present application do not show the figure.

[0163] Further, the flip-chip stacked transistor provided by the embodiments of the present application can be detected by detection analysis instruments, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), and the like. Taking the TEM as an example, the embodiments of the present application can adopt the TEM sectioning method to detect the above semiconductor structure.

[0164] The embodiments of the present application provide a semiconductor device, which includes the semiconductor structure of the above embodiments. The specific limitations of the semiconductor structure can be referred to the semiconductor structure described above, which will not be repeated here.

[0165] The electronic device includes a circuit board and the semiconductor device according to the above embodiments, and the semiconductor device is arranged on the circuit board. The semiconductor device includes the semiconductor structure. The semiconductor structure is described above, and thus is not described here.

[0166] In the description of the embodiments of the present application, the description of the terms "one embodiment", "an embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the illustrative description of the above terms is not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the skilled person in the art can combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0167] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. The present application can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method comprises the following steps: forming a first electrode structure on a first region of a substrate and forming a first transistor in a flip-chip stacked transistor on a second region of the substrate, the first region and the second region being different regions of the substrate in a first direction; developing the first electrode structure and the first transistor and removing the substrate; forming a second electrode structure on the first region and forming a second transistor in the flip-chip stacked transistor on the second region, the ion doping type of the second electrode structure being different from that of the first electrode structure; wherein the first electrode structure is a base electrode structure, the second electrode is a collector electrode structure, or the first electrode structure is the collector electrode structure, and the second electrode structure is the base electrode structure; and forming an emitter electrode structure on a third region of the base electrode structure by ion doping, the ion doping type of the emitter electrode structure being different from that of the base electrode structure.

2. The method of claim 1, wherein, The method comprises the following steps: forming a first mask on the second region; forming a first electrode on the first region by ion doping; removing the first mask; forming a first electrode contact metal on the first electrode in the case of forming the first transistor based on the second region, the first electrode and the first electrode contact metal constituting the first electrode structure.

3. The method of claim 1, wherein, The method comprises the following steps: forming a second mask on the second region; forming a second electrode on the first region by ion doping, the ion doping type of the second electrode being different from that of the first electrode; removing the second mask; forming a second electrode contact metal on the second electrode in the case of forming the second transistor based on the second region, the second electrode and the second electrode contact metal constituting the second electrode structure.

4. The method of claim 2, wherein, In the case of the first electrode being a collector electrode, the method comprises the following steps: forming a third mask on the first region and etching the substrate in the second region to form an active structure, the active structure comprising a first active structure away from the substrate and a second active structure close to the substrate; forming a first semiconductor structure based on the first active structure; removing the third mask; forming a first source / drain structure in the second region by ion implantation and forming a collector contact structure on the collector electrode of the first region, the first source / drain structure being formed after ion implantation of the first semiconductor structure, and the ion concentration of the collector contact structure being higher than that of the collector electrode; forming a first gate structure and a first source / drain metal in the first transistor on the second region in sequence, and forming a collector contact metal on the collector contact structure of the first region.

5. The method of claim 4, wherein, The forming the first gate structure and the first source-drain metal in the first transistor on the second region in sequence comprises: forming a first dielectric layer on the first source-drain structure and the collector contact structure; forming the first gate structure based on the first active structure; etching the first dielectric layer to form the first source-drain metal on the first source-drain structure and the collector contact metal on the collector contact structure.

6. The method of claim 3, wherein, In the case that the second pole is a base pole, the forming the second pole contact metal on the second pole based on the second region comprises: forming a fourth mask on the first region and forming a second source-drain structure based on a second active structure on the second region; forming the fourth mask on the second region and etching the fourth mask on the first region to expose a region where the emitter is located; forming the emitter on the first region by ion implantation; removing the fourth mask; The forming the second gate structure and the second source-drain metal in the second transistor on the second region in sequence, the base pole contact metal on the base pole of the first region, and the emitter pole contact metal on the emitter pole comprises:

7. The method of claim 6, wherein, forming a second dielectric layer on the second source-drain structure, the base pole and the emitter pole; forming the second gate structure based on the second active structure; etching the second dielectric layer to form the second source-drain metal on the second source-drain structure, the base pole contact metal on the base pole, and the emitter pole contact metal on the emitter pole. In the case that the first pole structure is a base pole structure, the forming the first pole on the first region by ion doping comprises:

8. The method of claim 2, wherein, forming a collector pole on the first region by ion doping; forming a base pole on the collector pole by ion doping, the ion doping type of the base pole being different from the ion doping type of the collector pole. In the case that the first pole is a base pole, the forming the first pole contact metal on the first pole based on the second region comprises:

9. The method of claim 2, wherein, forming a fifth mask on the first region and etching the substrate in the second region to form an active structure, the active structure comprising a first active structure away from the substrate and a second active structure close to the substrate; forming a first source-drain structure based on the first active structure, the ion doping type in the first source-drain structure being the same as the ion doping type of the base pole structure; forming the fifth mask on the second region and etching the fifth mask on the first region to expose a region where the emitter is located; forming the emitter on the first region by ion implantation; removing the fifth mask; ​ forming a base contact metal on the base of the first region and an emitter contact metal on the emitter while forming a first gate structure and a first source-drain metal of the first transistor on the second region in sequence.

10. The method of claim 3, wherein, In the case that the second pole is a collector, forming a second pole contact metal on the second pole in the case that the second transistor is formed based on the second region, comprising: forming a sixth mask on the first region, and forming a second semiconductor structure based on a second active structure on the second region; removing the sixth mask; forming a second source-drain structure on the second region by ion implantation, and forming a collector contact structure on the collector of the first region, the second source-drain structure being formed after ion implantation of the second semiconductor structure, and the ion concentration of the collector contact structure being higher than that of the collector; forming a second gate structure and a second source-drain metal of the second transistor on the second region in sequence while forming a collector contact metal on the collector contact structure of the first region.

11. A semiconductor structure produced using the production method according to any one of claims 1 to 10, characterized in that, comprising: flip-chip stacked transistors and bipolar junction transistors located in different regions, the flip-chip stacked transistors and the bipolar junction transistors being formed simultaneously; wherein the flip-chip stacked transistors comprise a first transistor and a second transistor arranged oppositely, and the bipolar junction transistor comprises a collector structure, a base structure and an emitter structure, the collector structure being arranged oppositely to the base structure and the emitter structure.

12. A semiconductor device, characterized by comprising: comprising: the semiconductor structure of claim 11.

13. An electronic device, comprising: comprising: a circuit board and the semiconductor device of claim 12, the semiconductor device being disposed on the circuit board.

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