Display panel and display device

Abstract

The embodiment of the invention discloses a display panel and a display device. The display panel comprises a substrate base plate; the first transistor and the second transistor are formed on the substrate, the first transistor comprises a first active layer, a first grid electrode, a first source electrode and a first drain electrode, and the first active layer comprises silicon; the second transistor comprises a second active layer, a second grid electrode, a second source electrode and a second drain electrode, and the second active layer comprises an oxide semiconductor; the second active layer is located on the side, away from the substrate, of the first active layer; in the direction perpendicular to the substrate, the distance between the first grid electrode and the first active layer is D1, the distance between the second grid electrode and the second active layer is D2, and D1 is smaller than D2; the display panel comprises a pixel circuit and a driving circuit providing driving signals for the pixel circuit, the driving circuit comprises a second transistor, and the pixel circuit comprises a first transistor or the driving circuit comprises the first transistor.

Description

[0001] This application is a divisional application of a patent for display panel and display device, with application date of December 30, 2020, application number: 202011613598.3, and invention name: Technical Field

[0002] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] With the continuous development of science and technology, more and more electronic devices with display functions are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable and important tool for people today.

[0004] The display panel is an important component for electronic devices to realize the display function. The display panel generally includes a pixel circuit and a driving circuit that provides a driving signal for the pixel circuit. Transistors are provided in both the pixel circuit and the driving circuit. The transistors often use indium gallium zinc oxide (IGZO) as an active layer to reduce leakage in the transistor. However, since the indium gallium zinc oxide material is more sensitive to hydrogen elements, water and oxygen content in the external environment, when the transistors in the pixel circuit and / or the driving circuit use IGZO material as the active layer, the IGZO active layer may be corroded by hydrogen elements and water and oxygen in the organic film layer in the display panel, affecting the performance of the IGZO transistor, and then affecting the performance of the driving circuit and / or the pixel circuit. Summary of the invention

[0005] In view of this, embodiments of the present invention provide a display panel and a display device to solve the problem in the prior art that the performance of IGZO transistors is affected, thereby affecting the performance of driving circuits and / or pixel circuits.

[0006] An embodiment of the present invention provides a display panel, the display panel comprising

[0007] substrate substrate;

[0008] a first transistor and a second transistor, wherein the first transistor and the second transistor are formed on the substrate, the first transistor comprises a first active layer, a first gate, a first source and a first drain, the first active layer comprises silicon; the second transistor comprises a second active layer, a second gate, a second source and a second drain, the second active layer comprises an oxide semiconductor; the second active layer is located on a side of the first active layer away from the substrate;

[0009] In a direction perpendicular to the substrate, a distance between the first gate and the first active layer is D1, and a distance between the second gate and the second active layer is D2, wherein D1<D2;

[0010] The display panel includes a pixel circuit and a driving circuit providing a driving signal to the pixel circuit, wherein the driving circuit includes the second transistor and the pixel circuit includes the first transistor or the driving circuit includes the first transistor.

[0011] Another aspect of an embodiment of the present invention further provides a display device, which includes the above-mentioned display panel.

[0012] The display panel provided by the embodiment of the present invention includes a first transistor and a second transistor, the first active layer of the first transistor includes silicon, the second active layer of the second transistor includes an oxide semiconductor, and the second active layer is located on the side of the first active layer away from the substrate. By setting the distance between the first gate and the first active layer to be smaller than the distance between the second gate and the second active layer, the second active layer can be protected to prevent hydrogen elements and water oxygen from corroding the second active layer, thereby ensuring good performance of the second transistor; at the same time, the carrier migration performance in the first transistor is ensured, thereby ensuring good performance of the first transistor, thereby achieving the effect of improving the performance of the driving circuit and the performance of the pixel circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0014] Figure 1 is a schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention;

[0015] Figure 2 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0016] Figure 3 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0017] Figure 4 is a structural schematic diagram of a scan drive unit provided by an embodiment of the present invention;

[0018] Figure 5 is a schematic structural diagram comparing the first active layer and the second active layer provided by an embodiment of the present invention;

[0019] Figure 6 is a schematic structural diagram comparing the first active layer and the second active layer provided by an embodiment of the present invention;

[0020] Figure 7 is a schematic diagram of a film layer structure of another display panel provided by an embodiment of the present invention;

[0021] Figure 8 is a schematic diagram of a film layer structure of another display panel provided by an embodiment of the present invention;

[0022] Fig. 9 is a schematic diagram of a film layer structure of another display panel provided by an embodiment of the present invention;

[0023] Fig.10 is a schematic diagram of a film layer structure of another display panel provided by an embodiment of the present invention;

[0024] Fig.11 is a schematic diagram of a film layer structure of another display panel provided by an embodiment of the present invention;

[0025] Fig.12 is a schematic diagram of a film layer structure of another display panel provided by an embodiment of the present invention;

[0026] Fig.13 is a schematic diagram of a film layer structure of another display panel provided by an embodiment of the present invention;

[0027] Fig.14 is a schematic diagram of a film layer structure of another display panel provided by an embodiment of the present invention;

[0028] Fig.15 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0030] Figure 1 is a schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention, such as Figure 1 As shown, the display panel 100 provided by the embodiment of the present invention includes a base substrate 10; a first transistor 20 and a second transistor 30, the first transistor 20 and the second transistor 30 are formed on the base substrate 10, the first transistor 20 includes a first active layer 21, a first gate 22, a first source 23 and a first drain 24, and the first active layer 21 includes silicon; the second transistor 30 includes a second active layer 31, a second gate 32, a second source 33 and a second drain 34, and the second active layer 31 includes an oxide semiconductor; the second active layer 31 is located on the side of the first active layer 21 away from the base substrate 10. Among them, Figure 1The first transistor 20 and the second transistor 30 in the figure are both top-gate transistors, that is, the first gate 22 is located on the side of the first active layer 21 away from the substrate 10, and the second gate 32 is located on the side of the second active layer 31 away from the substrate 10. In addition, Figure 1 The first source 23 and the first drain 24 in the first transistor 20 and the second source 33 and the second drain 34 in the second transistor 30 are located in the same film layer, that is, the first source 23, the first drain 24, the second source 33 and the second drain 34 are prepared by the same process, so that the process steps can be simplified and the preparation efficiency of the display panel can be improved. However, it can be understood that the specific film layer position relationship of the first transistor 20 and the second transistor 30 is not limited to Figure 1 As shown, those skilled in the art can make settings according to actual conditions.

[0031] In a direction perpendicular to the base substrate 10, the distance between the first gate 22 and the first active layer 21 is D1, and the distance between the second gate 32 and the second active layer 31 is D2, wherein D1<D2; the display panel 100 includes a pixel circuit ( Figure 1 ) and a driving circuit 40 for providing a driving signal to the pixel circuit, wherein the driving circuit 40 includes a second transistor 30, and the pixel circuit includes a first transistor 20 or the driving circuit 40 includes the first transistor 20. Figure 1 Take the driving circuit 40 including the first transistor 20 as an example.

[0032] It should be noted that in the present application, the first transistor 20 and the second transistor 30 can be transistors in a driving circuit, that is, the driving circuit 40 includes the first transistor 20 or the second transistor 30; in addition, the first transistor 20 and the second transistor 30 can also be transistors in a pixel circuit, that is, the pixel circuit includes the first transistor 20 or the second transistor 30. If the second transistor 30 is located in the pixel circuit, it can be a driving transistor or a switching transistor.

[0033] For example, Figure 2 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention, such as Figure 2 As shown, the display panel 100 includes a display area AA and a non-display area NAA, and the non-display area NAA is located on at least one side of the display area AA. Figure 2 The non-display area NAA is located on one side of the display area AA. The display area AA includes a plurality of sub-pixels 101 arranged in an array; it also includes a scan line 102 and a data line 103, and the scan line 102 and the data line 103 intersect to define the plurality of sub-pixels 101, wherein each sub-pixel 101 includes a pixel circuit ( Figure 2The non-display area NAA is used to set a driving circuit 40, wherein the driving circuit 40 may include at least one of a scanning driving circuit or a light emitting control driving circuit. Figure 2 Take the drive circuit 40 as a scan drive circuit 104 as an example. Figure 2 As shown, the scan driving circuit 104 includes a plurality of cascaded scan driving units 105. When the display panel 100 displays a frame of an image, the plurality of cascaded scan driving units 105 sequentially input corresponding scan signals to each scan line 102 of the display panel 100, so that the data signal can be written into the corresponding sub-pixel 101 of the display area AA through the corresponding data line 103.

[0034] It should be noted that the specific structure of the driving circuit 40 can be set according to the structure in the pixel circuit. For example, the pixel circuit may include a 2T1C pixel circuit or a 7T1C pixel circuit, etc., which is not limited in this embodiment. When the pixel circuit includes a 2T1C pixel circuit, the driving circuit 40 may, for example, only include a scanning driving circuit, and there is no need to set a light-emitting control driving circuit. When the pixel circuit is a 7T1C pixel circuit, the driving circuit 40 may, for example, include a scanning driving circuit, and may also include a light-emitting control driving circuit, etc. Exemplarily, Figure 3 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention. Figure 3 As shown, when the pixel circuit is a 7T1C pixel circuit, the pixel circuit includes a light-emitting control transistor (M1 and M6), a data writing transistor M2, a driving transistor M3, a threshold compensation transistor M4, a reset transistor (M5 and M7) and a storage capacitor Cst. At this time, the driving circuit 40 may include a scanning driving circuit and a light-emitting control driving circuit. The driving signal provided by the driving circuit 40 to the pixel circuit may include, for example, a light-emitting control signal Emit (output of the light-emitting control driving circuit) and scanning signals S1 and S2 (output of the scanning driving circuit), wherein the light-emitting control signal Emit controls the light-emitting control transistor (M1 and M6) to be turned on or off; the scanning signal S1 controls the reset transistor (M5 and M7) to be turned on or off, and the scanning signal S2 controls the data writing transistor M2 and the threshold compensation transistor M4 to be turned on or off. Figure 3The driving process of the pixel circuit driving the light-emitting element 50 is, for example: in the reset stage, the scanning signal S1 provided by the driving circuit 40 turns on the reset transistor (M5 and M7) in the pixel circuit to reset the N1 node and the anode of the light-emitting element 50; in the data writing stage, the driving circuit 40 provides the scanning signal S2 to turn on the data writing transistor M2 and the threshold compensation transistor M4 in the pixel circuit, at which time the data signal Vdata can write the data voltage into the storage capacitor Cst; in the light-emitting stage, the light-emitting control signal Emit provided by the driving circuit 40 turns on the light-emitting control transistor (M1 and M6) in the pixel circuit, thereby driving the light-emitting element 50 to emit light through the driving transistor M3.

[0035] The scanning driving circuit and / or the light emitting control driving circuit in the driving circuit 40 may include, for example, a plurality of transistors, and the conduction or cut-off of the internal transistors thereof may be controlled by corresponding signals, such as clock signals, to output corresponding light emitting control signals Emit and / or scanning signals S1 and S2. The specific structure of the driving circuit 40 is not limited in this embodiment either.

[0036] In the present embodiment, the first active layer 21 in the first transistor 20 comprises silicon, which may be polysilicon, that is, the first active layer 21 is a polysilicon active layer, for example, a low temperature polysilicon (LTPS) active layer. The second active layer 31 in the second transistor 30 comprises an oxide semiconductor, that is, the second active layer 31 is an oxide semiconductor active layer, for example, an IGZO active layer. Low temperature polysilicon thin film transistors have the advantages of high carrier mobility, fast response, and low power consumption, and oxide semiconductor thin film transistors have the advantage of low leakage current. When the driving circuit 40 comprises the first transistor 20 and the second transistor 30, the driving circuit 40 takes into account the advantages of high carrier mobility, fast response, low power consumption, and low leakage current, thereby ensuring that the driving circuit 40 has good performance and improving the display performance of the display panel 100.

[0037] Furthermore, in the present embodiment, the distance D1 between the first gate 22 and the first active layer 21 is smaller than the distance D2 between the second gate 32 and the second active layer 31. On the one hand, by setting the distance between the second gate 32 and the second active layer 31 to be larger, that is, the thickness of the insulating layer between the second gate 32 and the second active layer 31 is thicker, so as to fully protect the second active layer 31 and prevent the hydrogen element and water oxygen in the organic film layer on the side of the second active layer 31 away from the substrate 10 from corroding the second active layer 31; on the other hand, by setting the distance between the first gate 22 and the first active layer 21 to be smaller, the migration rate of the carriers in the first transistor 20 is increased, thereby providing the response speed of the first transistor 20. That is to say, in this embodiment, by setting the distance between the first gate 22 and the first active layer 21 to be smaller than the distance between the second gate 32 and the second active layer 31, the second active layer 31 of the second transistor 30 can be fully protected so that the performance of the second transistor 20 is good; at the same time, the carrier migration performance in the first transistor 20 is guaranteed; in this way, when the driving circuit includes the first transistor 20 and the second transistor 30, the driving circuit 40 is guaranteed to have good performance; when the pixel circuit includes the first transistor 20, the pixel circuit is guaranteed to have good performance.

[0038] In summary, the display panel provided in this embodiment includes a first transistor and a second transistor, the first active layer of the first transistor includes silicon, the second active layer of the second transistor includes an oxide semiconductor, and the second active layer is located on the side of the first active layer away from the substrate. By setting the distance between the first gate and the first active layer to be smaller than the distance between the second gate and the second active layer, the second active layer can be protected to prevent hydrogen elements and water oxygen from corroding the second active layer, thereby ensuring the good performance of the second transistor; at the same time, the carrier migration performance in the first transistor is guaranteed, thereby ensuring the good performance of the first transistor, thereby achieving the effect of improving the performance of the driving circuit and the pixel circuit.

[0039] The specific structure of the driving circuit in the above content is not limited. However, in actual settings, the specific structure of the driving circuit can be multiple. The working principles of driving circuits with different structures are slightly different. The following is an explanation of a typical example. It should be noted that the following content does not limit the present application.

[0040] Optionally, the driving circuit includes an input module, a logic transmission module and an output module, the input module is connected between the input end and the logic transmission module, and the output module is connected between the logic transmission module and the output end; the logic transmission module is connected to the high-level signal end or the low-level signal end, and the output end is connected to the pixel circuit; wherein the logic transmission module includes a second transistor or the input module includes a second transistor, and the output module includes a first transistor.

[0041] As can be seen from the foregoing, the driving circuit may be a scanning driving circuit that provides a scanning signal to a pixel circuit, or a light-emitting control driving circuit that provides a light-emitting control signal to a pixel circuit, or a general term for a scanning driving circuit that provides a scanning signal to a pixel circuit and a light-emitting control driving circuit that provides a light-emitting control signal to a pixel circuit, and this embodiment does not limit this. The following will take the driving circuit as an example of a scanning driving circuit as an example to briefly introduce the driving process of the driving circuit.

[0042] For example, Figure 4 is a schematic diagram of the structure of a scanning driving unit provided by an embodiment of the present invention, see Figure 2 and Figure 4The drive circuit 40 includes a scan drive circuit 104, and the scan drive circuit 104 includes a plurality of cascaded scan drive units 105. The scan drive unit 105 includes an input module 41, a logic transmission module 42, and an output module 43. The input module 41 is composed of two transmission gates 111 and 112 to control the transmission of the signal of the forward scan input terminal IN1 or the reverse scan input terminal IN2 to the logic transmission module 42 according to the forward scan enable signal of the forward scan enable terminal EN1 and the reverse scan enable signal of the reverse scan enable terminal EN2. The logic transmission module 42 may include, for example, a shift unit 421 and a NAND gate circuit 422. The shift unit 421 is composed of a first inverter 121, a second inverter 124, a first clock inverter 122, a second clock inverter 123, and a reset unit 125. The input end of the first inverter 121 is electrically connected to the first clock signal terminal CK1, and the output end of the first inverter 121 is electrically connected to the control end of the first clock inverter 122 and the control end of the second clock inverter 123 respectively; the input end of the first clock inverter 122 is electrically connected to the input module 41, and receives the signal of the forward scanning input terminal IN1 or the reverse scanning input terminal IN2 input by the input module 41; the output end of the first clock inverter 122 is electrically connected to the input end of the second inverter 124, and the clock end of the first clock inverter 122 is electrically connected to the first clock signal terminal CK1; the input end of the second clock inverter 123 is electrically connected to the output end of the second inverter 124, the clock end of the second clock inverter 123 is electrically connected to the first clock signal terminal CK1, and the output end of the second clock inverter 123 is electrically connected to the input end of the second inverter 124; the output end of the second inverter 124 is also electrically connected to the output module 13 and the shift signal output terminal Next.The first inverter 121 is composed of a transistor M11 and a transistor M12, and when the first clock signal received at the first clock signal terminal CK1 is at a low level, the first electrode of the transistor M11 receives a first level signal at the first level signal terminal VGH, and when the first clock signal received at the first clock signal terminal CK1 is at a high level, the first electrode of the transistor M12 receives a second level signal at the second level signal terminal VGL; the first clock inverter 122 is composed of transistors M13, M14, M15 and M16, and when the first clock signal received at the first clock signal terminal CK1 is at a high level, the first clock inverter 122 is composed of transistors M13, M14, M15 and M16, and when the first clock signal received at the first clock signal terminal CK1 is at a low level, the first electrode of the transistor M11 receives a first level signal at the first level signal terminal VGH, and when the first clock signal received at the first clock signal terminal CK1 is at a high level, the first clock inverter 122 is composed of transistors M13, M14, M15 and M16, and when the first clock signal received at the first clock signal terminal CK1 is at a high level, the first clock inverter 122 is composed of transistors M13, M14, M15 and M16, and when the first clock signal received at the first clock signal terminal CK1 is at a high level, the first electrode of the transistor M12 receives a second level signal at the second level signal terminal VGL ... When the clock signal is at a high level and the input module 41 inputs a high level signal, the first electrode of the output transistor M16 receives the second level signal of the second level signal terminal VGL, and when the input module 41 inputs a low level signal and the first inverter 121 outputs a second level signal, the first electrode of the output transistor M13 receives the first level signal of the first level signal terminal VGH; the second clock inverter 123 is composed of transistors M17, M18, M19 and M110, and the first clock signal received at the first clock signal terminal CK1 is at a low level and the second inverter 1 When the first inverter 121 outputs a first level signal and the second inverter 124 outputs a high level signal, the first electrode of the output transistor M110 receives a first level signal of the first level signal terminal VGL; when the first inverter 121 outputs a first level signal and the second inverter 124 outputs a high level signal, the first electrode of the output transistor M110 receives a second level signal of the second level signal terminal VGL; the second inverter 124 is composed of transistors M111 and M112, and when a high level signal is input to the input terminal of the second inverter 124, the first electrode of the output transistor M112 receives a second level signal of the second level signal terminal VGL; When a low level signal is input to the input terminal of the second inverter 124, the first electrode of the output transistor M111 receives the first level signal of the first level signal terminal VGH; the control terminal of the reset unit 125 is electrically connected to the reset signal input terminal Rest, the input terminal of the reset unit 125 is electrically connected to the first level signal terminal VGH, the output terminal of the reset unit 125 is electrically connected to the input terminal of the second inverter 124, and the reset unit 125 is composed of a transistor M113 to reset the signal at the input terminal of the second inverter 124 according to the reset signal of the reset signal input terminal Rest. The NAND gate circuit 422 is composed of transistors M21, M22, M23 and M24, and realizes the NAND function of the second clock signal of the second clock signal terminal CK2 and the shift signal output by the shift unit 421; the output module 43 is composed of three inverters composed of transistors M25, M26, M27, M28, M29 and M210, so as to transmit the signal output by the NAND gate circuit 422 to the scanning signal output terminal OUT, and realize the output of the scanning signal. By the above content and. Figure 4It can be seen that no matter the input module 41, the logic transmission module 42, or the output module 43, they are all composed of a plurality of transistors. In this embodiment, at least one of the transistors in the input module 41 or the logic transmission module 42 is a second transistor. Since the distance between the second gate and the second active layer of the second transistor is large, that is, the thickness of the insulating layer between the second gate and the second active layer is thick, the second active layer is fully protected, and at the same time, the transistor has a lower leakage current in the off state, thereby avoiding the influence of the high and low levels after the logic transmission due to the transistor leakage current, which affects the normal transmission of the next node signal. And at least one of the transistors in the output module 43 is a first transistor. Since the distance between the first gate and the first active layer of the first transistor is small, the transistor in the output module 43 has a faster response speed and driving ability, thereby ensuring the response and driving ability of the driving circuit, and avoiding the display panel from generating signal hysteresis due to the driving circuit. In other words, by setting at least one of the transistors in the input module 41 or the logic transmission module 42 as a second transistor, and at least one of the transistors in the output module 43 as a first transistor, the performance of the driving circuit 40 can be improved.

[0043] Optionally, the width of the channel region of the first transistor 20 is W1, and the width of the channel region of the second transistor 30 is W2; the length of the channel region of the second transistor 20 is L1, and the length of the channel region of the second transistor 30 is L2; ​​the width-to-length ratio of the first transistor 20 is R1=W1 / L1, and the width-to-length ratio of the second transistor 30 is R2=W2 / L2, and R1 / R2≥D1 / D2.

[0044] For example, Figure 5 is a schematic diagram of a top view structure comparing the first active layer and the second active layer provided in an embodiment of the present invention, such as Figure 5As shown, the first active layer 21 of the first transistor 20 includes a source region 211, a drain region 212 and a channel region 213. The source region 211 of the first active layer 21 is used to set the first source electrode 23, the drain region 212 of the first active layer 21 is used to set the first drain electrode 24, and the overlapping portion of the first gate 22 and the first active layer 21 is the channel region 213 of the first active layer 21, wherein the width of the channel region 213 of the first transistor 20 is W1, the length is L1, and the width-to-length ratio of the channel region 213 of the first transistor 20 is R1=W1 / L1. The second active layer 31 of the second transistor 30 includes a source region 311, a drain region 312 and a channel region 313. The source region 311 of the second active layer 31 is used to set the second source electrode 33. The drain region 312 of the second active layer 31 is used to set the second drain electrode 34. The overlapping portion of the second gate 32 and the second active layer 31 is the channel region 313 of the second active layer 31. The width of the channel region 213 of the second transistor 30 is W2, and the length is L2. The width-to-length ratio of the channel region 213 of the second transistor 30 is R2=W2 / L2. By setting the ratio of the width-to-length ratio of the channel region 213 in the first transistor 20 to the width-to-length ratio of the channel region 313 in the second transistor 30 to be greater than the ratio of the distance D1 between the first gate 22 and the first active layer 21 to the distance D2 between the second gate 32 and the second active layer 32, that is, the width-to-length ratio of the channel region 213 of the first transistor 20 is larger, that is, the width of the channel region 213 of the first transistor 20 is wider, thereby increasing the mobility of carriers in the first transistor 20, and further improving the response speed of the first transistor 20.

[0045] It should be noted that, in order to clearly compare the width W1 and length L1 of the channel region 213 of the first active layer 21 of the first transistor 20 with the width W2 and length L2 of the channel region 213 of the second active layer 31 of the second transistor 30, Figure 5 The first active layer 21 and the second active layer 31 are only exemplarily shown as rectangular shapes, but in actual configuration, the shapes of the first active layer 21 and the second active layer 31 are configured according to the actual situation. The following embodiments are the same and will not be described in detail.

[0046] Optional, Figure 6 is a schematic diagram of a top view structure comparing a first active layer and a second active layer provided by an embodiment of the present invention, such as Figure 6As shown, the width of the channel region 213 of the first transistor 20 is W1, and the width of the channel region 213 of the second transistor 30 is W2; the length of the channel region 313 of the second transistor 30 is L1, and the length of the channel region 313 of the second transistor 30 is L2, wherein W1 / L1≤W2 / L2. The advantage of such a setting is that the carrier migration rate of the second transistor 30 is improved, and the response speed of the second transistor 30 is improved, so that the second transistor 30 can not only prevent the hydrogen element and water oxygen in the organic film layer on the side of the second active layer 32 away from the substrate 10 from corroding the second active layer 31, improve the performance of the second transistor 30, but also ensure the response speed of the second transistor 30.

[0047] On the basis of the above scheme, optional, continue to refer to Figure 4 and Figure 6 , the width-to-length ratio of the first transistor is R1=W1 / L1, the width-to-length ratio of the second transistor is R2=W2 / L2, R1 / R2≤D1 / D2; the driving circuit 40 includes an input module 41, a logic transmission module 42 and an output module 43, the input module 41 is connected between the input end and the logic transmission module 42, and the output module 43 is connected between the logic transmission module 42 and the output end; the logic transmission module 42 is connected to the high-level signal end or the low-level signal end, and the output end is connected to the pixel circuit 60; wherein the output module 43 includes a second transistor 30.

[0048] In this embodiment, by setting the ratio of the width-to-length ratio of the channel region 213 in the first transistor 20 to the width-to-length ratio of the channel region 313 in the second transistor 30 to be smaller than the ratio of the spacing D1 between the first gate 22 and the first active layer 21 to the spacing D2 between the second gate 32 and the second active layer 32, that is, the width of the channel region 213 of the second transistor 30 is wider, thereby increasing the migration rate of carriers in the second transistor 30, and thereby increasing the response speed of the second transistor 30. In this way, when the output module 43 includes the second transistor 30, it can also be ensured that the output module 43 has a faster response speed and driving capability, thereby ensuring the response and driving capability of the driving circuit, and avoiding problems such as signal delay of the display panel due to the driving circuit.

[0049] It should be noted that the width and length of the channel region mentioned above and appearing later, where the length of the channel region refers to the dimension in the direction in which the carriers in the channel region migrate between the source and the drain, if this direction is defined as the second direction, then the width of the channel region refers to the dimension of the channel region in the third direction, where the second direction may be perpendicular to the third direction.

[0050] Optional, Figure 7 is a schematic diagram of a film layer structure of another display panel provided by an embodiment of the present invention, such as Figure 7As shown, the pixel circuit 60 includes a third transistor 70, the third transistor 70 includes a third active layer 71, a third gate 72, a third source 73 and a third drain 74, and the third active layer 71 includes an oxide semiconductor; wherein, in a direction perpendicular to the substrate 10, the distance between the third gate 72 and the third active layer 71 is D3, wherein D1<D3. Figure 3 The pixel circuit 60 including the first transistor 20 is taken as an example for description.

[0051] For example, Figure 7 As shown, the display panel 100 includes a display area AA and a non-display area NAA, the driving circuit 40 is located in the non-display area NAA, and the pixel circuit 60 is located in the display area AA. The pixel circuit 60 includes a first transistor 20 and a third transistor 70, and the third active layer 71 in the third transistor 70 includes an oxide semiconductor, that is, the third active layer 71 is an oxide semiconductor active layer, for example, an IGZO active layer. The leakage current of the oxide semiconductor thin film transistor is very small, which can ensure that the leakage current is small during the operation of the pixel circuit 60; and because the first active layer 21 in the first transistor 20 contains silicon, it can be selected as polycrystalline silicon, that is, the first active layer 21 is a polycrystalline silicon active layer, for example, a low-temperature polycrystalline silicon (Low Temperature Poly-Silicon, LTPS) active layer, and the low-temperature polycrystalline silicon thin film transistor has the advantages of high carrier mobility, fast response, and low power consumption. Therefore, when the pixel circuit 60 includes the first transistor 20 and the third transistor 70, the pixel circuit 60 takes into account the advantages of high carrier mobility, fast response, low power consumption and low leakage current, thereby ensuring that the pixel circuit 60 has good performance and improving the display performance of the display panel 100. In addition, in this embodiment, not only the second transistor 30 in the driving circuit 40 is set as an oxide semiconductor transistor, but the third transistor 70 in the pixel circuit 60 is also set as an oxide semiconductor transistor. In this way, the leakage current in the working process of the driving circuit 40 and the pixel circuit 60 is ensured to be small, thereby making the performance of the driving circuit 40 and the pixel circuit 60 good, further improving the display performance of the display panel 100.

[0052] Furthermore, this embodiment also sets the distance D1 between the first gate 22 and the first active layer 21 to be smaller than the distance D3 between the third gate 72 and the third active layer 71. On the one hand, by setting the distance between the third gate 72 and the third active layer 71 to be larger, that is, the thickness of the insulating layer between the third gate 72 and the third active layer 71 is thicker, so as to fully protect the third active layer 71 and prevent the hydrogen element and water oxygen in the organic film layer on the side of the third active layer 71 away from the substrate 10 from corroding the third active layer 71; on the other hand, by setting the distance between the first gate 22 and the first active layer 21 to be smaller, the migration rate of the carriers in the first transistor 20 is increased, thereby providing the response speed of the first transistor 20. That is to say, in this embodiment, by setting the distance between the first gate 22 and the first active layer 21 to be smaller than the distance between the third gate 72 and the third active layer 71, the third active layer 71 of the third transistor 70 can be fully protected so that the performance of the third transistor 70 is good; at the same time, the carrier migration performance in the first transistor 20 is guaranteed; in this way, when the pixel circuit 60 includes the first transistor 20 and the third transistor 70, the performance of the pixel circuit 60 is guaranteed.

[0053] It should be noted that the third gate 72 can be arranged in the same layer as the second gate 32, and the second active layer 31 and the third active layer 71 can be arranged in the same layer. In this case, the distance D2 between the second gate 32 and the second active layer 31 and the distance D3 between the third gate 72 and the third active layer 31 are the same; or, the third gate 72 and the second gate 32 and the second active layer 31 and the third active layer 71 are all located in different film layers. When the third gate 72 can be arranged in the same layer as the second gate 32, and the second active layer 31 and the third active layer 71 are arranged in the same layer, the process steps can be simplified, wherein, Figure 7 The third gate electrode 72 is provided in the same layer as the second gate electrode 32, and the second active layer 31 is provided in the same layer as the third active layer 71. In addition, in this embodiment, the third source electrode 73 and the third drain electrode 74 in the third transistor 70 are provided in the same layer as the second source electrode 33 and the second drain electrode 34 in the second transistor 30, and the first source electrode 23 and the first drain electrode 24 in the first transistor 20, so that the process steps can be simplified and the manufacturing efficiency of the display panel can be improved.

[0054] Figure 8 is a schematic diagram of a film layer structure of another display panel provided by an embodiment of the present invention. Based on the above solution, optionally, Figure 8 As shown, the third transistor 70 is a switch transistor of the pixel circuit 60, wherein D2≤D3.

[0055] Generally speaking, in a pixel circuit, the transistor whose gate is connected to the scanning signal or the light-emitting control signal is a switching transistor, and the transistor other than the switching transistor in the pixel circuit is a driving transistor. The driving transistor is arranged in series on the transmission path of the first power signal (PVDD signal) and the second power signal (PVEE signal), and the data signal is written into the gate of the driving transistor. As the data signal is written, the gate potential of the driving transistor changes.

[0056] Still taking the pixel circuit as 7T1C pixel circuit as an example, continue to refer to Figure 3 , the 7T1C pixel circuit includes a light emission control transistor (M1 and M6), a data writing transistor M2, a driving transistor M3, a threshold compensation transistor M4, a reset transistor (M5 and M7) and a storage capacitor Cst. Among them, other transistors except the driving transistor M3, such as the light emission control transistor (M1 and M6), the data writing transistor M2, the threshold compensation transistor M4, and the reset transistor (M5 and M7) are all switch transistors.

[0057] The pixel circuit 60 is sometimes applied to the low-frequency driving mode. When the pixel circuit 60 is applied to the low-frequency driving mode, the switching transistor in the pixel circuit 60 is turned off for a longer time, while the transistor in the driving circuit 40 is turned on more frequently. Figure 8 By setting the distance D3 between the third gate 72 in the third transistor 70 and the third active layer 31 to be greater than or equal to the distance D2 between the second gate 32 in the second transistor 30 and the second active layer 21, on the one hand, by setting the distance between the third gate 72 and the third active layer 71 to be larger, that is, the thickness of the insulating layer between the third gate 72 and the third active layer 71 is thicker, so as to protect the third active layer 71 and ensure that the third transistor 70 can still maintain a low leakage current and stability in a longer off state; on the other hand, by setting the distance between the second gate 32 and the second active layer 31 to be smaller, the migration rate of the carriers in the second transistor 30 is increased to ensure the response speed when the second transistor in the driving circuit 40 is frequently turned on, thereby improving the performance of the driving circuit 40 and the pixel circuit 60.

[0058] It is understandable that when the third gate 72 and the second gate 32 are located in the same film layer, and the third active layer 71 and the second active layer 31 are located in the same film layer, the insulating layer between the third gate 72 and the second gate 32 and the insulating layer between the third active layer 71 and the second active layer 31 are the same insulating layer. At this time, for example, the Halftone Mask (half-tone mask) technology can be used to make the thickness of different regions of the insulating layer different. Of course, the method of making the thickness of different regions of the insulating layer different is not limited to the Halftone Mask technology; and is not limited to the third gate 72 and the second gate 32 being located in the same film layer and the third active layer 71 and the second active layer 31 being located in the same film layer.

[0059] Optionally, the third transistor 70 is a driving transistor of the pixel circuit 60 , wherein D2<D3.

[0060] If the third transistor 70 is a driving transistor of the pixel circuit 60, then, because the driving transistor has the function of writing data in the pixel circuit 60, and the data writing process involves the threshold capture of the driving transistor, the subthreshold swing of the driving transistor cannot be too low. By setting the spacing between the third active layer 71 and the third gate 72 to be larger, the subthreshold swing of the third transistor 70 is ensured to be larger, and the third transistor 70 can be ensured to perform the threshold capture process more slowly; at the same time, by setting the spacing between the second gate 32 and the second active layer 31 to be smaller, the migration rate of the carriers in the second transistor 30 is increased to ensure the response speed of the second transistor 30 in the driving circuit 40, thereby improving the performance of the driving circuit 40 and the pixel circuit 60.

[0061] Optional, Fig. 9 is a schematic diagram of a film layer structure of another display panel provided by an embodiment of the present invention, such as Fig. 9 As shown, the second gate 32 is located on the side of the first active layer 21 away from the substrate 10, and the third gate 72 is located on the side of the third active layer 71 away from the substrate 10; wherein, the second transistor 30 includes a fourth gate 35, and the third transistor 70 includes a fifth gate 75, the fourth gate 35 is located on the side of the second active layer 31 facing the substrate 10, and the fifth gate 75 is located on the side of the third active layer 71 facing the substrate 10; in the direction perpendicular to the substrate 10, the spacing between the fourth gate 35 and the second active layer 31 is a fourth spacing D4, and the spacing between the fifth gate 75 and the third active layer 71 is a fifth spacing D5; wherein, D1<D4, and D1<D5.

[0062] Specifically, the second transistor 30 includes not only the second gate 32 but also the fourth gate 35, that is, the second transistor 30 is a dual-gate transistor, so that the mobility of the carriers in the second transistor 30 can be enhanced, and the response capability of the second transistor 30 can be enhanced. The third transistor 70 includes not only the third gate 72 but also the fifth gate 75, that is, the third transistor 70 is also a dual-gate transistor, so that the mobility of the carriers in the third transistor 70 can be enhanced, and the response capability of the third transistor 70 can be enhanced. It should be noted that since the second transistor 30 and the third transistor 70 can be oxide semiconductor transistors, generally speaking, the volume of oxide semiconductor transistors is relatively large, and setting the second transistor 30 as a dual-gate transistor with a top gate and a bottom gate stack and the third transistor 70 as a dual-gate transistor with a top gate and a bottom gate stack is conducive to reducing the volume of the second transistor 30 and the volume of the third transistor 70. In addition, by setting the distance D4 between the fourth gate 35 and the second active layer 31 to be larger, and the distance D2 between the second gate 32 and the second active layer 31 to be larger, the second active layer 31 is fully protected to prevent the hydrogen element, water and oxygen in the film layer of the second active layer 31 away from the substrate 10 and the film layer close to the substrate 10 from corroding the second active layer 31. By setting the distance D5 between the fifth gate 75 and the third active layer 71 to be larger, and the distance D3 between the third gate 72 and the third active layer 71 to be larger, the third active layer 71 is fully protected to prevent the hydrogen element, water and oxygen in the film layer of the third active layer 71 away from the substrate 10 and the film layer close to the substrate 10 from corroding the third active layer 71.

[0063] On the basis of the above scheme, optionally, D2<D4, and D3<D5, that is, when the transistor includes two gates, the distances from different gates in the same transistor to the active layer are different. Specifically, in the second transistor 30, the second gate 32 is the main gate of the second transistor 30, and the fourth gate 35 is the auxiliary gate of the second transistor 30. By setting the spacing D2 between the second gate 32 (main gate) and the second active layer 31 to be smaller than the spacing D4 between the fourth gate 35 (auxiliary gate) and the second active layer 31, the control ability of the main gate to the second transistor 30 is ensured. In the third transistor 70, the third gate 72 is the main gate of the third transistor 70, and the fifth gate 75 is the auxiliary gate of the third transistor 70. By setting the spacing D3 between the third gate 72 (main gate) and the third active layer 71 to be smaller than the spacing D5 between the fifth gate 75 (auxiliary gate) and the third active layer 71, the control ability of the main gate to the third transistor 70 is ensured.

[0064] On the basis of the above solution, optionally, the third transistor 70 is a driving transistor of the pixel circuit 60, wherein D4-D2>D5-D3. That is, the difference between the distance D5 between the fifth gate 75 (auxiliary gate) and the third active layer 71 and the distance D3 between the third gate 72 (main gate) and the third active layer 71 is small, that is, although the distance D5 between the fifth gate 75 (auxiliary gate) and the third active layer 71 is greater than the distance D3 between the third gate 72 (main gate) and the third active layer 71, their values ​​are very close.

[0065] As can be seen from the above content, if the third transistor 70 is the driving transistor of the pixel circuit 60, then, because the driving transistor bears the function of data writing in the pixel circuit 60, and the data writing process involves the threshold capture of the driving transistor, the subthreshold swing of the driving transistor cannot be too low. Therefore, in this embodiment, by setting the distance D5 between the fifth gate 75 (auxiliary gate) and the third active layer 71 to be slightly larger than the distance D3 between the third gate 72 (main gate) and the third active layer 71, it can not only ensure the control ability of the main gate over the third transistor 70, but also ensure that the subthreshold swing of the third transistor 70 is larger, ensuring that the third transistor 70 can perform the threshold capture process more slowly, thereby improving the performance of the pixel circuit 60.

[0066] Fig.10 is a schematic diagram of a film layer structure of another display panel provided by an embodiment of the present invention. Based on the above solution, optionally, Fig.10 As shown, D3>D2, and D5<D4. When the third transistor 70 is a driving transistor, by setting the distance D3 between the third gate 72 (main gate) and the third active layer 71 to be appropriately larger, the subthreshold swing of the third transistor 70 is ensured to be larger, and the third transistor 70 can perform the threshold capture process more slowly, thereby improving the performance of the pixel circuit 60.

[0067] Similarly, when the second gate 32 and the third gate 72 are located in the same film layer, and the second active layer 31 and the third active layer 71 are located in the same layer, and the fourth gate 35 and the fifth gate 75 are located in the same film layer, but it is required that the distance D3 between the third gate 72 (main gate) and the third active layer 71 is different from the distance D2 between the second gate 32 and the second active layer 31, and the distance D5 between the fifth gate 75 (auxiliary gate) and the third active layer 71 is different from the distance D4 between the fourth gate 35 and the second active layer 31, when preparing the insulating layer between the fourth gate 35 and the second active layer 31 and the insulating layer between the second active layer 31 and the second gate 32, for example, the Halftone Mask technology can be used to make the thickness of different areas of the insulating layer different.

[0068] Optional, Fig.11 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, such as Fig.11 As shown, the third transistor 70 is a driving transistor of the pixel circuit 60, wherein the length of the second gate 32 in the first direction X is L2, and the length of the third gate 72 in the first direction X is L3; the length of the fourth gate 35 in the first direction X is L4, and the length of the fifth gate 75 in the first direction X is L5; wherein L3-L2<L5-L4; the first direction X is the current transmission direction in the transistor.

[0069] The driving transistor is a core component in the pixel circuit 60, and its performance directly affects the driving current, and further affects the luminous effect of the light-emitting element. By setting the difference between the length L5 of the fifth gate 75 in the first direction X and the length L4 of the fourth gate 35 in the first direction X to be relatively large, that is, the length L5 of the fifth gate 75 of the driving transistor in the pixel circuit 60 in the first direction X is larger than the fourth gate 35 of the driving circuit 40, the third transistor 70 is fully protected by the fifth gate 75 in the third transistor 70 (the auxiliary gate of the third transistor 70), the stability of the third transistor 70 is improved, the luminous effect of the light-emitting element is improved, and the display effect of the display panel 100 is improved.

[0070] Optional, continue to see Figure 7 The third transistor 70 includes a switching transistor of the pixel circuit 60; a first insulating layer 80 is included between the first gate 22 and the first active layer 21; a second insulating layer 81 is included between the second gate 32 and the second active layer 31, and a third insulating layer 82 is included between the third gate 72 and the third active layer 71; wherein the concentration of hydrogen elements in the third insulating layer 82 is less than the concentration of hydrogen elements in the second insulating layer 81.

[0071] The display panel 100 may be used in the case of low-frequency refresh. During low-frequency refresh, the switching transistor in the pixel circuit 60 is in the off state for a long time, while the transistor in the drive circuit 40 is turned on more frequently. By setting the concentration of hydrogen in the gate insulating layer of the second transistor 30 in the drive circuit 40 to be greater than the concentration of hydrogen in the gate insulating layer of the third transistor 70 in the pixel circuit 60, that is, the concentration of hydrogen in the second insulating layer 81 is greater, defects in the second insulating layer 81 can be repaired, defects in the first insulating layer 80 can be prevented from capturing carriers in the second transistor 30, and the stability of the second transistor 30 can be improved. In this way, even if the second transistor 30 in the drive circuit 40 is turned on more frequently, the overall characteristics of the drive circuit 50 can be guaranteed to be good. Optionally, see further. Figure 7The third transistor 70 includes a driving transistor of the pixel circuit 60; a first insulating layer 80 is included between the first gate 22 and the first active layer 21; a second insulating layer 81 is included between the second gate 32 and the second active layer 31, and a third insulating layer 82 is included between the third gate 72 and the third active layer 71; wherein the concentration of hydrogen elements in the third insulating layer 82 is greater than the concentration of hydrogen elements in the second insulating layer 81.

[0072] When the pixel circuit 60 is applied to the low-frequency driving mode, the driving transistor in the pixel circuit 60 remains in the turned-on state longer than the transistor in the driving circuit 40. By setting the concentration of hydrogen elements in the gate insulating layer of the third transistor 70 in the pixel circuit 60 to be greater than the concentration of hydrogen elements in the gate insulating layer of the second transistor 30 in the driving circuit 40, that is, the concentration of hydrogen elements in the third insulating layer 82 is greater, the defects in the third insulating layer 82 are repaired, the defects in the third insulating layer 82 are prevented from capturing the carriers in the third transistor 70, and the stability of the third transistor 70 is improved. In this way, even if the third transistor 70 in the pixel circuit 60 remains in the turned-on state for a long time, the overall characteristics of the pixel circuit 60 can be guaranteed to be good. It should be noted that when the second insulating layer 81 and the third insulating layer 82 are located in the same film layer, different concentrations of hydrogen elements can be injected into the second insulating layer 81 and the third insulating layer 82 respectively by an ion implantation process, so that the concentration of hydrogen elements in the third insulating layer 82 is greater than the concentration of hydrogen elements in the second insulating layer 81.

[0073] It should be noted that the above-mentioned concentrations, unless otherwise specified, refer to atomic concentrations, that is, the atomic content per unit area.

[0074] Optional, Fig.12 is a schematic diagram of a film layer structure of another display panel provided by an embodiment of the present invention, such as Fig.12 As shown, the pixel circuit 60 also includes a fourth transistor 90, which includes a fourth active layer 91, a sixth gate 92, a fourth source 93 and a fourth drain 94, and the fourth active layer 91 includes an oxide semiconductor; wherein, in a direction perpendicular to the substrate 10, a distance between the sixth gate 92 and the fourth active layer 91 is D6, wherein D1<D6.

[0075] Specifically, the pixel circuit 60 further includes a fourth transistor 90, and the fourth active layer 91 in the fourth transistor 90 may also be an oxide semiconductor active layer, for example, an IGZO active layer. That is, the third transistor 70 and the fourth transistor 90 in the pixel circuit 60 in this embodiment are both oxide semiconductor transistors, which ensures that the leakage current of the pixel circuit 60 is small during operation, and ensures that the pixel circuit 60 has good performance. In addition, in this embodiment, the distance D6 between the sixth gate 92 and the fourth active layer 91 is set to be larger than the distance D1 between the first gate 22 and the first active layer 21. On the one hand, by setting the distance between the sixth gate 92 and the fourth active layer 91 to be larger, that is, the thickness of the insulating layer between the sixth gate 92 and the fourth active layer 91 is thicker, so as to fully protect the fourth active layer 91 and prevent the hydrogen element and water oxygen in the organic film layer on the side of the fourth active layer 91 away from the substrate 10 from corroding the fourth active layer 91; on the other hand, by setting the distance between the first gate 22 and the first active layer 21 to be smaller, the migration rate of the carriers in the first transistor 20 is increased, thereby providing the response speed of the first transistor 20. That is to say, in this embodiment, by setting the distance between the first gate 22 and the first active layer 21 to be smaller than the distance between the sixth gate 92 and the fourth active layer 91, the fourth active layer 91 of the fourth transistor 90 can be fully protected so that the performance of the fourth transistor 90 is good; at the same time, the carrier migration performance in the first transistor 20 is guaranteed; in this way, when the pixel circuit 60 includes the first transistor 20, the third transistor 70 and the fourth transistor 90, the performance of the pixel circuit 60 is guaranteed.

[0076] It should be noted that the fourth active layer 91 of the fourth transistor 90, the third active layer 71 of the third transistor 70, and the second active layer 31 of the second transistor 30 are arranged on the same layer, and the sixth gate 92 of the fourth transistor 90, the third gate 72 of the third transistor 70, and the second gate 32 of the second transistor 30 are arranged on the same layer; and the fourth source 93 and the fourth drain 94 in the fourth transistor 90, the third source 73 and the third drain 74 in the third transistor 70, the second source 33 and the second drain 34 in the second transistor 30, and the first source 23 and the first drain 24 in the first transistor 20 are arranged on the same layer. In this way, the process steps are simplified and the preparation efficiency of the display panel is improved.

[0077] Optional, Fig.13 is a schematic diagram of a film layer structure of another display panel provided by an embodiment of the present invention, such as Fig.13 As shown, the third transistor 70 is a driving transistor of the pixel circuit 60, and the fourth transistor 90 is a switching transistor of the pixel circuit 60, wherein D3>D6.

[0078] In this embodiment, by setting the distance D3 between the third active layer 71 and the third gate 72 to be larger, the subthreshold swing of the third transistor 70 is ensured to be larger. When the third transistor 70 is the driving transistor of the pixel circuit 60, it is ensured that the third transistor 70 can perform the threshold capture process more slowly, thereby improving the performance of the pixel circuit 60.

[0079] Optional, continue to see Fig.13 The third transistor 70 includes a fifth gate 75, and the third gate 72 and the fifth gate 75 are respectively located on both sides of the third active layer 71; the fourth transistor 90 includes a seventh gate 95, and the sixth gate 92 and the seventh gate 95 are respectively located on both sides of the fourth active layer 91; wherein, in a direction perpendicular to the base substrate 10, a distance between the fifth gate 75 and the third active layer 71 is D5, and a distance between the seventh gate 95 and the fourth active layer 91 is D7, wherein D5-D3<D7-D6.

[0080] That is, the difference between the distance D5 between the fifth gate 75 (auxiliary gate) and the third active layer 71 and the distance D3 between the third gate 72 (main gate) and the third active layer 71 is small, that is, although the distance D5 between the fifth gate 75 (auxiliary gate) and the third active layer 71 is greater than the distance D3 between the third gate 72 (main gate) and the third active layer 71, their values ​​are very close, that is, the distance D5 between the fifth gate 75 (auxiliary gate) and the third active layer 71 is slightly greater than the distance D3 between the third gate 72 (main gate) and the third active layer 71. In this way, when the third transistor 70 is used as the driving transistor of the pixel circuit 60, it can not only ensure the control ability of the main gate over the third transistor 70, but also ensure that the subthreshold swing of the third transistor 70 is large, so that the third transistor 70 can perform the threshold capture process more slowly, thereby improving the performance of the pixel circuit 60.

[0081] Optional, Fig.14 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, such as Fig.14 As shown, the length of the third gate 72 in the first direction X is L3, and the length of the fifth gate 75 in the first direction X is L5; the length of the sixth gate 92 in the first direction X is L6, and the length of the seventh gate 95 in the first direction X is L7; wherein, L3-L6<L5-L7; the first direction X is the current transmission direction in the transistor.

[0082] The driving transistor is a core component in the pixel circuit 60, and its performance directly affects the driving current, and further affects the luminous effect of the light-emitting element. By setting the difference between the length L5 of the fifth gate 75 in the first direction X and the length L7 of the seventh gate 95 in the first direction X to be relatively large, that is, the length L5 of the fifth gate 75 of the driving transistor in the pixel circuit 60 in the first direction X is larger than the seventh gate 95 of the switch transistor in the pixel circuit 60, the driving transistor is fully protected by the fifth gate 75 (the auxiliary gate of the third transistor 70) in the driving transistor, the stability of the driving transistor is improved, the luminous effect of the light-emitting element is improved, and the display effect of the display panel 100 is improved.

[0083] Based on the same inventive concept, an embodiment of the present invention further provides a display device, which includes any display panel provided in the above embodiments. Fig.15 As shown, the display device 1000 includes a display panel 100. Therefore, the display device also has the beneficial effects of the display panel in the above embodiment, and the similarities can be understood by referring to the above explanation of the display panel, which will not be repeated below.

[0084] The display device 1000 provided in the embodiment of the present invention can be Fig.15 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, industrial control equipment, medical display screens, touch interactive terminals, etc. The embodiments of the present invention do not specifically limit this.

[0085] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include substrate substrate; a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are formed on the substrate, the third transistor comprises a third active layer, a third gate, a third source and a third drain, and the third active layer comprises an oxide semiconductor; the fourth transistor comprises a fourth active layer, a sixth gate, a fourth source and a fourth drain, and the fourth active layer comprises an oxide semiconductor; In a direction perpendicular to the substrate, a distance between the third gate and the third active layer is D3, and a distance between the sixth gate and the fourth active layer is D6; The display panel includes a pixel circuit and a driving circuit for providing a driving signal to the pixel circuit, the third transistor is a driving transistor of the pixel circuit, and the fourth transistor is a switching transistor of the pixel circuit; wherein, D3>D6.

2. The display panel according to claim 1, characterized in that: The third transistor includes a fifth gate, and the third gate is located on a side of the third active layer away from the substrate; the fifth gate is located on a side of the third active layer facing the substrate; wherein, D5>D3.

3. The display panel according to claim 1, characterized in that: The third transistor includes a fifth gate, and the third gate and the fifth gate are respectively located on both sides of the third active layer; the fourth transistor includes a seventh gate, and the sixth gate and the seventh gate are respectively located on both sides of the fourth active layer; wherein, In a direction perpendicular to the substrate, the distance between the fifth gate and the third active layer is D5, and the distance between the seventh gate and the fourth active layer is D7, wherein: D5-D3<D7-D6.

4. The display panel according to claim 3, characterized in that: The length of the third gate in the first direction is L3, the length of the fifth gate in the first direction is L5; the length of the sixth gate in the first direction is L6, and the length of the seventh gate in the first direction is L7; wherein L3-L6<L5-L7; The first direction is a current transmission direction in the transistor.

5. The display panel according to claim 1, characterized in that: The display panel further includes a second transistor, the second transistor including a second active layer, a second gate, a second source electrode and a second drain electrode, the second active layer including an oxide semiconductor; In a direction perpendicular to the substrate, the distance between the second gate and the second active layer is D2; wherein, D2<D3.

6. The display panel according to claim 5, characterized in that: The second transistor includes a fourth gate, the second gate and the fourth gate are respectively located on both sides of the second active layer, and the third transistor includes a fifth gate, the third gate and the fifth gate are respectively located on both sides of the third active layer; wherein, In a direction perpendicular to the substrate, the distance between the fourth gate and the second active layer is a fourth distance D4, and the distance between the fifth gate and the third active layer is D5, wherein, D2<D4, and D3<D5.

7. The display panel according to claim 6, characterized in that: D4-D2>D5-D3.

8. The display panel according to claim 6, characterized in that: D3>D2, and D5<D4.

9. The display panel according to claim 6, characterized in that: The length of the second gate in the first direction is L2, the length of the third gate in the first direction is L3; the length of the fourth gate in the first direction is L4, and the length of the fifth gate in the first direction is L5; wherein, L3-L2<L5-L4; The first direction is a current transmission direction in the transistor.

10. The display panel according to claim 5, characterized in that: The driving circuit includes a second transistor.

11. The display panel according to claim 10, characterized in that: The driving circuit includes an input module, a logic transmission module and an output module, wherein the input module is connected between the input end and the logic transmission module, and the output module is connected between the logic transmission module and the output end; the logic transmission module is connected to the high level signal end or the low level signal end, and the output end is connected to the pixel circuit; wherein, The output module includes the second transistor.

12. The display panel according to claim 1, characterized in that: The display panel further includes a first transistor, the first transistor including a first active layer, a first gate, a first source and a first drain, the first active layer including silicon; In a direction perpendicular to the substrate, the distance between the first gate and the first active layer is D1; ​​wherein, D1<D3.

13. The display panel according to claim 12, characterized in that: D1<D6.

14. The display panel according to claim 12, characterized in that: The pixel circuit includes the first transistor or the driving circuit includes the first transistor.

15. The display panel according to claim 5, characterized in that: The display panel further includes a first transistor, the first transistor including a first active layer, a first gate, a first source and a first drain, the first active layer including silicon; In a direction perpendicular to the substrate, the distance between the first gate and the first active layer is D1; ​​wherein, D1<D2.

16. The display panel according to claim 15, characterized in that: The width of the channel region of the first transistor is W1, and the width of the channel region of the second transistor is W2; the length of the channel region of the second transistor is L1, and the length of the channel region of the second transistor is L2, wherein W1 / L1≤W2 / L2.

17. The display panel according to claim 15, characterized in that: The width of the channel region of the first transistor is W1, and the width of the channel region of the second transistor is W2; the length of the channel region of the second transistor is L1, and the length of the channel region of the second transistor is L2; The width-to-length ratio of the first transistor is R1=W1 / L1, the width-to-length ratio of the second transistor is R2=W2 / L2, and R1 / R2≥D1 / D2.

18. The display panel according to claim 15, characterized in that: A first insulating layer is included between the first gate and the first active layer; A second insulating layer is included between the second gate and the second active layer, and a third insulating layer is included between the third gate and the third active layer; wherein, The concentration of hydrogen in the third insulating layer is greater than the concentration of hydrogen in the second insulating layer.

19. The display panel according to claim 15, characterized in that: The second active layer is located on a side of the first active layer away from the substrate.

20. The display panel according to claim 15, characterized in that: The second transistor includes a fourth gate, the second gate and the fourth gate are respectively located on both sides of the second active layer, and the third transistor includes a fifth gate, the third gate and the fifth gate are respectively located on both sides of the third active layer; wherein, In a direction perpendicular to the base substrate, a distance between the fourth gate and the second active layer is a fourth distance D4, and a distance between the fifth gate and the third active layer is D5; wherein D1<D4, and D1<D5.

21. The display panel according to claim 20, characterized in that: The second gate is located on a side of the first active layer facing away from the base substrate, the third gate is located on a side of the third active layer facing away from the base substrate, the fourth gate is located on a side of the second active layer facing the base substrate, and the fifth gate is located on a side of the third active layer facing the base substrate.

22. A display device, characterized in that: A display panel comprising any one of claims 1-21.

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