Display panel and display device

Abstract

The invention discloses a display panel and a display device, and belongs to the technical field of display, the display panel comprises a first transistor and a second transistor, and a first active layer of the first transistor comprises silicon; a second active layer of the second transistor includes an oxide semiconductor; the length of the channel region of the first transistor is L1, the distance between the first grid electrode and the first active layer is D1, and the first area S1 is equal to L1 * D1; the length of the channel region of the second transistor is L2, the distance between the second grid electrode and the second active layer is D2, and the second area S2 is equal to L2 * D2; s1 is less than S2; the driving circuit comprises a second transistor, and the pixel circuit comprises a first transistor or the driving circuit comprises the first transistor. The display device comprises the display panel. According to the invention, the stability and normal work of the transistor can be ensured, the space of a panel is saved, and a better display effect is provided.

Description

[0001] This application is a divisional application with the application date of December 30, 2020, application number: 202011612371.7, and the name of the invention is: Display panel and display device. Technical Field

[0002] The present invention relates to the field of display technology, and more particularly, to a display panel and a display device. Background Art

[0003] Display panels are currently widely used in portable electronic products such as mobile phones and PDAs, such as Thin Film Transistor-Liquid Crystal Display (TFT-LCD), Organic Light Emitting Diode (OLED), Low Temperature Poly-silicon (LTPS) and Plasma Display Panel (PDP).

[0004] Displays such as organic light emitting diode displays have an array of display pixels based on light emitting diodes. In this type of display, each display pixel includes a light emitting diode and a thin film transistor for controlling the application of signals to the light emitting diode. Thin film display driver circuits are often included in the display. For example, gate driver circuits and demultiplexer circuits on the display may be formed from thin film transistors.

[0005] With the development of display technology and driven by market competition, more and more display devices with better display effects are being sought after. The pixel density of a display (Pixels Per Inch, which means the number of pixels per inch) has become an important indicator for measuring the display effect of a display. The higher the PPI value, the higher the density at which the display can display images, and the higher the degree of realism.

[0006] Therefore, how to further improve the PPI of the display panel, thereby making the display effect more superior and the product more advantageous, is a technical problem that needs to be urgently solved by those skilled in the art. Summary of the invention

[0007] In view of this, the present invention provides a display panel and a display device to solve the problem in the prior art that the pixel density of the display cannot be further improved and the display effect needs to be improved.

[0008] The present invention discloses a display panel comprising a substrate; a first transistor and a second transistor, the first transistor and the second transistor are formed on the substrate, the first transistor comprises a first active layer, a first gate, a first source and a first drain, the first active layer comprises silicon; the second transistor comprises a second active layer, a second gate, a second source and a second drain, the second active layer comprises an oxide semiconductor; the length of the channel region of the first transistor is L1, in a direction perpendicular to the substrate, the spacing between the first gate and the first active layer is D1, and the first area S1=L1×D1; the length of the channel region of the second transistor is L2, in a direction perpendicular to the substrate, the spacing between the second gate and the second active layer is D2, and the second area S2=L2×D2; wherein S1<S2; the display panel comprises a pixel circuit and a driving circuit for providing a driving signal to the pixel circuit, wherein the driving circuit comprises the second transistor, the pixel circuit comprises the first transistor or the driving circuit comprises the first transistor.

[0009] Based on the same inventive concept, the present invention also discloses a display device, which includes the above-mentioned display panel.

[0010] Compared with the prior art, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0011] The display panel provided by the present invention is arranged in a direction perpendicular to the substrate, the distance between the first gate of the first transistor and the first active layer is D1, and the first area S1=L1×D1; the distance between the second gate of the second transistor and the second active layer is D2, and the second area S2=L2×D2; and S1<S2. Since the first transistor of the silicon transistor has good response capability, in order to fully improve the PPI of the display panel, the present invention utilizes the respective advantages of silicon transistors and oxide semiconductor transistors, and designs the lengths of the channel regions of the two types of transistors to be as small as possible, which is beneficial to saving circuit space and further beneficial to improving the PPI of the display panel. The present invention is arranged in a direction perpendicular to the base substrate of the display panel, and the first area S1 is less than the second area S2, wherein the first area S1=L1×D1, the second area S2=L2×D2, the spacing between the first gate of the first transistor of the silicon transistor and the first active layer is D1, and the spacing between the second gate of the second transistor of the oxide semiconductor transistor and the second active layer is D2, so that the respective characteristics and advantages of the silicon transistor and the oxide semiconductor transistor can be fully utilized, while ensuring the stability and normal operation of the transistor, saving the space of the display panel, improving the PPI of the display panel, and then helping to improve the display quality of the display panel, making the display effect more superior, and making the product more competitive.

[0012] Of course, any product implementing the present invention does not necessarily need to achieve all of the above-mentioned technical effects at the same time.

[0013] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0015] Figure 1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0016] Figure 2 yes Figure 1 The partial membrane cross-sectional structure diagram of area A in the middle;

[0017] Figure 3 yes Figure 1 The partial membrane cross-sectional structure diagram of the middle B area;

[0018] Figure 4 is a circuit connection block diagram of the driving circuit provided in this embodiment;

[0019] Figure 5 yes Figure 2 A schematic diagram of a top view structure of a first transistor and a second transistor;

[0020] Figure 6 yes Figure 3 A schematic diagram of a top view structure of a first transistor and a second transistor;

[0021] Figure 7 yes Figure 1 Another partial film layer cross-sectional structure diagram of area A in the middle;

[0022] Figure 8 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0023] Fig. 9 yes Figure 8 Working timing diagram of the pixel circuit in FIG.

[0024] Fig.10 yes Figure 1 Another partial film layer cross-sectional structure diagram of area A in the middle;

[0025] Fig.11 yes Figure 1 Another partial membrane cross-sectional structure diagram of area B in the middle;

[0026] Fig.12 yes Figure 1Another partial film layer cross-sectional structure diagram of area A in the middle;

[0027] Fig.13 yes Figure 1 Another partial membrane cross-sectional structure diagram of area B in the middle;

[0028] Fig.14 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0029] Fig.15 yes Fig.14 The local film layer cross-sectional structure diagram of the C area in FIG;

[0030] Fig.16 yes Fig.14 Another partial film layer cross-sectional structure diagram of the C region in FIG.

[0031] Fig.17 yes Fig.14 Another partial film layer cross-sectional structure diagram of the C region in FIG.

[0032] Fig.18 yes Fig.14 Another partial film layer cross-sectional structure diagram of the C region in FIG.

[0033] Fig.19 yes Fig.14 Another partial film layer cross-sectional structure diagram of the C region in FIG.

[0034] Fig. 20 yes Fig.14 Another partial film layer cross-sectional structure diagram of the C region in FIG.

[0035] Fig.21 yes Fig.14 Another partial film layer cross-sectional structure diagram of the C region in FIG.

[0036] Fig. 22 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0037] Fig.23 yes Fig. 22 The local film layer cross-sectional structure diagram of the D area in FIG;

[0038] Fig.24 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0039] Fig.25 yes Fig.24 A local enlarged view of the E region in FIG.

[0040] Fig.26 yes Fig.24 Another partial enlarged view of the E region in FIG.

[0041] Fig. 27 It is a schematic diagram of a planar structure of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0043] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0044] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0045] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0046] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0047] Please refer to Figure 1-Figure 3 , Figure 1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Figure 2 yes Figure 1 The partial membrane cross-sectional structure diagram of area A in the middle. Figure 3 yes Figure 1 The partial film layer cross-sectional structure diagram of the middle B area (it can be understood that Figure 2 and Figure 3 Only a partial film layer diagram of a first transistor and a second transistor is schematically drawn to clearly illustrate the technical features of the first transistor and the second transistor. The first transistor and the second transistor are drawn together for schematic illustration, which does not represent the actual arrangement positions of the first transistor and the second transistor in the display panel. In specific implementation, the arrangement positions and connection relationships of the first transistor and the second transistor are determined according to the layout of the driving circuit and the pixel circuit. The display panel 000 provided in this embodiment includes: a substrate 10;

[0048] A first transistor 20 and a second transistor 30, the first transistor 20 and the second transistor 30 are formed on a substrate 10, the first transistor 20 includes a first active layer 201, a first gate 20G, a first source 20S and a first drain 20D, the first active layer 201 includes silicon; the second transistor 30 includes a second active layer 301, a second gate 30G, a second source 30S and a second drain 30D, the second active layer 301 includes an oxide semiconductor; optionally, the present embodiment takes the first transistor 20 and the second transistor 30 as transistors with top gate structures as an example for illustration, and in specific implementation, the first transistor 20 and the second transistor 30 may also be other transistors with bottom gate structures, etc.;

[0049] The length of the channel region of the first transistor 20 is L1, and in the direction Z perpendicular to the substrate 10, the distance between the first gate 20G and the first active layer 201 is D1, and the first area S1 = L1×D1;

[0050] The length of the channel region of the second transistor 30 is L2, and in the direction Z perpendicular to the base substrate 10, the distance between the second gate 30G and the second active layer 301 is D2, and the second area S2 = L2 × D2; wherein,

[0051] S1<S2;

[0052] The display panel 000 includes a pixel circuit 40 and a driving circuit 50 for providing a driving signal to the pixel circuit 40, wherein the first transistor 20 and the second transistor 30 may be transistors in the driving circuit, that is, the driving circuit 50 includes the first transistor 20 or the second transistor 30; in addition, the first transistor 20 and the second transistor 30 may also be transistors in the pixel circuit, that is, the pixel circuit includes the first transistor 20 or the second transistor 30, and if the second transistor 30 is located in the pixel circuit, it may be a driving transistor or a switching transistor;

[0053] In some optional implementations, the driving circuit 50 includes the second transistor 30 , the pixel circuit 40 includes the first transistor 20 , or the driving circuit 50 includes the first transistor 20 .

[0054] Specifically, the display panel 000 of the present embodiment includes a pixel circuit 40 and a driving circuit 50 for providing a driving signal to the pixel circuit 40. Optionally, the driving circuit 50 may be a gate driving circuit for providing a scanning driving signal to the scanning line G of the display panel 000. The gate driving circuit may be formed on the base substrate 10, for example, disposed at the left edge of the display panel 000 (it can be understood that the gate driving circuit of the present embodiment is not limited to the gate driving circuit of the display panel 000). Figure 1The block diagram only illustrates a structure of a driving circuit 50 on the display panel, but is not limited thereto. The specific connection structure of the driving circuit 50 is not limited in this embodiment. The driving circuit 50 may be located on the right edge, only on a single edge of the display panel 000, or at other locations in the display panel 000. The driving circuit 50 may also be a demultiplexer circuit (not shown in the figure, the demultiplexer circuit may be located between the binding area and the display area of ​​the display panel 000), which is used to demultiplex the data signal from the driving chip or the flexible circuit board in the binding area to a plurality of corresponding data lines S. The display panel 000 may include a plurality of display pixels 400, each of which may include a pixel circuit 40. The scan lines G and the data lines S of the display panel 000 are cross-insulated to define the area where the display pixels 400 are located. It can be understood that in this embodiment, Figure 1 The connection structure of the pixel circuit 40 is not shown, but is only shown in a block diagram. The pixel circuit 40 may be a circuit structure including a plurality of transistors and a storage capacitor. This embodiment does not specifically limit this, and only needs to be able to provide a display driving signal for the display pixel 400. Figure 2 The driving circuit 50 includes a second transistor 30, and the pixel circuit 40 includes a first transistor 20. Figure 3 It is shown that the driving circuit 50 includes the second transistor 30 and the first transistor 20. In specific implementation, the structure of the pixel circuit 40 and the driving circuit 50 is not limited to this. This embodiment does not specifically limit the circuit structure of the pixel circuit 40 and the driving circuit 50 that provides the driving signal for the pixel circuit 40. It only needs to satisfy that the driving circuit 50 includes the second transistor 30, the pixel circuit 40 includes the first transistor 20, or the driving circuit 50 includes the first transistor 20, so that there are at least two types of transistors on the substrate 10 of the display panel 000. In specific implementation, it can be understood according to the structure of the pixel circuit and the driving circuit designed by the display panel 000 in the relevant technology to realize the display function.

[0055] The first transistor 20 and the second transistor 30 of this embodiment are formed on the substrate 10. The first transistor 20 includes a first active layer 201, a first gate 20G, a first source 20S and a first drain 20D. The first active layer 201 includes silicon, that is, the first transistor 20 is a silicon transistor. The silicon can be polysilicon deposited by a low temperature method, that is, LTPS (Low Temperature Poly-silicon) or low temperature polysilicon. The length of the channel region of the first transistor 20 is L1, wherein the channel region of the first transistor 20 is the region where the first active layer 201 of the first transistor 20 overlaps with the first gate 20G, and the length of the channel region of the first transistor 20 is the length of the channel region of the first transistor 20 in the current transmission direction between the first source 20S and the first drain 20D. The second transistor 30 includes a second active layer 301, a second gate 30G, a second source 30S and a second drain 30D. The second active layer 301 includes an oxide semiconductor, that is, the second transistor 30 is an oxide semiconductor transistor, and the oxide semiconductor material is amorphous indium gallium zinc oxide, that is, IGZO (Indium Gallium Zinc Oxide). The length of the channel region of the second transistor 30 is L2, wherein the channel region of the second transistor 30 is the region where the second active layer 301 of the second transistor 30 overlaps with the second gate 30G, and the length of the channel region of the second transistor 30 is the length of the channel region of the second transistor 30 in the current transmission direction between the second source 30S and the second drain 30D.

[0056] The display panel 000 provided in this embodiment is arranged in a direction Z perpendicular to the base substrate 10, the distance between the first gate 20G and the first active layer 201 is D1, and the first area S1=L1×D1; the distance between the second gate 30G and the second active layer 301 is D2, and the second area S2=L2×D2; and S1<S2. Optionally, the distance D1 between the first gate 20G and the first active layer 201 can be set to be smaller than the distance D2 between the second gate 30G and the second active layer 301, and the length L1 of the channel region of the first transistor 20 can be set to be smaller than the length L2 of the channel region of the second transistor 30. The distance D1 between the first gate 20G and the first active layer 201 can be set to be smaller than the distance D2 between the second gate 30G and the second active layer 301, and the length L1 of the channel region of the first transistor 20 is smaller than the length L2 of the channel region of the second transistor 30, so as to achieve that the first area S1 is smaller than the second area S2. Since the first transistor 20 of the present embodiment is a silicon transistor and the second transistor 30 is an oxide semiconductor transistor, the carrier migration rate of the first transistor 20 which is a silicon transistor is faster than that of the second transistor 30 which is an oxide semiconductor transistor, and the first active layer 201 of the first transistor 20 includes silicon, while the second active layer 301 of the second transistor 30 includes an oxide semiconductor, and the silicon transistor is not as sensitive to hydrogen elements, water oxygen, etc. in the external environment as the oxide semiconductor transistor, therefore, the distance D1 between the first gate 20G of the first transistor 20 and the first active layer 201 can be set to be smaller than the distance D2 between the second gate 30G of the second transistor 30 and the second active layer 301 (e.g., Figure 2 and Figure 3As shown); since the first transistor 20 of the silicon transistor has good response capability, in order to fully improve the PPI of the display panel 000, this embodiment utilizes the respective advantages of the silicon transistor and the oxide semiconductor transistor, and designs the lengths of the channel regions of the two types of transistors (L1 and L2) to be as small as possible, which is beneficial to saving circuit space, and further beneficial to improving the PPI (Pixels Per Inch, pixel density, indicating the number of pixels per inch) of the display panel 000. The present embodiment is arranged in a direction Z perpendicular to the base substrate 10 of the display panel 000, and the first area S1 is less than the second area S2, wherein the first area S1=L1×D1, the second area S2=L2×D2, the spacing between the first gate 20G of the first transistor 20 of the silicon transistor and the first active layer 201 is D1, and the spacing between the second gate 30G of the second transistor 30 of the oxide semiconductor transistor and the second active layer 301 is D2, so that the respective characteristics and advantages of the silicon transistor and the oxide semiconductor transistor can be fully utilized, while ensuring the stability and normal operation of the transistor, saving the space of the display panel and improving the PPI of the display panel, which is beneficial to improving the display quality of the display panel 000, making the display effect more superior and making the product more competitive.

[0057] It should be noted that the width and length of the channel region mentioned above and appearing later, where the length of the channel region refers to the dimension in the direction in which the carriers in the channel region migrate between the source and the drain, if this direction is defined as the second direction, then the width of the channel region refers to the dimension of the channel region in the third direction, where the second direction may be perpendicular to the third direction.

[0058] In addition, it should be noted that Figure 1-Figure 3 The planar structure of the display panel 000 and the cross-sectional structure of a local film layer are only exemplarily drawn. The structure included in the display panel 000 is not limited to this, and may also include other film layer structures that can realize the relevant functions of the display panel, such as various insulating layers, light-emitting layers, electrode layers (organic light-emitting display panel), etc. This embodiment is not described in detail here. During the specific implementation, the structure of the display panel in the related technology can be referred to for understanding.

[0059] In some optional embodiments, please refer to Figure 1-Figure 3 and Figure 4 , Figure 4: is a circuit connection block diagram of the driving circuit provided in this embodiment. In this embodiment, the driving circuit 50 includes an input module 501, a logic transmission module 502 and an output module 503. The input module 501 is connected between the input terminal in and the logic transmission module 502, and the output module 503 is connected between the logic transmission module 502 and the output terminal out; the logic transmission module 502 is connected to the high level signal terminal VGH or the low level signal terminal VGL, and the output terminal out is connected to the pixel circuit 40; wherein,

[0060] The logic transmission module 502 includes the second transistor 30 or the input module 501 includes the second transistor 30 , and the output module 503 includes the first transistor 20 .

[0061] This embodiment explains that the driving circuit 50 can be a gate driving circuit, which is used to connect to the pixel circuit 40 through the scanning line G and provide a scanning driving signal to the pixel circuit 40. The driving circuit 50 may include an input module 501, a logic transmission module 502 and an output module 503. One end of the input module 501 is connected to the input terminal in of the driving circuit 50, and the other end is connected to the logic transmission module 502. The input terminal in can provide an input signal to the input module 501 by connecting a driving chip or a flexible circuit board; the logic transmission module 502 is connected to the high-level signal terminal VGH or the low-level signal terminal VGL, generally including a NAND gate and a NOR gate circuit, etc., which is usually a gating circuit of the high-level signal terminal VGH and the low-level signal terminal VGL; the other end of the logic transmission module 502 is connected to the output module 503, the output module 503 is connected to the output terminal out of the driving circuit 50, and the output terminal out is connected to the pixel circuit 40, so as to provide a scanning driving signal to the pixel circuit 40 through the driving circuit 50. In this embodiment, the logic transmission module 502 of the driving circuit 50 includes the second transistor 30, or the input module 501 of the driving circuit 50 includes the second transistor 30, and the output module 503 includes the first transistor 20. Since the first area S1 of the first transistor 20 is smaller than the second area S2 of the second transistor 30, the length L1 of the channel region of the first transistor 20 is set to be smaller, or the distance D1 between the first gate 20G and the first active layer 201 in the direction Z perpendicular to the base substrate 10 is smaller, both of which can make the first area S1 of the first transistor 20 smaller, thereby enabling the first transistor 20 to respond faster. In the driving circuit 50 provided in the present embodiment, for the input module 501 and the logic transmission module 502, especially the NAND gate and NOR gate circuit of the logic transmission module 502, it is usually a gating circuit of the high-level signal terminal VGH and the low-level signal terminal VGL. The gating circuit of the high-level signal terminal VGH and the low-level signal terminal VGL generally requires the transistor to have a lower leakage current in the off state, so as to avoid the influence of the leakage current of the transistor on the high-level signal and the low-level signal after the logic signal is transmitted, thereby affecting the normal transmission of the next node signal. Therefore, in the present embodiment, the logic transmission module 502 is set to include the second transistor 30 of the oxide semiconductor transistor, and the input module 501 includes the second transistor 30 of the oxide semiconductor transistor. The oxide semiconductor transistor has a lower leakage current in the off state, so it can be avoided that the gating of the high-level signal and the low-level signal after the logic signal transmission of the input module 501 and the logic transmission module 502 is affected due to the leakage current of other transistors, thereby affecting the normal transmission of the next node signal.The output module 503 of the driving circuit 50 is generally required to have a faster response speed and driving capability. Therefore, in this embodiment, the output module 503 includes a first transistor 20 of a silicon transistor. The first area S1 of the first transistor 20 is smaller and the response speed is faster, thereby ensuring the response and driving capability of the driving circuit 50 and avoiding problems such as signal delay in the display panel 000 due to the driving circuit 50.

[0062] It should be noted that this embodiment uses a block diagram to illustrate the connection structure of each module in the driving circuit 50. During specific implementation, the circuit connection structure inside each module of the driving circuit 50 can be designed according to actual needs, and this embodiment does not limit it.

[0063] In some optional embodiments, please refer to Figure 1-Figure 4 and Figure 5 , Figure 6 , Figure 5 yes Figure 2 A schematic diagram of a top view structure of a first transistor and a second transistor, Figure 6 yes Figure 3 Schematic diagram of the top view structure of the first transistor and the second transistor in the embodiment, in which the width of the channel region of the first transistor 20 is W1, the width of the channel region of the second transistor 30 is W2, the first volume V1=S1×W1, the second volume V2=S2×W2; wherein, V1>V2. The channel region of the first transistor 20 is the region where the first active layer 201 of the first transistor 20 overlaps with the first gate 20G, the length L1 of the channel region of the first transistor 20 is the length of the channel region of the first transistor 20 in the current transmission direction between the first source 20S and the first drain 20D, and the width W1 of the channel region of the first transistor 20 is the length of the channel region of the first transistor 20 in the direction perpendicular to the length of the channel region of the first transistor 20, that is, the length direction of the channel region of the first transistor 20 and the width direction of the channel region of the first transistor 20 are mutually opposite. vertical; the channel region of the second transistor 30 is the region where the second active layer 301 of the second transistor 30 overlaps with the second gate 30G, the length of the channel region of the second transistor 30 is the length of the channel region of the second transistor 30 in the current transmission direction between the second source 30S and the second drain 30D, and the width W2 of the channel region of the second transistor 30 is the length of the channel region of the second transistor 30 in the direction perpendicular to the length of the channel region of the second transistor 30, that is, the length direction of the channel region of the second transistor 30 and the width direction of the channel region of the second transistor 30 are perpendicular to each other.

[0064] This embodiment explains that the width of the channel region of the first transistor 20 of the silicon transistor is W1, the first volume V1=S1×W1, the width of the channel region of the second transistor 30 of the oxide semiconductor transistor is W2, the second volume V2=S2×W2, although the first area S1<the second area S2, but this embodiment sets the first volume V1>the second volume V2, so that by fully increasing the width W1 of the channel region of the first transistor 20 of the silicon transistor, that is, W1 / W2>S2 / S1, the ratio of the width W1 of the channel region of the first transistor 20 to the width W2 of the channel region of the second transistor 30 is greater than the ratio of the second area S2 to the first area S1, so that the first volume V1>the second volume V2, which can further ensure the responsiveness of the transistor of the output module 503 of the driving circuit 50 using the first transistor 20, and then ensure the output performance of the driving circuit 50, which is beneficial to improving the output effect.

[0065] In some optional embodiments, please refer to Figure 1 and Figure 7 , Figure 8 , Figure 7 yes Figure 1 Another partial film layer cross-sectional structure diagram of area A in the middle. Figure 8 is a structural diagram of a pixel circuit 40 provided in an embodiment of the present invention. In this embodiment, the pixel circuit 40 includes a first transistor 20, and the first transistor 20 is a driving transistor of the pixel circuit 40, wherein D1 / D2<L1 / L2.

[0066] This embodiment explains that the pixel circuit 40 of the display pixel 400 may include a first transistor 20 of a silicon transistor, and the first transistor 20 may be a driving transistor of the pixel circuit 40. In the organic light-emitting display panel, the first transistor 20 as a driving transistor may be electrically connected to the light-emitting unit, and provide an anode voltage signal to the anode of each light-emitting unit, so that a certain driving electric field is formed between the anode and the cathode of the light-emitting unit, and the light-emitting layer is realized, thereby realizing the display function. Since the driving transistor of the pixel circuit 40 is responsible for writing the data of the pixel circuit 40, the accuracy of the threshold voltage of the driving transistor and the stability of the gate potential are very high. Therefore, it is necessary to appropriately increase the spacing between the gate of the transistor and the active layer or appropriately increase the length of the channel region of the transistor, so as to obtain a more accurate threshold voltage and ensure the stability of the gate potential of the driving transistor. Therefore, in this embodiment, the driving transistor of the pixel circuit 40 is set to be the first transistor 20 of the silicon transistor, and the carrier migration rate of the silicon transistor is relatively large. When the first area S1 is ensured to be smaller than the second area S2, when the length L1 of the channel region of the first transistor 20 is set to increase more, it will not cause much impact on the response rate of the first transistor 20. Therefore, in this embodiment, the driving transistor of the pixel circuit 40 is set to be the first transistor 20 of the silicon transistor, and the ratio of the spacing D1 between the first gate 20G of the first transistor 20 and the first active layer 201 to the spacing D2 between the second gate 30G of the second transistor 30 and the second active layer 301 is smaller than the length L1 of the channel region of the first transistor 20 and the length L2 of the channel region of the second transistor 30, that is, the length L1 of the channel region of the first transistor 20 can be greater than or equal to the length L2 of the channel region of the second transistor 30, so that while a more accurate threshold voltage of the driving transistor can be obtained and the stability of the gate potential of the driving transistor can be ensured, too much influence on the response rate of the first transistor 20 can be avoided, which is beneficial to ensuring the response capability of the pixel circuit 40.

[0067] Optional, such as Figure 8 and Fig. 9 As shown, Fig. 9 yes Figure 8The working timing diagram of the pixel circuit in the pixel circuit 40 includes a plurality of switching transistors and driving transistors (M1-M7), a storage capacitor Cst, and a light-emitting diode OLED (7T1C), wherein transistor M3 is a driving transistor and the remaining transistors are switching transistors. Taking the structure of the pixel circuit 40 as an example, the working principle of the pixel circuit 40 is as follows: in the initial reset stage T1, transistors M5 and M7 are turned on, the remaining transistors are turned off, the potential of node N1 is the reference voltage Vref, the potential of node N4 is the reference voltage Vref, and the anode of the light-emitting diode OLED is reset; in the data writing and threshold capture stage T2, transistors M2, M3, and M4 are turned on, the remaining transistors are turned off, the potential of node N2 is the data voltage Vdata, the potential of nodes N1 and N3 is Vdata-|Vth|, where Vth is the transistor The threshold voltage of M3; in the light-emitting stage T3, the transistors M1, M3 and M6 are turned on, and the other transistors are turned off. The signal of the positive power supply voltage PVDD is transmitted to the transistor M3, and the transistor M3 generates a driving current to drive the light-emitting diode OLED to emit light. The potential of the node N2 is the positive power supply voltage PVDD, the potential of the node N1 is Vdata-|Vth|, the potential of the node N3 is PVEE+Voled, PVEE is the negative power supply voltage, Voled is the corresponding voltage on the light-emitting diode OLED, and the light-emitting current Id=k(Vsg-|Vth|) 2 =k(PVDD-Vdata-|Vth|) 2 Optionally, in this embodiment, the structure of the pixel circuit 40 is taken as an example, and the first transistor 20 of the silicon transistor may be the driving transistor M3 in the pixel circuit 40 .

[0068] It should be noted that this embodiment only illustrates an exemplified circuit structure of a pixel circuit 40 that can be implemented, but is not limited thereto. The structure of the pixel circuit 40 can be other structures, which is not limited in this embodiment.

[0069] In some optional embodiments, please refer to Figure 1 and Fig.10 , Fig.11 , Fig.10 yes Figure 1 Another partial film layer cross-sectional structure diagram of area A in the middle. Fig.11 yes Figure 1Another partial film layer cross-sectional structure diagram of the middle B area. In this embodiment, the second transistor 30 also includes a fourth gate 30G2. In the direction Z perpendicular to the substrate 10, the distance between the fourth gate 30G2 and the second active layer 301 is D4, and D2<D4; the channel region of the second transistor 30 defined by the second gate 30G is the second channel region, and the length of the second channel region is L2; ​​the second channel region is the region where the second active layer 301 of the second transistor 30 overlaps with the second gate 30G, and the length of the second channel region is the length of the second channel region of the second transistor 30 in the current transmission direction between the second source 30S and the second drain 30D. The channel region of the second transistor 30 defined by the fourth gate 30G2 is the fourth channel region, and the length of the fourth channel region is L4; the fourth channel region is the region where the second active layer 301 of the second transistor 30 overlaps with the fourth gate 30G2, and the length of the fourth channel region is the length of the fourth channel region of the second transistor 30 in the current transmission direction between the second source 30S and the second drain 30D; wherein, the fourth area S4=L4×D4, S2<S4.

[0070] This embodiment explains that the second transistor 30 of the oxide semiconductor transistor can be a dual-gate transistor, and the second transistor 30 includes a second gate 30G and a fourth gate 30G2. In the direction Z perpendicular to the substrate 10, the distance D4 between the fourth gate 30G2 and the second active layer 301 is greater than the distance D2 between the second gate 30G and the second active layer 301, that is, the second transistor 30 of the dual-gate structure includes two control gates, the second gate 30G is the main gate, and the fourth gate 30G2 is the auxiliary gate. From a structural point of view, it can be considered as a series connection of two single-gate transistors. The added fourth gate 30G2 has a certain shielding effect, which can make the feedback capacitance between the drain and the second gate 30G very small, which is beneficial to improving the display quality of the display panel. In addition, this embodiment is arranged in the direction Z perpendicular to the base substrate 10, and the distance D4 between the fourth gate 30G2 and the second active layer 301 is greater than the distance D2 between the second gate 30G and the second active layer 301, that is, the insulating layer between the fourth gate 30G2 and the second active layer 301 is arranged to be thicker, which can play a role in protecting the second active layer 301.

[0071] In some optional embodiments, please continue to refer to Figure 1 , Fig.10 , Fig.11In this embodiment, the product of the length L4 of the fourth channel region of the second transistor 30 defined by the fourth gate 30G2 of the second transistor 30 and the distance D4 between the fourth gate 30G2 and the second active layer 301 is the fourth area S4, the product of the length L1 of the channel region of the first transistor 20 and the distance D1 between the first gate 20G and the first active layer 201 is the first area S1, and the product of the length L2 of the channel region of the second transistor 30 and the distance D2 between the second gate 30G and the second active layer 301 is the second area S2, S4+S1>2S2, that is, the sum of the fourth area S4 and the first area S1 is greater than twice the second area S2.

[0072] This embodiment explains that the difference between the fourth area S4 defined by the fourth gate 30G2 of the second transistor 30 of the dual-gate oxide semiconductor transistor and the second area S2 defined by the second gate 30G of the second transistor 30 is greater than the difference between the second area S2 defined by the second gate 30G of the second transistor 30 and the first area S1 defined by the first gate 20G of the first transistor 20, that is, S4-S2>S2-S1, S4+S1>2S2. In this embodiment, the distance D4 between the fourth gate 30G2 and the second active layer 301 is greater than the distance D2 between the second gate 30G and the second active layer 301, that is, the insulating layer between the fourth gate 30G2 and the second active layer 301 is set thicker, which can protect the second active layer 301, and the fourth area S4 defined by the fourth gate 30G2 is set larger, which can make the fourth area S4 larger than the second area S2, and the first area S1 and the second area S2 are both areas defined by the main gate of the transistor, and when the first transistor 20 and the second transistor 30 are both used as switch transistors, although there is an area difference between the two, the difference is generally not set very large, that is, S4-S2>S2-S1. The second transistor 30 of this embodiment is an oxide semiconductor transistor with a dual-gate structure, and the fourth gate 30G2 is an auxiliary gate, which is located at the bottom of the second active layer 301. The auxiliary gate can improve the stability of the oxide semiconductor transistor and protect the second active layer 301.

[0073] In some optional embodiments, please refer to Figure 1 and Fig.12 , Fig.13 , Fig.12 yes Figure 1 Another partial film layer cross-sectional structure diagram of area A in the middle. Fig.13 yes Figure 1Another partial film layer cross-sectional structure diagram of the middle B area. In this embodiment, the first transistor 20 also includes a third gate 20G2. In the direction Z perpendicular to the substrate 10, the distance between the third gate 20G2 and the first active layer 201 is D3, and D1<D3; the channel region of the first transistor 20 defined by the first gate 20G is the first channel region, and the length of the first channel region is L1; the first channel region is the region where the first active layer 201 of the first transistor 20 overlaps with the first gate 20G, and the length of the first channel region is the length of the first channel region of the first transistor 20 in the current transmission direction between the first source 20S and the first drain 20D. The channel region of the first transistor 20 defined by the third gate 20G2 is the third channel region, and the length of the third channel region is L3; the third channel region is the region where the first active layer 201 of the first transistor 20 overlaps with the third gate 20G2, and the length of the third channel region is the length of the third channel region of the first transistor 20 in the current transmission direction between the first source 20S and the first drain 20D; wherein, the third area S3=L3×D3, S1<S3.

[0074] This embodiment explains that the first transistor 20 of the silicon transistor can be a dual-gate transistor, the first transistor 20 includes a first gate 20G and a third gate 20G2, in the direction Z perpendicular to the substrate 10, the distance D3 between the third gate 20G2 and the first active layer 201 is greater than the distance D1 between the first gate 20G and the first active layer 201, that is, the first transistor 20 of the dual-gate structure includes two control gates, the first gate 20G is the main gate, and the third gate 20G2 is the auxiliary gate. From a structural point of view, it can be considered as a series connection of two single-gate transistors. The added third gate 20G2 has a certain shielding effect, which can make the feedback capacitance between the drain and the first gate 20G very small, which is beneficial to improving the display quality of the display panel. In addition, in this embodiment, the third area S3 defined by the third gate 20G2 is set to be larger, and the third area S3 is larger than the first area S1, that is, the first area S1 defined by the main gate is smaller than the third area S3 defined by the auxiliary gate, and in the direction Z perpendicular to the base substrate 10, the distance D3 between the third gate 20G2 and the first active layer 201 is larger than the distance D1 between the first gate 20G and the first active layer 201, that is, the insulating layer between the third gate 20G2 and the first active layer 201 is set to be thicker, which can protect the first active layer 201.

[0075] In some optional embodiments, please continue to refer to Figure 1 and Fig.12 , Fig.13 In this embodiment, the third gate 20G2 of the first transistor 20 includes hydrogenated amorphous silicon.

[0076] This embodiment explains that the material of the third gate 20G2 of the first transistor 20 can be hydrogen-containing amorphous silicon (a-Si:H), so that hydrogen elements can be provided to the first active layer 201 of the first transistor 20 of the silicon transistor to repair defects in the first active layer 201.

[0077] In some optional embodiments, please continue to refer to Figure 1 , Figure 8 and Fig.12 , Fig.13 In this embodiment, the first transistor 20 is a driving transistor of the pixel circuit 40, wherein S3-S1<S4-S2.

[0078] This embodiment explains that the pixel circuit 40 of the display pixel 400 may include a first transistor 20 of a silicon transistor, and the first transistor 20 may be a driving transistor of the pixel circuit 40. In the organic light-emitting display panel, the first transistor 20 as a driving transistor may be electrically connected to the light-emitting unit, and provide an anode voltage signal to the anode of each light-emitting unit, so that a certain driving electric field is formed between the anode and the cathode of the light-emitting unit, so as to realize the light emission of the light-emitting layer, and then realize the display function.

[0079] In this embodiment, the difference between the third area S3 and the first area S1 is set to be smaller than the difference between the fourth area S4 and the second area S2, that is, the first transistor 20 and the second transistor 30 are both dual-gate structures, and the difference between the third area S3 defined by the bottom gate (third gate 20G2) of the first transistor 20 and the first area S1 defined by the top gate (first gate 20G) is S3-S1, and the difference between the fourth area S4 defined by the bottom gate (fourth gate 30G2) of the second transistor 30 and the second area S2 defined by the top gate (second gate 30G) is S4-S2. 2. The material of the bottom gate (third gate 20G2) of the first transistor 20 includes hydrogen-containing amorphous silicon, which can provide hydrogen elements for the first active layer 201 to repair defects in the first active layer 201, and can also play a shielding role to prevent the first transistor 20 from being interfered by other components in the display device. Therefore, the third area S3 defined by the bottom gate (third gate 20G2) of the first transistor 20 does not need to be set larger than the first area S1 defined by the top gate (first gate 20G), that is, the difference S3-S1 can be smaller. The material of the second active layer 301 of the second transistor 30 is an oxide semiconductor material, which is more sensitive than silicon material. In particular, when both the oxide semiconductor transistor and the silicon transistor are arranged in the display panel 000, because the silicon transistor is in an environment with a relatively high hydrogen content, in order to fully protect the oxide semiconductor transistor, after the second transistor 30 is set with a dual-gate structure, the fourth area S4 defined by its bottom gate (auxiliary gate-fourth gate 30G2) can be set larger, thereby improving the stability of the second transistor 30 while protecting the second active layer 301 of the second transistor 30 from the influence of hydrogen elements through the larger area of ​​the fourth gate 30G2. Therefore, in this embodiment, S3-S1 is set to be less than S4-S2.

[0080] Furthermore, since the third gate 20G2 of the first transistor 20 of the present embodiment is mainly used to supplement hydrogen to the first active layer 201 of the first transistor 20 and to play a shielding role, in the direction Z perpendicular to the base substrate 10, the distance D3 between the third gate 20G2 and the first active layer 201 does not need to be set larger. As for the second transistor 30, in order to fully protect the oxide semiconductor transistor, the distance D2 between the second gate 30G and the second active layer 301 and the distance D4 between the fourth gate 30G2 and the second active layer 301 are generally set larger (that is, the thickness of the insulating layer between the second gate 30G and the second active layer 301 and the thickness of the insulating layer between the fourth gate 30G2 and the second active layer 301 are both thicker), so that the second transistor 30 can be fully protected, which is beneficial to improving the display quality.

[0081] Optional, such as Figure 8 As shown, Figure 8It is a structural schematic diagram of a pixel circuit 40 provided in an embodiment of the present invention. The pixel circuit 40 includes multiple switching transistors and driving transistors, a storage capacitor, and a light-emitting diode OLED (7T1C). Taking the structure of the pixel circuit 40 as an example, the first transistor 20 of the silicon transistor can be the driving transistor M3 in the pixel circuit 40.

[0082] In some optional embodiments, please refer to Fig.14 and Fig.15 , Fig.14 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Fig.15 yes Fig.14 The local film layer cross-sectional structure diagram of the C area in (it can be understood that Fig.15 Only partial film layer diagrams of a first transistor, a second transistor, and a third transistor are schematically drawn in order to clearly illustrate the technical solution of this embodiment. The first transistor, the second transistor, and the third transistor are drawn together for schematic illustration, which does not represent the actual setting positions of the first transistor, the second transistor, and the third transistor in the display panel. In specific implementation, the setting positions and connection relationships of the first transistor, the second transistor, and the third transistor are determined according to the layout of the driving circuit and the pixel circuit). In this embodiment, the pixel circuit 40 includes a third transistor 60, and the third transistor 60 includes a fifth gate 60G, a third active layer 601, a third source 60S, and a third drain 60D, and the third active layer 601 includes an oxide semiconductor; in the direction Z perpendicular to the substrate 10, the distance between the fifth gate 60G and the third active layer 601 is D5, and the channel region of the third transistor 60 defined by the fifth gate 60G is the fifth channel region, the length of the fifth channel region is L5, and the fifth area S5=L5×D5; wherein, S1<S5.

[0083] This embodiment explains that the pixel circuit 40 of the display panel 000 also includes a third transistor 60, the third transistor 60 includes a fifth gate 60G, a third active layer 601, a third source 60S and a third drain 60D, the third active layer 601 includes an oxide semiconductor, that is, the third transistor 60 is also an oxide semiconductor transistor, the oxide semiconductor material is such as amorphous indium gallium zinc oxide, that is, IGZO (Indium Gallium Zinc Oxide), the driving circuit 50 includes a second transistor 30 of an oxide semiconductor transistor, and the pixel circuit 40 also includes a third transistor 60 of an oxide semiconductor transistor. The length of the channel region of the third transistor 60 is L5, wherein the channel region of the third transistor 60 is the region where the third active layer 601 of the third transistor 60 overlaps with the fifth gate 60G, and the length of the channel region of the third transistor 60 is the length of the channel region of the third transistor 60 in the current transmission direction between the third source 60S and the third drain 60D.

[0084] The display panel 000 provided in this embodiment is arranged in a direction Z perpendicular to the base substrate 10, the distance between the fifth gate 60G and the third active layer 601 is D5, the length of the fifth channel region of the third transistor 60 defined by the fifth gate 60G is L5, the fifth area S5=L5×D5, and S1<S5. Optionally, the distance D1 between the first gate 20G and the first active layer 201 can be set to be smaller than the distance D5 between the fifth gate 60G and the third active layer 601, the length L1 of the channel region of the first transistor 20 can also be set to be smaller than the length L5 of the channel region of the third transistor 60, the distance D1 between the first gate 20G and the first active layer 201 can also be set to be smaller than the distance D5 between the fifth gate 60G and the third active layer 601, and the length L1 of the channel region of the first transistor 20 is smaller than the length L5 of the channel region of the third transistor 60, so as to achieve that the first area S1 is smaller than the fifth area S5. Since the first transistor 20 of the present embodiment is a silicon transistor and the third transistor 60 is an oxide semiconductor transistor, the carrier migration rate of the first transistor 20 of the silicon transistor is faster than that of the third transistor 60 of the oxide semiconductor transistor, and the first active layer 201 of the first transistor 20 includes silicon, while the third active layer 601 of the third transistor 60 includes an oxide semiconductor, and the silicon transistor is not as sensitive to hydrogen elements, water oxygen, etc. in the external environment as the oxide semiconductor transistor, therefore, the distance D1 between the first gate 20G of the first transistor 20 and the first active layer 201 can be set to be smaller than the distance D5 between the fifth gate 60G of the third transistor 60 and the third active layer 601 (e.g., Fig.15As shown); since the first transistor 20 of the silicon transistor has good response capability, in order to fully improve the PPI of the display panel 000, this embodiment utilizes the respective advantages of the silicon transistor and the oxide semiconductor transistor, and designs the lengths of the channel regions of the two types of transistors (L1 and L5) to be as small as possible, which is beneficial to saving circuit space, and further beneficial to improving the PPI (Pixels Per Inch, pixel density, indicating the number of pixels per inch) of the display panel 000. This embodiment is arranged in the direction Z perpendicular to the base substrate 10 of the display panel 000, and the first area S1 is less than the fifth area S5, wherein the first area S1=L1×D1, the fifth area S5=L5×D5, the distance between the first gate 20G of the first transistor 20 of the silicon transistor and the first active layer 201 is D1, and the distance between the fifth gate 60G of the third transistor 60 of the oxide semiconductor transistor and the third active layer 601 is D5, so that the respective characteristics and advantages of the silicon transistor and the oxide semiconductor transistor can be fully utilized, while ensuring the stability and normal operation of the transistor, saving the space of the display panel and improving the PPI of the display panel, which is beneficial to improving the display quality of the display panel 000, making the display effect more superior and making the product more competitive.

[0085] In some optional embodiments, please refer to Figure 8 , Fig.14 and Fig.16 , Fig.16 yes Fig.14 Another partial film layer cross-sectional structure diagram of the C region in (it can be understood that Fig.16 Only a partial film layer diagram of a first transistor, a second transistor, and a third transistor is schematically drawn in order to clearly illustrate the technical solution of the present embodiment. The first transistor, the second transistor, and the third transistor are drawn together for schematic illustration, and do not represent the actual setting positions of the first transistor, the second transistor, and the third transistor in the display panel. In specific implementation, the setting positions and connection relationships of the first transistor, the second transistor, and the third transistor are determined according to the layout of the driving circuit and the pixel circuit). In the present embodiment, the third transistor 60 is a switching transistor of the pixel circuit 40, wherein S2>S5.

[0086] This embodiment explains that the second area S2 defined by the second gate 30G of the second transistor 30 in the driving circuit 50 is larger than the fifth area S5 defined by the fifth gate 60G of the third transistor 60 in the pixel circuit 40. When the third transistor 60 of the oxide semiconductor transistor is a switch transistor of the pixel circuit 40, the third transistor 60 generally only plays the role of a switch. Therefore, the fifth area S5 defined by the fifth gate 60G of the third transistor 60 does not need to be set too large, and can be set smaller than the second area S2 defined by the second gate 30G of the second transistor 30 in the driving circuit 50, which can save the space of the panel and is conducive to further improving the PPI of the display panel 000. The driving circuit 50 is generally arranged at the left and right edges of the display panel 000, or only on a single edge of the display panel 000, or at other positions in the display panel 000. The space available for layout is relatively large, and the driving circuit 50 is used to provide signals to the pixel circuit 40, and the length L2 of the channel region of the second transistor 30 of the oxide semiconductor transistor is appropriately lengthened (such as Fig.16 As shown), the second area S2 defined by the second gate 30G of the second transistor 30 can be made larger, and the delay and distortion of the signal of the driving circuit 50 can be avoided as much as possible, which is beneficial to improving the reliability of the driving circuit 50.

[0087] Optional, such as Figure 8 As shown, Figure 8 It is a structural schematic diagram of a pixel circuit 40 provided in an embodiment of the present invention. The pixel circuit 40 includes multiple switching transistors and driving transistors, a storage capacitor, and a light-emitting diode OLED (7T1C). Taking the structure of the pixel circuit 40 as an example, the third transistor 60 of the oxide semiconductor transistor can be any one or more of the switching transistors M1, M2, M4, M5, M6, and M7 in the pixel circuit 40.

[0088] In some optional embodiments, please refer to Figure 8 , Fig.14 and Fig.17 , Fig.17 yes Fig.14 Another partial film layer cross-sectional structure diagram of the C region in (it can be understood that Fig.17 Only a partial film layer diagram of a first transistor, a second transistor, and a third transistor is schematically drawn in order to clearly illustrate the technical solution of the present embodiment. The first transistor, the second transistor, and the third transistor are drawn together for schematic illustration, and do not represent the actual setting positions of the first transistor, the second transistor, and the third transistor in the display panel. In specific implementation, the setting positions and connection relationships of the first transistor, the second transistor, and the third transistor are determined according to the layout of the driving circuit and the pixel circuit). In the present embodiment, the third transistor 60 is the driving transistor of the pixel circuit 40, wherein S2<S5.

[0089] This embodiment explains that the second area S2 defined by the second gate 30G of the second transistor 30 in the driving circuit 50 is smaller than the fifth area S5 defined by the fifth gate 60G of the third transistor 60 in the pixel circuit 40. When the third transistor 60 of the oxide semiconductor transistor is the driving transistor of the pixel circuit 40, since the driving transistor is a core component of the pixel circuit 40, it generally provides a driving current for the pixel circuit 40, and before providing a driving current for the display pixel 400 of the pixel circuit 40, it is necessary to store a data voltage signal through the gate of the driving transistor during the data writing stage. Therefore, in this embodiment, the fifth area S5 defined by the fifth gate 60G of the third transistor 60 used as the driving transistor is larger, and the length L5 of the channel region of the third transistor 60 of the oxide semiconductor transistor can be appropriately lengthened (such as Fig.17 As shown), the third transistor 60 used as a driving transistor can have a relatively stable threshold voltage and can also improve the stability of its gate potential, which is conducive to better realizing the gate storage data voltage signal of the driving transistor.

[0090] Optional, such as Figure 8 As shown, Figure 8 It is a structural schematic diagram of a pixel circuit 40 provided in an embodiment of the present invention. The pixel circuit 40 includes multiple switching transistors and driving transistors, a storage capacitor, and a light-emitting diode OLED (7T1C). Taking the structure of the pixel circuit 40 as an example, the third transistor 60 of the oxide semiconductor transistor can be the driving transistor M3 in the pixel circuit 40.

[0091] In some optional embodiments, please refer to Fig.14 and Fig.18 , Fig.18 yes Fig.14Another partial film layer cross-sectional structure diagram of the C region in the embodiment, in this embodiment, the third transistor 60 also includes a sixth gate 60G2, in the direction Z perpendicular to the substrate 10, the distance between the fifth gate 60G and the third active layer 601 is D5, the channel region of the third transistor 60 defined by the fifth gate 60G is the fifth channel region, the length of the fifth channel region is L5, and the fifth area S5=L5×D5; in the direction Z perpendicular to the substrate 10, the distance between the sixth gate 60G2 and the third active layer 601 is D6, D5<D6; the channel region of the third transistor 60 defined by the sixth gate 60G2 is the sixth channel region, the length of the sixth channel region is L6, the sixth channel region is the region where the third active layer 601 of the third transistor 60 overlaps with the sixth gate 60G2, and the length of the sixth channel region is the length of the sixth channel region of the third transistor 60 in the current transmission direction between the third source 60S and the third drain 60D. The channel region of the third transistor 60 defined by the sixth gate 60G2 is a sixth channel region, and the length of the sixth channel region is L6; the sixth area S6=L6×D6; wherein, S5<S6.

[0092] This embodiment explains that the third transistor 60 of the oxide semiconductor transistor in the pixel circuit 40 can be a dual-gate transistor, and the third transistor 60 includes a fifth gate 60G and a sixth gate 60G2. In the direction Z perpendicular to the substrate 10, the distance D6 between the sixth gate 60G2 and the third active layer 601 is greater than the distance D5 between the fifth gate 60G and the third active layer 601, that is, the third transistor 60 of the dual-gate structure includes two control gates, the fifth gate 60G is the main gate, and the sixth gate 60G2 is the auxiliary gate. From a structural point of view, it can be considered as a series connection of two single-gate transistors. The added sixth gate 60G2 has a certain shielding effect, which can make the feedback capacitance between the drain and the fifth gate 60G very small, which is beneficial to improving the display quality of the display panel. In addition, this embodiment is arranged in the direction Z perpendicular to the base substrate 10, and the distance D6 between the sixth gate 60G2 and the third active layer 601 is greater than the distance D5 between the fifth gate 60G and the third active layer 601, that is, the insulating layer between the sixth gate 60G2 and the third active layer 601 is arranged to be thicker, which can play a role in protecting the third active layer 601.

[0093] In some optional embodiments, please continue to refer to Figure 8 , Fig.14 and Fig.18 In this embodiment, the third transistor 60 is a switch transistor of the pixel circuit 40, wherein S6<S4.

[0094] This embodiment explains that when the third transistor 60 in the pixel circuit 40 is used as a switch transistor, compared with the second transistor 30 in the driving circuit 50, the sixth area S6 defined by the sixth gate 60G2 of the third transistor 60 with a dual-gate structure is smaller than the fourth area S4 defined by the fourth gate 30G2 of the second transistor 30 with a dual-gate structure. Since there are many pixel circuits in the display area of ​​the display panel 000 and the structure is relatively complex, in this embodiment, when the third transistor 60 is used as a switch transistor, the sixth gate 60G2 of the third transistor 60 in the pixel circuit 40 is made smaller than the fourth area S4 defined by the fourth gate 30G2 of the second transistor 30 with a dual-gate structure. The sixth area S6 defined by 0G2 is relatively small, which can reduce the load caused by the parasitic capacitance of the pixel circuit 40, which is beneficial to improving the response speed of the pixel circuit 40 and reducing the hysteresis problem; and the driving circuit 50 is generally arranged at the left edge and the right edge of the display panel 000, or only on a single edge of the display panel 000, or at other positions in the display panel 000, and the space available for layout is relatively large. Therefore, in this embodiment, the fourth area S4 defined by the fourth gate 30G2 of the second transistor 30 is relatively large, that is, S6<S4, which is beneficial to improving the reliability of the driving circuit 50.

[0095] Optional, such as Figure 8 As shown, Figure 8 It is a structural schematic diagram of a pixel circuit 40 provided in an embodiment of the present invention. The pixel circuit 40 includes multiple switching transistors and driving transistors, a storage capacitor, and a light-emitting diode OLED (7T1C). Taking the structure of the pixel circuit 40 as an example, the third transistor 60 of the oxide semiconductor transistor can be any one or more of the switching transistors M1, M2, M4, M5, M6, and M7 in the pixel circuit 40.

[0096] In some optional embodiments, please continue to refer to Figure 8 , Fig.14 and Fig.18 In this embodiment, the third transistor 60 is a switch transistor of the pixel circuit 40, wherein S4-S2>S6-S5.

[0097] This embodiment explains that when the third transistor 60 in the pixel circuit 40 is used as a switching transistor, compared with the second transistor 30 in the driving circuit 50, the difference between the sixth area S6 defined by the sixth gate 60G2 of the third transistor 60 of the dual-gate structure oxide semiconductor transistor and the fifth area S5 defined by the fifth gate 60G of the third transistor 60 is smaller than the difference between the fourth area S4 defined by the fourth gate 30G2 of the second transistor 30 of the dual-gate structure oxide semiconductor transistor and the second area S2 defined by the second gate 30G of the second transistor 30. Since there are many pixel circuits within the display area of ​​the display panel 000 and the structure is relatively complex, in this embodiment, when the third transistor 60 is used as a switching transistor, the sixth area S6 defined by the third transistor 60 in the pixel circuit 40 is smaller than the difference between the fourth area S4 defined by the fourth gate 30G2 of the second transistor 30 of the dual-gate structure oxide semiconductor transistor and the second area S2 defined by the second gate 30G of the second transistor 30. The sixth area S6 defined by the gate 60G2 and the fifth area S5 defined by the fifth gate 60G are both relatively small, that is, the difference between S6-S5 is also relatively small, which can reduce the load caused by the parasitic capacitance of the pixel circuit 40, which is beneficial to improving the response speed of the pixel circuit 40 and reducing the hysteresis problem; and the driving circuit 50 is generally arranged at the left edge and the right edge of the display panel 000, or only on a single edge of the display panel 000, or at other positions in the display panel 000, and the space available for layout is relatively large. Therefore, in this embodiment, the fourth area S4 defined by the fourth gate 30G2 of the second transistor 30 and the second area S2 defined by the second gate 30G are both relatively large, that is, the difference between S4-S2 is also relatively large, so that S4-S2>S6-S5, which is beneficial to improving the reliability of the driving circuit 50.

[0098] Optional, such as Figure 8 As shown, Figure 8 It is a structural schematic diagram of a pixel circuit 40 provided in an embodiment of the present invention. The pixel circuit 40 includes multiple switching transistors and driving transistors, a storage capacitor, and a light-emitting diode OLED (7T1C). Taking the structure of the pixel circuit 40 as an example, the third transistor 60 of the oxide semiconductor transistor can be any one or more of the switching transistors M1, M2, M4, M5, M6, and M7 in the pixel circuit 40.

[0099] In some optional embodiments, please refer to Figure 8 , Fig.14 and Fig.19 , Fig.19 yes Fig.14 Another partial film layer cross-sectional structure diagram of the C region in FIG. 1 , in this embodiment, the third transistor 60 is a driving transistor of the pixel circuit 40 , wherein S6>S4.

[0100] This embodiment explains that when the third transistor 60 in the pixel circuit 40 is used as a driving transistor, the fourth area S4 defined by the fourth gate 30G2 (auxiliary gate) of the second transistor 30 in the driving circuit 50 is smaller than the sixth area S6 defined by the sixth gate 60G2 (auxiliary gate) of the third transistor 60 in the pixel circuit 40. When the third transistor 60 of the oxide semiconductor transistor is the driving transistor of the pixel circuit 40, since the driving transistor is a core component of the pixel circuit 40, it generally provides a driving current for the pixel circuit 40, and before providing a driving current to the display pixel 400 of the pixel circuit 40, it is necessary to store a data voltage signal through the gate of the driving transistor during the data writing stage. Therefore, in this embodiment, the sixth area S6 defined by the sixth gate 60G2 (auxiliary gate) of the third transistor 60 used as the driving transistor is larger, and the length L6 of the channel region of the third transistor 60 of the oxide semiconductor transistor can be appropriately lengthened (such as Fig.19 As shown), the third transistor 60 used as a driving transistor can have a relatively stable threshold voltage, and the stability of the gate potential of the driving transistor can be improved, which is conducive to better realizing the gate storage data voltage signal of the driving transistor.

[0101] Optional, such as Figure 8 As shown, Figure 8 It is a structural schematic diagram of a pixel circuit 40 provided in an embodiment of the present invention. The pixel circuit 40 includes multiple switching transistors and driving transistors, a storage capacitor, and a light-emitting diode OLED (7T1C). Taking the structure of the pixel circuit 40 as an example, the third transistor 60 of the oxide semiconductor transistor can be the driving transistor M3 in the pixel circuit 40.

[0102] In some optional embodiments, please refer to Figure 8 , Fig.14 and Fig. 20 , Fig. 20 yes Fig.14 Another partial film layer cross-sectional structure diagram of the C region in the embodiment, in this embodiment, the pixel circuit 40 further includes a first capacitor C1, the first capacitor C1 is used to store the data voltage transmitted to the gate of the third transistor 60, wherein the sixth gate 60G2 (auxiliary gate) of the third transistor 60 is reused as a plate of the first capacitor C1, and optionally, the other plate of the first capacitor C1 can be in the same layer as other metal conductive film layers and is arranged opposite to the sixth gate 60G2, such as Fig. 20 As shown, the other plate of the first capacitor C1 can be arranged in the same layer as the first gate 20G of the first transistor 20.

[0103] This embodiment explains that the pixel circuit 40 may also include a first capacitor C1 used as a storage capacitor for storing the data voltage transmitted to the gate of the third transistor 60. The sixth gate 60G2 (auxiliary gate) of the third transistor 60 is reused as a plate of the first capacitor C1. Since the sixth area S6 defined by the sixth gate 60G2 (auxiliary gate) of the third transistor 60 in the pixel circuit 40 is larger than the fourth area S4 defined by the fourth gate 30G2 (auxiliary gate) of the second transistor 30 in the driving circuit 50, the relative areas of the two plates of the first capacitor C1 can be made larger, which is beneficial to improving the storage capacity of the first capacitor C1, so that the storage capacitor has better storage capacity, and the driving effect of the pixel circuit 40 is improved.

[0104] Optional, such as Figure 8 As shown, Figure 8 It is a structural schematic diagram of a pixel circuit 40 provided in an embodiment of the present invention. The pixel circuit 40 includes multiple switching transistors and driving transistors, a storage capacitor, and a light-emitting diode OLED (7T1C). Taking the structure of the pixel circuit 40 as an example, the first capacitor can be the storage capacitor Cst in the pixel circuit 40.

[0105] In some optional embodiments, please refer to Fig.14 and Fig.21 , Fig.21 yes Fig.14 Another partial film layer cross-sectional structure diagram of the C region in the embodiment, in this embodiment, the driving circuit 50 also includes a second capacitor C2, wherein the fourth gate 30G2 is reused as a plate of the second capacitor C2, and optionally, the other plate of the second capacitor C2 can be in the same layer as other metal conductive film layers and is arranged opposite to the fourth gate 30G2, such as Fig.21 As shown, the other plate of the second capacitor C2 can be arranged in the same layer as the first gate 20G of the first transistor 20, and the capacitance value of the first capacitor C1 is greater than the capacitance value of the second capacitor C2.

[0106] This embodiment explains that the driving circuit 50 also includes a second capacitor C2, and the second transistor 30 in the driving circuit 50 is electrically connected to the second capacitor C2, and the fourth gate 30G2 of the second transistor 30 can be reused as a plate of the second capacitor C2. In this embodiment, the capacitance value of the first capacitor C1 is set to be greater than the capacitance value of the second capacitor C2. Since the first capacitor C1 is a storage capacitor in the pixel circuit 40, it needs to play a role in storing data voltage signals, and the ability to store data voltage signals directly determines the driving current of the light-emitting element in the display pixel 400. Therefore, for the first capacitor C1 used as a storage capacitor in the pixel circuit 40, a larger capacitance value is required, which can enable the first capacitor C1 to have a higher storage capacity. The second capacitor C2 in the driving circuit 50 is generally set to stabilize the node potential, and the storage capacity requirement is lower than the first capacitor C1 used as a storage capacitor in the pixel circuit 40. Therefore, in this embodiment, the capacitance value of the first capacitor C1 is set to be greater than the capacitance value of the second capacitor C2, which can meet the requirements of the first capacitor C1 having a higher storage capacity and stabilizing the node potential in the driving circuit 50.

[0107] In some optional embodiments, please continue to refer to Figure 8 , Fig.14 and Fig.21 In this embodiment, the third transistor 60 is a driving transistor of the pixel circuit 40, wherein S4-S2<S6-S5.

[0108] This embodiment explains that when the third transistor 60 in the pixel circuit 40 is used as a driving transistor, compared with the second transistor 30 in the driving circuit 50, the difference between the sixth area S6 defined by the sixth gate 60G2 of the third transistor 60 of the dual-gate oxide semiconductor transistor and the fifth area S5 defined by the fifth gate 60G of the third transistor 60 is greater than the difference between the fourth area S4 defined by the fourth gate 30G2 of the second transistor 30 of the dual-gate oxide semiconductor transistor and the second area S2 defined by the second gate 30G of the second transistor 30, and the third transistor 60 of the oxide semiconductor transistor When the driving transistor is a driving transistor of the pixel circuit 40, since the driving transistor is a core component of the pixel circuit 40, it generally provides a driving current for the pixel circuit 40, and before providing a driving current for the display pixel 400 of the pixel circuit 40, it is necessary to store a data voltage signal through the gate of the driving transistor in the data writing stage. Therefore, in this embodiment, the sixth area S6 defined by the sixth gate 60G2 (auxiliary gate) of the third transistor 60 used as the driving transistor and the fifth area S5 defined by the fifth gate 60G are both large, and the lengths L5 and L6 of the channel region of the third transistor 60 of the oxide semiconductor transistor can be appropriately lengthened (such as Fig.21As shown), S6-S5>S4-S2, so that the third transistor 60 used as a driving transistor has a relatively stable threshold voltage, and can also improve the stability of the gate potential of the driving transistor, which is conducive to better realizing the gate storage data voltage signal of the driving transistor.

[0109] Optional, such as Figure 8 As shown, Figure 8 It is a structural schematic diagram of a pixel circuit 40 provided in an embodiment of the present invention. The pixel circuit 40 includes multiple switching transistors and driving transistors, a storage capacitor, and a light-emitting diode OLED (7T1C). Taking the structure of the pixel circuit 40 as an example, the third transistor 60 of the oxide semiconductor transistor can be the driving transistor M3 in the pixel circuit 40.

[0110] In some optional embodiments, please refer to Fig. 22 and Fig.23 , Fig. 22 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Fig.23 yes Fig. 22 The local film layer cross-sectional structure diagram of the D area in (it can be understood that Fig.23 Only partial film layer diagrams of a first transistor, a second transistor, a third transistor, and a fourth transistor are schematically drawn to clearly illustrate the technical solution of the present embodiment. The first transistor, the second transistor, the third transistor, and the fourth transistor are drawn together for schematic illustration, but do not represent the actual arrangement positions of the first transistor, the second transistor, the third transistor, and the fourth transistor in the display panel. In specific implementation, the arrangement positions and connection relationships of the first transistor, the second transistor, the third transistor, and the fourth transistor are determined according to the arrangement of the driving circuit and the pixel circuit). In the display panel 000 provided in the present embodiment, the pixel circuit 40 further includes a fourth transistor 70;

[0111] The fourth transistor 70 includes a seventh gate 70G, a fourth active layer 701, a fourth source 70S and a fourth drain 70D, and the fourth active layer 701 includes an oxide semiconductor;

[0112] In the direction Z perpendicular to the base substrate 10, the distance between the seventh gate 70G and the fourth active layer 701 is D7, the channel region of the fourth transistor 70 defined by the seventh gate 70G is the seventh channel region, the length of the seventh channel region is L7, and the seventh area S7=L7×D7;

[0113] The fourth transistor 70 also includes an eighth gate 70G2. In the direction Z perpendicular to the substrate 10, the distance between the eighth gate 70G2 and the fourth active layer 701 is D8. The channel region of the fourth transistor 70 defined by the eighth gate 70G2 is the eighth channel region. The length of the eighth channel region is L8, and the eighth area S8=L8×D8; wherein, D7<D8, S7<S8.

[0114] This embodiment explains that the pixel circuit 40 also includes a fourth transistor 70, and the fourth transistor 70 includes a seventh gate 70G, a fourth active layer 701, a fourth source 70S and a fourth drain 70D. The fourth active layer 701 contains an oxide semiconductor, that is, the fourth transistor 70 is an oxide semiconductor transistor, and the oxide semiconductor material is such as amorphous indium gallium zinc oxide, that is, IGZO (Indium Gallium Zinc Oxide). The channel region of the fourth transistor 70 defined by the seventh gate 70G of the fourth transistor 70 is the seventh channel region, and the length of the seventh channel region is L7, wherein the seventh channel region of the fourth transistor 70 is the region where the fourth active layer 701 of the fourth transistor 70 overlaps with the seventh gate 70G, and the length of the seventh channel region of the fourth transistor 70 is the length of the seventh channel region of the fourth transistor 70 in the current transmission direction between the fourth source 70S and the fourth drain 70D. The fourth transistor 70 can be a transistor with a dual-gate structure. The fourth transistor 70 also includes an eighth gate 70G2. In the direction Z perpendicular to the substrate 10, the distance between the eighth gate 70G2 and the fourth active layer 701 is D8. The channel region of the fourth transistor 70 defined by the eighth gate 70G2 is the eighth channel region, and the length of the eighth channel region is L8. The eighth channel region of the fourth transistor 70 is the region where the fourth active layer 701 of the fourth transistor 70 overlaps with the eighth gate 70G2, and the length of the eighth channel region of the fourth transistor 70 is the length of the eighth channel region of the fourth transistor 70 in the current transmission direction between the fourth source 70S and the fourth drain 70D. The pixel circuit 40 of the present embodiment may include a first transistor 20 of a silicon transistor with a dual-gate structure, a third transistor 60 of an oxide semiconductor transistor, and a fourth transistor 70 of an oxide semiconductor transistor, that is, the fourth transistor 70 of the dual-gate structure includes two control gates, the seventh gate 70G is the main gate, and the eighth gate 70G2 is the auxiliary gate. Structurally, it can be considered as a series connection of two single-gate transistors. The added eighth gate 70G2 has a certain shielding effect, which can make the feedback capacitance between the drain and the seventh gate 70G very small, which is beneficial to improving the display quality of the display panel.

[0115] This embodiment is arranged in the direction Z perpendicular to the base substrate 10, and the distance D7 between the seventh gate 70G (main gate) and the fourth active layer 701 is smaller than the distance D8 between the eighth gate 70G2 (auxiliary gate) and the fourth active layer 701. The seventh area S7 defined by the seventh gate 70G is smaller than the eighth area S8 defined by the eighth gate 70G2, so that the insulating layer between the eighth gate 70G2 and the fourth active layer 701 can be set thicker, which can protect the fourth active layer 701.

[0116] In some optional embodiments, please continue to refer to Figure 8 , Fig. 22 and Fig.23 In this embodiment, the third transistor 60 is a driving transistor, and the fourth transistor 70 is a switching transistor, wherein S6>S8.

[0117] This embodiment explains that when the third transistor 60 in the pixel circuit 40 is used as a driving transistor and the fourth transistor 70 is used as a switching transistor, the eighth area S8 defined by the eighth gate 70G2 (auxiliary gate) of the fourth transistor 70 is smaller than the sixth area S6 defined by the sixth gate 60G2 (auxiliary gate) of the third transistor 60. When the third transistor 60 of the oxide semiconductor transistor is the driving transistor of the pixel circuit 40, since the driving transistor is a core component of the pixel circuit 40, it generally provides a driving current for the pixel circuit 40, and before providing a driving current for the display pixel 400 of the pixel circuit 40, it is necessary to store a data voltage signal through the gate of the driving transistor during the data writing stage. Therefore, in this embodiment, the sixth area S6 defined by the sixth gate 60G2 (auxiliary gate) of the third transistor 60 used as the driving transistor is larger, and the length L6 of the channel region of the third transistor 60 of the oxide semiconductor transistor can be appropriately lengthened (such as Fig.23 As shown), the third transistor 60 used as a driving transistor can have a relatively stable threshold voltage, and the stability of the gate potential of the driving transistor can be improved, which is conducive to better realizing the gate storage data voltage signal of the driving transistor. When the fourth transistor 70 of the oxide semiconductor transistor is used as a switching transistor of the pixel circuit 40, the fourth transistor 70 generally only plays the role of a switch, so the eighth area S8 defined by the eighth gate 70G2 (auxiliary gate) of the fourth transistor 70 does not need to be set too large, which can save the space of the panel and is conducive to further improving the PPI of the display panel 000.

[0118] Optional, such as Figure 8 As shown, Figure 8It is a structural schematic diagram of a pixel circuit 40 provided in an embodiment of the present invention. The pixel circuit 40 includes multiple switching transistors and driving transistors, a storage capacitor, and a light-emitting diode OLED (7T1C). Taking the structure of the pixel circuit 40 as an example, the third transistor 60 of the oxide semiconductor transistor can be the driving transistor M3 in the pixel circuit 40, and the fourth transistor 70 of the oxide semiconductor transistor can be any one or more of the switching transistors M1, M2, M4, M5, M6, and M7 in the pixel circuit 40.

[0119] In some optional embodiments, please continue to refer to Figure 8 , Fig. 22 and Fig.23 In this embodiment, the third transistor 60 is a driving transistor, and the fourth transistor 70 is a switching transistor, wherein S6-S5>S8-S7.

[0120] This embodiment explains that when the third transistor 60 in the pixel circuit 40 is used as a driving transistor and the fourth transistor 70 is used as a switching transistor, the difference between the sixth area S6 defined by the sixth gate 60G2 of the third transistor 60 of the dual-gate oxide semiconductor transistor and the fifth area S5 defined by the fifth gate 60G of the third transistor 60 is greater than the difference between the eighth area S8 defined by the eighth gate 70G2 (auxiliary gate) of the fourth transistor 70 of the dual-gate oxide semiconductor transistor and the seventh area S7 defined by the seventh gate 70G of the fourth transistor 70, and the third transistor 60 of the oxide semiconductor transistor is When 0 is a driving transistor of the pixel circuit 40, since the driving transistor is a core component of the pixel circuit 40, it generally provides a driving current for the pixel circuit 40, and before providing a driving current for the display pixel 400 of the pixel circuit 40, it is necessary to store a data voltage signal through the gate of the driving transistor in the data writing stage. Therefore, in this embodiment, the sixth area S6 defined by the sixth gate 60G2 (auxiliary gate) of the third transistor 60 used as the driving transistor and the fifth area S5 defined by the fifth gate 60G are both large, and the lengths L5 and L6 of the channel region of the third transistor 60 of the oxide semiconductor transistor can be appropriately lengthened (such as Fig.23As shown), S6-S5>S8-S7, so that the third transistor 60 used as a driving transistor has a relatively stable threshold voltage, and can also improve the stability of the gate potential of the driving transistor, which is conducive to better realizing the gate storage data voltage signal of the driving transistor. When the fourth transistor 70 of the oxide semiconductor transistor is used as a switching transistor of the pixel circuit 40, the fourth transistor 70 generally only plays the role of a switch, so the seventh area S7 defined by the seventh gate 70G of the fourth transistor 70 and the eighth area S8 defined by the eighth gate 70G2 (auxiliary gate) do not need to be set too large, which can save the space of the panel and is conducive to further improving the PPI of the display panel 000.

[0121] Optional, such as Figure 8 As shown, Figure 8 It is a structural schematic diagram of a pixel circuit 40 provided in an embodiment of the present invention. The pixel circuit 40 includes multiple switching transistors and driving transistors, a storage capacitor, and a light-emitting diode OLED (7T1C). Taking the structure of the pixel circuit 40 as an example, the third transistor 60 of the oxide semiconductor transistor can be the driving transistor M3 in the pixel circuit 40, and the fourth transistor 70 of the oxide semiconductor transistor can be any one or more of the switching transistors M1, M2, M4, M5, M6, and M7 in the pixel circuit 40.

[0122] In some optional embodiments, please continue to refer to Fig. 22 and Fig.23 In this embodiment, in the pixel circuit 40, the difference between the sixth area S6 defined by the sixth gate 60G2 of the third transistor 60 of the dual-gate oxide semiconductor transistor and the fifth area S5 defined by the fifth gate 60G of the third transistor 60 is S6-S5; in the driving circuit 50, the difference between the fourth area S4 defined by the fourth gate 30G2 of the second transistor 30 of the dual-gate oxide semiconductor transistor and the second area S2 defined by the second gate 30G of the second transistor 30 is S4-S2; in the pixel circuit 40, the difference between the eighth area S8 defined by the eighth gate 70G2 (auxiliary gate) of the fourth transistor 70 of the dual-gate oxide semiconductor transistor and the seventh area S7 defined by the seventh gate 70G of the fourth transistor 70 is S8-S7, and (S6-S5)-(S8-S7)>(S8-S7)-(S4-S2), that is, (S6-S5)+(S4-S2)>2(S8-S7).

[0123] This embodiment explains that when the third transistor 60 in the pixel circuit 40 is used as a driving transistor, compared with the fourth transistor 70 used as a switching transistor in the pixel circuit 40, the difference between the sixth area S6 defined by the sixth gate 60G2 of the third transistor 60 of the dual-gate oxide semiconductor transistor and the fifth area S5 defined by the fifth gate 60G of the third transistor 60 is greater than the difference between the eighth area S8 defined by the eighth gate 70G2 of the fourth transistor 70 of the dual-gate oxide semiconductor transistor and the seventh area S7 defined by the seventh gate 70G of the fourth transistor 70. Since there are many pixel circuits with complex structures within the display area of ​​the display panel 000, in this embodiment, when the fourth transistor 70 is used as a switching transistor, the eighth area S8 defined by the eighth gate 70G2 of the fourth transistor 70 in the pixel circuit 40 and the seventh area S7 defined by the seventh gate 70G of the fourth transistor 70 are both smaller, that is, the difference S8-S7 is also smaller, which can reduce the load caused by the parasitic capacitance of the pixel circuit 40, which is beneficial to improving the response speed of the pixel circuit 40 and reducing the hysteresis problem. Since the eighth area S8 defined by the eighth gate 70G2 of the fourth transistor 70 and the seventh area S7 defined by the seventh gate 70G of the fourth transistor 70 are both relatively small, the difference between the eighth area S8 defined by the eighth gate 70G2 of the fourth transistor 70 of the dual-gate oxide semiconductor transistor and the seventh area S7 defined by the seventh gate 70G of the fourth transistor 70 is greater than the difference between the fourth area S4 defined by the fourth gate 30G2 of the second transistor 30 of the dual-gate oxide semiconductor transistor and the second area S2 defined by the second gate 30G of the second transistor 30. At the same time, the difference between (S8-S7) and (S4-S2) will not be set too large, that is, the difference between (S6-S5) and (S8-S7) is greater than the difference between (S8-S7) and (S4-S2), which is beneficial to improve the PPI of the display panel while also improving the reliability of the pixel circuit 40.

[0124] In some optional embodiments, please refer to Fig.24 , Fig.25 , Fig.24 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Fig.25 yes Fig.24 A partial enlarged view of the E region in FIG. Fig.25Only a partial top view of a first transistor and a second transistor is schematically drawn in order to clearly illustrate the technical solution of this embodiment. The first transistor and the second transistor are drawn together for schematic illustration, which does not represent the actual setting position of the first transistor and the second transistor in the display panel. In specific implementation, the setting position and connection relationship of the first transistor and the second transistor are determined according to the layout of the driving circuit and the pixel circuit). In this embodiment, the display panel 000 is a folding display panel, and the display panel 000 includes a bending axis 80 extending along the first direction Y, wherein the angle α2 between the length L2 direction of the channel region of the second transistor 30 and the first direction Y is greater than 45 degrees, and the angle α1 between the length L1 direction of the channel region of the first transistor 20 and the first direction Y is less than 45 degrees.

[0125] This embodiment explains that the first transistor 20 and the second transistor 30 of the display panel 000 are formed on the substrate 10, and the first transistor 20 includes a first active layer 201, a first gate 20G, a first source 20S and a first drain 20D. The first active layer 201 contains silicon, that is, the first transistor 20 is a silicon transistor, and the silicon can be polysilicon deposited by a low-temperature method, that is, LTPS (Low Temperature Poly-silicon) or low-temperature polysilicon. The length of the channel region of the first transistor 20 is L1, wherein the channel region of the first transistor 20 is the region where the first active layer 201 and the first gate 20G of the first transistor 20 overlap, and the length L1 of the channel region of the first transistor 20 is the current transmission direction of the channel region of the first transistor 20 between the first source 20S and the first drain 20D (such as Fig.25 The second transistor 30 includes a second active layer 301, a second gate 30G, a second source 30S and a second drain 30D. The second active layer 301 includes an oxide semiconductor, that is, the second transistor 30 is an oxide semiconductor transistor. The oxide semiconductor material is, for example, amorphous indium gallium zinc oxide, i.e., IGZO (Indium Gallium Zinc Oxide). The length of the channel region of the second transistor 30 is L2, wherein the channel region of the second transistor 30 is the region where the second active layer 301 of the second transistor 30 overlaps with the second gate 30G. The length of the channel region of the second transistor 30 is the current transmission direction (such as the channel region of the second transistor 30 between the second source 30S and the second drain 30D) of the second transistor 30. Fig.25The length in the direction X2). The display panel 000 of this embodiment can be a foldable display panel, which includes a bending axis 80 extending along a first direction Y, and an angle α2 between a length direction X2 of a channel region of the second transistor 30 and the first direction Y is greater than 45 degrees, and an angle α1 between a length direction X1 of a channel region of the first transistor 20 and the first direction Y is less than 45 degrees. The second transistor 30 of the oxide semiconductor transistor has better bending performance. Therefore, in this embodiment, an angle α2 between a length direction X2 of a channel region of the second transistor 30 and the first direction Y is set to be greater than 45 degrees, that is, the angle α2 is more inclined to 90 degrees, and an angle α1 between a length direction X1 of a channel region of the first transistor 20 and the first direction Y is less than 45 degrees, that is, the angle α1 is more inclined to 0 degrees. The second transistor 30 with better bending performance can pass through the area where the bending axis 80 is located as much as possible and bear a greater bending pressure, while the first transistor 20 with poorer bending performance can avoid passing through the area where the bending axis 80 is located as much as possible, so as to avoid failure of the first transistor 20 due to bending, which is beneficial to improving product yield.

[0126] In some optional embodiments, please refer to Fig.24 , Fig.26 , Fig.26 yes Fig.24 Another partial enlarged view of the E region in FIG. Fig.26 Only a partial top view of a first transistor and a second transistor is schematically drawn in order to clearly illustrate the technical solution of this embodiment. The first transistor and the second transistor are drawn together for schematic illustration, which does not represent the actual setting position of the first transistor and the second transistor in the display panel. In specific implementation, the setting position and connection relationship of the first transistor and the second transistor are determined according to the layout of the driving circuit and the pixel circuit). In this embodiment, the length direction X2 of the channel region of the second transistor 30 is perpendicular to the first direction Y; the length direction X1 of the channel region of the first transistor 20 is parallel to the first direction Y.

[0127] This embodiment explains that the first transistor 20 and the second transistor 30 of the display panel 000 are formed on the substrate 10, and the first transistor 20 includes a first active layer 201, a first gate 20G, a first source 20S and a first drain 20D. The first active layer 201 contains silicon, that is, the first transistor 20 is a silicon transistor, and the silicon can be polysilicon deposited by a low-temperature method, that is, LTPS (Low Temperature Poly-silicon) or low-temperature polysilicon. The length of the channel region of the first transistor 20 is L1, wherein the channel region of the first transistor 20 is the region where the first active layer 201 and the first gate 20G of the first transistor 20 overlap, and the length L1 of the channel region of the first transistor 20 is the current transmission direction of the channel region of the first transistor 20 between the first source 20S and the first drain 20D (such as Fig.26 The second transistor 30 includes a second active layer 301, a second gate 30G, a second source 30S and a second drain 30D. The second active layer 301 includes an oxide semiconductor, that is, the second transistor 30 is an oxide semiconductor transistor. The oxide semiconductor material is, for example, amorphous indium gallium zinc oxide, i.e., IGZO (Indium Gallium Zinc Oxide). The length of the channel region of the second transistor 30 is L2, wherein the channel region of the second transistor 30 is the region where the second active layer 301 of the second transistor 30 overlaps with the second gate 30G. The length of the channel region of the second transistor 30 is the current transmission direction (such as the channel region of the second transistor 30 between the second source 30S and the second drain 30D) of the second transistor 30. Fig.26 The display panel 000 of this embodiment may be a foldable display panel, which includes a bending axis 80 extending along a first direction Y, and the length direction X2 of the channel region of the second transistor 30 is perpendicular to the first direction, and the length direction X1 of the channel region of the first transistor 20 is parallel to the first direction Y. The second transistor 30 of the oxide semiconductor transistor has better bending performance. Therefore, in this embodiment, the angle between the length direction X2 of the channel region of the second transistor 30 and the first direction Y is set to 90 degrees, and the angle between the length direction X1 of the channel region of the first transistor 20 and the first direction Y is 0 degrees, which can further make the second transistor 30 with better bending performance pass through the area where the bending axis 80 is located as much as possible, and bear greater bending pressure, while the first transistor 20 with poor bending performance tries to avoid passing through the area where the bending axis 80 is located, which can better avoid the failure of the first transistor 20 due to bending and ensure product yield.

[0128] In some alternative embodiments, please refer to Fig. 27 , Fig. 271 is a schematic diagram of a planar structure of a display device provided in an embodiment of the present invention. The display device 111 provided in this embodiment includes the display panel 000 provided in the above embodiment of the present invention. Fig. 27 The embodiment only takes a mobile phone as an example to illustrate the display device 111. It can be understood that the display device 111 provided in the embodiment of the present invention can be a computer, a television, a car display device or other display device 111 with a display function, and the present invention does not specifically limit this. The display device 111 provided in the embodiment of the present invention has the beneficial effects of the display panel 000 provided in the embodiment of the present invention. For details, please refer to the specific description of the display panel 000 in the above embodiments, and this embodiment will not be repeated here.

[0129] It can be seen from the above embodiments that the display panel and the display device provided by the present invention achieve at least the following beneficial effects:

[0130] The display panel provided by the present invention is arranged in a direction perpendicular to the substrate, the distance between the first gate of the first transistor and the first active layer is D1, and the first area S1=L1×D1; the distance between the second gate of the second transistor and the second active layer is D2, and the second area S2=L2×D2; and S1<S2. Since the first transistor of the silicon transistor has good response capability, in order to fully improve the PPI of the display panel, the present invention utilizes the respective advantages of silicon transistors and oxide semiconductor transistors, and designs the lengths of the channel regions of the two types of transistors to be as small as possible, which is beneficial to saving circuit space and further beneficial to improving the PPI of the display panel. The present invention is arranged in a direction perpendicular to the base substrate of the display panel, and the first area S1 is less than the second area S2, wherein the first area S1=L1×D1, the second area S2=L2×D2, the spacing between the first gate of the first transistor of the silicon transistor and the first active layer is D1, and the spacing between the second gate of the second transistor of the oxide semiconductor transistor and the second active layer is D2, so that the respective characteristics and advantages of the silicon transistor and the oxide semiconductor transistor can be fully utilized, while ensuring the stability and normal operation of the transistor, saving the space of the display panel, improving the PPI of the display panel, and then helping to improve the display quality of the display panel, making the display effect more superior, and making the product more competitive.

[0131] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that the above embodiments may be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A display panel, characterized in that: include: substrate substrate; a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are formed on the substrate, the third transistor comprises a sixth gate, a third active layer, a third source and a third drain, and the third active layer comprises an oxide semiconductor; the fourth transistor comprises an eighth gate, a fourth active layer, a fourth source and a fourth drain, and the fourth active layer comprises an oxide semiconductor; In a direction perpendicular to the substrate, a distance between the sixth gate and the third active layer is D6, a channel region of the third transistor defined by the sixth gate is a sixth channel region, a length of the sixth channel region is L6, and a sixth area S6=L6×D6; In a direction perpendicular to the substrate, a distance between the eighth gate and the fourth active layer is D8, a channel region of the fourth transistor defined by the eighth gate is an eighth channel region, a length of the eighth channel region is L8, and an eighth area S8=L8×D8; The display panel includes a pixel circuit and a driving circuit for providing a driving signal to the pixel circuit, wherein the third transistor is a driving transistor of the pixel circuit, and the fourth transistor is a switching transistor of the pixel circuit; wherein, S6>S8.

2. The display panel according to claim 1, characterized in that: The third transistor includes a fifth gate, a third active layer, a third source and a third drain, wherein the third active layer includes an oxide semiconductor; In a direction perpendicular to the substrate, the distance between the fifth gate and the third active layer is D5, the channel region of the third transistor defined by the fifth gate is the fifth channel region, the length of the fifth channel region is L5, and the fifth area S5=L5×D5; wherein D5<D6, and / or, S5<S6.

3. The display panel according to claim 1, characterized in that: The fourth transistor includes a seventh gate, a fourth active layer, a fourth source and a fourth drain, wherein the fourth active layer includes an oxide semiconductor; In a direction perpendicular to the substrate, the distance between the seventh gate and the fourth active layer is D7, the channel region of the fourth transistor defined by the seventh gate is the seventh channel region, the length of the seventh channel region is L7, and the seventh area S7=L7×D7; wherein, D7<D8, and / or, S7<S8.

4. The display panel according to claim 3, characterized in that: The third transistor includes a fifth gate, a third active layer, a third source and a third drain, wherein the third active layer includes an oxide semiconductor; In a direction perpendicular to the substrate, the distance between the fifth gate and the third active layer is D5, the channel region of the third transistor defined by the fifth gate is the fifth channel region, the length of the fifth channel region is L5, and the fifth area S5=L5×D5; wherein S6-S5>S8-S7.

5. The display panel according to claim 3, characterized in that: The pixel circuit or the driving circuit includes a second transistor, the second transistor includes a second active layer, a second gate, a second source and a second drain, and the second active layer includes an oxide semiconductor; The length of the channel region of the second transistor is L2, and in a direction perpendicular to the substrate, the distance between the second gate and the second active layer is D2, S2 = L2 × D2; The third transistor includes a fifth gate, a third active layer, a third source and a third drain, wherein the third active layer includes an oxide semiconductor; In a direction perpendicular to the substrate, a distance between the fifth gate and the third active layer is D5, a channel region of the third transistor defined by the fifth gate is a fifth channel region, a length of the fifth channel region is L5, and a fifth area S5=L5×D5; S2<S5.

6. The display panel according to claim 5, characterized in that: The second transistor further includes a fourth gate, and in a direction perpendicular to the substrate, a distance D4 between the fourth gate and the second active layer; A channel region of the second transistor defined by the second gate is a second channel region, and a length of the second channel region is L2; The channel region of the second transistor defined by the fourth gate is a fourth channel region, and the length of the fourth channel region is L4; wherein the fourth area S4=L4×D4; D2<D4, and / or, S2<S4.

7. The display panel according to claim 6, characterized in that: S6>S4.

8. The display panel according to claim 6, characterized in that: S4-S2<S6-S5.

9. The display panel according to claim 6, characterized in that: (S6-S5)+(S4-S2)>2×(S8-S7).

10. The display panel according to claim 2, characterized in that: The display panel further includes a first transistor, the pixel circuit includes the first transistor or the driving circuit includes the first transistor; The first transistor includes a first active layer, a first gate, a first source and a first drain, the first active layer includes silicon; the length of the channel region of the first transistor is L1, the distance between the first gate and the first active layer in a direction perpendicular to the substrate is D1, and the first area S1=L1×D1; wherein, S1<S5.

11. The display panel according to claim 10, characterized in that: The pixel circuit or the driving circuit includes a second transistor, the second transistor includes a second active layer, a second gate, a second source and a second drain, and the second active layer includes an oxide semiconductor; The length of the channel region of the second transistor is L2, and in a direction perpendicular to the substrate, the distance between the second gate and the second active layer is D2, S2 = L2 × D2; S1<S2.

12. The display panel according to claim 1, characterized in that: The pixel circuit further includes a first capacitor, and the first capacitor is used to store a data voltage transmitted to the gate of the third transistor, wherein: The sixth gate is multiplexed as a plate of the first capacitor.

13. The display panel according to claim 1, characterized in that: The display panel is a folding display panel, which includes a bending axis extending along a first direction, wherein the angle between the length direction of the channel region of the second transistor and the first direction is greater than 45 degrees, and the angle between the length direction of the channel region of the first transistor and the first direction is less than 45 degrees.

14. The display panel according to claim 13, characterized in that: A length direction of a channel region of the second transistor is perpendicular to the first direction; A length direction of a channel region of the first transistor is parallel to the first direction.

15. A display panel, characterized in that: include: substrate substrate; a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are formed on the substrate, the third transistor comprises a sixth gate, a third active layer, a third source and a third drain, and the third active layer comprises an oxide semiconductor; the fourth transistor comprises an eighth gate, a fourth active layer, a fourth source and a fourth drain, and the fourth active layer comprises an oxide semiconductor; In a direction perpendicular to the substrate, a distance between the sixth gate and the third active layer is D6, a channel region of the third transistor defined by the sixth gate is a sixth channel region, a length of the sixth channel region is L6, and a sixth area S6=L6×D6; In a direction perpendicular to the substrate, a distance between the eighth gate and the fourth active layer is D8, a channel region of the fourth transistor defined by the eighth gate is an eighth channel region, a length of the eighth channel region is L8, and an eighth area S8=L8×D8; S6>S8.

16. The display panel according to claim 15, characterized in that: The third transistor includes a fifth gate, a third active layer, a third source and a third drain, wherein the third active layer includes an oxide semiconductor; In a direction perpendicular to the substrate, the distance between the fifth gate and the third active layer is D5, the channel region of the third transistor defined by the fifth gate is the fifth channel region, the length of the fifth channel region is L5, and the fifth area S5=L5×D5; wherein D5<D6, and / or, S5<S6.

17. The display panel according to claim 15, characterized in that: The fourth transistor includes a seventh gate, a fourth active layer, a fourth source and a fourth drain, wherein the fourth active layer includes an oxide semiconductor; In a direction perpendicular to the substrate, the distance between the seventh gate and the fourth active layer is D7, the channel region of the fourth transistor defined by the seventh gate is the seventh channel region, the length of the seventh channel region is L7, and the seventh area S7=L7×D7; wherein, D7<D8, and / or, S7<S8.

18. The display panel according to claim 17, characterized in that: The third transistor includes a fifth gate, a third active layer, a third source and a third drain, wherein the third active layer includes an oxide semiconductor; In a direction perpendicular to the substrate, the distance between the fifth gate and the third active layer is D5, the channel region of the third transistor defined by the fifth gate is the fifth channel region, the length of the fifth channel region is L5, and the fifth area S5=L5×D5; wherein S6-S5>S8-S7.

19. The display panel according to claim 17, characterized in that: The pixel circuit or the driving circuit includes a second transistor, the second transistor includes a second active layer, a second gate, a second source and a second drain, and the second active layer includes an oxide semiconductor; The length of the channel region of the second transistor is L2, and in a direction perpendicular to the substrate, the distance between the second gate and the second active layer is D2, S2 = L2 × D2; The third transistor includes a fifth gate, a third active layer, a third source and a third drain, wherein the third active layer includes an oxide semiconductor; In a direction perpendicular to the substrate, a distance between the fifth gate and the third active layer is D5, a channel region of the third transistor defined by the fifth gate is a fifth channel region, a length of the fifth channel region is L5, and a fifth area S5=L5×D5; S2<S5.

20. The display panel according to claim 19, characterized in that: The second transistor further includes a fourth gate, and in a direction perpendicular to the substrate, a distance D4 between the fourth gate and the second active layer; A channel region of the second transistor defined by the second gate is a second channel region, and a length of the second channel region is L2; The channel region of the second transistor defined by the fourth gate is a fourth channel region, and the length of the fourth channel region is L4; wherein the fourth area S4=L4×D4; D2<D4, and / or, S2<S4.

21. The display panel according to claim 20, characterized in that: S6>S4.

22. The display panel according to claim 20, characterized in that: S4-S2<S6-S5.

23. The display panel according to claim 20, characterized in that: (S6-S5)+(S4-S2)>2×(S8-S7).

24. The display panel according to claim 16, characterized in that: The display panel further includes a first transistor, the pixel circuit includes the first transistor or the driving circuit includes the first transistor; The first transistor includes a first active layer, a first gate, a first source and a first drain, the first active layer includes silicon; the length of the channel region of the first transistor is L1, the distance between the first gate and the first active layer in a direction perpendicular to the substrate is D1, and the first area S1=L1×D1; wherein, S1<S5.

25. The display panel according to claim 24, characterized in that: The pixel circuit or the driving circuit includes a second transistor, the second transistor includes a second active layer, a second gate, a second source and a second drain, and the second active layer includes an oxide semiconductor; The length of the channel region of the second transistor is L2, and in a direction perpendicular to the substrate, the distance between the second gate and the second active layer is D2, S2 = L2 × D2; S1<S2.

26. The display panel according to claim 15, characterized in that: The pixel circuit further includes a first capacitor, and the first capacitor is used to store a data voltage transmitted to the gate of the third transistor, wherein: The sixth gate is multiplexed as a plate of the first capacitor.

27. A display device, characterized in that: A display panel comprising any one of claims 1-26.

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