Solar cell, preparation method thereof and solar cell module

Abstract

The invention discloses a solar cell and a preparation method thereof and a solar cell module, the solar cell comprises a silicon substrate, the solar cell is provided with a metal grid line contact area and a non-metal grid line contact area, a plurality of hollowed-out grooves arranged in an array are formed in the non-metal grid line contact area, and the metal grid line contact area is connected with the non-metal grid line contact area. And each hollow groove sequentially penetrates through the passivation layer, the poly layer and the dielectric layer on the back surface of the silicon substrate in the thickness direction of the solar cell. According to the solar cell provided by the invention, the use amount of Poly-Si materials in the areas where the hollowed-out grooves are formed can be effectively reduced through the plurality of hollowed-out grooves formed in the array in the non-metal grid line contact area, so that parasitic absorption is effectively reduced, the photoelectric conversion efficiency is improved, and the photoelectric conversion efficiency is improved. As the whole surface of the solar cell does not need to be subjected to laser treatment, the thermal damage risk of the solar cell is reduced.

Description

Technical Field

[0001] The invention relates to the technical field of solar cells, and in particular to a solar cell and a preparation method thereof, and a solar cell assembly. Background Art

[0002] Related technologies point out that traditional crystalline silicon solar cells, such as aluminum back surface field (Al-BSF) cells, are limited by surface recombination losses and metal contact resistance, making it difficult to further improve conversion efficiency. Traditional cell designs have room for improvement in light capture, especially in reducing reflections and optimizing incident light paths. By introducing selective contacts formed by tunneling oxide layers and polysilicon layers, the TOPCon structure significantly reduces the surface recombination velocity and increases the open circuit voltage.

[0003] The optimized current collection path reduces the series resistance, improves the fill factor (FF), and thus improves the overall conversion efficiency; through the use of texturing, anti-reflective coating and other means, TOPCon cells can better absorb photons and increase the short-circuit current density (Jsc). As the global demand for clean energy continues to increase, the market demand for high-efficiency solar cells is also growing.

[0004] Although TOPCon technology increases the complexity of the process, through large-scale production and process optimization, the cost can be reduced, making it more competitive in the market; the high efficiency and low temperature coefficient of TOPCon batteries make them perform well under various environmental conditions and meet the requirements of sustainable development. However, the current TOPCon batteries have problems such as uneven stress distribution and fragmentation. Summary of the invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention is to provide a solar cell, which can adjust the stress distribution and reduce the fragmentation problem.

[0006] The invention also provides a method for preparing the solar cell.

[0007] The present invention also provides a solar cell assembly having the solar cell.

[0008] According to the first aspect of the present invention, the solar cell comprises: a silicon substrate, the front side of the silicon substrate being sequentially an emitter layer, a passivation layer and a metal contact layer in the direction away from the silicon substrate, the back side of the silicon substrate being sequentially a dielectric layer, a poly layer, a passivation layer and a metal contact layer in the direction away from the silicon substrate, the solar cell having a metal grid line contact area and a non-metal grid line contact area, a plurality of hollow grooves arranged in an array are formed in the non-metal grid line contact area, each of the hollow grooves sequentially penetrates the passivation layer, the poly layer and the dielectric layer on the back side of the silicon substrate in the thickness direction of the solar cell.

[0009] According to the solar cell of the present invention, by forming a plurality of hollow grooves arranged in an array in the non-metallic grid line contact area, the amount of Poly-Si material used in the area where the hollow grooves are located can be effectively reduced, thereby effectively reducing parasitic absorption and improving photoelectric conversion efficiency. In addition, since there is no need to perform laser processing on the entire surface of the solar cell, the risk of thermal damage to the solar cell is reduced.

[0010] In some embodiments, the ratio of the total area of ​​the hollow grooves to the area of ​​the non-metallic gate line contact region is 0.2-1.

[0011] In some embodiments, the depth of the hollow groove is 1 μm-5 μm.

[0012] In some embodiments, the distance between each two adjacent hollow grooves is 30 μm-100 μm.

[0013] In some embodiments, a size of each of the hollow grooves in a width direction of the solar cell is 30 μm-500 μm, and / or a size of each of the hollow grooves in a length direction of the solar cell is 30 μm-500 μm.

[0014] In some embodiments, the silicon substrate is an N-type silicon substrate.

[0015] In some embodiments, the size of each of the hollow grooves is consistent.

[0016] The method for preparing a solar cell according to the second aspect of the present invention is used to produce the solar cell according to the first aspect of the present invention, and the method comprises:

[0017] Step S1, texturing the surface of the silicon substrate;

[0018] Step S2, diffusing boron into the silicon substrate to form a PN junction, and cleaning and oxidizing the back side of the silicon substrate to form a dielectric layer;

[0019] Step S3, performing alkali polishing on the silicon substrate to remove the borosilicate glass and the boron diffusion layer on the back side of the silicon substrate;

[0020] Step S4, forming a poly layer on the surface of the dielectric layer facing away from the silicon substrate by low pressure chemical vapor deposition;

[0021] Step S5, performing phosphorus doping treatment on the poly layer;

[0022] Step S6, forming a hollow groove on the back side of the silicon substrate by laser;

[0023] Step S7, removing the phosphosilicate glass on the silicon substrate and etching the silicon substrate;

[0024] Step S8, depositing an aluminum oxide layer on the silicon substrate by ALD to form a passivation layer;

[0025] Step S9, coating the front surface of the silicon substrate;

[0026] Step S10, coating the back of the silicon substrate;

[0027] Step S11 : printing a first fine grid on the back side of the solar cell, and printing a second fine grid on the front side of the solar cell.

[0028] According to the method for preparing solar cells of the present invention, the solar cells of the first aspect mentioned above reduce the fragmentation problem of solar cells by using the preparation method of the present invention, while ensuring the optimal balance between optical performance and electrical performance, effectively reducing surface recombination losses, improving conversion efficiency, and having better temperature coefficient and bifaciality, thereby improving the overall performance of the solar cell.

[0029] In some embodiments, the power of the laser is 60W-100W, and / or the usage ratio of the laser power is 10%-100%.

[0031] A solar cell module according to a third aspect of the present invention comprises a plurality of solar cells according to the first aspect of the present invention.

[0032] According to the solar cell assembly of the present invention, by arranging a plurality of solar cells according to the first aspect of the present invention, the energy conversion efficiency of the solar cell assembly is improved, the performance of the solar cell assembly is enhanced, the power generation and land space utilization rate are increased, the production and installation costs are reduced, and the economic benefits are ensured.

[0033] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1is a schematic structural diagram of a solar cell according to an embodiment of the first aspect of the present invention;

[0035] Figure 2 yes Figure 1 Schematic diagram of the hollow groove of the solar cell shown in;

[0036] Figure 3 is a flow chart of a method for preparing a solar cell according to an embodiment of the second aspect of the present invention.

[0037] Reference numerals:

[0038] 100. Solar cell; 1. Silicon substrate; 2. Emitter layer; 3. Passivation layer; 4. Metal contact layer; 5. Dielectric layer; 6. Poly layer; 7. Hollow groove; 8. Metal grid line contact area; 9. Non-metal grid line contact area. DETAILED DESCRIPTION

[0039] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0040] Reference below Figure 1 and Figure 2 A solar cell 100 according to an embodiment of the first aspect of the present invention is described.

[0041] like Figure 1 and Figure 2 As shown, a solar cell 100 according to an embodiment of the first aspect of the present invention includes: a silicon substrate 1.

[0042] Specifically, the front side of the silicon substrate 1 in the direction away from the silicon substrate 1 comprises an emitter layer 2, a passivation layer 3 and a metal contact layer 4 in sequence, and the back side of the silicon substrate 1 in the direction away from the silicon substrate 1 comprises a dielectric layer 5, a poly layer 6, a passivation layer 3 and a metal contact layer 4 in sequence, and the solar cell 100 has a metal grid line contact area 8 and a non-metal grid line contact area 9, and a plurality of hollow grooves 7 arranged in an array are formed in the non-metal grid line contact area 9, and each hollow groove 7 penetrates the passivation layer 3, the poly layer 6 and the dielectric layer 5 on the back side of the silicon substrate 1 in sequence in the thickness direction of the solar cell 100.

[0043] It is understood that the silicon substrate 1, as the basic material of the battery, is usually an N-type or P-type doped single crystal silicon wafer. The emitter layer 2 is located on the front of the silicon substrate 1, which is usually a highly doped n+ or p+ layer for forming a pn junction; the passivation layer 3 covers the emitter layer 2 to reduce the surface recombination rate and improve the battery efficiency; the metal contact layer 4 is the outermost layer, used for current collection, and is composed of fine grid lines. It is understood that the metal contact layer can also include main grid lines. The poly layer 6 is a polycrystalline silicon layer, which combines with the dielectric layer 5 to form a selective contact, which helps to improve carrier transport and provide a good passivation effect; the passivation layer 3 is similar to the passivation layer 3 on the front, but its function is to protect the poly layer 6 and the dielectric layer 5 and further reduce surface recombination; the metal contact layer 4 is used for current collection on the back.

[0044] The metal gate line contact area 8 is the actual current collection area; the non-metal gate line contact area 9 refers to the area without direct metal contact. The hollow grooves 7 (also called local grooves) in these areas penetrate all the layers on the back side to the surface of the silicon substrate 1. The purpose of the local grooves is to retain the passivation effect of part of the poly layer 6 and the dielectric layer 5 without affecting the current collection ability of the metal contact area.

[0045] When the solar cell 100 is subjected to processes such as heat treatment or chemical vapor deposition, there are uneven conditions in the flow rate and distribution of the special gas in the furnace tube, resulting in a more sufficient supply of reactants near the gas inlet, thereby making the passivation layer formation quality of the solar cell 100 uneven; in the production process of the solar cell 100, automated tools are used to process the silicon substrate 1 (such as cutting, printing electrodes, etc.), and there are cases where surface damage is caused due to equipment accuracy problems or improper operation, thereby affecting the passivation effect; in the heat treatment step, due to the existence of a temperature gradient, the temperature difference at different positions of the solar cell 100 will affect the passivation quality.

[0046] According to the solar cell 100 of the embodiment of the present invention, the plurality of hollow grooves 7 arranged in an array formed in the non-metallic grid line contact area 9 can effectively reduce the amount of Poly-Si material in the area where the hollow grooves 7 are located, thereby effectively reducing parasitic absorption and improving the photoelectric conversion efficiency. In addition, since there is no need to perform laser processing on the entire surface of the solar cell 100, the risk of thermal damage to the solar cell 100 is reduced.

[0047] Specifically, in the solar cell 100, a capacitor is formed between the Poly layer 6 and the underlying silicon substrate 1. Here, the capacitor is caused by the dielectric layer between the two conductive layers. When the thickness or coverage area of ​​the Poly layer 6 decreases, the capacitance between the Poly layer 6 and the silicon substrate 1 will also decrease accordingly. Therefore, when the solar cell 100 is working, less energy is stored between the Poly layer 6 and the silicon substrate 1, thereby improving the conversion efficiency of the solar cell 100. In addition, reducing the amount of unnecessary Poly-Si material can shorten the current path, thereby reducing the series resistance, increasing the fill factor, and thereby improving the overall performance of the solar cell 100.

[0048] Furthermore, the conventional full-layer removal treatment method will damage the passivation layer 3 on the surface of the solar cell 100, resulting in an increase in the interface state density, thereby reducing the open-circuit voltage and the overall performance and efficiency of the solar cell 100. Compared with the conventional full-layer removal treatment method, the surface of the Poly layer 6 of the solar cell 100 of the embodiment of the present invention can retain part of the passivation layer 3 as much as possible by forming a hollow groove 7, thereby reducing the reduction of the open-circuit voltage and reducing the carrier recombination loss. Moreover, by retaining the Poly layer 6 in the area with higher current density, a lower contact resistivity can be provided, reducing the series resistance, thereby improving the fill factor. Removing the Poly layer 6 in the low current density area can reduce the recombination probability of photogenerated carriers, maintain a higher open-circuit voltage, and thus improve the overall efficiency of the solar cell 100.

[0049] The whole-layer uniform thinning treatment method means that the thickness of the Poly layer 6 removed from the battery is consistent, that is, the surface of the solar cell 100 is still completely covered with the Poly layer 6. In this way, in the solar cell 100, the capacitance value of the capacitor formed between the Poly layer 6 and the silicon substrate 1 below is large, which causes the battery to react slowly to rapidly changing light conditions or load requirements, and also becomes a recombination center for carriers, resulting in unnecessary recombination losses, reducing the open circuit voltage (Voc) and short-circuit current density, and, in a high temperature environment, the capacitance value may change, affecting the stability and long-term reliability of the battery, especially in an outdoor environment, where changes in ambient temperature can cause unstable capacitance characteristics, thereby affecting battery performance. Compared with the whole-layer thinning treatment method, the solar cell 100 of the embodiment of the present invention reduces the capacitance between the Poly layer 6 and the silicon substrate 1 by forming a hollow groove 7 on the surface, improves the battery's response speed to rapidly changing light regulation or load requirements, reduces carrier recombination losses, effectively reduces parasitic absorption, reduces the degree of change in capacitance value, ensures the stability and reliability of the battery, and improves the photoelectric conversion efficiency.

[0050] It should be noted here that the silicon substrate 1 described in the embodiment of the present invention is an N-type single crystal silicon wafer, and the silicon substrate 1 described below is all an N-type silicon substrate. It can be understood that the silicon substrate can also be a P-type single crystal silicon wafer.

[0051] In some embodiments of the present invention, the ratio of the total area of ​​the hollow grooves 7 to the area of ​​the non-metallic grid line contact area 9 is 0.2-1. It can be understood that the hollow grooves 7 with a suitable ratio can retain the passivation layer 3 as much as possible, reduce the reduction of the open circuit voltage, reduce the carrier recombination loss, and by retaining the Poly layer 6 in the area with higher current density, it can provide a lower contact resistivity, reduce the series resistance, and thus improve the fill factor. Removing the Poly layer 6 in the low current density area can reduce the recombination probability of photogenerated carriers, maintain a higher open circuit voltage, and thus improve the overall efficiency of the solar cell 100.

[0052] Specifically, the ratio of the total area of ​​the hollow grooves 7 to the area of ​​the non-metallic gate line contact region 9 can be any value between 0.2 and 1, for example, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1.0, etc.

[0053] In some embodiments of the present invention, the depth of the hollow groove 7 is 1 μm-5 μm. It is understood that the appropriate depth of the hollow groove 7 ensures the effective removal of the poly layer 6 and the dielectric layer 5, thereby allowing electrons or holes to smoothly reach the back metal contact layer 4. By removing the poly layer 6 and the dielectric layer 5, a low resistance path is formed, so that carriers can be more smoothly transferred from the silicon substrate to the back metal contact layer 4.

[0054] Specifically, if the hollow groove 7 is too shallow, the Poly layer 6 and the dielectric layer 5 are not completely removed, and the remaining materials will form a high resistance path, which will prevent the carriers (electrons or holes) from smoothly reaching the back metal contact layer 4 from the silicon substrate, significantly increase the series resistance, reduce the fill factor (FF), and thus reduce the overall current output. The incompletely removed Poly layer and dielectric layer may introduce additional interface states, become the recombination center of the carriers, and lead to more recombination losses, reduce the open circuit voltage (Voc) and short circuit current density (Jsc), and weaken the overall conversion efficiency of the battery. In addition, the residual Poly layer and dielectric layer may lead to insufficient surface passivation effect, increase the surface state density, affect the carrier transmission, and increase unnecessary recombination losses, further reducing the battery performance.

[0055] If the hollow groove is too deep, the silicon substrate 1 itself may be damaged, surface defects may be increased, resulting in higher composite losses, lower open circuit voltage and fill factor, change surface morphology, affect the incident angle and path of light, and be detrimental to light absorption.

[0056] Therefore, the appropriate depth of the hollow groove 7 helps to reduce the reflection of light in the contact area, increase the chance of photons entering the silicon substrate 1, and thus increase the short-circuit current density. In addition, the depth of the hollow groove 7 will also affect the stress distribution. A reasonable depth can disperse the stress and reduce the fragmentation problem. However, if the hollow groove 7 is too deep, it may weaken the mechanical strength of the silicon substrate 1, especially during the handling and installation process, it is easy to crack or break. At the same time, the hollow groove 7 is too deep, which will also cause the carriers inside the silicon substrate to bypass the deeper depth for lateral transmission, which is not conducive to the transmission and collection of carriers.

[0057] For example, preferably, the depth of the hollow groove 7 can be any value of 1μm-5μm, for example, it can be 1.0μm, 1.2μm, 1.4μm, 1.6μm, 1.8μm, 2.0μm, 2.2μm, 2.4μm, 2.6μm, 2.8μm, 3.0μm, 3.2μm, 3.4μm, 3.6μm, 3.8μm, 4.0μm, 4.2μm, 4.4μm, 4.6μm, 4.8μm, 5.0μm and the like.

[0058] In some embodiments of the present invention, the spacing between each two adjacent hollow grooves 7 is 30μm-100μm. It is understandable that when the spacing is small, more areas are covered by the hollow grooves 7, which helps to improve the current collection efficiency and the photoelectric conversion efficiency. However, if the spacing is too small, it may cause an increase in local current density, which in turn causes local heating and reliability problems; a larger spacing means fewer hollow grooves 7, resulting in a longer current path, increased series resistance, and reduced fill factor.

[0059] In addition, a reasonable spacing can help disperse stress and reduce the problem of fragmentation. If the spacing is too small, the mechanical strength of the silicon substrate 1 may be weakened, especially during handling and installation, and cracks or breakage may occur; while if the spacing is too large, stress concentration may occur, which is also not conducive to mechanical stability.

[0060] Specifically, the spacing between each two adjacent hollow grooves 7 can be any value of 30 μm-100 μm, for example, the spacing between each two adjacent hollow grooves 7 can be 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, 75 μm, 80 μm, 85 μm, 90 μm, 95 μm, 100 μm, etc. It can be understood that the spacing between each two adjacent hollow grooves 7 can be equal or unequal.

[0061] Preferably, the intervals between every two adjacent hollow grooves 7 are equal, and the plurality of hollow grooves 7 are evenly distributed in the non-metallic grid line contact area, so as to optimize the stress distribution of the battery and reduce the fragmentation rate.

[0062] In some embodiments of the present invention, the size of each hollow groove 7 in the width direction of the solar cell 100 is 30μm-500μm, and the size of each hollow groove 7 in the length direction of the solar cell 100 is 30μm-500μm. It is understandable that an overly large hollow groove 7 may increase the local current density, cause local heating problems, and may weaken the mechanical strength of the silicon substrate 1, especially prone to cracks or breakage during handling and installation; smaller hollow groove 7 sizes help reduce series resistance because they can reduce the length of the current path while maintaining good current collection, but if the size is too small, it may not be enough to reduce the parasitic absorption of poly, affecting carrier transmission, and may also cause stress concentration, which is not conducive to mechanical stability.

[0063] Therefore, too large or too small a size of the hollow groove 7 may lead to a decrease in photoelectric conversion efficiency. A reasonable size of the hollow groove 7 can help disperse stress and reduce the problem of fragmentation.

[0064] Specifically, the size of each hollow groove 7 in the width direction of the solar cell 100 can be any value of 30μm-500μm, for example: 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm and the like; the size of each hollow groove 7 in the length direction of the solar cell 100 can be any value of 30μm-500μm, for example: 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm and the like. It is understandable that the size of each hollow groove 7 can be equal or different.

[0065] In some embodiments of the present invention, the size of each hollow groove 7 is consistent. It can be understood that the consistent size of the hollow groove 7 makes it easier to control and optimize the process steps such as laser grooving and etching, reducing the complexity of the process. Since all the hollow grooves 7 have the same size, the setting and adjustment of the production equipment are simpler, thereby improving the overall efficiency of the production line; the consistent size of the hollow groove 7 ensures the uniform distribution of carriers on the back of the silicon substrate 1, helps to achieve a more stable current collection efficiency, avoids the performance differences caused by the hollow grooves 7 of different sizes, makes the performance of each battery more consistent, and improves the quality of the overall product. In addition, if the size of the hollow groove 7 is consistent and carefully designed, the position of the metal grid line can be better planned, the shading area can be reduced, and the effective illumination area can be increased; the consistent size of the hollow groove 7 helps to evenly disperse stress and reduce debris problems, especially to maintain structural integrity during handling and installation.

[0066] Reference Figure 2 As shown, the plurality of hollow grooves 7 are all rectangular, and the size of each hollow groove 7 is consistent, and the distance between two adjacent hollow grooves 7 is also consistent.

[0067] In some embodiments, the shape of the hollow groove 7 can also be a regular or irregular polygon such as a square or trapezoid (not shown), or a regular or irregular arc shape such as a circle, an ellipse, a honeycomb, a cloud, etc. (not shown), and the present invention is not limited thereto.

[0068] It should be explained in detail here that when the thickness of the dielectric layer 5 is less than 2nm, the carriers mainly pass through the dielectric layer 5 through the quantum tunneling mechanism, so that electrons or holes can pass through the insulating barrier with a higher probability through the tunneling effect in quantum mechanics without sufficient energy to overcome the entire potential barrier. In the TOPCon battery, the thickness of the dielectric layer 5 is usually less than 2nm, and the majority carriers pass through while blocking the minority carriers, thereby reducing the recombination loss and improving the fill factor; when the thickness of the dielectric layer 5 is greater than 2nm, pinholes (pinhole defects) exist in the dielectric layer 5, and the carriers directly pass through the dielectric layer 5 through tiny holes, that is, when it is greater than 2nm, the carriers are more transmitted through pinholes.

[0069] It is understood that when the thickness of the dielectric layer 5 is less than 2nm, it is a tunneling layer of the TOPCon cell. In the solar cell 100 of the embodiment of the present invention, the thickness of the dielectric layer 5 is less than 2nm, that is, the embodiment of the present invention is a TOPCon cell. It is understood that the thickness of the dielectric layer 5 can also be set to be greater than 2nm, and the carriers are transmitted through the pinholes, which will not be repeated here.

[0070] The method for preparing the solar cell 100 according to the second embodiment of the present invention is used to produce the solar cell 100 according to the first embodiment of the present invention.

[0071] Specifically, Figure 3 As shown, the preparation method comprises:

[0072] Step S1, texturing the surface of the silicon substrate 1;

[0073] Step S2, performing boron diffusion on the silicon substrate 1 to form a PN junction, and cleaning and oxidizing the back side of the silicon substrate 1 to form a dielectric layer 5;

[0074] Step S3, performing alkali polishing on the silicon substrate 1 to remove the borosilicate glass and the boron diffusion layer on the back side of the silicon substrate 1;

[0075] Step S4, forming a poly layer 6 on the surface of the dielectric layer 5 facing away from the silicon substrate 1 by low pressure chemical vapor deposition;

[0076] Step S5, performing phosphorus doping treatment on the poly layer 6;

[0077] Step S6, forming a hollow groove 7 on the back side of the silicon substrate 1 by laser;

[0078] Step S7, removing the phosphosilicate glass on the silicon substrate 1, and etching the silicon substrate 1;

[0079] Step S8, depositing an aluminum oxide layer on the silicon substrate 1 by ALD to form a passivation layer 3;

[0080] Step S9, coating the front surface of the silicon substrate 1;

[0081] Step S10, performing coating treatment on the back side of the silicon substrate 1;

[0082] Step S11 : printing a first fine grid on the back side of the solar cell 100 , and printing a second fine grid on the front side of the solar cell 100 .

[0083] According to the method for preparing the solar cell 100 of the embodiment of the present invention, the solar cell 100 of the first aspect embodiment above reduces the fragmentation problem of the solar cell 100 by using the preparation method of the embodiment of the present invention, while ensuring the optimal balance between optical performance and electrical performance, effectively reducing surface recombination losses, improving conversion efficiency, and having a better temperature coefficient and bifaciality, thereby improving the overall performance of the solar cell 100.

[0084] It is understandable that in step S1, an alkaline or acidic solution is usually used to treat the surface of the N-type silicon substrate 1 to form a microstructure to improve the light capture capability, thereby increasing the light absorption rate and reducing reflection;

[0085] In step S2, a pn junction is formed on the front side of the silicon substrate 1 by high-temperature diffusion of a boron source; the back side is then cleaned and subjected to low-temperature oxidation treatment to form a high-quality tunneling oxide layer, thereby forming a p+ emitter on the front side and an ultra-thin tunneling oxide layer on the back side;

[0086] In step S3, alkaline solution is used for light polishing to improve the surface quality, and wet chemical cleaning is used to remove borosilicate glass (BSG) and remove excess boron impurities on the back side to prepare for the subsequent deposition of poly layer 6;

[0087] In step S4, a uniform polysilicon layer is deposited at a relatively low pressure using LPCVD technology, so that a layer of polysilicon is deposited as part of the tunnel passivation contact;

[0088] In step S5, phosphorus atoms may be introduced by ion implantation or diffusion, followed by annealing to activate the dopant, converting the poly layer 6 into n+ doping to enhance its conductivity and selective contact performance;

[0089] In step S6, a laser with a power of 60W-100W is used to form hollow grooves 7 arranged in an array according to the design requirements. The laser power usage ratio is 10%-100%, so that local grooving is achieved, ensuring effective removal of the poly layer 6 and the dielectric layer 5, while maintaining a good passivation effect;

[0090] In step S7, wet chemical cleaning is used to remove the phosphosilicate glass, and then etching is performed to ensure that the surface is clean and flat, remove the phosphosilicate glass formed during the phosphorus diffusion process, and optimize the surface morphology;

[0091] In step S8, a high-quality aluminum oxide layer is deposited using atomic layer deposition (ALD) technology to ensure uniform coverage, provide additional surface passivation, and further reduce the surface recombination velocity;

[0092] In step S9, PECVD or other suitable coating techniques may be used to deposit materials such as silicon nitride to form an anti-reflective coating to improve light absorption efficiency;

[0093] In step S10, PECVD and other technologies can also be used for coating. The specific material is selected according to the design requirements to protect the back structure and may provide additional optical management functions;

[0094] In step S11, screen printing technology is used to print silver paste on the back to form a fine grid; a fine grid is printed at the corresponding position on the front to ensure that the grid lines on both sides are aligned with each other, defining a non-metallic grid line contact area 9, and the hollow groove 7 is located in the non-metallic grid line contact area 9, thereby forming an efficient current collection system.

[0095] Here, a second fine grid may be printed on the front side of the solar cell 100 at a position aligned with the first fine grid.

[0096] In other embodiments, silver paste is printed on the back of the solar cell 100 to form fine grids and main grids, and the fine grids and main grids are perpendicular to each other. In some embodiments of the present invention, in order to ensure accuracy, the boundary of the hollow groove 7 is determined according to the gray value tested after low pressure chemical vapor deposition.

[0097] In some embodiments of the present invention, the power of the laser is 60 W-100 W. For example, the power of the laser can be 60 W, 65 W, 70 W, 75 W, 80 W, 85 W, 90 W, 95 W, 100 W, and the like.

[0098] Further, the usage ratio of the laser power is 10%-100%. For example, the usage ratio of the laser power can be 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, 100%, etc.

[0099] In some embodiments of the present invention, non-metallic grid line contact regions 9 are defined between the first fine grids, and hollow grooves 7 are formed between the first fine grids, thereby achieving efficient current collection while maintaining a good surface passivation effect, thereby improving the overall performance and reliability of the solar cell 100.

[0100] The solar cell assembly according to the third aspect of the present invention comprises a plurality of solar cells 100 according to the first aspect of the present invention. It is understandable that the plurality of solar cells 100 constitute the solar cell assembly, and the plurality of solar cells 100 can be combined together in series, parallel or mixed connection. Due to the use of efficient single solar cells 100, the energy conversion efficiency of the entire solar cell assembly is improved, thereby generating more power output under the same light regulation and reducing the installation area.

[0101] The solar cell assembly according to the embodiment of the present invention improves the energy conversion efficiency of the solar cell assembly, enhances the performance of the solar cell assembly, increases the power generation and land space utilization, reduces the production and installation costs, and ensures economic benefits by disposing a plurality of solar cells 100 according to the first aspect of the present invention.

[0102] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0103] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0104] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0105] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0106] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A solar cell, characterized in that: include: A silicon substrate, wherein the front side of the silicon substrate is sequentially an emitter layer, a passivation layer and a metal contact layer in a direction away from the silicon substrate, and the back side of the silicon substrate is sequentially a dielectric layer, a poly layer, a passivation layer and a metal contact layer in a direction away from the silicon substrate, the solar cell has a metal grid line contact area and a non-metal grid line contact area, a plurality of hollow grooves arranged in an array are formed in the non-metal grid line contact area, and each of the hollow grooves sequentially penetrates the passivation layer, the poly layer and the dielectric layer on the back side of the silicon substrate in a thickness direction of the solar cell.

2. The solar cell according to claim 1, characterized in that The ratio of the total area of ​​the hollow grooves to the area of ​​the non-metallic gate line contact region is 0.2-1.

3. The solar cell according to claim 1, characterized in that The depth of the hollow groove is 1 μm-5 μm.

4. The solar cell according to claim 1, characterized in that The distance between each two adjacent hollow grooves is 30 μm-100 μm.

5. The solar cell according to claim 1, characterized in that: The size of each hollow groove in the width direction of the solar cell is 30 μm-500 μm, and / or the size of each hollow groove in the length direction of the solar cell is 30 μm-500 μm.

6. The solar cell according to any one of claims 1 to 5, characterized in that: The silicon substrate is an N-type silicon substrate.

7. The solar cell according to any one of claims 1 to 5, characterized in that: The size of each hollow groove is consistent.

8. A method for preparing a solar cell, characterized in that: For producing the solar cell according to any one of claims 1 to 7, the preparation method comprises: Step S1, texturing the surface of the silicon substrate; Step S2, diffusing boron into the silicon substrate to form a PN junction, and cleaning and oxidizing the back side of the silicon substrate to form a dielectric layer; Step S3, performing alkali polishing on the silicon substrate to remove the borosilicate glass and the boron diffusion layer on the back side of the silicon substrate; Step S4, forming a poly layer on the surface of the dielectric layer facing away from the silicon substrate by low pressure chemical vapor deposition; Step S5, performing phosphorus doping treatment on the poly layer; Step S6, forming a hollow groove on the back side of the silicon substrate by laser; Step S7, removing the phosphosilicate glass on the silicon substrate and etching the silicon substrate; Step S8, depositing an aluminum oxide layer on the silicon substrate by ALD to form a passivation layer; Step S9, coating the front surface of the silicon substrate; Step S10, coating the back of the silicon substrate; Step S11 : printing a first fine grid on the back side of the solar cell, and printing a second fine grid on the front side of the solar cell.

9. The preparation method according to claim 8, characterized in that: The power of the laser is 60W-100W, and / or the utilization ratio of the laser power is 10%-100%.

10. A solar cell module, characterized in that: The invention comprises a plurality of solar cells according to any one of claims 1 to 9.

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