Laser battery array chip

Abstract

The invention discloses a laser battery array chip, which comprises a substrate, a laser battery array and an electrode connecting part, wherein the laser battery array and the electrode connecting part are positioned on the surface of one side of the substrate; the laser battery array comprises at least two battery units, and each battery unit comprises a first sub-battery layer, a second sub-battery layer and a third sub-battery layer which are sequentially stacked from bottom to top; the working wavelength of the laser cell array chip is 850 nm to 1200 nm. The first junction sub-cell layer, the second junction sub-cell layer and the third junction sub-cell layer each comprise a gradual change buffer layer, an optical spacing layer, a transparent layer, a base layer, an emission layer, a window layer, a contact layer and a grid electrode which are sequentially stacked from bottom to top. By using the above structure, compared with a two-junction sub-cell layer, the energy conversion efficiency of the chip and the output density of unit energy are improved, and the laser heat effect of the chip is reduced.

Description

Technical Field

[0001] The invention relates to the field of laser technology, in particular to a laser wireless energy transmission device, and in particular to a laser battery array chip. Background Art

[0002] With the continuous expansion of the application scenarios of aerospace unmanned aerial vehicles and the rapid development of the aerospace industry, higher requirements are placed on the endurance and payload of aerospace unmanned aerial vehicles. At present, micro-aerospace unmanned aerial vehicles generally use airborne batteries for endurance. Because the energy density and power density of batteries are low, the payload, flight altitude and endurance of the aircraft are very limited. In order to enable micro-unmanned aerial vehicles to have long flight time, large load and high-altitude flight, charging them by remote wireless charging is considered to be one of the most feasible solutions in the future. Lasers have the advantages of high power density, long transmission distance, strong anti-electromagnetic interference and good directionality, and are considered to be the most promising wireless energy transmission carrier. The key to achieving high energy density laser wireless energy transmission per unit area is miniaturized, high voltage, lightweight, efficient and high temperature resistant laser energy conversion batteries. Therefore, it is of great economic value to develop battery array chips with high output energy per unit area, high voltage, small size, light weight and laser resistance.

[0003] The energy conversion layer in the existing laser battery array chip usually uses a two-junction cell to achieve laser energy conversion. However, the use of a two-junction cell will result in low energy conversion efficiency, low output density per unit energy, and high chip surface temperature under laser radiation, resulting in poor performance of the final laser battery array chip, which is difficult to meet actual performance requirements. Summary of the invention

[0004] The present invention provides a laser battery array chip that utilizes a three-junction battery layer structure. Under the same conditions, compared with a two-junction battery, the chip's energy conversion efficiency and unit energy output density are greatly improved, the chip's surface temperature is reduced under laser radiation, and it has a smaller volume and lighter weight, making it more suitable for applications in the future in areas such as wireless charging of drones.

[0005] The present invention provides a laser battery array chip, comprising a substrate, and a laser battery array located on one side surface of the substrate;

[0006] The laser battery array includes at least two battery units, each of which includes a first junction battery layer, a second junction battery layer and a third junction battery layer stacked in sequence from bottom to top;

[0007] The operating wavelength of the laser cell array chip is 850nm-1200nm. The first junction cell layer, the second junction cell layer and the third junction cell layer all include a gradient buffer layer, an optical spacer layer, a transparent layer, a base layer, an emission layer, a window layer, a contact layer and a gate which are stacked in sequence from bottom to top.

[0008] Optionally, the thicknesses of the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer decrease sequentially.

[0009] Optionally, the base layer includes a first base layer, a second base layer and a third base layer stacked sequentially from bottom to top;

[0010] The gradient buffer layer includes (Al 0.6 Ga) 0.55 ln 0.4 As, the optical spacer layer includes (Al 0.55 Ga) 0.65 ln 0.35 As, the transparent layer includes (Al 0.51 Ga) 0.7 ln 0.3 As, the first base layer includes p-Galn 0.3 As, the second base layer includes p-GalnAs, the third base layer includes i-GalnAs; the emission layer includes n-GalnAs; the window layer includes n-GalnP; the contact layer includes GalnAs; and the gate includes Au.

[0011] Optionally, the thickness of the gradient buffer layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer is the same; the thickness of the optical spacer layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer is the same; the thickness of the transparent layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer is the same; the thickness of the first base layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer decreases successively; the thickness of the second base layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer is the same; the thickness of the third base layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer is the same; the thickness of the emission layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer is the same; the thickness of the window layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer is the same.

[0012] Optionally, each battery cell further includes a first tunnel junction layer and a second tunnel junction layer, the first tunnel junction layer is arranged between the first junction sub-battery layer and the second junction sub-battery layer, and the second tunnel junction layer is arranged between the second junction sub-battery layer and the third junction sub-battery layer;

[0013] The first tunnel junction layer and the second tunnel junction layer each include an n-GaAs-Te layer and a p-Al layer stacked in sequence. 0.3 GaAs-C layer; n-GaAs-Te layer and p-Al 0.3 The thickness of the GaAs-C layers is the same.

[0014] Optionally, the chip further includes an electrode connection portion; the electrode connection portion is located on a side of the substrate facing the laser cell array;

[0015] The electrode connection portion includes an internal electrode connection structure, a first electrode and a second electrode, one end of the internal electrode connection structure is connected to the top of a battery cell, and the other end of the internal electrode connection structure is connected to the bottom of another battery cell, so that the battery cells are connected in series in sequence; the first electrode is electrically connected to the first battery cell among the battery cells connected in series in sequence, and the second electrode is electrically connected to the last battery cell among the battery cells connected in series in sequence.

[0016] Optionally, the battery cell further includes a buffer layer, a gap layer and an anti-reflection layer;

[0017] The buffer layer is arranged between the substrate and the first junction sub-cell layer, the gap layer is arranged between the third junction sub-cell layer and the anti-reflection layer, and the anti-reflection layer is located between the gap layer and the internal electrode connection structure.

[0018] Optionally, the laser cell array further includes an insulating passivation layer;

[0019] The insulating passivation layer is attached to the side wall of the battery cell, and one end of the insulating passivation layer is embedded in the substrate.

[0020] Optionally, the internal electrode connection structure includes an internal first electrode, a sidewall electrode layer and an internal second electrode;

[0021] A first electrode is arranged on the surface of the insulating passivation layer and some battery cells away from the substrate; one end of the sidewall electrode layer is connected to the internal first electrode and adheres to the surface of the insulating passivation layer; one end of the internal second electrode is connected to the other end of the sidewall electrode layer, and the other end is connected to the adjacent battery cell.

[0022] Optionally, the laser battery array further includes an isolation groove located between two adjacent battery units;

[0023] Part of the internal electrode connection structure is located in the isolation groove, and part of the internal electrode connection structure is located at the ends of the same side of two adjacent battery cells.

[0024] The technical solution of the present invention, when the working wavelength of the laser battery array chip is 850nm-1200nm, by setting three sequentially stacked first junction sub-battery layers, second junction sub-battery layers and third junction sub-battery layers, when the laser is incident on each battery unit, the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer absorb photon energy of different wavelengths and stimulate electron transition to generate electron-hole pairs, which are separated under the action of the built-in electric field, and the electrons flow to the negative electrode and the holes flow to the positive electrode, thereby forming a current. The above structure greatly improves the unit energy output density of the laser battery array chip, reduces the surface temperature, improves the energy conversion efficiency of the laser battery array chip, and has a smaller volume and lighter weight, which is more suitable for applications in the fields of wireless charging of drones in the future.

[0025] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 A front view schematic diagram of a laser battery array chip provided by an embodiment of the present invention;

[0028] Figure 2 A schematic top view of a laser cell array chip provided by an embodiment of the present invention;

[0029] Figure 3 A schematic diagram of the structure of a battery unit provided by an embodiment of the present invention;

[0030] Figure 4 A schematic diagram of the structure of a second battery unit provided by an embodiment of the present invention;

[0031] Figure 5 A schematic structural diagram of a third battery unit provided by an embodiment of the present invention;

[0032] Figure 6 A schematic structural diagram of a fourth battery unit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0035] In one embodiment, Figure 1 A front view schematic diagram of a laser battery array chip provided by an embodiment of the present invention, Figure 2 A schematic top view of a laser cell array chip provided by an embodiment of the present invention, Figure 3 This is a schematic diagram of the structure of a battery unit provided by an embodiment of the present invention. This embodiment can be applied to the situation where the laser energy conversion efficiency and unit energy output density of the laser battery array chip are improved in the near-infrared band, and the laser thermal effect of the chip is reduced, such as Figures 1 to 3 As shown, the present invention provides a laser cell array chip, including a substrate 1, and a laser cell array 2 and an electrode connecting part 3 located on one side surface of the substrate 1; the laser cell array 2 includes at least two battery cells 21, and each battery cell 21 includes a first junction sub-cell layer 211, a second junction sub-cell layer 212 and a third junction sub-cell layer 213 stacked in sequence from bottom to top; the operating wavelength of the laser cell array chip is 850nm-1200nm, and the first junction sub-cell layer 211, the second junction sub-cell layer 212 and the third junction sub-cell layer 213 all include a gradient buffer layer 209, an optical spacer layer 205, a transparent layer 206, a base layer 202, an emission layer 203, a window layer 204, a contact layer (not shown in the figure) and a gate 200 stacked in sequence.

[0036] Optionally, the chip also includes an electrode connecting portion 3; the electrode connecting portion 3 is located on the side of the substrate 1 facing the laser battery array 2; the electrode connecting portion 3 includes an internal electrode connecting structure 31, a first electrode 32 and a second electrode 33, one end of the internal electrode connecting structure 31 is connected to the top of a battery cell 21, and the other end of the internal electrode connecting structure 31 is connected to the bottom of another battery cell 21, so that the battery cells 21 are connected in series in sequence; the first electrode 32 is electrically connected to the first battery cell 21 of the battery cells 21 connected in series in sequence, and the second electrode 33 is electrically connected to the last battery cell 21 of the battery cells 21 connected in series in sequence.

[0037] Among them, the substrate 1 is the base of the laser cell array chip, which is used to support the entire laser cell array. In this embodiment, the substrate 1 can be an insulating substrate or a semi-insulating substrate. The insulating substrate can be one of silicon oxide, sapphire substrate, polyimide substrate and silicon carbide substrate. The laser cell array 2 is a device based on laser wireless energy transmission technology, and its core function is to convert the received laser energy into electrical energy. It usually includes a plurality of laser photoelectric conversion devices (battery units), which are arranged into an array in a specific integration method to improve energy conversion efficiency and output power. In this embodiment, the material of the laser cell array 2 may include but is not limited to gallium arsenide (GaAs) or perovskite stack. The laser cell array 2 includes at least two battery units 21, and each battery unit 2 includes a first junction sub-battery layer 211, a second junction sub-battery layer 212 and a third junction sub-battery layer 213 stacked in sequence from bottom to top. The third junction sub-battery layer 213 refers to the first photoelectric conversion unit at the top layer in the multi-junction laser cell array 1, which is usually used to absorb photons with the highest energy (shortest wavelength), such as ultraviolet light and blue light. This layer of material generally uses semiconductor materials with a wide bandgap to ensure that it can effectively absorb and convert high-energy photons into electrical energy and generate photogenerated carriers (electrons and holes). The second junction subcell layer 212 is the second photoelectric conversion unit, located below the third junction subcell layer 213, and is used to absorb photons with intermediate wavelengths, such as green light and yellow light. The material used in this layer has a bandgap width between the first junction subcell layer 211 and the third junction subcell layer 213, such as indium gallium phosphide (InGaP) or gallium arsenide (GaAs), to match the corresponding spectral absorption range and improve the overall energy conversion efficiency. The first junction subcell layer 211 is the third photoelectric conversion unit, located at the bottom layer of the multi-junction laser cell array 1, and is used to absorb photons with the lowest energy (longest wavelength), such as red light and near-infrared light. This layer usually uses semiconductor materials with a narrow bandgap to more effectively capture the energy of this part of the spectrum, and work together with the first two subcell layers to form a multi-junction stacked structure, increase the output voltage and current, and improve the overall performance. The internal electrode connection structure 31 is used to connect two adjacent battery cells 2 to ensure that each battery cell 2 is connected in series in sequence. The first electrode 32 and the second electrode 33 are two opposite electrodes of the laser battery array chip 2, which are used to connect an external circuit or load. Among them, if the first electrode 32 is a positive electrode, the second electrode 33 is a negative electrode; if the first electrode 32 is a negative electrode, the second electrode 33 is a positive electrode, and no specific limitation is made here. The material of the electrode connection part 3 may include but is not limited to gold. In this embodiment, the operating wavelength of the laser battery array chip is 850nm-1200nm, that is, the near-infrared band.

[0038] Among them, the Gradual Buffer Layer (GB) 209 is a transition layer used between materials or structures, and the composition or structure of the material changes gradually in space, mainly used to alleviate the lattice mismatch and thermal expansion coefficient difference between different materials, thereby improving the structural stability and performance of the chip. The Optical Spacer Layer (OS) 205 is an intermediate layer used to adjust the optical path and optimize the propagation of light. It is used to reduce the reflection and loss of light by controlling the propagation path and phase of light, thereby improving the transmission efficiency of light and the overall performance of the chip. The Transparent Layer (TL) 206 is a material layer with high transmittance for light of a specific wavelength, mainly used to ensure that the optical signal can pass through the chip structure efficiently, while reducing the scattering and absorption of light, thereby improving the transmission efficiency of light and the optical performance of the chip. The base layer 202 is the main light absorption layer of the battery unit 21, usually including P-type GaAs, which is responsible for absorbing most of the incident light and generating photogenerated carriers (electrons and holes). The emission layer 203 is located on the base layer 202 and is used to form a PN junction. Together with the base layer 202, it constitutes the photoelectric conversion core area of ​​the battery unit 21, which is responsible for separating and transporting photogenerated carriers to the external circuit. The window layer 204 is located on the emission layer 203 and is used to reduce surface recombination, while allowing more light to enter the battery unit 21 to be absorbed, and can also protect the chip surface from the influence of the external environment. The contact layer is a structure arranged between the battery unit and the electrode connection part. Its main function is to improve the contact condition by forming an ohmic contact with the electrode, thereby improving the performance of the laser battery array chip. The gate 200 is a structure formed on the electrode connection part by a photolithography process. It plays a role in controlling the current path and isolating adjacent sub-batteries in the battery chip to increase the charge collection of photons and improve the energy conversion efficiency; in the manufacturing process, the formation of the gate 200 is usually achieved by opening a window on the metal electrode material covering the top surface of the contact layer. The material of the gate 200 is the same as that of the electrode connection part 3.

[0039] Specifically, when the laser is irradiated onto the laser battery array 2, the laser will be incident on the first junction sub-battery layer 211, the second junction sub-battery layer 212 and the third junction sub-battery layer 213 on the battery unit 21, and the first junction sub-battery layer 211, the second junction sub-battery layer 212 and the third junction sub-battery layer 213 will absorb photon energy of different wavelengths and stimulate electron transitions to generate electron-hole pairs; the electron-hole pairs are separated under the action of the built-in electric field, and the electrons flow to the negative electrode and the holes flow to the positive electrode, thereby forming a current. By connecting multiple battery units 21 in series, the output current of the laser battery array chip can be increased to realize the conversion of laser light energy to electrical energy. In this embodiment, when the operating wavelength of the laser cell array chip is 850nm-1200nm, by setting three sequentially stacked first junction sub-cell layers 211, second junction sub-cell layers 212 and third junction sub-cell layers 213, under the same laser conditions, the unit energy output density of the laser cell array chip can be increased by 1 to 1.5 times, and the surface temperature of the laser cell array chip can be reduced by 1 time, so that the energy conversion efficiency is greatly improved.

[0040] The technical solution of the embodiment of the present invention is that when the working wavelength of the laser battery array chip is 850nm-1200nm, three first junction sub-battery layers, second junction sub-battery layers and third junction sub-battery layers are stacked in sequence, so that when the laser is incident on each battery unit, the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer absorb the photon energy of different wavelengths and stimulate electron transitions to generate electron-hole pairs. The electron-hole pairs are separated under the action of the built-in electric field, and the electrons flow to the negative electrode and the holes flow to the positive electrode, thereby forming a current. The above structure greatly improves the unit energy output density of the laser battery array chip, reduces the surface temperature, improves the energy conversion efficiency of the laser battery array chip, and has a smaller volume and lighter weight, which is more suitable for applications in the future fields of wireless charging of drones.

[0041] In another specific embodiment, optionally, because the third junction sub-battery layer 213 close to the laser incident side absorbs the most photons when the laser is incident, and the first junction sub-battery layer 211 closest to the substrate 1 absorbs the least photons, when setting the thickness of the first junction sub-battery layer 211, the second junction sub-battery layer 212 and the third junction sub-battery layer 213, the thickness of the first junction sub-battery layer 211, the second junction sub-battery layer 212 and the third junction sub-battery layer 213 are set to decrease in sequence, even if the thickness of the sub-battery layer farther away from the substrate 1 is smaller, this can ensure that the output current of each junction sub-battery is the same, so as to optimize the energy conversion efficiency of the chip, improve the stability of the chip, and extend the service life of the chip.

[0042] In another specific embodiment, Figure 4A schematic diagram of the structure of a second battery cell provided in an embodiment of the present invention, referring to Figure 4 As shown, optionally, when the operating wavelength of the laser cell array chip is 650nm-850nm, the first junction sub-cell layer 211, the second junction sub-cell layer 212 and the third junction sub-cell layer 213 all include a back field layer 201, a base layer 202, an emission layer 203 and a window layer 204 stacked in sequence from bottom to top.

[0043] The back field layer 201 is located at the bottom of each junction cell layer and contacts the substrate 1, and is used to reduce the recombination of photogenerated carriers on the back of the chip, improve the collection efficiency of carriers, and thus improve the energy conversion efficiency of the chip. In addition, the meaning and function of the base layer 202, the emission layer 203 and the window layer 204 can be referred to the previous embodiment, and will not be repeated here. In this embodiment, the back field layer 201 includes Al 0.3 GaAs, the base layer 202 and the emission layer 203 both include GaAs, and the window layer 204 includes Alln 0.5 P.

[0044] Optional, continue to refer to Figure 4 , the thickness of the back field layer 201 in the first junction sub-battery layer 211, the second junction sub-battery layer 212 and the third junction sub-battery layer 213 are all the same; the thickness of the base layer 202 in the first junction sub-battery layer 211, the second junction sub-battery layer 212 and the third junction sub-battery layer 213 decreases successively; the thickness of the emission layer 203 in the first junction sub-battery layer 211, the second junction sub-battery layer 212 and the third junction sub-battery layer 213 are all the same; the thickness of the window layer 204 in the first junction sub-battery layer 211, the second junction sub-battery layer 212 and the third junction sub-battery layer 213 are all the same.

[0045] Specifically, when the operating wavelength of the GaAs-based laser cell array chip is 650nm-850nm, the substrate 1 can be an insulating sapphire substrate. At this time, the structure of each junction cell layer includes a back field layer 201, a base layer 202, an emission layer 203 and a window layer 204 arranged from bottom to top. Among them, the back field layer 201 is Al 0.3 GaAs, the base layer 202 is GaAs, the emission layer 203 is GaAs, and the window layer 204 is Alln 0.5P; and in each battery cell 21, the thickness of the back field layer 201 in the first junction sub-battery layer 211, the second junction sub-battery layer 212 and the third junction sub-battery layer 213 is the same. In this embodiment, the thickness of the back field layer 201 is 60nm. The thickness of the base layer 202 in the first junction sub-battery layer 211, the second junction sub-battery layer 212 and the third junction sub-battery layer 213 decreases successively. In this embodiment, the thickness of the first junction sub-battery layer 211 is 3000nm, the thickness of the second junction sub-battery layer 212 is 2500nm, and the thickness of the third junction sub-battery layer 211 is 2000nm. The thickness of the emission layer 203 in the first junction sub-battery layer 211, the second junction sub-battery layer 212 and the third junction sub-battery layer 213 is the same. In this embodiment, the thickness of the emission layer 203 is 100nm. The thickness of the window layer 204 in the first junction sub-cell layer 211 , the second junction sub-cell layer 212 and the third junction sub-cell layer 213 are all the same. In the present embodiment, the thickness of the window layer 204 is 1000 nm.

[0046] In another specific embodiment, optionally, continue to refer to Figure 3 The base layer 202 includes a first base layer 2021, a second base layer 2022 and a third base layer 2023 stacked in sequence from bottom to top; the gradient buffer layer 209 includes (Al 0.6 Ga) 0.55 ln 0.4 As, the optical spacing layer 205 includes (Al 0.55 Ga) 0.65 ln 0.35 As, the transparent layer 206 includes (Al 0.51 Ga) 0.7 ln 0.3 As, the first base layer 2021 includes p-Galn 0.3 As, the second base layer 2022 includes p-GalnAs, the third base layer 2023 includes i-GalnAs; the emission layer 203 includes n-GalnAs; the window layer 204 includes n-GalnP; the contact layer includes GalnAs; and the gate includes Au.

[0047] Optional, continue to refer to Figure 3, the thickness of the gradient buffer layer 209 in the first junction sub-battery layer 211, the second junction sub-battery layer 212 and the third junction sub-battery layer 213 is the same; the thickness of the optical spacer layer 205 in the first junction sub-battery layer 211, the second junction sub-battery layer 212 and the third junction sub-battery layer 213 is the same; the thickness of the transparent layer 206 in the first junction sub-battery layer 211, the second junction sub-battery layer 212 and the third junction sub-battery layer 213 is the same; the thickness of the first base layer 2021 in the first junction sub-battery layer 211, the second junction sub-battery layer 212 and the third junction sub-battery layer 213 decreases in sequence. small; the thickness of the second base layer 2022 in the first junction sub-battery layer 211, the second junction sub-battery layer 212 and the third junction sub-battery layer 213 are all the same; the thickness of the third base layer 2023 in the first junction sub-battery layer 211, the second junction sub-battery layer 212 and the third junction sub-battery layer 213 are all the same; the thickness of the emission layer 203 in the first junction sub-battery layer 211, the second junction sub-battery layer 212 and the third junction sub-battery layer 213 are all the same; the thickness of the window layer 204 in the first junction sub-battery layer 211, the second junction sub-battery layer 212 and the third junction sub-battery layer 213 are all the same.

[0048] Specifically, when the operating wavelength of the GaAs-based laser cell array chip is 850nm-1200nm, the substrate 1 is an insulating sapphire substrate, and the structure of each junction cell layer at this time includes a back field layer 101, an OS layer 205, a TL layer 206, a first base layer 2021, a second base layer 2022, a third base layer 2023, an emission layer 203 and a window layer 204 arranged from bottom to top. Among them, the gradient buffer layer 209, that is, the GB layer is (Al 0.6 Ga) 0.55 ln 0.4 As, the optical spacing layer 205 is (Al 0.55 Ga) 0.65 ln 0.35 As, transparent layer 206 is (Al 0.51 Ga) 0.7 ln 0.3 As, the first base layer 2021 is p-doped Galn 0.3As, the second base layer 2022 is p-doped GalnAs, and the third base layer 2023 is undoped GalnAs; the emission layer 203 is n-doped GalnAs; and the window layer 204 is n-doped GalnP. In each battery unit 21, the thickness of the gradient buffer layer 209 in the first junction sub-battery layer 211, the second junction sub-battery layer 212, and the third junction sub-battery layer 213 is the same. In this embodiment, the thickness of the gradient buffer layer 209 may be 2000nm. The thickness of the optical spacer layer 205 in the first junction sub-battery layer 211, the second junction sub-battery layer 212, and the third junction sub-battery layer 213 is the same. In this embodiment, the thickness of the optical spacer layer 205 may be 500nm. The thickness of the transparent layer 206 in the first junction sub-battery layer 211, the second junction sub-battery layer 212, and the third junction sub-battery layer 213 is the same. In this embodiment, the thickness of the transparent layer 206 may be 300nm. The thickness of the first base layer 2021 in the first junction sub-battery layer 211, the second junction sub-battery layer 212, and the third junction sub-battery layer 213 decreases in sequence. In this embodiment, the thickness of the first base layer 2021 in the first junction sub-battery layer 211 is 2300nm, the thickness of the first base layer 2021 in the second junction sub-battery layer 212 is 2000nm, and the thickness of the first base layer 2021 in the third junction sub-battery layer 211 is 1700nm. The thickness of the second base layer 2022 in the first junction sub-battery layer 211, the second junction sub-battery layer 212, and the third junction sub-battery layer 213 is the same. In this embodiment, the thickness of the second base layer 2022 may be 300nm. The thickness of the third base layer 2023 in the first junction sub-battery layer 211, the second junction sub-battery layer 212, and the third junction sub-battery layer 213 is the same. In this embodiment, the thickness of the third base layer 2023 may be 110nm. The thickness of the emission layer 203 in the first junction sub-battery layer 211, the second junction sub-battery layer 212, and the third junction sub-battery layer 213 is the same. In this embodiment, the thickness of the emission layer 203 can be 220nm. The thickness of the window layer 204 in the first junction sub-battery layer 211, the second junction sub-battery layer 212, and the third junction sub-battery layer 213 is the same. In this embodiment, the thickness of the window layer 204 can be 100nm. In this way, the size of the resistance in each battery cell 21 can be reduced, the current can be increased, and the photoelectric conversion efficiency of the chip can be enhanced.

[0049] Optional, continue to refer to Figure 1 , Figure 3 and Figure 4Each battery cell 21 further includes a first tunnel junction layer 214 and a second tunnel junction layer 215. The first tunnel junction layer 214 is disposed between the first junction sub-battery layer 211 and the second junction sub-battery layer 212, and the second tunnel junction layer 215 is disposed between the second junction sub-battery layer 212 and the third junction sub-battery layer 213. The first tunnel junction layer 214 and the second tunnel junction layer 215 both include an n-GaAs-Te layer 207 and a p-Al layer 208 stacked in sequence. 0.3 GaAs-C layer 208; n-GaAs-Te layer 207 and p-Al 0.3 The thickness of the GaAs-C layer 208 is the same.

[0050] Among them, the first tunnel junction layer 214 is located between the first junction sub-battery layer 211 and the second junction sub-battery layer 212. It is a special semiconductor junction, including highly doped p-type and n-type semiconductors, forming a very thin area, so that electrons can easily pass through this barrier through the quantum tunneling effect, that is, from the first junction sub-battery layer 211 to the second junction sub-battery layer 212, thereby reducing energy loss. The second tunnel junction layer 215 is located between the second junction sub-battery layer 212 and the third junction sub-battery layer 213. Its structure is similar to that of the first tunnel junction layer 214. Its function is to ensure that the current can be effectively transmitted from the second junction sub-battery layer 212 to the third junction sub-battery layer 213, while minimizing energy loss and avoiding dislocation defects caused by lattice mismatch at the heterogeneous interface. In this embodiment, the first tunnel junction layer 214 and the second tunnel junction layer 215 both include n-doped GaAs-Te layers 207 and p-doped Al2O3 layers stacked in sequence. 0.3 GaAs-C layer 208, GaAs-Te layer 207 and Al 0.3 The thickness of the GaAs-C layer 208 is the same as that of the GaAs-Te layer 207 and the Al 0.3 The thickness of the GaAs-C layer 208 can be 20nm or 30nm, which can be determined according to the working wavelength of the laser battery array chip. When the working wavelength is 650nm-850nm, the GaAs-Te layer 207 and the Al 0.3 The thickness of the GaAs-C layer 208 is 20 nm. When the operating wavelength is 850 nm-1200 nm, the GaAs-Te layer 207 and the Al 0.3 The thickness of the GaAs-C layer 208 is 30 nm, which can reduce the overall resistance of the laser cell array chip and improve the photoelectric conversion efficiency of the chip.

[0051] Optional, continue to refer to Figures 1 to 4The battery cell 21 also includes a buffer layer 216, a gap layer 217 and an anti-reflection layer 218; the buffer layer 216 is arranged between the substrate 1 and the first junction sub-battery layer 211, the gap layer 217 is arranged between the third junction sub-battery layer 213 and the anti-reflection layer 218, and the anti-reflection layer 218 is located between the gap layer 217 and the internal electrode connection structure 31.

[0052] Among them, the buffer layer 216 is used to provide an intermediate layer between the substrate 1 and the first junction cell layer 211 to improve the interface characteristics between them, reduce defects, and improve the stability and performance of the overall structure. The gap layer 217 generally refers to a structure used to isolate or separate different functional layers, which can be used to prevent direct contact between different functional layers, avoid short circuits or unnecessary electrical connections, reduce reflection and scattering of light between different layers, improve light transmission efficiency, reduce heat conduction between different functional layers, and avoid the impact of heat on chip performance. In this embodiment, the gap layer 217 may be GaAs and / or GalnAs. The main function of the anti-reflection layer 218 is to reduce the reflection of the laser, improve the transmittance of the laser, and thus increase the absorption of the incident light. In this embodiment, the anti-reflection layer 218 may include but is not limited to titanium oxide and / or silicon oxide anti-reflection films. In addition, the thickness of the gap layer 217 in each battery cell 21 may be equal or unequal, and can be determined according to actual conditions, and is not limited here. In this embodiment, the thickness of the gap layer 217 in each battery cell 21 is equal, and illustratively, the thickness of the gap layer 217 is 400nm. Similarly, the thickness of the buffer layer 216 in each battery cell 21 can be equal or different, and can be determined according to actual conditions, and is not limited here. In this embodiment, the thickness of the buffer layer 216 in each battery cell 21 is equal, and illustratively, the thickness of the buffer layer 216 is 1000nm.

[0053] Optional, continue to refer to Figure 1 The laser cell array 1 further includes an insulating passivation layer 4 ; the insulating passivation layer 4 is adhered to the side wall of the battery unit 21 , and one end of the insulating passivation layer 4 is embedded in the substrate 1 .

[0054] The insulating passivation layer 4 is an insulating material layer covering the side wall of the battery cell 21, and is generally used to protect the battery cell 21 and prevent the external environment from affecting the battery cell 21. In this embodiment, one end of the insulating passivation layer 4 is embedded in the substrate 1, which can effectively isolate the electrical connection between adjacent battery cells 21 and prevent the occurrence of leakage, thereby improving the electrical insulation effect of the chip.

[0055] Optional, continue to refer to Figure 1The internal electrode connection structure 31 includes an internal first electrode 311, a sidewall electrode layer 312 and an internal second electrode 313; the first electrode 311 is provided on the surface of the insulating passivation layer 4 and part of the battery cell 21 away from the substrate 1; one end of the sidewall electrode layer 312 is connected to the internal first electrode 311 and adheres to the surface of the insulating passivation layer 4; one end of the internal second electrode 313 is connected to the other end of the sidewall electrode layer 312, and the other end is connected to the adjacent battery cell 21.

[0056] Among them, the internal first electrode 311, the side wall electrode layer 312 and the internal second electrode 313 form a bridge electrode, the internal first electrode 311 is connected to the top of a battery cell 21, and the internal second electrode 313 is connected to the bottom of another battery cell 21. The side wall electrode layer 312 is attached to the surface of the insulating passivation layer 4 and connects the internal first electrode 311 and the internal second electrode 313, thereby realizing the series connection between each battery cell 21.

[0057] Optional, continue to refer to Figure 1 and Figure 2 The laser battery array 1 also includes an isolation groove 5 located between two adjacent battery cells; a portion of the internal electrode connection structure 31 is located in the isolation groove 5, and a portion of the internal electrode connection structure 31 is located at the ends of the same side of two adjacent battery cells 21.

[0058] The isolation groove 5 is a groove formed in the chip by an etching process, which is usually used to physically and electrically isolate different functional areas. In this embodiment, in the same row of battery cells 21, part of the internal electrode connection structure 31 for connecting two adjacent battery cells 21 in series is located in the isolation groove 5, so that the battery cells 21 in a row are connected in series. In different rows, such as upper and lower battery cells 21, part of the internal electrode connection structure 31 for connecting the upper and lower battery cells 21 in series is located at the same side end of the two adjacent battery cells 21, so that the battery cells 21 in different rows are connected in series.

[0059] In a specific embodiment, Figure 5 The schematic diagram of the structure of the third battery unit provided by the embodiment of the present invention is a GaAs-based laser battery array chip structure for the 650nm-850nm band as follows:

[0060] like Figure 5 As shown, the triple junction cell structure includes, from bottom to top, a buffer layer, a first junction GaAs sub-cell layer 3-1, a first tunnel junction layer 3-2, a second junction GaAs sub-cell layer 3-3, a second tunnel junction layer 3-4, a third junction GaAs sub-cell layer 3-5 and a gap layer.

[0061] The first junction GaAs sub-cell layer 3-1 includes from bottom to top: Al 0.3GaAs back field layer 60nm, GaAs base layer 3000nm, GaAs emitter layer 100nm and Alln 0.5 P window layer 1000nm;

[0062] The second junction GaAs sub-cell layer 3-3 includes from bottom to top: Al 0.3 GaAs back field layer 60nm, GaAs base layer 2500nm, GaAs emitter layer 100nm and Alln 0.5 P window layer 1000nm;

[0063] The third junction GaAs sub-cell layer 3-5 includes, from bottom to top, Al 0.3 GaAs back field layer 60nm, GaAs base layer 200nm, GaAs emitter layer 100nm and Alln 0.5 P window layer 1000nm;

[0064] The first tunneling junction layer 3-2 and the second tunneling junction layer 3-4 include: n-GaAs-Te 20nm and p-Al 0.3 GaAs-C20nm;

[0065] The insulating substrate is a sapphire substrate;

[0066] The anti-reflection layer is a titanium oxide / silicon oxide anti-reflection film.

[0067] In another specific embodiment, Figure 6 The schematic diagram of the structure of the fourth battery unit provided by the embodiment of the present invention is a GaAs-based laser battery array chip structure for the 850nm-1200nm band as follows:

[0068] like Figure 6 As shown, the triple junction cell structure includes, from bottom to top, a buffer layer, a first junction GaAs sub-cell layer 3-1, a first tunnel junction layer 3-2, a second junction GaAs sub-cell layer 3-3, a second tunnel junction layer 3-4, a third junction GaAs sub-cell layer 3-5 and a gap layer.

[0069] The first junction GaAs sub-cell layer 3-1 includes from bottom to top: (Al 0.6 Ga) 0.55 ln 0.4 As GB layer 2000nm, (Al 0.55 Ga) 0.65 ln 0.35 As OS layer 500nm, (Al 0.51 Ga) 0.7 ln 0.3 As TL layer 300nm, p-Galn 0.3The As base layer is 2300nm, the p-GalnAs base layer is 300nm, the i-GalnAs base layer is 110nm, the n-GalnAs emission layer is 220nm and the n-GalnP window layer is 100nm.

[0070] The second junction GaAs sub-cell layer 3-3 includes from bottom to top: (Al 0.6 Ga) 0.55 ln 0.4 As GB layer 2000nm, (Al 0.55 Ga) 0.65 ln 0.35 As OS layer 500nm, (Al 0.51 Ga) 0.7 ln 0.3 As TL layer 300nm, p-Galn 0.3 The As base layer is 2000nm, the p-GalnAs base layer is 300nm, the i-GalnAs base layer is 110nm, the n-GalnAs emission layer is 220nm and the n-GalnP window layer is 100nm.

[0071] The third junction GaAs sub-cell layer 3-5 includes from bottom to top: (Al 0.6 Ga) 0.55 ln 0.4 As GB layer 2000nm, (Al 0.55 Ga) 0.65 ln 0.35 As OS layer 500nm, (Al 0.51 Ga) 0.7 ln 0.3 As TL layer 300nm, p-Galn 0.3 The As base layer is 1700nm, the p-GalnAs base layer is 300nm, the i-GalnAs base layer is 110nm, the n-GalnAs emission layer is 220nm and the n-GalnP window layer is 100nm.

[0072] The first tunnel junction layer 3-2 and the second tunnel junction layer 3-4 include: n-GaAs-Te 15nm and p-Al0.3GaAs-C 30nm;

[0073] The insulating substrate is a sapphire substrate;

[0074] The anti-reflection layer is a titanium oxide / silicon oxide anti-reflection film.

[0075] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0076] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A laser battery array chip, characterized in that: It includes a substrate, and a laser cell array located on one side surface of the substrate; The laser battery array comprises at least two battery units, each of which comprises a first junction battery layer, a second junction battery layer and a third junction battery layer stacked sequentially from bottom to top; The operating wavelength of the laser cell array chip is 850nm-1200nm, and the first junction sub-cell layer, the second junction sub-cell layer and the third junction sub-cell layer all include a gradient buffer layer, an optical spacer layer, a transparent layer, a base layer, an emission layer, a window layer, a contact layer and a gate which are stacked in sequence from bottom to top.

2. The laser cell array chip according to claim 1, characterized in that: The thicknesses of the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer decrease in sequence.

3. The laser cell array chip according to claim 1, characterized in that: The base layer comprises a first base layer, a second base layer and a third base layer stacked in sequence from bottom to top; The gradient buffer layer comprises (Al 0.6 Ga) 0.55 ln 0.4 As, the optical spacing layer includes (Al 0.55 Ga) 0.65 ln 0.35 As, the transparent layer includes (Al 0.51 Ga) 0.7 ln 0.3 As, the first base layer includes p-Galn 0.3 As, the second base layer includes p-GalnAs, the third base layer includes i-GalnAs; the emission layer includes n-GalnAs; the window layer includes n-GalnP; the contact layer includes GalnAs; and the gate includes Au.

4. The laser cell array chip according to claim 3, characterized in that: The thickness of the gradient buffer layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer is the same; the thickness of the optical spacer layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer is the same; the thickness of the transparent layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer is the same; the thickness of the first base layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer decreases successively; the thickness of the second base layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer is the same; the thickness of the third base layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer is the same; the thickness of the emission layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer is the same; the thickness of the window layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer is the same.

5. The laser cell array chip according to claim 1, characterized in that: Each of the battery cells further includes a first tunnel junction layer and a second tunnel junction layer, wherein the first tunnel junction layer is disposed between the first junction sub-battery layer and the second junction sub-battery layer, and the second tunnel junction layer is disposed between the second junction sub-battery layer and the third junction sub-battery layer; The first tunnel junction layer and the second tunnel junction layer each include an n-GaAs-Te layer and a p-Al layer stacked in sequence. 0.3 GaAs-C layer; the n-GaAs-Te layer and the p-Al 0.3 The thickness of the GaAs-C layers is the same.

6. The laser cell array chip according to claim 1, characterized in that: It also includes an electrode connecting portion; the electrode connecting portion is located on a side of the substrate facing the laser cell array; The electrode connecting portion includes an internal electrode connecting structure, a first electrode and a second electrode, one end of the internal electrode connecting structure is connected to the top of one of the battery cells, and the other end of the internal electrode connecting structure is connected to the bottom of another battery cell, so that the battery cells are connected in series in sequence; the first electrode is electrically connected to the first battery cell among the battery cells connected in series in sequence, and the second electrode is electrically connected to the last battery cell among the battery cells connected in series in sequence.

7. The laser cell array chip according to claim 6, characterized in that: The battery cell also includes a buffer layer, a gap layer and an anti-reflection layer; The buffer layer is disposed between the substrate and the first junction sub-cell layer, the gap layer is disposed between the third junction sub-cell layer and the anti-reflection layer, and the anti-reflection layer is located between the gap layer and the internal electrode connection structure.

8. The laser cell array chip according to claim 7, characterized in that: The laser cell array further comprises an insulating passivation layer; The insulating passivation layer is attached to the side wall of the battery unit, and one end of the insulating passivation layer is embedded in the substrate.

9. The laser cell array chip according to claim 8, characterized in that: The internal electrode connection structure includes an internal first electrode, a sidewall electrode layer and an internal second electrode; The first electrode is provided on the surface of the insulating passivation layer and part of the battery cells away from the substrate; one end of the sidewall electrode layer is connected to the internal first electrode and adheres to the surface of the insulating passivation layer; one end of the internal second electrode is connected to the other end of the sidewall electrode layer, and the other end is connected to the adjacent battery cell.

10. The laser cell array chip according to claim 6, characterized in that: The laser battery array further includes an isolation groove located between two adjacent battery units; Part of the internal electrode connection structure is located in the isolation groove, and part of the internal electrode connection structure is located at the ends of the same side of two adjacent battery cells.

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