An infrared-enhanced single-photon avalanche diode device

Abstract

The application discloses an infrared-enhanced single-photon avalanche diode device, which comprises a P+ photosensitive region located at the center of the surface of the device, a P-injection region surrounded by the P+ photosensitive region, a deep N well surrounded by the P-injection region, and a P-type substrate surrounded by the deep N well; the upper surfaces of the P+ photosensitive region, the P-injection region, the deep N well and the P-type substrate are flush; the P+ photosensitive region absorbs photons as a photosensitive surface, and a metal anode is led out from the surface to form an ohmic contact; a P-type charge layer is embedded in the P-injection region, and an N buried layer is embedded in the deep N well, wherein the N buried layer is located below the P-type charge layer, and the P-type charge layer and the N buried layer are located at the center of the device; and the N buried layer forms a main avalanche region with a relatively deep depth. The application can effectively improve the detection efficiency of a silicon-based single-photon avalanche diode in a near-infrared wave band.

Description

Technical Field

[0001] This invention belongs to the field of single-photon detection technology, specifically relating to an infrared-enhanced single-photon avalanche diode device. Background Technology

[0002] For near-infrared single-photon detection, traditional silicon-based single-photon detectors have limitations in detection efficiency and performance. In recent years, with the development of nanotechnology and new materials, researchers have begun to explore avalanche mechanism photoelectric detection technologies based on novel low-dimensional materials, aiming to achieve detectors with high gain, room temperature operation, and wide-band response. However, these new technologies are still in the research stage and have not yet achieved large-scale application.

[0003] Silicon-based avalanche photodiodes (SAPDs) are relatively mature in the visible light band, but their detection efficiency is low in the near-infrared band. Currently, near-infrared single-photon detection technology mainly relies on avalanche photodiodes made of materials such as indium gallium arsenide (InGaAs).

[0004] While existing solutions have expanded the detection wavelength range of SPADs to some extent, they also have the following drawbacks:

[0005] High cost: Although the detection wavelength range can be extended by introducing new materials, the complex preparation of InAsGa APD and the high cost of materials such as silicon-germanium and superconductors lead to additional costs and complexity.

[0006] Complex process: Optimizing device structure by introducing reflective and diffraction layers requires high-precision nanofabrication technology, and high-voltage deep-trap process also requires extremely high process control precision.

[0007] Non-room temperature operation: Materials such as silicon-germanium and superconductors typically need to operate at low temperatures, which increases their dependence on the low-temperature environment and limits their application at room temperature.

[0008] System complexity: Frequency upconversion systems typically require additional pump sources, nonlinear media, and precise optical alignment, increasing system complexity and cost.

[0009] In conclusion, although these solutions have addressed the limited detection range of SPADs to some extent, their respective drawbacks restrict their widespread application. Summary of the Invention

[0010] In order to overcome the shortcomings of the prior art, the present invention aims to provide an infrared-enhanced single-photon avalanche diode device, which can effectively improve the detection efficiency of silicon-based single-photon avalanche diodes in the near-infrared band.

[0011] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0012] An infrared-enhanced single-photon avalanche diode device,

[0013] The device includes a P-type substrate, a deep N-well recessed on the top surface of the P-type substrate, a P-injection region recessed on the top surface of the deep N-well, a P+ photosensitive region recessed on the top surface of the P-injection region, an N-buried layer disposed below the P-injection region in the deep N-well, and the N-buried layer does not contact the P-injection region or the P-type substrate. A P-type charge layer disposed below the P+ photosensitive region in the P-injection region, and the P-type charge layer does not contact the P+ photosensitive region or the deep N-well.

[0014] In a deep N-well, N+ regions are set on both sides of the P- injection region, with the metal cathode set in the N+ region and the metal anode set in the P+ photosensitive region.

[0015] The deep N-well is further provided with an N-well, which is located below and in contact with the N+ region;

[0016] The N+ region and N-well are formed above by ion implantation. The N+ region is a heavily doped region that forms an ohmic contact cathode, while the N-well is uniformly doped.

[0017] The deep N-well is flanked by N-wells and STI protection rings. The virtual protection ring structure formed by the N-wells and STI protection rings can effectively prevent edge breakdown.

[0018] The P-type substrate also includes an STI protection ring, which contacts both the N+ region and the N-well, forming a virtual protection ring structure.

[0019] The doping concentration of the P-type charge layer is higher than that of the P-implantation region. Therefore, the electric field in the central region is stronger than that in the edge region, effectively preventing edge breakdown.

[0020] The doping concentration of the P-implantation region is 10. 15 cm -3 -10 16 cm -3 The N+ region doping concentration is 1*10 19 ~5*10 20 The N-buried layer is a moderately doped region with a doping concentration of 5*10⁻⁶. 17 -5*10 18 The P-implantation region does not need to be connected to the substrate, which greatly reduces the difficulty of the process.

[0021] The P+ photosensitive region is surrounded by a lightly doped P- implanted region with a larger diameter, which serves as a light absorption region to absorb photons. It can also increase the depletion layer thickness, thereby improving the photon detection efficiency. Furthermore, the larger diameter can effectively prevent edge breakdown effects.

[0022] The P-charge layer forms a single charge layer in the P- region and forms a main PN junction with a thicker depletion layer with the deep N-well. An edge PN junction is formed at the edge of the P-injection region and the deep N-well.

[0023] The heavily doped N-buried layer forms a single buried layer structure in the deep N-well, making the drift electric field distribution in the middle more concentrated, serving as the main avalanche region of the device. The presence of the buried layer improves the electric field uniformity and also effectively suppresses the edge breakdown effect.

[0024] P+ regions connected to ground are added to both sides of the deep N-well to serve as grounding electrodes.

[0025] When the device is working, the voltage in the N+ region is set to 0 by default. A reverse negative bias is applied to the P+ photosensitive region connected to the metal anode, so that the device works in Geiger mode. When a photon arrives and is absorbed by the device, a hole-electron pair is generated. Due to the multiplication effect, the hole-electron pair undergoes avalanche breakdown inside the device, generating a large avalanche breakdown current, which can detect weak light signals or even single photon signals.

[0026] The P-type substrate is 20-50 μm wide and 6-15 μm high; the deep N-well is 12-18 μm wide and 0.8-1.4 μm high; the P-injection region is 8-14 μm wide and smaller than the deep N-well, with a height of 0.6-1.2 μm; the P-type charge layer is 4-13 μm wide and smaller than the P-injection region, with a height of 0.1-0.2 μm; the P+ photosensitive region is 0.8-1.2 μm wide and 0.05-0.1 μm high; the N+ region is 0.8-1.2 μm wide and 0.05-0.1 μm high; the N buried layer is 4-13 μm wide and smaller than the deep N-well, with a height of 0.1-0.2 μm; the N-well is 0.8-1.2 μm wide and 0.6-1.2 μm high.

[0027] A method for fabricating an infrared-enhanced single-photon avalanche diode device includes the following steps;

[0028] Step (1): P+ regions and deep N-wells are formed on a P-type silicon substrate using CMOS processes such as photolithography, oxidation, diffusion, ion implantation, and annealing;

[0029] Step (2) An N+ region and an N-well are formed above the deep N-well by ion implantation. The N+ region is a heavily doped region that forms an ohmic contact cathode, and the N-well is uniformly doped.

[0030] Step (3): A moderately doped N-buried layer is formed in the center of the deep N-well by Gaussian doping;

[0031] Step (4): P-type heavy doping is performed in the central region of the device to form a P+ photosensitive region and a P- implantation region, wherein the P+ photosensitive region is connected to the metal anode of the SPAD;

[0032] Step (5): A P-type charge layer is prepared in the P-implanted region by ion implantation and annealing. The P-type charge layer forms a PN junction with the deep N-well.

[0033] Step (6): Fabricate contact holes related to the electrodes;

[0034] Step (7): Use photolithography, etching and metallization processes to prepare other high-layer interconnect metals to lead the electrical signals of SPAD to the contact pads; prepare infrared-enhanced single-photon avalanche diode devices.

[0035] Step (8): Sequentially deposit silicon oxide / silicon nitride passivation layers on the upper surface of the chip to prevent chip scratches and external environmental influences.

[0036] The infrared-enhanced silicon-based single-photon avalanche diode device is used in fields such as eye safety and lidar, and can be integrated on a large scale.

[0037] The beneficial effects of this invention are:

[0038] This invention increases the depletion layer thickness and improves device performance. Due to the presence of the low-doped P-injection region and the P-type charge layer, a PN junction with a wider depletion layer can be formed with the deep N-well region. The wider the depletion layer, the larger the light absorption junction area, which improves the ability to absorb photons and thus improves the detection efficiency of SPAD devices.

[0039] It increases the avalanche probability and effectively suppresses premature edge breakdown. Edge breakdown effect refers to the phenomenon that after applying reverse bias to SPAD, the electric field at the edge of the PN junction may be stronger than the electric field at the center, which eventually leads to premature avalanche in the edge region. The presence of the N buried layer 105 can concentrate the strong electric field in the center region of the device, making the electric field in the center region higher than that in the edge region. The higher the electric field, the greater the probability of avalanche. Therefore, the avalanche probability in the center region increases and the uniformity of the center electric field is improved.

[0040] This reduces tunneling noise. Classic SPAD structures, due to the high doping concentration of the P-wells, result in high tunneling noise in the PN junction formed with the deep N-wells. However, the lower doping concentration in the P-implantation region and the P-type charge layer effectively reduces tunneling noise.

[0041] Mature technology and low manufacturing cost: The device is a silicon-based SPAD device based on the 180nm standard CMOS process. After years of development, the CMOS process has formed a mature process flow and manufacturing system. This makes the CMOS process highly stable and reliable during production, which helps to reduce production costs and improve production efficiency, enabling large-scale integration. Silicon material is inexpensive and readily available, which also greatly reduces manufacturing costs.

[0042] Good environmental adaptability: The device can work stably at room temperature without the need for additional low-temperature environments. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the silicon-based SPAD device structure designed in Embodiment 1 of the present invention.

[0044] Figure 2 This is a reference structural diagram of Embodiment 2 of the present invention.

[0045] Figure 3 This is an avalanche probability curve of the SPAD device designed in Embodiment 1 of the present invention under different overbias voltages.

[0046] Figure 4 This is a graph showing the current-voltage characteristics of the P-type charge layer of the SPAD device designed in Example 1 at different concentrations.

[0047] Figure 5 This is a graph showing the detection efficiency of the P-type charge layer of the SPAD device designed in Example 1 at different depths.

[0048] Figure 6 This is a graph showing the detection efficiency of the SPAD device designed in Example 1 when the N-type buried layer is located at different depths.

[0049] Figure 7 This is a graph showing the variation of the SPAD device designed in Example 1 and the PDE of the reference structure in Example 2 with wavelength. Detailed Implementation

[0050] The present invention will now be described in further detail with reference to the accompanying drawings.

[0051] like Figure 1 As shown, a silicon-based single-photon avalanche diode structure with a single charge layer and a single buried layer includes a P+ photosensitive region 101, a P- injection region 102, a P-type charge layer 103, a deep N-well 104, an N-buried layer 105, a P-type substrate 106, an N+ region 107, an N-well 108, a metal anode 109, a metal cathode 110, a P+ region 111, and a shallow trench STI guard ring 112.

[0052] Its central region is a heavily doped P+ photosensitive region 101 with a diameter of 10 μm, which acts as a photosensitive surface to absorb photons. A metal anode 109 is drawn out from the surface to form an ohmic contact. However, because the doping concentration of the P+ photosensitive region 101 is high, the contact resistance is not significantly affected by light.

[0053] The doping concentration of the P-implantation region 102 is 10. 15 cm -3The N-buried layer 105 and the inverted doped deep N-well 104 form a deep main avalanche region. Since near-infrared photons can still be absorbed at deeper locations in the device, the near-infrared detection efficiency can be improved. Burying the N-buried layer 105 in the deep N-well 104 can concentrate the electric field in the central region, reduce the edge breakdown effect, and further improve the detection efficiency.

[0054] The P-injection region 102 is not connected to the substrate 106; the P-injection region 102 does not need to be connected to the substrate 106, which greatly reduces the process difficulty.

[0055] The P+ photosensitive region 101 is surrounded by a lightly doped P- implanted region 102 with a larger diameter, which serves as a light absorption region to further absorb photons. It can also increase the depletion layer thickness, thereby improving the photon detection efficiency. Furthermore, the larger diameter can effectively prevent edge breakdown effects.

[0056] The deep N-well 104 is flanked by N-well 108 and STI protection ring 112. The virtual protection ring structure formed by N-well 108 and STI protection ring 112 can effectively prevent edge breakdown.

[0057] The doping concentration of the P-type charge layer 103 is higher than that of the P-implantation region 102. Therefore, the electric field in the central region is stronger than that in the edge region, effectively preventing edge breakdown. At the same time, the thick depletion layer also broadens the spectral range of the device towards the near-infrared direction.

[0058] A P-charge layer 103 is inserted into the P-injection region 102 to form a single charge layer, and together with the deep N-well 104, they form a main PN junction with a relatively thick depletion layer. At the edge, the P-injection region 102 and the deep N-well 104 form an edge PN junction.

[0059] A heavily doped N-buried layer 105 is embedded in the deep N-well 104, forming a single buried layer structure. This makes the drift electric field distribution in the middle more concentrated, serving as the main avalanche region of the device. The presence of the buried layer improves the electric field uniformity and also effectively suppresses the edge breakdown effect.

[0060] P+ regions 111 connected to the ground are added to both sides of the deep N-well 104 as grounding electrodes.

[0061] When the device is working, the voltage of the N+ region 107 is set to 0 by default. A reverse negative bias voltage is applied to the P+ photosensitive region 101 connected to the metal anode 109, so that the device works in Geiger mode. When a photon arrives and is absorbed by the device, a hole-electron pair is generated. Due to the multiplication effect, the hole-electron pair undergoes avalanche breakdown inside the device, generating a large avalanche breakdown current, which can detect weak light signals or even single photon signals.

[0062] Near-infrared detection efficiency was optimized by structural modeling using TCAD software, with the doping concentration of the p-type charge layer 103 increasing from 5 × 10⁻⁶. 17 cm -3 Increased to 5×10 18 cm -3 The current-voltage characteristic curve also gradually shifts to the left, and the avalanche breakdown voltage of the SPAD device also increases.

[0063] When other conditions remain unchanged, the longitudinal center position of the P-type charge layer 103 is taken at 0.7 μm, 0.8 μm, 0.9 μm and 1.0 μm away from the device surface, respectively. It can be seen that the deeper the depth, the shorter the short-wavelength detection efficiency continuously decreases, while the longer the long-wavelength detection efficiency first increases and then decreases.

[0064] The depths of the N-buried layer 105 were set to 1.5 μm, 2 μm, and 2.5 μm, respectively;

[0065] Finally, the parameters were determined: the position of the P-type charge layer 103 was 0.9 μm, and the concentration was 1 × 10⁻⁶. 18 A novel SPAD device with an optimal structure was obtained by setting the N-layer 105 position at 1.5 μm in cm-3, achieving a detection efficiency of 15.6% at 850 nm. Based on the established detection efficiency calculation model, the simulation results are presented more intuitively.

[0066] Example 1:

[0067] The above-mentioned device structure was modeled using TCAD software in two dimensions. Since this SPAD structure is a planar symmetrical SPAD, simulating only half of the device would not affect the performance results; therefore, the right half of the device was selected for simulation. The two-dimensional simulation modeling process is as follows:

[0068] (1) Complete the initial grid design, define a rectangular region 1 with a length of 10μm in the x direction and a height of 6μm in the y direction, and the material is silicon. Lightly dopant the region 1 in a uniform distribution to form a P-type substrate 106.

[0069] (2) Define an STI protective ring structure 112 with SiO2 material and a depth of 0.5μm at a position of 8-8.5μm in the x direction;

[0070] (3) Taking the position of 1.4 μm in the y direction as the position of the highest doping concentration, Gaussian doping is performed in the range of 0 to 8 μm in the x direction to form a deep N-well 104 with a standard deviation of 0.5 and a diffusion coefficient of 0.2.

[0071] (4) N doping is performed in a region of 7-8 μm in the x direction and 0-1 μm in the y direction to form an N well 108.

[0072] (5) In the x-direction 9-10 μm range, P-type Gaussian heavy doping is performed on the surface to diffuse and form P+ region 111.

[0073] (6) At a distance of 7-8 μm in the x direction, N-type heavy doping is carried out from the surface with a Gaussian distribution to form N+ region 107.

[0074] (7) The P-type charge layer 103 is located in the x direction from 0 to 5.5 micrometers, the doping peak is 0.8 micrometers in the y direction, the standard deviation is 0.05, and the diffusion coefficient is 0.5;

[0075] (8) Lightly doping the device surface to form a P-implantation region 102 in the range of 0 to 6 micrometers, with a standard deviation of 1.2 and a diffusion coefficient of 0.5;

[0076] (9) The N buried layer 105 has a doping peak of 0 to 4 micrometers in the x direction, a doping peak of 2 micrometers in the y direction, a standard deviation of 0.2, and a diffusion coefficient of 0.5.

[0077] (10) A P+ active region is formed by heavy doping on the surface, with a doping range of 0 to 5 micrometers in the x direction, a standard deviation of 0.05, and a diffusion coefficient of 0.1.

[0078] (11) Finally, metal electrodes are set in N+ region 107 and P+ photosensitive region 101. N+ region 107 is connected to metal cathode 110 and P+ region 101 is connected to anode 109.

[0079] The temperature was set to 300K, and the device was modeled based on the Geiger model, impact ionization model, Fermi model, SRH model, mobility model, and Auger recombination model. Other process parameters are shown in Table 1. The final modeling results are consistent with those in the appendix. Figure 1 The design structure is consistent with that of the Chinese.

[0080] Table 1. SPAD process parameters for single-charge-layer and single-buried-layer structures

[0081]

[0082]

[0083] This device is compatible with 180nm CMOS technology, and the main fabrication steps are as follows:

[0084] P+ photosensitive region 101, P- region 102, P-type charge layer 103, deep N-well 104, N-buried layer 105, P-type substrate 106, N+ region 107, N-well 108, metal anode 109, metal cathode 110, P+ region 111 and shallow trench STI protection ring 112.

[0085] (1) A P+ region 111 and a deep N-well 104 are formed on a P-type silicon substrate 106 using CMOS processes such as photolithography, oxidation, diffusion, ion implantation, and annealing. The deep N-well 104 is reverse-doped.

[0086] (2) An N+ region 107 and an N-well region 108 are formed above the deep N-well 104 by ion implantation. The N+ region 107 is a heavily doped region that forms an ohmic contact cathode, and 108 is uniformly doped.

[0087] (3) A moderately doped N-buried layer 105 region is formed in the central deep N-well 104 by Gaussian doping;

[0088] (4) P+ photosensitive region 101 and P- implantation region 102 are formed by P-type heavy doping in the central region of the device using a diffusion process, wherein the P+ photosensitive region 101 is connected to the metal anode 109 of the SPAD.

[0089] (5) A P-type charge layer 103 is prepared in the P-implantation region 102 by ion implantation and annealing, and the P-type charge layer 103 forms a PN junction with the deep N-well 104.

[0090] (6) Fabricate contact holes related to the electrodes;

[0091] (7) Other high-layer interconnect metals are prepared using photolithography, etching and metallization processes to bring out the electrical signals of SPAD to the contact pads;

[0092] (8) Sequentially deposit silicon oxide / silicon nitride passivation layers on the chip surface to prevent chip scratches and external environmental influences.

[0093] Photon detection efficiency (PDE) can be represented as the product of quantum efficiency and avalanche triggering probability. However, to further quantify it and make it more intuitive and data-driven in simulation results, a scientifically effective model for calculating detection efficiency is needed.

[0094] Since the light absorption efficiency varies in different regions of the device, the calculation model for photon detection efficiency can be mainly divided into three parts, including the top photon detection efficiency P. Top Depletion layer photon detection efficiency P Dep and bottom photon detection efficiency P Bot Then the total photon detection efficiency is PDE = P Top +P Dep +P Bot .

[0095] The top layer is a P-neutral region composed of P+ region 101 and P- region 102. Regarding the top photon detection efficiency, photons are absorbed at the top layer of the device, generating photogenerated carriers. These photogenerated carriers diffuse to the depletion layer and may trigger avalanche photocurrents. Therefore, the top photon detection efficiency P... Top :

[0096]

[0097] Where α is the absorption coefficient of the device material for light with wavelength λ, and L e W1 is the electron diffusion length of the top layer, and W1 is the thickness from the top to the upper boundary of the depletion layer. See Appendix for details. Figure 1 The electron-triggered avalanche breakdown probability at the depletion region boundary is P. e (W1) can be obtained through simulation.

[0098] The depletion layer consists of an avalanche region formed between the P-type charge layer 103 and the deep N-well 104, containing a strong electric field, hence the name depletion layer. Regarding the photon detection efficiency in this part, photons are absorbed in the depletion layer, and the resulting electron-hole pairs drift in opposite directions under the influence of the electric field, potentially triggering an avalanche photocurrent. Therefore, the photon detection efficiency P of the depletion layer is... Dep :

[0099]

[0100] Where W2 is the depletion layer thickness, see appendix for details. Figure 1 α is the absorption coefficient of the device material for light with wavelength λ, and the probabilities of electrons and holes triggering avalanches at the longitudinal position x are P0 and P1, respectively. e and P h ,

[0101] The bottom portion of the deep N-well 104 lies below the depletion region. For the bottom photon detection efficiency, photons are absorbed in the well region below the depletion layer boundary, and the resulting electron-hole pairs do not recombine and directly reach the lower boundary of the depletion layer. Therefore, the bottom photon detection efficiency P... Bot :

[0102]

[0103] Where α is the absorption coefficient of the device material for light with wavelength λ, and W1+W2 is the distance from the lower boundary of the depletion layer to the device surface, see Appendix for details. Figure 1 Lp is the diffusion length of the hole in the N-well.

[0104] Example 2:

[0105] To verify that the designed device structure has optimized detection efficiency in the near-infrared band, a classic P+ / deep N-well structure was modeled using TCAD software. The device structure is shown below. Figure 2As shown.

[0106] Including: P+ region 201, P-well 202, deep N-well 203, N+ region 204, N-well 205, P-substrate 206, metal anode 207, metal cathode 208, and STI protection ring 209.

[0107] The two-dimensional simulation modeling process is as follows:

[0108] (1) Complete the initial mesh design, define a rectangular region 1 with a length of 10μm in the x direction and a height of 6μm in the y direction, and the material is silicon; define an STI protective ring structure 209 with a material of SiO2 and a depth of 0.5μm at 6~7μm and 8~10μm in the x direction; and define the electrodes.

[0109] (2) Lightly doping is uniformly distributed in region 1 to form P substrate 206.

[0110] (3) Taking the position of 1.55 μm in the y direction as the position of the highest doping concentration, Gaussian doping is performed in the range of 0 to 8 μm in the x direction to form a deep N-well 203 with a diffusion coefficient of 0.2.

[0111] (4) Uniform P doping and N doping are performed in regions of 0-4 μm in the x direction and 0-0.49 μm in the y direction, and 6-8 μm in the x direction and 0-0.7 μm in the y direction, respectively, to form P-well 202 and N-well 205.

[0112] (5) In the x-direction 0-3.5μm range, P-type Gaussian heavy doping is performed on the surface to diffuse and form P+ region 201.

[0113] (6) At a distance of 7-8 μm in the x direction, N-type Gaussian heavy doping is performed on the surface to diffuse and form N+ region 204.

[0114] (7) Set the temperature and physical model. Other process parameters are shown in Table 2.

[0115] Table 2. Process parameters of classic SPAD structure

[0116]

[0117] Based on the established model, the structural parameters of the designed SPAD device were changed using TCAD software, including the P-type charge layer concentration, P-type charge layer depth, and N-type buried layer depth. Simulation results were obtained under different structural parameters.

[0118] Over-biasing can also affect the avalanche probability of a device, thus causing changes in photon detection efficiency. For example... Figure 3The total avalanche probability distribution is shown when the overbias voltage is 1V, 3V, 4.5V and 5V respectively, with other parameters being the same. It can be seen that as the overbias voltage increases, the avalanche probability changes more gradually, that is, the total avalanche probability in the avalanche zone is greater.

[0119] Using the `Impact` statement, the collision ionization model is set to the Selberrherr model, and the `Models` statement is used to set the band-to-band tunneling standard model. Then, the cathode voltage of the avalanche diode is set to 0V, and a reverse voltage from 0V to -20V is applied to the device through the metal anode. The iteration voltage is -0.25V. After simulation, the current-voltage characteristic curves corresponding to different P-charge layer concentrations are output, such as... Figure 4 As shown. The P-type charge layer concentration was taken as 5 × 10⁻⁶. 17 cm -3 1×10 18 cm -3 and 5×10 18 cm -3 As shown in the figure, with the increase of P-type charge layer concentration, the current-voltage characteristic curve gradually shifts to the left, and the avalanche breakdown voltage of the SPAD device also increases. When the concentration is taken as 1×10⁻⁶... 18 cm -3 At that time, the SPAD breakdown voltage was approximately 11.8V.

[0120] like Figure 5 The PDE curves are shown for the P-type charge layer at different depths, with the longitudinal center positions taken at 0.7 μm, 0.8 μm, 0.9 μm, and 1.0 μm from the device surface, respectively. An overbias voltage of 30% of the breakdown voltage is used. It can be seen that as the depth of the P-type charge layer center increases, the detection efficiency in the short-wavelength range continuously decreases, while the long-wavelength detection efficiency first increases and then decreases. Taking the P-type charge layer at 0.9 μm as an example, the peak value is still found in the short-wavelength range, but compared to the values ​​at 0.7 μm and 0.8 μm, the peak value decreases and shifts towards the long-wavelength direction. However, the detection efficiency is somewhat improved in the near-infrared wavelength range; for example, at 850 nm, the detection efficiency reaches 13.68%, which is not significantly different from the detection efficiency at 1.0 μm.

[0121] like Figure 6The detection efficiency versus wavelength curves of the SPAD structure under different buried layer conditions are shown, with and without a buried layer, and with buried layers at 1.5 μm, 2 μm, and 2.5 μm, all other things being equal. As can be seen from the figures, the curve without a buried layer reaches its maximum value of 88% at 450 nm. With the addition of a buried layer, the curve shifts upwards overall, but the peak position remains at 450 nm. Furthermore, as the buried layer depth increases, the detection efficiency in the near-infrared wavelength range gradually decreases. For example, when the buried layer depth is 1.5 μm, the detection efficiency at 850 nm is 14.5%, higher than that without a buried layer and at buried depths of 2 μm and 2.5 μm. This is because the electric field distribution is more concentrated in the deep N-well, resulting in a larger PDE after integration. Therefore, under the same conditions, a buried layer depth of 1.5 μm is the optimal solution.

[0122] The above analysis shows that, under operating conditions at 300K, the optimal parameters for the location of the P-type charge layer in the new structure are 0.9 μm and the optimal concentration is 1 × 10⁻⁶. 18 To achieve a smaller breakdown voltage and suitable overbias, the buried layer is positioned at 1.5 μm with a diameter of 5 μm to ensure the electric field is concentrated in the central avalanche region. Figure 7 The curves show the detection efficiency of the reference structure SPAD and the single-charge-layer single-buried-layer structure SPAD as a function of wavelength, with overbias voltages of 1V, 3V, and 5V, respectively. As can be seen from the figures, the detection efficiency gradually increases with increasing overbias voltage. Compared to the reference structure, the detection efficiency of the new structure SPAD is significantly improved overall, with the peak region shifting towards longer wavelengths and the spectral response range widening. Particularly in the near-infrared band, when the overbias voltage is 3V, the detection efficiency of the reference structure SPAD at 850nm is approximately 4.3%, while the detection efficiency of the single-charge-layer single-buried-layer structure SPAD increases to 15.6%. This verifies that the single-charge-layer and single-buried-layer structure SPAD proposed in this invention effectively improves the detection efficiency in the near-infrared band, especially at 850nm.

Claims

1. An infrared-enhanced single-photon avalanche diode device, characterized in that, The system includes a P-type substrate (106), a deep N-well (104) disposed on the top surface of the P-type substrate (106), a P-injection region (102) disposed on the top surface of the deep N-well (104), a P+ photosensitive region (101) disposed on the top surface of the P-injection region (102), an N-buried layer (105) disposed below the P-injection region (102) in the deep N-well (104), and the N-buried layer (105) does not contact the P-injection region (102) or the P-type substrate (106). A P-type charge layer (103) disposed below the P+ photosensitive region (101) in the P-injection region (102), and the P-type charge layer (103) does not contact the P+ photosensitive region (101) or the deep N-well (104). In the deep N-well (104), N+ regions (107) are set on both sides of the P-injection region (102), the metal cathode (110) is set in the N+ region (107), and the metal anode (109) is set in the P+ photosensitive region (101).

2. The infrared-enhanced single-photon avalanche diode device according to claim 1, characterized in that, The deep N-well (104) is further provided with an N-well (108), which is located below the N+ region (107) and in contact with the N+ region (107); The N+ region (107) and N-well (108) are formed above by ion implantation. The N+ region (107) is a heavily doped region that forms an ohmic contact cathode, and the N-well (108) is uniformly doped.

3. The infrared-enhanced single-photon avalanche diode device according to claim 1, characterized in that, The deep N-well (104) is flanked by an N-well (108) and an STI protection ring (112), forming a virtual protection ring structure. The P-type substrate (106) is also provided with an STI protection ring (112), which is in contact with both the N+ region (107) and the N-well (108) to form a virtual protection ring structure.

4. The infrared-enhanced single-photon avalanche diode device according to claim 1, characterized in that, The doping concentration of the P-implantation region (102) is 10. 15 cm -3 -10 16 cm -3 The doping concentration of the N+ region (107) is 1*10 19 ~5*10 20 cm -3 The N-buried layer (105) is a moderately doped region, and the doping concentration of the N-buried layer (105) is 5*10. 17 -5*10 18 cm -3 .

5. The infrared-enhanced single-photon avalanche diode device according to claim 4, characterized in that, The doping concentration of the P-type charge layer (103) is higher than that of the P-implantation region (102).

6. The infrared-enhanced single-photon avalanche diode device according to claim 5, characterized in that, The P-type charge layer (103) forms a single charge layer in the P-injection region (102) and forms a main PN junction with a thicker depletion layer with the deep N-well (104). An edge PN junction is formed at the edge of the P-injection region (102) and the deep N-well (104). The N-buried layer (105) forms a single-buried layer structure in the deep N-well (104).

7. The infrared-enhanced single-photon avalanche diode device according to claim 1, characterized in that, The deep N-well (104) has P+ regions (111) connected to the ground on both sides as grounding electrodes.

8. The infrared-enhanced single-photon avalanche diode device according to claim 1, characterized in that, When the device is working, the voltage of the N+ region (107) is set to 0 by default. A reverse negative bias voltage is applied to the P+ photosensitive region (101) connected to the metal anode (109), so that the device works in Geiger mode. When a photon arrives and is absorbed by the device, a hole-electron pair is generated. Due to the multiplication effect, the hole-electron pair undergoes avalanche breakdown inside the device, generating a large avalanche breakdown current, which can detect weak light signals or even single photon signals.

9. The infrared-enhanced single-photon avalanche diode device according to claim 1, characterized in that, The P-type substrate (106) is 20-50 μm wide and 6-15 μm high; the deep N-well (104) is 12-18 μm wide and 0.8-1.4 μm high; the P-injection region (102) is 8-14 μm wide and smaller than the deep N-well (104) and 0.6-1.2 μm high; the P-type charge layer (103) is 4-13 μm wide and smaller than the P-injection region (102) and 0.1-0.2 μm high; the P+ photosensitive region (101) is 0.8-1.2 μm wide and 0.05-0.1 μm high; the N+ region (107) is 0.8-1.2 μm wide and 0.05-0.1 μm high; the N buried layer (105) is 4-13 μm wide and smaller than the deep N-well (104) and 0.1-0.2 μm high; and the N-well (108) is 0.8-1.2 μm wide and 0.6-1.2 μm high.

10. A method for fabricating an infrared-enhanced single-photon avalanche diode device as described in any one of claims 1-9, characterized in that, Includes the following steps; Step (1): A P+ region (111) and a deep N well (104) are formed on a P-type silicon substrate (106) using CMOS processes of photolithography, oxidation, diffusion, ion implantation and annealing. Step (2) An N+ region (107) and an N-well (108) are formed above the deep N-well (104) by ion implantation. The N+ region (107) is a heavily doped region that forms an ohmic contact cathode, and the N-well (108) is uniformly doped. Step (3): A moderately doped N buried layer (105) is formed in the center of the deep N well (104) by Gaussian doping. Step (4): P-type heavy doping is performed in the central region of the device to form a P+ photosensitive region (101) and a P- implantation region (102), wherein the P+ photosensitive region (101) is connected to the metal anode (109) of the SPAD. Step (5): A P-type charge layer (103) is prepared in the P-implantation region (102) by ion implantation and annealing. The P-type charge layer (103) forms a PN junction with the deep N-well (104). Step (6): Fabricate contact holes related to the electrodes; Step (7): Use photolithography, etching and metallization processes to prepare other high-layer interconnect metals to bring out the electrical signals of SPAD to the contact pads; Fabrication of infrared-enhanced single-photon avalanche diode devices.

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