Preparation method of solar cell and solar cell

By dividing the thickness interval of the doped polysilicon layer on the first surface of the solar cell and gradually increasing the laser power, the problem of damage to the doped polysilicon layer in the silicon wafer during laser processing is solved, and the effect of improving open circuit voltage and efficiency is achieved.

CN119997655AActive Publication Date: 2025-05-13JINKO SOLAR (HAINING) CO LTS

Patent Information

Application Number
CN202510451719.5
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-04-10
Publication Date
2025-05-13
Estimated Expiration
2045-04-10

AI Technical Summary

Technical Problem

During the laser processing process of existing TOPCon solar cells, due to consistent power, the damage to the thinner position of the polycrystalline silicon layer in the silicon wafer is increased, affecting the increase of the open circuit voltage.

Method used

By dividing the thickness intervals of the doped polysilicon layer along the center of the base layer toward the outer peripheral edge on the first surface of the solar cell, and gradually increasing the power of the laser process as the thickness of each interval is gradually increased to avoid damage to the thinner area in the middle by excessive power.

Benefits of technology

It effectively reduces laser damage on the back of the solar cell, increases the open circuit voltage, improves the efficiency of the solar cell, and extends the service life of the laser.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN119997655A_ABST
    Figure CN119997655A_ABST
Patent Text Reader

Abstract

The invention relates to the technical field of solar cells, in particular to a preparation method of a solar cell and the solar cell. The solar cell comprises a substrate layer, the substrate layer is provided with a first face and a second face which are oppositely arranged, the first face is provided with a first area and a second area, and the preparation method comprises the steps that a doped polycrystalline silicon layer is formed on the first face; and removing the doped polycrystalline silicon layer in the first region by adopting a laser process, and gradually increasing the power of the laser process along with the gradual increase of the thickness of the doped polycrystalline silicon layer in the direction from the center of the substrate layer to the peripheral edge. The corresponding laser power is set according to the thicknesses of different regions of the doped polycrystalline silicon layer, and the damage to the middle region of the solar cell due to the fact that the doped polycrystalline silicon layer in the middle thin region is removed by using relatively high power is avoided, so that the open-circuit voltage is improved, the efficiency is improved, and the service life of the solar cell is prolonged under the condition that the doped polycrystalline silicon layer is removed. The service life of the laser is prolonged, and the fragmentation rate of silicon wafers in the laser processing process is reduced.
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a method for preparing a solar cell and a solar cell. Background Art

[0002] In the current tunneling oxide passivated contact (TOPCon) cells, the thickness distribution of the doped polysilicon layer on the back of the silicon wafer after phosphorus diffusion is thick in the middle and thin at the edges. In order to ensure that the doped polysilicon layer can be removed cleanly, the power of the laser setting is currently consistent.

[0003] However, consistent laser power will cause greater damage to the thinner part of the doped polysilicon layer in the middle of the silicon wafer, which is not conducive to the improvement of the open circuit voltage. Summary of the invention

[0004] The embodiments of the present application provide a method for preparing a solar cell and a solar cell, aiming to reduce laser damage to the back side of the solar cell, increase the open circuit voltage, and improve the efficiency of the solar cell.

[0005] The embodiment of the present application provides a method for preparing a solar cell, wherein the solar cell includes a substrate layer, wherein the substrate layer has a first surface and a second surface arranged opposite to each other, wherein the first surface has a first region and a second region, and the preparation method includes: forming a doped polysilicon layer on the first surface; The doped polysilicon layer located in the first region is processed by a laser process, and the doped polysilicon layer (13) in the first region (11a1) is divided into thickness intervals with a gradient increasing from a preset thickness along the direction from the center of the base layer to the outer edge, and the power of the laser process is gradually increased as the thickness of the doped polysilicon layer in each thickness interval gradually increases.

[0006] In a possible design, in the step of gradually increasing the power of the laser process as the thickness of the doped polysilicon layer gradually increases, the preparation method further includes: Along the direction from the center to the peripheral edge of the base layer, the power of the laser process increases by 1%-2% for every 3 nm increase in the thickness of the doped polysilicon layer.

[0007] In a possible design, after the step of forming the doped polysilicon layer on the first surface, the preparation method further includes: Measuring the thickness of the doped polysilicon layer in the first region along the direction from the center to the outer edge of the base layer by using an ellipsometer, and dividing the thickness of the doped polysilicon layer in the first region into n thickness intervals with a gradient increasing by the preset thickness; Among them, the n thickness intervals include at least a first thickness interval and a second thickness interval, the laser process is provided with at least a first laser and a second laser, the first laser processes the doped polysilicon layer in the first thickness interval, the second laser processes the doped polysilicon layer in the second thickness interval, and the power of the second laser is greater than the power of the first laser.

[0008] In one possible design, the power of the laser process is 45W-60W.

[0009] In one possible design, the frequency of the laser process is 600KHz; The speed of the laser process is 50000 mm / s, and the pulse width of the laser process is 0.5 μs.

[0010] In a possible design, in the step of processing the doped polysilicon layer located in the first region by using the laser process, the preparation method further includes: The doped polysilicon layer in the first region is laser etched at least twice using the laser process.

[0011] In a possible design, after the step of processing the doped polysilicon layer located in the first region by laser processing, the preparation method further includes: The first region is cleaned with an alkaline solution.

[0012] In one possible design, the preparation method further includes: Texturing the first surface to form a first tower base; After cleaning with an alkaline solution, the size of the first tower base in the first area is a, and the size of the first tower base in the second area is b, 2≤a / b≤4.

[0013] In one possible design, the preparation method further includes: A first electrode is formed on the second region.

[0014] The embodiment of the present application further provides a solar cell, the solar cell is prepared by the above-mentioned method for preparing a solar cell, the solar cell comprises a substrate layer, the substrate layer has a first surface and a second surface arranged opposite to each other; A tunneling oxide layer, a doped polysilicon layer, a back anti-reflection layer and a first electrode are formed on the first surface.

[0015] The beneficial effects of the embodiments of the present application are as follows: according to the thickness of different areas of the doped polysilicon layer, the corresponding laser power is set to avoid using a larger power to remove the doped polysilicon layer in the thinner middle area, which would damage the middle area of ​​the solar cell. This can ensure that the doped polysilicon layer is removed, thereby increasing the open circuit voltage, improving the efficiency, and increasing the service life of the laser, and reducing the fragmentation rate of the silicon wafer during the laser processing process.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic cross-sectional view of a partial structure of a solar cell provided in this application; Figure 2 A schematic diagram of the first surface of the solar cell provided in this application; Figure 3 A schematic diagram of forming a tunneling oxide layer on a first surface of a solar cell provided in the present application; Figure 4 A schematic diagram of forming a doped polysilicon layer on a first surface of a solar cell provided in the present application; Figure 5 is a schematic diagram of using a laser process to process a doped polysilicon layer in a first region of a first surface; Figure 6 A schematic diagram of various thickness gradients of a doped polysilicon layer in a first region of a first surface provided by the present application; Figure 7 A schematic diagram of the thickness of the doped polysilicon layer corresponding to the first region provided in the present application using the corresponding laser.

[0018] Reference numerals: 1- Solar cell; 11 - basal layer; 11a-side 1; 11a1-first area; 11a2-Second area; 11b-side 2; 12- tunneling oxide layer; 13- doped polysilicon layer; 13a-amorphous silicon; 14- back anti-reflection layer; 15- a first electrode; 16-emitter; 17- passivation layer; 18- positive anti-reflection layer; 19- a second electrode; 21- first thickness interval; 22- second thickness interval; 23- third thickness interval; 31-first laser; 32-second laser; 33- The third laser.

[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application. DETAILED DESCRIPTION

[0020] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0021] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0022] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0023] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0024] It should be noted that the directional words such as "upper", "lower", "left", and "right" described in the embodiments of the present application are described at the angles shown in the accompanying drawings and should not be understood as limiting the embodiments of the present application. In addition, in the context, it is also necessary to understand that when it is mentioned that an element is connected to another element "upper" or "lower", it can not only be directly connected to another element "upper" or "lower", but also indirectly connected to another element "upper" or "lower" through an intermediate element.

[0025] like Figure 1The figure shows a schematic cross-sectional view of a solar cell 1, which includes a substrate layer 11, which is an N-type silicon substrate. The substrate layer 11 has a first surface 11a and a second surface 11b that are arranged opposite to each other, and a tunneling oxide layer 12, a doped polysilicon layer 13, a back anti-reflection layer 14, and a first electrode 15 are sequentially formed on the first surface 11a of the solar cell 1. An emitter 16, a passivation layer 17, a front anti-reflection layer 18, and a second electrode 19 are sequentially formed on the second surface 11b of the solar cell 1.

[0026] Among them, Figure 2 The schematic diagram of the first surface 11a of the solar cell 1 is shown. Both the first surface 11a and the second surface 11b have a first region 11a1 and a second region 11a2. The second region 11a2 refers to a region on the first surface 11a where a metal electrode is disposed, and the first region 11a1 refers to a region on the first surface 11a where no metal electrode is disposed. That is, the region on the first surface 11a other than the second region 11a2 is the first region 11a1. The distribution of the first region 11a1 and the second region 11a2 on the second surface 11b is similar to that on the first surface 11a, and this embodiment will not be described in detail here.

[0027] based on Figure 1 The solar cell 1 shown, the preparation method of the solar cell 1 may include: S1: The first surface 11a and the second surface 11b of the base layer 11 are textured to form a first tower base on the first surface 11a and a second tower base on the second surface 11b, thereby reducing the reflectivity of the first surface 11a and the second surface 11b and removing mechanical damage on the first surface 11a and the second surface 11b of the base layer 11.

[0028] S2: doping the base layer 11 with boron to form a PN junction to achieve conversion of light energy into electrical energy.

[0029] S3: Alkaline polishing treatment is performed to remove redundant PN junctions on the first surface 11 a to prevent a diffusion layer from being formed around the first surface 11 a and causing a short circuit.

[0030] S4: Continue to deposit SiO2 on the first surface 11a to form a tunnel oxide layer 12 to provide good interface passivation.

[0031] S5: forming amorphous silicon on the tunnel oxide layer 12, doping the amorphous silicon with phosphorus, and forming a doped polysilicon layer 13 after annealing to form a good passivation contact structure. The tunnel oxide layer 12 and the doped polysilicon layer 13 effectively reduce the interface recombination loss of the solar cell 1, improve the open circuit voltage and fill factor of the solar cell 1, and thus improve the photoelectric conversion efficiency of the solar cell 1.

[0032] S6: using a laser process to process the doped polysilicon layer 13 in the first region 11a1 of the first surface 11a to reduce parasitic light absorption.

[0033] S7: Cleaning the doped polysilicon layer 13 using the RCA process.

[0034] S8: depositing an Al2O3 electrode on the emitter 16 of the second surface 11b to form a passivation layer 17, passivating the first surface 11a, reducing the recombination rate of the first surface 11a, and increasing secondary reflection.

[0035] S9: depositing SiNx on the doped polysilicon layer 13 to form a back anti-reflection layer 14 .

[0036] S10: SiNx is deposited on the passivation layer 17 to form a positive anti-reflection layer 18 , and the thin film interference principle is used to reduce the reflection of light, thereby reducing the light reflection on the surface of the first surface 11 a and improving the conversion efficiency of the solar cell 1 .

[0037] S11: Screen printing and sintering are performed on the second region 11a2 of the back anti-reflection layer 14 to form a first electrode 15. Screen printing and sintering are performed on the second region 11a2 of the front anti-reflection layer 18 to form a second electrode 19. The first electrode 15 and the second electrode 19 can collect the current generated in the PN junction of the solar cell 1 due to light and transmit it to an external load.

[0038] In other embodiments, the solar cell may be manufactured by using other manufacturing processes, which is not limited in this embodiment.

[0039] Among them, please refer to Figure 3 , Figure 3 Schematic diagram of forming a tunnel oxide layer 12 on a silicon wafer. After removing the first surface 11a by an alkali polishing process, SiO2 is deposited on the first surface by an LPCAD (Low Pressure Chemical Vapor Deposition) process to form a tunnel oxide layer 12, and amorphous silicon 13a is formed on the tunnel oxide layer 12.

[0040] Please refer to Figure 4 , Figure 4 To form a schematic diagram of a doped polysilicon layer 13 , the amorphous silicon 13 a is further doped with phosphorus (the dots in the figure represent phosphorus) to form a doped polysilicon layer 13 (including PSG (Phosphosilicate Glass)).

[0041] Then, please refer to Figure 5 , Figure 5The schematic diagram of using laser technology to process the doped polysilicon layer 13 in the first area 11a of the first surface 11a is shown in the figure. The curved box area in the figure represents the laser scanning area. After the doped polysilicon layer 13 is formed, the first area 11a1 of the first surface 11a is scanned by laser to remove the doped polysilicon layer 13 located in the first area 11a1.

[0042] It should be noted that, in actual operation, when processing the doped polysilicon layer 13 located in the first region 11a1 of the first surface 11a, part of the tunneling oxide layer 12 located in the first region 11a1 of the first surface 11a may also be removed (e.g. Figure 4 Alternatively, in actual operation, when processing the doped polysilicon layer 13 located in the first region 11a1 of the first surface 11a, a portion of the tunneling oxide layer 12 located in the first region 11a1 of the first surface 11a will not be removed.

[0043] Specifically, the specific process of forming the phosphorus-doped polysilicon layer 13 may be: Step 1: Place the silicon wafer that has undergone the LPCAD (Low Pressure Chemical Vapor Deposition) process into the phosphorus expansion furnace tube to complete the temperature increase T1 and leak detection.

[0044] Among them, in step 1, the silicon wafer enters the furnace tube and needs to be heated to the required temperature (the temperature will decrease when the furnace door is opened), and a leak test is performed to determine the furnace tube conditions. After the furnace tube conditions are qualified, the normal process can be carried out.

[0045] Specifically, the heating temperature T1 can be set at 780°C~800°C, the constant pressure can be set at 50mBar~150mBar, and the N2 flow rate can be set at 500sccm~4000sccm. Among them, the pressure setting can be set to 1030mBar to check the airtightness.

[0046] Step 2: Raise the temperature to the preset deposition temperature T2 to complete the pre-oxidation.

[0047] Among them, in step 2, the role of the pre-oxidation is to generate an oxide layer, reduce the influence of the dead layer, and improve surface passivation.

[0048] Specifically, the heating temperature T2 can be set at 800°C~850°C, the constant pressure can be set at 50mBar~150mBar, the front oxygen N2 flow rate can be set at 500sccm~4000sccm, the O2 flow rate can be set at 500sccm~4000sccm, and the small nitrogen flow rate can be set at 500sccm~4000sccm.

[0049] Step 3: Raise the temperature to T3 to complete deposition.

[0050] Wherein, in step 3, impurity deposition is performed on the surface of the silicon wafer.

[0051] Specifically, the heating temperature T3 can be set at 800℃~860℃, the constant pressure can be set at 50mBar~150mBar, the front oxygen N2 flow rate can be set at 500sccm~4000sccm, the O2 flow rate can be set at 500sccm~4000sccm, the small nitrogen flow rate can be set at 100sccm~4000sccm, and the source chemical can be set to POCL3.

[0052] Step 4: Raise the temperature to the push temperature T4 to perform push crystallization.

[0053] Among them, in step 4, the impurities deposited on the surface diffuse into the interior of the silicon wafer, and the polysilicon is crystallized at high temperature.

[0054] Specifically, the heating temperature T4 can be set at 870° C. to 920° C., the constant pressure can be set at 50 mBar to 300 mBar, and the N2 flow rate can be set at 500 sccm to 4000 sccm.

[0055] Step 5: Oxidation cooling annealing.

[0056] Among them, in step 5, after oxidation cooling annealing, a thicker PSG (Phosphosilicate Glass) is generated to serve as a protective layer for subsequent processes. Annealing causes the metal impurities inside the silicon wafer to condense and reduce recombination.

[0057] Specifically, the oxidation cooling to the outlet temperature can be set at 780°C~860°C, the O2 flow rate can be set at 500sccm~4000sccm, the N2 flow rate can be set at 500sccm~4000sccm, and the constant pressure can be set at 300 mBar~600mBar.

[0058] In other embodiments, other manufacturing processes may be used to manufacture the doped polysilicon layer, which is not limited in this embodiment.

[0059] Among them, in the step of forming the doped polysilicon layer 13, since the surrounding gas atmosphere in the reaction chamber (furnace tube) is more likely to contact the surroundings of the silicon wafer, the generated SiO2 has the characteristics of being thin in the middle and thick at the edges. The deposited SiO2 and P2O5 also have the characteristics of being thin in the middle and thick at the edges. The doped polysilicon layer 13 formed in the subsequent oxidation annealing process also has the characteristics of being thick at the surroundings and thin in the middle, resulting in the thickness distribution of PSG (Phosphosilicate Glass) in the generated doped polysilicon layer 13 having the characteristics of being thin in the middle and thick at the edges.

[0060] In this regard, in this embodiment, in the step of using a laser process to remove the doped polysilicon layer 13 located in the first area 11a1, the preparation method also includes: along the direction from the center of the base layer 11 to the outer edge, as the thickness of the doped polysilicon layer 13 gradually increases, the power of the laser process gradually increases.

[0061] That is to say, along the direction from the center to the outer edge of the base layer 11, the doped polysilicon layer 13 of the first area 11a1 is divided into thickness intervals with a gradient increasing by a preset thickness, and as the thickness of the doped polysilicon layer 13 in each thickness interval gradually increases, the power of the laser process gradually increases.

[0062] Specifically, if Figure 6 The diagram shows the distribution of the doped polysilicon layer 13 in the first area 11a1 on the first surface 11a. According to the thickness variation of the doped polysilicon layer 13, the doped polysilicon layer 13 in the first area 11a1 is divided into n thickness intervals, where n≥2. The density of the shaded portion in the figure indicates the thickness of the doped polysilicon layer 13 in each interval, that is, the greater the density of the shaded portion, the thicker the thickness of the doped polysilicon layer 13 in the interval, and the less the density of the shaded portion, the thinner the thickness of the doped polysilicon layer 13 in the area.

[0063] For example, please refer to Figure 6 In this embodiment, the doped polysilicon layer 13 in the first area 11a1 is divided into three thickness intervals as an example. Along the direction from the center to the outer edge of the base layer 11, the doped polysilicon layer 13 in the first area 11a1 is divided into a first thickness interval 21, a second thickness interval 22 and a third thickness interval 23. The thickness of the doped polysilicon layer 13 in the first thickness interval 21 is less than the thickness of the doped polysilicon layer 13 in the second thickness interval 22, and the thickness of the doped polysilicon layer 13 in the second thickness interval 22 is less than the thickness of the doped polysilicon layer 13 in the third thickness interval 23.

[0064] Correspondingly, as shown in FIG7 , it is a schematic diagram of using different laser powers for processing according to the thickness of each thickness interval. Specifically, the first laser 31 is set to process the doped polysilicon layer 13 of the first thickness interval 21, the second laser 32 is set to process the doped polysilicon layer 13 of the second thickness interval 22, and the third laser 33 is set to process the doped polysilicon layer 13 of the third thickness interval 23. Among them, since the thickness of the doped polysilicon layer 13 in the first thickness interval 21 is less than the thickness of the doped polysilicon layer 13 in the second thickness interval 22, and the thickness of the doped polysilicon layer 13 in the second thickness interval 22 is less than the thickness of the doped polysilicon layer 13 in the third thickness interval 23, the power of the first laser 31 is set to be less than the power of the second laser 32, and the power of the second laser 32 is set to be less than the power of the third laser 33.

[0065] Of course, according to the step change of the thickness of the doped polysilicon layer 13, the doped polysilicon layer 13 in the first region 11a1 may also include a fourth thickness range, a fifth thickness range, etc. Correspondingly, a fourth laser is set to process the doped polysilicon layer 13 in a fourth thickness range, a fifth laser is set to process the doped polysilicon layer 13 in a fifth thickness range, and so on. The specific settings can be made according to actual conditions and are not limited in this embodiment.

[0066] In this embodiment, the corresponding laser power is set according to the thickness of different regions of the doped polysilicon layer 13, so as to avoid using a larger power to remove the doped polysilicon layer 13 in the middle thinner region, thereby avoiding damage to the middle region of the solar cell 1. While ensuring the removal of the doped polysilicon layer 13, the open circuit voltage is increased, the efficiency is improved, and the fragmentation rate of the silicon wafer during the laser processing process is reduced.

[0067] At the same time, it avoids the waste of laser resources, increases the service life of the laser and saves costs.

[0068] Specifically, in this embodiment, the thickness of the doped polysilicon layer 13 in the first region 11a1 is set to increase by 3nm as a gradient, and the laser power is adjusted by 1%-2% accordingly. That is, along the direction from the center to the peripheral edge of the base layer 11, the power of the laser process increases by 1%-2% for every 3nm increase in the thickness of the doped polysilicon layer 13.

[0069] For example, please continue to refer to Figure 6 and Figure 7 In this embodiment, the thickness of the doped polysilicon layer 13 is changed by 3nm as a gradient, and the doped polysilicon layer 13 of the first region 11a1 is divided into multiple thickness intervals. Specifically, the thickness of the doped polysilicon layer 13 in the first thickness interval 21 is approximately 3nm different from the thickness of the doped polysilicon layer 13 in the second thickness interval 22, and the thickness of the doped polysilicon layer 13 in the second thickness interval 22 is approximately 3nm different from the thickness of the doped polysilicon layer 13 in the third thickness interval 23, and so on. Correspondingly, the power of the second laser 32 can be increased by 1%-2% compared with the power of the first laser 31, and the power of the third laser 33 can be increased by 1%-2% compared with the power of the second laser 32, and so on.

[0070] For further example, the thickness of the doped polysilicon layer 13 in the first thickness interval 21 may be 34 nm, and correspondingly, the power of the first laser 31 may be set to 53 W. The thickness of the doped polysilicon layer 13 in the second thickness interval 22 may be 37 nm, and correspondingly, the power of the second laser 32 may be set to 53.7 W. The thickness of the doped polysilicon layer 13 in the third thickness interval 23 may be 40 nm, and correspondingly, the power of the third laser 33 may be set to 54.4 W, and so on.

[0071] In this embodiment, if the laser power for processing the doped polysilicon layer 13 in the first thickness interval 21 is too large, such as using the power of the third laser 33 to process the doped polysilicon layer 13 in the first thickness interval 21, the base layer 11 may be affected and damaged. If the power of the third laser corresponding to processing the doped polysilicon layer 13 in the third thickness interval 23 is too small, such as using the power of the first laser 31 to process the doped polysilicon layer 13 in the third thickness interval 23, the doped polysilicon layer 13 in the third thickness interval 23 may not be completely removed.

[0072] Similarly, if the laser power for processing the doped polysilicon layer 13 in the second thickness interval 22 is too large, such as using the power of the third laser 33 to process the doped polysilicon layer 13 in the second thickness interval 22, the base layer 11 may be affected and damaged. If the power of the second laser corresponding to processing the doped polysilicon layer 13 in the second thickness interval 22 is too small, such as using the power of the first laser 31 to process the doped polysilicon layer 13 in the second thickness interval 22, the doped polysilicon layer 13 in the second thickness interval 22 may not be completely removed.

[0073] Alternatively, along the direction from the center to the peripheral edge of the base layer 11, the rising preset thickness of the doped polysilicon layer 13 of the first region 11a1 can also be set to other values. For example, the doped polysilicon layer 13 of the first region 11a1 can also be divided into multiple thickness intervals according to the thickness of the doped polysilicon layer 13 changing by 2nm as a gradient, the thickness of the doped polysilicon layer 13 changing by 4nm as a gradient, the thickness of the doped polysilicon layer 13 changing by 5nm as a gradient, etc. Correspondingly, the laser power corresponding to each thickness interval is adjusted on the basis of being able to remove the doped polysilicon layer 13 of each thickness interval and minimizing damage to other layer structures. The specific setting can be based on the actual situation, and this embodiment is not limited here.

[0074] In some embodiments, the power of the laser process for processing the doped polysilicon layer 13 of the first region 11a1 can be set to 45W-60W, and the corresponding laser power can be adjusted according to the thickness of the doped polysilicon layer 13 in each thickness range. For details, please refer to the above content, and this embodiment will not be repeated here. The parameters of the laser process can be set according to actual conditions, and the parameters are increased or decreased, which are not limited in this embodiment.

[0075] The laser may be an infrared laser, an ultraviolet laser, etc., which scans the first area 11a1 to process the doped polysilicon layer 13 of the first area 11a1, while the doped polysilicon layer 13 of the second area 11a2 will not be affected, which is convenient for subsequent etching processing.

[0076] In some embodiments, the frequency of the laser process may be 600 KHz to improve efficiency. The parameters of the laser process may be increased or decreased according to actual conditions, and this embodiment is not limited thereto.

[0077] In some embodiments, the speed of the laser process can be 50000 mm / s to reduce the processing time. The pulse width of the laser process can be 0.5 μs, the laser process light-on delay can be 40 μs, and the laser process light-off delay can be 100 μs. The parameters of the laser process can be increased or decreased according to the actual situation, and this embodiment is not limited here.

[0078] In some embodiments, in the step of removing the doped polysilicon layer 13 located in the first region 11a1 by using a laser process, the preparation method further includes: performing laser etching on the doped polysilicon layer 13 in the first region 11a1 at least twice by using a laser process.

[0079] Since the width of a single laser scan is limited, the number of laser scans can be adjusted according to the width range of each thickness interval when the laser scans each thickness interval to ensure that the doped polysilicon layer 13 in each thickness interval is completely removed.

[0080] Exemplarily, the number of laser scans may be 2 times, 3 times, 4 times, etc., and may be specifically set according to actual conditions to increase or decrease the number of laser scans, which is not limited in this embodiment.

[0081] In some embodiments, the thickness of the doped polysilicon layer 13 is measured by an instrument to ensure the accuracy of the measurement. For example, an ellipsometer can be used for measurement. Alternatively, other instruments can be used to measure the thickness of the doped polysilicon layer 13 to ensure the accuracy of the thickness measurement of the doped polysilicon layer 13, which is not limited in this embodiment.

[0082] Specifically, after the step of forming the doped polysilicon layer 13 on the first surface 11a, the preparation method further includes: measuring the thickness of the doped polysilicon layer 13 in the first area 11a1 along the direction from the center to the outer edge of the base layer 11 by using an ellipsometer, dividing the thickness of the doped polysilicon layer 13 in the first area 11a1 into a plurality of thickness intervals with a gradient increase of 3nm, and correspondingly adjusting the laser process to a power corresponding to each gradient thickness interval for laser etching.

[0083] Ellipsometer is an optical measuring device used to detect film thickness, optical constants and material microstructure. The ellipsometer does not contact the sample to be tested, does not damage the sample to be tested and does not require a vacuum test environment. Ellipsometer has the advantages of high measurement accuracy, non-contact, non-destructive and does not require a vacuum.

[0084] It should be noted that the operating principle of the ellipsometer is a known technology and will not be described in detail in this embodiment.

[0085] After the step of processing the doped polysilicon layer 13 located in the first region 11 a 1 by using a laser process, the preparation method further comprises: cleaning the first region 11 a 1 by using an alkaline solution.

[0086] The first region 11 a 1 is cleaned and modified by an alkaline solution to remove impurities in the first region 11 a 1 , in preparation for depositing the back anti-reflection layer 14 .

[0087] The alkaline solution may be a potassium hydroxide solution or an aqueous solution. Alternatively, other solutions may be used, which may be set according to actual conditions and are not limited in this embodiment.

[0088] After the first area 11a1 is cleaned with an alkaline solution, the first tower base of the first area 11a1 is etched, and the size of the first tower base is increased, which can increase the number of reflections of light between the first tower bases in the first area 11a1, reduce the reflectivity of the first area 11a1, and improve the photoelectric conversion efficiency and performance of the solar cell 1.

[0089] In some embodiments, the size of the first tower base is a, the size of the first tower base in the second area 11a2 is b, 2≤a / b≤4. For example, the size of the first tower base in the first area 11a1 can be 2, 3, 4 times the size of the first tower base in the second area 11a2.

[0090] This embodiment also provides a photovoltaic module, which includes a first cover plate, a first adhesive film, a battery string, a second adhesive film, and a second cover plate in a stacked manner, wherein the battery string includes a plurality of electrically connected solar cells 1. The solar cell is prepared by the preparation method described above.

[0091] The first cover is located on the light-facing side of the battery string, used to transmit sunlight, and also used to improve the waterproof and moisture-proof ability of the photovoltaic module, and seal the battery string together with the second cover. During the lamination process of the photovoltaic module, the first adhesive film and the second adhesive film are used to encapsulate the battery string to prevent the external environment from affecting the performance of the battery string, and at the same time, the first cover, the battery string and the second cover are bonded into a whole.

[0092] The material of the first adhesive film and the second adhesive film can be one of the materials such as ethylene-vinyl acetate copolymer (Ethylene-VinylAcetate Copolymer EVA), polyolefin elastomer (Polyolefin Elastomer POE), polyvinyl butyral (Polyvinyl Butyral PVB), and can also be EPE adhesive film (EVA-POE-EVA co-extrusion structure) or EP adhesive film (EVA-EP co-extrusion structure).

[0093] This embodiment also provides a stacked cell, which includes a top cell, an intermediate connection layer and a bottom cell, wherein the intermediate connection layer is connected between the bottom cell and the top cell. The top cell is one of a perovskite cell, a cadmium telluride solar cell 1, a copper indium gallium selenide solar cell 1 or a gallium arsenide solar cell 1, and the bottom cell is the above-mentioned solar cell 1.

[0094] For the selection of the intermediate connection layer, a transparent material with a high refractive index is usually selected. An effective intermediate connection layer needs to have high light transmittance to reduce the reflection and absorption of light at the connection layer interface, and good conductivity to reduce the impact of series resistance on device performance. For example, a transparent conductive metal oxide film (ITO) can be used as the intermediate connection layer.

[0095] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a solar cell, characterized in that: The solar cell (1) comprises a base layer (11), the base layer (11) having a first surface (11a) and a second surface (11b) arranged opposite to each other, the first surface (11a) having a first region (11a1) and a second region (11a2), and the preparation method comprises: forming a doped polysilicon layer (13) on the first surface (11a); The doped polysilicon layer (13) located in the first region (11a1) is processed by a laser process, and the doped polysilicon layer (13) in the first region (11a1) is divided into thickness intervals with a gradient of increasing preset thicknesses along a direction from the center of the base layer (11) to the peripheral edge, and as the thickness of the doped polysilicon layer (13) in each thickness interval gradually increases, the power of the laser process gradually increases.

2. The method for preparing a solar cell according to claim 1, characterized in that: In the step where the power of the laser process is gradually increased as the thickness of the doped polysilicon layer (13) gradually increases, the preparation method further comprises: Along the direction from the center to the peripheral edge of the base layer (11), the power of the laser process increases by 1%-2% for every 3nm increase in the thickness of the doped polysilicon layer (13).

3. The method for preparing a solar cell according to claim 1, characterized in that: After the step of forming the doped polysilicon layer (13) on the first surface (11a), the preparation method further comprises: Along the direction from the center of the base layer (11) to the peripheral edge, the thickness of the doped polysilicon layer (13) in the first region (11a1) is measured using an ellipsometer, and the thickness of the doped polysilicon layer (13) in the first region (11a1) is divided into n thickness intervals with a gradient increasing from the preset thickness; The n thickness intervals include at least a first thickness interval (21) and a second thickness interval (22); the laser process is provided with at least a first laser (31) and a second laser (32); the first laser (31) processes the doped polysilicon layer (13) in the first thickness interval (21); the second laser (32) processes the doped polysilicon layer (13) in the second thickness interval (22); and the power of the second laser (31) is greater than the power of the first laser (32).

4. The method for preparing a solar cell according to any one of claims 1 to 3, characterized in that: The power of the laser process is 45W-60W.

5. The method for preparing a solar cell according to any one of claims 1 to 3, characterized in that: The frequency of the laser process is 600KHz; The speed of the laser process is 50000 mm / s, and the pulse width of the laser process is 0.5 μs.

6. The method for preparing a solar cell according to any one of claims 1 to 3, characterized in that: In the step of using the laser process to process the doped polysilicon layer (13) located in the first area (11a1), the preparation method further comprises: The doped polysilicon layer (13) in the first region (11a1) is laser etched at least twice using the laser process.

7. The method for preparing a solar cell according to any one of claims 1 to 3, characterized in that: After the step of processing the doped polysilicon layer (13) located in the first area (11a1) by laser processing, the preparation method further comprises: The first area (11a1) is cleaned with an alkaline solution.

8. The method for preparing a solar cell according to any one of claims 1 to 3, characterized in that: The preparation method further comprises: Forming a first tower base by forming a texture on the first surface (11a); After cleaning with an alkaline solution, the size of the first tower base in the first area (11a1) is a, and the size of the first tower base in the second area (11a2) is b, and 2≤a / b≤4.

9. The method for preparing a solar cell according to any one of claims 1 to 3, characterized in that: The preparation method further comprises: A first electrode (15) is formed on the second region (11a2).

10. A solar cell, characterized in that: The solar cell (1) is prepared by the method for preparing a solar cell (1) according to any one of claims 1 to 9, the solar cell (1) comprising a substrate layer (11), the substrate layer (11) having a first surface (11a) and a second surface (11b) arranged opposite to each other; The first surface (11a) is formed with a tunneling oxide layer (12), a doped polysilicon layer (13), a back anti-reflection layer (14) and a first electrode (15).

Citation Information

Patent Citations

  • Preparation method of solar cell, solar cell and photovoltaic module

    CN114784148A

  • Manufacturing method of solar cell

    CN115148586A

  • Battery piece scribing device

    CN117153947A

  • Solar cell and photovoltaic module

    CN117352563A

  • Back contact heterojunction solar cell, preparation method thereof and cell module

    CN118825138A

Cited By

  • Solar cell preparation method, solar cell, laminated cell and photovoltaic module

    CN121001445A