Back contact battery, preparation method thereof and photovoltaic system

Abstract

The invention relates to the technical field of back contact cells, and particularly discloses a back contact cell and a preparation method thereof, and a photovoltaic system, the back contact cell comprises a silicon substrate, and the backlight surface of the silicon substrate is provided with a plurality of first areas and second areas which are alternately arranged; the first semiconductor composite layer is arranged in the first region and comprises a tunneling passivation layer and a first doping layer which are sequentially arranged in the direction away from the silicon substrate; the second semiconductor composite layer is at least partially arranged in the second area and comprises a passivation contact layer and a second doping layer which are sequentially arranged in the direction away from the silicon substrate, and the polarity of the second doping layer is opposite to that of the first doping layer; the composite TCO layer is arranged in at least partial areas of the sides, back to the silicon substrate, of the first doping layer and the second doping layer, the composite TCO layer comprises a first TCO layer and a second TCO layer which are sequentially arranged in the direction away from the silicon substrate, a plurality of holes are distributed in the first TCO layer, and the holes are provided with openings at least in the side, away from the second TCO layer, of the first TCO layer. According to the back contact battery structure, the back reflection effect on light can be effectively improved, the light utilization rate is improved, and then the battery conversion efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of back-contact batteries, and in particular to a back-contact battery and a preparation method thereof, and a photovoltaic system. Background Art

[0002] Existing back-contact cells usually have P-type emitters and N-type back surface fields alternately arranged on the backlit side of the silicon wafer. In some back-contact cells, a layer of transparent conductive film is also sputtered on the P-type emitter and the N-type back surface field, and then the PN region spacing area is isolated by laser technology, and then a metal electrode is formed on the anti-reflection layer.

[0003] On the one hand, the transparent conductive film on the existing back-contact battery cannot effectively reduce the reflection of incident light, and the light is not fully utilized, which affects the conversion efficiency of the battery.

[0004] On the other hand, the existing back contact battery uses laser technology to achieve isolation of the PN region spacing area. During the laser grooving process, the high energy of the laser can easily lead to phosphorus and boron mutual doping in the PN region spacing area, causing lateral conduction between the P-type emitter and the N-type back surface field, and then causing a short circuit. Summary of the invention

[0005] The purpose of the present invention is to provide a back contact battery and a preparation method thereof, and a photovoltaic system in view of the existing technical status.

[0006] The back contact battery structure of the present invention can effectively enhance the back reflection effect of light, improve the light utilization rate, and further improve the battery conversion efficiency.

[0007] In order to achieve the above object, the present invention adopts the following technical scheme:

[0008] First, the present invention provides a back contact battery, comprising:

[0009] A silicon substrate, wherein a backlight surface of the silicon substrate has a plurality of first areas and second areas arranged alternately;

[0010] A first semiconductor composite layer, disposed in the first region, comprising a tunnel passivation layer and a first doping layer sequentially disposed in a direction away from the silicon substrate;

[0011] A second semiconductor composite layer, at least partially disposed in the second region, comprises a passivation contact layer and a second doping layer sequentially disposed in a direction away from the silicon substrate, wherein the polarity of the second doping layer is opposite to that of the first doping layer;

[0012] A composite TCO layer is provided in at least a portion of the first doped layer and the second doped layer on a side facing away from the silicon substrate,

[0013] The composite TCO layer includes a first TCO layer and a second TCO layer sequentially arranged in a direction away from the silicon substrate, a plurality of holes are distributed on the first TCO layer, and the holes are opened at least on one side of the first TCO layer away from the second TCO layer.

[0014] In some embodiments, the porosity of the first TCO layer is 0.5% to 5%.

[0015] In some embodiments, the porosity of the first TCO layer is 1.5% to 3%.

[0016] In some embodiments, the density of the first TCO layer is less than the density of the second TCO layer.

[0017] In some embodiments, the hole includes a blind hole having the opening and / or a through hole penetrating the first TCO layer.

[0018] In some embodiments, when the area per square centimeter is used as a calculation unit, the blind holes in a unit area account for at least 80% of the total amount of the through holes and the blind holes in the unit area.

[0019] In some embodiments, under the condition that the area per square centimeter is used as a calculation unit, the blind holes in a unit area account for 80% to 90% of the total amount of the through holes and the blind holes in the unit area.

[0020] In some embodiments, the ratio between the thickness of the first TCO layer and the depth of the hole is 1:0.5-0.8.

[0021] In some embodiments, the maximum width of the opening of each hole facing away from the second TCO layer is 20 nm to 60 nm.

[0022] In some embodiments, the thickness of the first TCO layer is 10 nm to 100 nm, and the thickness of the second TCO layer is 30 nm to 150 nm.

[0023] In some embodiments, the second semiconductor composite layer includes a stacked composite segment disposed in the first region.

[0024] The first doped layer is disposed on a side facing away from the silicon substrate on the mask layer, and the stacked composite section is disposed on a side facing away from the silicon substrate on the mask layer.

[0025] An avoidance hole is provided between the mask layer and the stacked composite section.

[0026] The composite TCO layer includes a first composite section disposed in the first region and a second composite section disposed in the second region,

[0027] The first composite section includes a first segment and a second segment, the first segment is arranged in the avoidance hole and directly contacts with a side of the first doped layer facing away from the silicon substrate, and a first electrode is arranged on a side of the first segment facing away from the silicon substrate, and the second segment is arranged on a side of the second doped extension section facing away from the silicon substrate.

[0028] A second electrode is disposed on a side of the second composite section facing away from the silicon substrate.

[0029] In some embodiments, the polarity of the first doping layer is the same as the polarity of the silicon substrate, and the polarity of the second doping layer is opposite to the polarity of the silicon substrate.

[0030] In some embodiments, the refractive index of the first TCO layer is greater than the refractive index of the second TCO layer.

[0031] Secondly, the present invention provides a method for preparing a back contact battery, comprising:

[0032] Providing a silicon substrate, wherein a backlight surface of the silicon substrate has a plurality of first areas and second areas arranged alternately;

[0033] Depositing a first semiconductor composite layer and a mask layer in sequence on the backlight surface of the silicon substrate, and removing the first semiconductor composite layer and the mask layer outside the first region, wherein the first semiconductor composite layer includes a tunnel passivation layer and a first doping layer arranged in sequence in a direction away from the silicon substrate;

[0034] Depositing a second semiconductor composite layer on the mask layer and the second region, and removing a portion of the mask layer and the second semiconductor composite layer located in the first region to expose a portion of the first doped layer, wherein the second semiconductor composite layer includes a passivation contact layer and a second doped layer sequentially arranged in a direction away from the silicon substrate, and the polarity of the second doped layer is opposite to that of the first doped layer;

[0035] A composite TCO layer is deposited on the second doped layer and the exposed first doped layer, wherein the composite TCO layer includes a first TCO layer and a second TCO layer sequentially arranged in a direction away from the silicon substrate, wherein a plurality of holes are distributed on the first TCO layer, and wherein the holes have openings at least on a side of the first TCO layer away from the second TCO layer.

[0036] In some embodiments, the step of depositing a composite TCO layer on the second doped layer and the exposed first doped layer comprises:

[0037] Depositing a first TCO layer and performing a first annealing process;

[0038] A second TCO layer is deposited and a second annealing process is performed.

[0039] In some embodiments, the preparation method comprises:

[0040] Printing ink on the composite TCO layer to form an electrode patterned structure, and then removing the composite TCO layer in the area not covered by the ink by a wet chemical process to form the composite TCO layer with an isolation area;

[0041] A low-temperature paste is printed on the composite TCO layer with the isolation area to form a first electrode and a second electrode, and low-temperature annealing is performed to form an electrode structure, wherein the first electrode is electrically connected to the first doped layer through the composite TCO layer, and the second electrode is electrically connected to the second doped layer through the composite TCO layer.

[0042] In some embodiments, the porosity of the first TCO layer is 0.5% to 5%.

[0043] In some embodiments, the porosity of the first TCO layer is 1.5% to 3%.

[0044] In some embodiments, the density of the first TCO layer is less than the density of the second TCO layer.

[0045] Furthermore, the present invention provides a photovoltaic system, including the above-mentioned back-contact cell, or, including a back-contact cell prepared by the above-mentioned preparation method.

[0046] The beneficial effects of the present invention are:

[0047] In the present invention, a composite TCO layer is arranged on the backlight surface of the back contact cell, wherein the composite TCO layer includes a first TCO layer and a second TCO layer arranged in sequence in a direction away from the silicon substrate, and a plurality of holes are distributed on the first TCO layer, and the holes are at least provided with an opening on a side of the first TCO layer away from the second TCO layer, and the first TCO layer forms a loose porous structure. After light passes through the silicon substrate, it is reflected by the composite TCO layer on the backlight surface and then enters the silicon substrate. In addition to the main surface of the first TCO layer, the sidewalls of the holes can also participate in the reflection of the light, which not only makes the end surface of the first TCO layer facing the silicon substrate have a With a larger surface area, the first TCO layer has more reflection angles for the light from the silicon substrate, thereby effectively increasing the scattering and reflection times of the light inside the battery, which is beneficial to increase the absorption rate of light of different wavelengths, so that the light can be reused, thereby effectively increasing the short-circuit current of the battery; and the second TCO layer is arranged on the outside of the first TCO layer to prevent the light from penetrating and escaping at the holes, further increasing the back reflection effect of the light, improving the light utilization rate, and then improving the battery conversion efficiency. At the same time, it can protect the inside of the battery, reduce the impact of environmental factors on the inside of the battery, and improve the long-term stability and reliability of the battery.

[0048] Secondly, compared with the existing single-layer transparent conductive layer, the loose porous structure of the first TCO layer is conducive to etching and cleaning by wet chemical process, making the composite TCO layer corresponding to the PN spacer area easier to remove, effectively avoiding the risk of short circuit in the PN area (positive and negative electrodes) inside the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 Schematic diagram of the structure of a back contact battery according to an embodiment of the present invention.

[0050] Figure 2 Another schematic structural diagram of a back contact battery according to an embodiment of the present invention.

[0051] Figure 3 The figure is a flow chart of a method for preparing a back contact battery according to an embodiment of the present invention.

[0052] Figure 4 This is one of the structural schematic diagrams of step 200 in the method for preparing a back contact battery according to an embodiment of the present invention.

[0053] Figure 5 This is one of the structural schematic diagrams of step 200 in the method for preparing a back contact battery according to an embodiment of the present invention.

[0054] Figure 6 This is one of the structural schematic diagrams of step 200 in the method for preparing a back contact battery according to an embodiment of the present invention.

[0055] Figure 7This is an electron microscope image of the composite TCO layer of an embodiment of the present invention.

[0056] Figure 8 Flow chart of step 400 in the method for preparing a back contact battery according to an embodiment of the present invention.

[0057] Fig. 9 This is an electron microscope image of a single transparent conductive layer in the prior art. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. In addition, it should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0059] In the description of the present invention, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" and "several" is two or more, unless otherwise clearly and specifically defined.

[0060] In the description of the present invention, unless otherwise clearly stipulated and limited, a first feature being “on” or “below” a second feature may include the first feature and the second feature being directly in contact, or may include the first feature and the second feature not being in direct contact but being in contact through another feature between them.

[0061] First, see Figure 1 to Figure 2 and Figure 7 As shown, the present invention provides a back contact battery, comprising:

[0062] A silicon substrate 1, wherein a backlight surface of the silicon substrate 1 has a plurality of first regions and second regions arranged alternately;

[0063] The first semiconductor composite layer 2 is disposed in the first region and includes a tunnel passivation layer 21 and a first doping layer 22 sequentially disposed in a direction away from the silicon substrate 1;

[0064] The second semiconductor composite layer 4 is at least partially disposed in the second region, and includes a passivation contact layer 41 and a second doping layer 42 sequentially disposed in a direction away from the silicon substrate 1, wherein the polarity of the second doping layer 42 is opposite to that of the first doping layer 22;

[0065] The composite TCO layer 5 is provided on at least a portion of the first doping layer 22 and the second doping layer 42 on a side facing away from the silicon substrate 1.

[0066] The composite TCO layer 5 includes a first TCO layer 51 and a second TCO layer 52 sequentially arranged in a direction away from the silicon substrate 1 . A plurality of holes 511 are distributed on the first TCO layer 51 . The holes 511 have openings at least on one side of the first TCO layer 51 away from the second TCO layer 52 .

[0067] It can be understood that since the composite TCO layer 5 is outside the doping layer (the first doping layer 22 and the second doping layer 42), there is a gap between the first TCO layer 51 and the doping layer at the position corresponding to the hole 511, which is enclosed by the hole 511 and the surface of the doping layer, that is, the doping layer does not fill the hole 511.

[0068] In the present invention, a composite TCO layer 5 is arranged on the backlight surface of the back contact cell, wherein the composite TCO layer 5 includes a first TCO layer 51 and a second TCO layer 52 arranged in sequence in a direction away from the silicon substrate 1, and a plurality of holes 511 are distributed on the first TCO layer 51, and the holes 511 are at least provided with an opening on one side of the first TCO layer 51 away from the second TCO layer 52, and the first TCO layer 51 forms a loose porous structure. After the light passes through the silicon substrate 1, it is reflected by the composite TCO layer 5 on the backlight surface and then enters the silicon substrate 1. In addition to the main surface of the first TCO layer 51, the sidewalls of the holes 511 can also participate in the reflection of the light, which not only makes the first TCO layer 51 face the backlight surface, but also makes the backlight surface of the first TCO layer 51 reflect the light. The end face on one side of the silicon substrate 1 has a larger surface area, which makes the first TCO layer 51 have more reflection angles for the light from the silicon substrate 1, thereby effectively increasing the number of scattering and reflection of the light inside the battery, which is beneficial to increase the absorption rate of light of different wavelengths, so that the light can be reused, thereby effectively improving the short-circuit current of the battery; and the second TCO layer 52 is arranged on the outer side of the first TCO layer 51 to prevent the light from penetrating and escaping at the hole 511, further increasing the back reflection effect of the light, improving the light utilization rate, and then improving the battery conversion efficiency. At the same time, it can protect the inside of the battery, reduce the impact of environmental factors on the inside of the battery, and improve the long-term stability and reliability of the battery.

[0069] Secondly, compared with the existing single-layer transparent conductive layer ( Fig. 9 shown), see Figure 2 and Figure 7 As shown, the loose porous structure of the first TCO layer 51 is conducive to etching and cleaning by wet chemical process, making it easier to remove the composite TCO layer 5 corresponding to the PN spacer area, effectively avoiding the short circuit risk of the PN area (positive and negative electrodes) inside the battery.

[0070] It is understandable that the silicon substrate 1 has a light-receiving surface and a backlight surface that are arranged relatively, wherein the light-receiving surface generally refers to the side that receives light, and its surface may also be provided with a passivation layer, an anti-reflection layer, etc. commonly used in the art, but not limited thereto. It should be noted that in some embodiments, the backlight surface may also absorb light incident through the backlight surface, thereby generating a photocurrent.

[0071] In some embodiments, the porosity of the first TCO layer 51 is greater than 0.5%.

[0072] When the porosity of the first TCO layer 51 is too low, the light utilization efficiency is effectively improved, and the difficulty of removing the composite TCO layer 5 corresponding to the PN gap region is increased.

[0073] In some embodiments, preferably, the porosity of the first TCO layer 51 is 0.5% to 5%.

[0074] Exemplarily, the porosity of the first TCO layer 51 is 0.5%, 0.55%, 0.6%, 0.65%, 0.68%, 0.7%, 0.72%, 0.75%, 0.78%, 0.8%, 0.85%, 0.9%, 0.95%, 0.98%, 1.0%, 1.2%, 1.5%, 1.8%, 2.0%, 2.5%, 2.8%, 3%, 3.5%, 4%, 4.5% or 5%, but is not limited to this.

[0075] When the porosity of the first TCO layer 51 is too high, it is easy to affect the collection of carriers. When the porosity of the first TCO layer 51 is 0.5% to 5%, the battery has a higher battery short-circuit current and a lower series resistance, and exhibits a better battery conversion efficiency as a whole, and is easier to implement.

[0076] In some embodiments, more preferably, the porosity of the first TCO layer 51 is 1.5% to 3%.

[0077] Exemplarily, the porosity of the first TCO layer 51 is 1.5%, 1.6%, 1.7%, 1.8%, 1.9%, 2.0%, 2.1%, 2.2%, 2.3%, 2.4%, 2.5%, 2.6%, 2.7%, 2.8%, 2.9% or 3%, but is not limited thereto.

[0078] In some embodiments, the density of the first TCO layer 51 is less than the density of the second TCO layer 52 .

[0079] On the one hand, the density of the first TCO layer 51 is lower than that of the second TCO layer 52, which helps to enhance the effect of preventing light from penetrating and escaping at the hole 511, further increase the back reflection effect of light, improve the light utilization rate, and thus improve the battery conversion efficiency. At the same time, it can more effectively protect the interior of the battery, reduce the impact of environmental factors on the interior of the battery, and improve the long-term stability and reliability of the battery.

[0080] On the other hand, since the first TCO layer 51 is located on the inner side of the second TCO layer 52, the density of the first TCO layer 51 is controlled to be smaller than the density of the second TCO layer 52, which is beneficial to the etching and cleaning of the wet chemical process, making the composite TCO layer 5 corresponding to the PN interval area easier to remove, effectively avoiding the risk of short circuit in the PN area (positive and negative electrodes) inside the battery.

[0081] In some embodiments, the hole 511 includes a blind hole having the above-mentioned opening and / or a through hole penetrating the first TCO layer 51 .

[0082] It can be understood that a blind hole refers to a hole 511 whose one end penetrates through the surface of one side of the first TCO layer 51 to form an opening facing away from the second TCO layer 52, and the other end does not penetrate through the other surface of the first TCO layer 51. A through hole refers to a hole 511 whose two ends both penetrate through the surface of the first TCO layer 51 to form not only an opening facing away from the second TCO layer 52, but also another opening facing the second TCO layer 52.

[0083] In the first embodiment, the holes 511 are all through holes penetrating the first TCO layer 51 .

[0084] In the second embodiment, the holes 511 are all blind holes with the above-mentioned openings.

[0085] In the third embodiment, the hole 511 includes a blind hole having the above-mentioned opening and a through hole penetrating the first TCO layer 51 .

[0086] After testing, the battery conversion efficiency of the second and third implementation schemes is better than that of the first implementation scheme. However, compared with the third implementation scheme, the production difficulty of the second implementation scheme is relatively higher.

[0087] In some embodiments, when the area per square centimeter is used as a calculation unit, the blind holes in a unit area account for at least 60% of the total number of through holes and blind holes in the unit area.

[0088] In some embodiments, preferably, under the condition that the area per square centimeter is used as a calculation unit, the blind holes in a unit area account for at least 80% of the total number of through holes and blind holes in the unit area, that is, under the condition that the area per square centimeter is used as a calculation unit, the number of blind holes in a unit area is recorded as N. 1 , the number of blind holes in a unit area is recorded as N 2 The total number of through holes and blind holes in a unit area is recorded as N a , then N a =N 1 +N 2 , and N 1 ≥N a ×80%.

[0089] For example, N 1 N a ×80%、N a ×82%、N a ×85%、N a ×88%、N a ×90%、N a ×92%、N a ×95%、N a ×98%、N a ×99% or N a ×100%, but not limited to this.

[0090] In this range, the holes 511 on the first TCO layer 51 are mainly blind holes, which prevents light from the silicon substrate 1 from directly penetrating through the through holes and escaping, and the battery has a better battery conversion efficiency.

[0091] In some embodiments, under the condition that the area per square centimeter is used as a calculation unit, the blind holes in a unit area account for 80% to 90% of the total amount of through holes and blind holes in the unit area.

[0092] For example, N 1 N a ×80%、N a ×81%、N a ×82%、N a ×83%、N a ×84%、N a ×85%、N a ×86%、N a ×87%、N a ×88%、N a ×89% or N a ×90%, but not limited to this.

[0093] Within this range, the battery can have both good battery conversion efficiency and lower production difficulty.

[0094] In some embodiments, the ratio between the thickness H of the first TCO layer 51 and the depth h of the hole 511 is 1:0.5-0.8.

[0095] It can be understood that h<H. At this time, the hole 511 is a blind hole, and the difference between H and h should not be too small, which will easily affect the back reflection effect of the light.

[0096] Exemplarily, H:h is 1:0.5, 1:0.55, 1:0.6, 1:0.65, 1:0.7, 1:0.75 or 1:0.8, but is not limited thereto.

[0097] The opening of the hole 511 may be regular or irregular. Exemplarily, the opening of the hole 511 is circular, elliptical, square, trapezoidal, triangular or irregular polygonal, but is not limited thereto.

[0098] In some embodiments, the maximum width W of the opening of each hole 511 disposed away from the second TCO layer 52 is 20 nm to 60 nm.

[0099] Illustratively, W is 20 nm, 25 nm, 28 nm, 30 nm, 32 nm, 35 nm, 38 nm, 40 nm, 42 nm, 45 nm, 48 nm, 50 nm, 50 nm, 55 nm, 58 nm or 60 nm, but is not limited thereto.

[0100] The opening of the hole 511 should not be too small, otherwise it is difficult for light to be reflected by the side wall of the hole 511. The opening of the hole 511 should not be too large, otherwise it will easily affect the collection of carriers.

[0101] In some embodiments, the thickness of the first TCO layer 51 is 10 nm to 100 nm, and the thickness of the second TCO layer 52 is 30 nm to 150 nm.

[0102] Exemplarily, the thickness of the first TCO layer 51 is 10nm, 15nm, 20nm, 25nm, 28nm, 30nm, 32nm, 35nm, 38nm, 40nm, 42nm, 45nm, 48nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 88nm, 90nm, 92nm, 95nm, 98nm or 100nm, but is not limited thereto.

[0103] Exemplarily, the thickness of the second TCO layer 52 is 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm, 125nm, 128nm, 130nm, 135nm, 138nm, 140nm, 145nm, 148nm or 150nm, but is not limited thereto.

[0104] By controlling the thickness of the first TCO layer 51 and the second TCO layer 52 to be within a more appropriate range, it is ensured that the composite TCO layer 5 has both good conductivity and good light transmittance, thereby further improving the cell conversion efficiency.

[0105] In some embodiments, the material of the first TCO layer 51 and / or the second TCO layer 52 is any one of ITO, IWO, and AZO.

[0106] In some embodiments, see Figure 1 to Figure 2 As shown, the second semiconductor composite layer 4 includes a stacked composite segment arranged in the first region,

[0107] The first doping layer 22 is disposed on the mask layer 3 on the side facing away from the silicon substrate 1, and the stacked composite section is disposed on the side facing away from the silicon substrate 1 of the mask layer 3.

[0108] An avoidance hole is provided between the mask layer 3 and the laminated composite section.

[0109] The composite TCO layer 5 includes a first composite section disposed in the first region and a second composite section disposed in the second region.

[0110] The first composite section includes a first segment 5A and a second segment 5B. The first segment 5A is arranged in the avoidance hole and directly contacts the side of the first doped layer 22 facing away from the silicon substrate 1. The first segment 5A is provided with a first electrode 61 on the side facing away from the silicon substrate 1. The second segment 5B is arranged on the side of the second doped extension section facing away from the silicon substrate 1.

[0111] A second electrode 62 is provided on the side of the second composite section facing away from the silicon substrate 1 .

[0112] The material of the mask layer 3 is PSG, SiN x Any one of .

[0113] On the one hand, the mask layer 3 can electrically isolate the first doping layer 22 and the second doping layer 42, and on the other hand, it can cooperate with the wet chemical process during the preparation process to prevent high-energy laser from directly acting on the first doping layer 22, effectively avoiding the risk of short circuit in the PN region (positive and negative electrodes) inside the battery.

[0114] In one embodiment, the polarity of the first doping layer 22 is opposite to the polarity of the silicon substrate 1 , and the polarity of the second doping layer 42 is the same as the polarity of the silicon substrate 1 .

[0115] In another embodiment, preferably, the polarity of the first doping layer 22 is the same as the polarity of the silicon substrate 1 , and the polarity of the second doping layer 42 is opposite to the polarity of the silicon substrate 1 , so that the battery conversion efficiency is higher.

[0116] In a first embodiment, the refractive index of the first TCO layer 51 is less than or equal to the refractive index of the second TCO layer 52 .

[0117] In the second embodiment, preferably, the refractive index of the first TCO layer 51 is greater than the refractive index of the second TCO layer 52 .

[0118] By setting the refractive index of the composite TCO layer 5 to increase from the outside to the inside, the refractive index difference between the outer TCO layer (the second TCO layer 52) and the air can be reduced, which is conducive to more light entering the composite TCO layer 5. At the same time, when light enters from the outer TCO layer (the second TCO layer 52), it is easier for the light to penetrate the interface and enter the first TCO layer 51 with a higher refractive index, and then enter the battery, thereby reducing reflection loss and regulating the overall spectral absorption characteristics of the composite TCO layer 5. In addition, the refractive index difference design between the first TCO layer 51 and the second TCO layer 52 has a better back reflection effect for the long-wave band (especially in the 900nm to 1200nm band). After the long-wave band passes through the silicon substrate 1, it is reflected by the composite TCO layer 5 on the backlight surface and then enters the silicon substrate 1. The long-wave band light can be reused, which can make full use of the long-wave band light and further improve the battery short-circuit current.

[0119] In some embodiments, a velvet structure is provided on the second area of ​​the backlight surface and / or the light-receiving surface to improve the reflection effect of light inside the battery.

[0120] In some embodiments, the silicon substrate 1 is single crystal silicon.

[0121] In some embodiments, the tunnel passivation layer 21 is made of silicon oxide, the first doped layer 22 is made of polysilicon, the second doped layer 42 is made of amorphous silicon or microcrystalline silicon, and the passivation contact layer 41 is made of amorphous silicon or microcrystalline silicon.

[0122] By setting a tunneling passivation layer 21 between the silicon substrate 1 and the first doped layer 22 of polycrystalline silicon, and setting a passivation contact layer 41 between the silicon substrate 1 and the second doped layer 42 of amorphous silicon or microcrystalline silicon, the interface recombination loss is effectively reduced, the open circuit voltage and fill factor of the battery are improved, and the battery conversion efficiency is further improved. Compared with the second doped layer 42 made of polycrystalline silicon, the second doped layer 42 made of amorphous silicon or microcrystalline silicon has a better passivation effect on the velvet structure, and has a lower contact resistivity with the composite TCO layer 5, thereby achieving a lower series resistance and a higher fill factor, and further improving the battery conversion efficiency.

[0123] In some embodiments, the light-receiving surface of the silicon substrate 1 is provided with a front passivation layer 71 and a front anti-reflection layer 72 in sequence in a direction away from the silicon substrate 1, wherein the material of the front passivation layer 71 is amorphous silicon or microcrystalline silicon, and the thickness is 3nm to 15nm. The material of the front anti-reflection layer 72 is any one of silicon nitride, silicon oxynitride, and silicon oxide, and the thickness is 20nm to 80nm.

[0124] Secondly, see Figure 3 As shown, the present invention provides a method for preparing a back contact battery, comprising:

[0125] S100. Providing a silicon substrate 1, the backlight surface of the silicon substrate 1 having a plurality of first regions and second regions arranged alternately;

[0126] S200. Depositing a first semiconductor composite layer 2 and a mask layer 3 on the backlight surface of the silicon substrate 1 in sequence, and removing the first semiconductor composite layer 2 and the mask layer 3 outside the first region, so that only the first semiconductor composite layer 2 and the mask layer 3 are retained in the first region, the first semiconductor composite layer 2 includes a tunnel passivation layer 21 and a first doping layer 22 sequentially arranged in a direction away from the silicon substrate 1;

[0127] S300. depositing a second semiconductor composite layer 4 on the mask layer 3 and the second region, and removing a portion of the mask layer 3 and the second semiconductor composite layer 4 located in the first region to expose a portion of the first doped layer 22, wherein the second semiconductor composite layer 4 includes a passivation contact layer 41 and a second doped layer 42 sequentially arranged in a direction away from the silicon substrate 1, and the polarity of the second doped layer 42 is opposite to that of the first doped layer 22;

[0128] S400. Depositing a composite TCO layer 5 on the second doped layer 42 and the exposed first doped layer 22, the composite TCO layer 5 comprising a first TCO layer 51 and a second TCO layer 52 sequentially arranged in a direction away from the silicon substrate 1, a plurality of holes 511 distributed on the first TCO layer 51, and an opening being arranged on at least one side of the first TCO layer 51 away from the second TCO layer 52.

[0129] In the present invention, a composite TCO layer 5 is arranged on the backlight surface of the back contact cell, wherein the composite TCO layer 5 includes a first TCO layer 51 and a second TCO layer 52 arranged in sequence in a direction away from the silicon substrate 1, and a plurality of holes 511 are distributed on the first TCO layer 51, and the holes 511 are at least provided with an opening on one side of the first TCO layer 51 away from the second TCO layer 52, and the first TCO layer 51 forms a loose porous structure. After the light passes through the silicon substrate 1, it is reflected by the composite TCO layer 5 on the backlight surface and then enters the silicon substrate 1. In addition to the main surface of the first TCO layer 51, the sidewalls of the holes 511 can also participate in the reflection of the light, which not only makes the first TCO layer 51 face the backlight surface, but also makes the backlight surface of the first TCO layer 51 reflect the light. The end face on one side of the silicon substrate 1 has a larger surface area, which makes the first TCO layer 51 have more reflection angles for the light from the silicon substrate 1, thereby effectively increasing the number of scattering and reflection of the light inside the battery, which is beneficial to increase the absorption rate of light of different wavelengths, so that the light can be reused, thereby effectively improving the short-circuit current of the battery; and the second TCO layer 52 is arranged on the outer side of the first TCO layer 51 to prevent the light from penetrating and escaping at the hole 511, further increasing the back reflection effect of the light, improving the light utilization rate, and then improving the battery conversion efficiency. At the same time, it can protect the inside of the battery, reduce the impact of environmental factors on the inside of the battery, and improve the long-term stability and reliability of the battery.

[0130] Secondly, compared with the existing single-layer transparent conductive layer ( Fig. 9 shown), see Figure 2 and Figure 7 As shown, the loose porous structure of the first TCO layer 51 is conducive to the etching and cleaning of the wet chemical process, so that the composite TCO layer 5 corresponding to the PN interval area is easier to remove, and the short circuit risk of the PN area (positive and negative electrodes) inside the battery is effectively avoided; at the same time, the present invention introduces a mask layer 3 between the first doping layer 22 and the second doping layer 42 in the first area, which can electrically isolate the first doping layer 22 and the second doping layer 42 on the one hand, and on the other hand, can cooperate with the wet chemical process during the preparation process to avoid high-energy laser directly acting on the first doping layer 22, and further avoid the short circuit risk of the PN area (positive and negative electrodes) inside the battery.

[0131] In some embodiments, see Figure 8 As shown, in step S400, the step of depositing the composite TCO layer 5 on the second doping layer 42 and the exposed first doping layer 22 includes:

[0132] S410. Depositing a first TCO layer 51 and performing a first annealing treatment;

[0133] S420 . Deposit a second TCO layer 52 , and perform a second annealing process.

[0134] On the one hand, the annealing treatment is beneficial to improving the back reflection effect of the first TCO layer 51 and the second TCO layer 52 on light. On the other hand, since the first TCO layer 51 undergoes two annealing treatments (the first annealing treatment and the second annealing treatment), a loose porous structure can be formed, which is conducive to wet chemical etching and cleaning. The composite TCO layer 5 in the PN interval area (non-ink covered area) is easier to remove, effectively avoiding the risk of short circuit in the PN area (positive and negative electrodes) inside the battery.

[0135] Exemplarily, the annealing temperature of the first annealing treatment and / or the second annealing treatment is 140°C.

[0136] ~160℃, annealing time 8min~10min, pressure 5×10 -4 mbar~2×10 -3 mbar, but not limited thereto.

[0137] In some embodiments, see Figure 3 As shown, the preparation method comprises:

[0138] S500. Metal Graphics:

[0139] S510. Printing ink on the composite TCO layer 5 to form a patterned electrode structure, and then removing the composite TCO layer 5 in the area not covered by the ink by a wet chemical process to form a composite TCO layer 5 with an isolation area;

[0140] S520. Print a low-temperature paste on the composite TCO layer 5 with the isolation area to form a first electrode 61 and a second electrode 62, and perform low-temperature annealing to form an electrode structure, wherein the first electrode 61 is electrically connected to the first doping layer 22 through the composite TCO layer 5, and the second electrode 62 is electrically connected to the second doping layer 42 through the composite TCO layer 5.

[0141] In the present invention, ink patterning combined with wet chemical process is used to effectively avoid the problem of lateral conduction between the P-type emitter and the N-type back surface field easily caused by the high energy of the laser during the laser grooving process, thereby avoiding the risk of short circuit in the PN region (positive and negative electrodes) inside the battery.

[0142] In some embodiments, in step S200, see Figures 4 to 6 As shown, the step of removing the first semiconductor composite layer 2 and the mask layer 3 outside the first region includes:

[0143] S210.See Figures 4 to 5 As shown, the mask layer 3 located on the second area is removed by laser etching technology, and the laser etching area is treated by wet chemical process to remove the first semiconductor composite layer 2 and the mask layer 3 located outside the first area;

[0144] S220.See Figure 6 As shown, a velvet structure is formed on the second region of the backlight surface and the light-receiving surface of the silicon substrate 1 by alkaline etching;

[0145] S230. A front passivation layer 71 and a front anti-reflection layer 72 are sequentially deposited on the light-receiving surface of the silicon substrate 1 .

[0146] The portion of the mask layer 3 located on the second area is first removed by laser etching technology, and then the first semiconductor composite layer 2 and the portion of the mask layer 3 located outside the first area are removed by wet chemical process. That is, when the first semiconductor composite layer 2 and the mask layer 3 are also deposited on the side walls or the front of the silicon substrate 1, they also need to be removed together, so that only the first semiconductor composite layer 2 and the mask layer 3 located in the first area are retained in the end. The mask layer 3 is combined with the wet chemical process to prevent high-energy laser from directly acting on the first doping layer 22, and effectively avoid the risk of short circuit in the PN area (positive and negative electrodes) inside the battery.

[0147] In some embodiments, in step S300, the step of removing a portion of the mask layer 3 and the second semiconductor composite layer 4 located in the first region includes:

[0148] S310. Using laser etching technology to remove a portion of the second semiconductor composite layer 4 located on the first region to expose a portion of the mask layer 3, and treating the laser etching area by a wet chemical process to remove the exposed portion of the mask layer 3.

[0149] Thus, by combining the mask layer 3 with the wet chemical process, the high-energy laser is prevented from directly acting on the first doping layer 22, and the risk of short circuit in the PN region (positive and negative electrodes) inside the battery is effectively avoided during the preparation process.

[0150] In some embodiments, the porosity of the first TCO layer 51 is 0.5% to 5%.

[0151] In some embodiments, the porosity of the first TCO layer 51 is 1.5% to 3%.

[0152] In some embodiments, the density of the first TCO layer 51 is less than the density of the second TCO layer 52 .

[0153] Furthermore, the present invention provides a photovoltaic system, including the above-mentioned back-contact cell, or, including a back-contact cell prepared by the above-mentioned preparation method.

[0154] Among them, photovoltaic systems can be used in photovoltaic power stations, such as ground power stations, rooftop power stations, water surface power stations, etc., and can also be used in equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars, solar buildings, etc., but not limited to these.

[0155] The present invention will be further described below in conjunction with the accompanying drawings and embodiments:

[0156] Example 1

[0157] The present invention provides a method for preparing a back contact battery, comprising:

[0158] S100. Provide a silicon substrate, wherein a backlight surface of the silicon substrate has a plurality of first regions and second regions that are alternately arranged.

[0159] S200. A first semiconductor composite layer and a mask layer are sequentially deposited on the backlight surface of the silicon substrate, and the first semiconductor composite layer and the mask layer located outside the first region are removed, so that only the first semiconductor composite layer and the mask layer located in the first region are retained, the first semiconductor composite layer includes a tunnel passivation layer and a first doping layer sequentially arranged in a direction away from the silicon substrate, and the polarity of the first doping layer is the same as the polarity of the silicon substrate, specifically:

[0160] S201. sequentially depositing a first semiconductor composite layer and a mask layer;

[0161] S210. Using laser etching technology to remove the mask layer located on the second region, and treating the laser etching area by a wet chemical process to remove the first semiconductor composite layer and the mask layer located outside the first region;

[0162] S220. Using alkaline etching, a suede structure is formed on the second area of ​​the backlight surface and the light-receiving surface of the silicon substrate.

[0163] S230. A front passivation layer and a front anti-reflection layer are sequentially deposited on the light-receiving surface of the silicon substrate.

[0164] S300. Depositing a second semiconductor composite layer on the mask layer and the second region, and removing a portion of the mask layer and the second semiconductor composite layer located in the first region to expose a portion of the first doped layer, the second semiconductor composite layer includes a passivation contact layer and a second doped layer sequentially arranged in a direction away from the silicon substrate, the polarity of the second doped layer is opposite to the polarity of the silicon substrate, specifically:

[0165] S301. Depositing a second semiconductor composite layer on the mask layer and the second region;

[0166] S310. Use laser etching technology to remove a portion of the second semiconductor composite layer located on the first area to expose a portion of the mask layer, and treat the laser etching area through a wet chemical process to remove the exposed portion of the mask layer.

[0167] S400. Depositing a composite TCO layer on the second doped layer and the exposed first doped layer, the composite TCO layer comprising a first TCO layer and a second TCO layer sequentially arranged in a direction away from the silicon substrate, a plurality of holes distributed on the first TCO layer, and the holes having an opening at least on one side of the first TCO layer away from the second TCO layer, specifically:

[0168] S410. Depositing a first TCO layer and performing a first annealing treatment;

[0169] S420. Deposit a second TCO layer and perform a second annealing process.

[0170] S500, metal graphics, specific:

[0171] S510. Printing ink on the composite TCO layer to form a patterned electrode structure, and then removing the composite TCO layer in the area not covered by the ink by a wet chemical process to form a composite TCO layer with an isolation area;

[0172] S520. Print a low-temperature paste on the composite TCO layer with the isolation area to form a first electrode and a second electrode, and perform low-temperature annealing to form an electrode structure, wherein the first electrode is electrically connected to the first doped layer through the composite TCO layer, and the second electrode is electrically connected to the second doped layer through the composite TCO layer.

[0173] Example 2

[0174] This embodiment provides a back contact battery, comprising:

[0175] A silicon substrate, wherein a backlight surface of the silicon substrate has a plurality of first areas and second areas arranged alternately;

[0176] A first semiconductor composite layer, disposed in the first region, comprises a tunnel passivation layer and a first doping layer sequentially disposed in a direction away from the silicon substrate;

[0177] A second semiconductor composite layer, at least partially disposed in the second region, comprises a passivation contact layer and a second doping layer sequentially disposed in a direction away from the silicon substrate, wherein the polarity of the second doping layer is opposite to that of the first doping layer;

[0178] The composite TCO layer is disposed on at least a portion of the first doped layer and the second doped layer on a side facing away from the silicon substrate.

[0179] The composite TCO layer includes a first TCO layer and a second TCO layer sequentially arranged in a direction away from the silicon substrate. A plurality of holes are distributed on the first TCO layer. The holes have openings at least on one side of the first TCO layer away from the second TCO layer.

[0180] In this embodiment, the porosity of the first TCO layer is 0.58%.

[0181] In this embodiment, the density of the first TCO layer is less than the density of the second TCO layer.

[0182] In this embodiment, the holes include blind holes with the above-mentioned openings and through holes penetrating the first TCO layer, wherein, taking each square centimeter of area as a calculation unit, the blind holes in a unit area account for (85±1)% of the total number of through holes and blind holes in the unit area.

[0183] In this embodiment, the ratio between the thickness H of the first TCO layer and the depth h of the blind hole is controlled to be 1:(0.7±0.05).

[0184] In this embodiment, the maximum width W of the opening of each hole that is disposed facing away from the second TCO layer is controlled to be (40±1) nm.

[0185] In this embodiment, the thickness of the first TCO layer is 40 nm, and the thickness of the second TCO layer is 80 nm.

[0186] In this embodiment, the material of the first TCO layer is AZO, and the material of the second TCO layer is IWO.

[0187] In this embodiment, the second semiconductor composite layer includes a stacked composite segment disposed in the first region.

[0188] The first doped layer is disposed on a side of the mask layer facing away from the silicon substrate, and the stacked composite section is disposed on a side of the mask layer facing away from the silicon substrate.

[0189] A avoidance hole is provided between the mask layer and the laminated composite section.

[0190] The composite TCO layer includes a first composite segment disposed in the first region and a second composite segment disposed in the second region,

[0191] The first composite section includes a first segment and a second segment, the first segment is arranged in the avoidance hole and directly contacts with the side of the first doped layer facing away from the silicon substrate, and a first electrode is arranged on the side of the first segment facing away from the silicon substrate, and the second segment is arranged on the side of the second doped extension section facing away from the silicon substrate.

[0192] A second electrode is disposed on a side of the second composite section facing away from the silicon substrate.

[0193] Among them, the material of the mask layer is SiN x .

[0194] In this embodiment, the polarity of the first doping layer is opposite to the polarity of the silicon substrate, and the polarity of the second doping layer is the same as the polarity of the silicon substrate.

[0195] In this embodiment, the refractive index of the first TCO layer is greater than the refractive index of the second TCO layer.

[0196] In this embodiment, a velvet structure is provided on the second area of ​​the backlight surface and on the light receiving surface.

[0197] In this embodiment, the silicon substrate is single crystal silicon.

[0198] In this embodiment, the tunnel passivation layer is made of silicon oxide, the first doped layer is made of polysilicon, the second doped layer is made of amorphous silicon, and the passivation contact layer is made of amorphous silicon.

[0199] In this embodiment, the light-receiving surface of the silicon substrate is provided with a front passivation layer and a front anti-reflection layer in sequence in a direction away from the silicon substrate, wherein the material of the front passivation layer is amorphous silicon with a thickness of 10nm, and the material of the front anti-reflection layer is silicon nitride with a thickness of 60nm.

[0200] The above-mentioned back contact battery is prepared by the preparation method of Example 1.

[0201] Example 3

[0202] This embodiment provides a back contact battery, comprising:

[0203] A silicon substrate, wherein a backlight surface of the silicon substrate has a plurality of first areas and second areas arranged alternately;

[0204] A first semiconductor composite layer, disposed in the first region, comprises a tunnel passivation layer and a first doping layer sequentially disposed in a direction away from the silicon substrate;

[0205] A second semiconductor composite layer, at least partially disposed in the second region, comprises a passivation contact layer and a second doping layer sequentially disposed in a direction away from the silicon substrate, wherein the polarity of the second doping layer is opposite to that of the first doping layer;

[0206] The composite TCO layer is disposed on at least a portion of the first doped layer and the second doped layer on a side facing away from the silicon substrate.

[0207] The composite TCO layer includes a first TCO layer and a second TCO layer sequentially arranged in a direction away from the silicon substrate. A plurality of holes are distributed on the first TCO layer. The holes have openings at least on one side of the first TCO layer away from the second TCO layer.

[0208] In this embodiment, the porosity of the first TCO layer is 3.00%.

[0209] In this embodiment, the density of the first TCO layer is less than the density of the second TCO layer.

[0210] In this embodiment, the holes include blind holes with the above-mentioned openings and through holes penetrating the first TCO layer, wherein, taking each square centimeter of area as a calculation unit, the blind holes in a unit area account for (85±1)% of the total number of through holes and blind holes in the unit area.

[0211] In this embodiment, the ratio between the thickness H of the first TCO layer and the depth h of the blind hole is controlled to be 1:(0.7±0.05).

[0212] In this embodiment, the maximum width W of the opening of each hole that is disposed facing away from the second TCO layer is controlled to be (40±1) nm.

[0213] In this embodiment, the thickness of the first TCO layer is 40 nm, and the thickness of the second TCO layer is 80 nm.

[0214] In this embodiment, the material of the first TCO layer is AZO, and the material of the second TCO layer is IWO.

[0215] In this embodiment, the second semiconductor composite layer includes a stacked composite segment disposed in the first region.

[0216] The first doped layer is disposed on a side of the mask layer facing away from the silicon substrate, and the stacked composite section is disposed on a side of the mask layer facing away from the silicon substrate.

[0217] A avoidance hole is provided between the mask layer and the laminated composite section.

[0218] The composite TCO layer includes a first composite segment disposed in the first region and a second composite segment disposed in the second region,

[0219] The first composite section includes a first segment and a second segment, the first segment is arranged in the avoidance hole and directly contacts with the side of the first doped layer facing away from the silicon substrate, and a first electrode is arranged on the side of the first segment facing away from the silicon substrate, and the second segment is arranged on the side of the second doped extension section facing away from the silicon substrate.

[0220] A second electrode is disposed on a side of the second composite section facing away from the silicon substrate.

[0221] Among them, the material of the mask layer is SiN x .

[0222] In this embodiment, the polarity of the first doping layer is opposite to the polarity of the silicon substrate, and the polarity of the second doping layer is the same as the polarity of the silicon substrate.

[0223] In this embodiment, the refractive index of the first TCO layer is greater than the refractive index of the second TCO layer.

[0224] In this embodiment, a velvet structure is provided on the second area of ​​the backlight surface and on the light receiving surface.

[0225] In this embodiment, the silicon substrate is single crystal silicon.

[0226] In this embodiment, the tunnel passivation layer is made of silicon oxide, the first doped layer is made of polysilicon, the second doped layer is made of amorphous silicon, and the passivation contact layer is made of amorphous silicon.

[0227] In this embodiment, the light-receiving surface of the silicon substrate is provided with a front passivation layer and a front anti-reflection layer in sequence in a direction away from the silicon substrate, wherein the material of the front passivation layer is amorphous silicon with a thickness of 10nm, and the material of the front anti-reflection layer is silicon nitride with a thickness of 60nm.

[0228] The above-mentioned back contact battery is prepared by the preparation method of Example 1.

[0229] Example 4

[0230] This embodiment provides a back contact battery, comprising:

[0231] A silicon substrate, wherein a backlight surface of the silicon substrate has a plurality of first areas and second areas arranged alternately;

[0232] A first semiconductor composite layer, disposed in the first region, comprises a tunnel passivation layer and a first doping layer sequentially disposed in a direction away from the silicon substrate;

[0233] A second semiconductor composite layer, at least partially disposed in the second region, comprises a passivation contact layer and a second doping layer sequentially disposed in a direction away from the silicon substrate, wherein the polarity of the second doping layer is opposite to that of the first doping layer;

[0234] The composite TCO layer is disposed on at least a portion of the first doped layer and the second doped layer on a side facing away from the silicon substrate.

[0235] The composite TCO layer includes a first TCO layer and a second TCO layer sequentially arranged in a direction away from the silicon substrate. A plurality of holes are distributed on the first TCO layer. The holes have openings at least on one side of the first TCO layer away from the second TCO layer.

[0236] In this embodiment, the porosity of the first TCO layer is 3.00%.

[0237] In this embodiment, the density of the first TCO layer is less than the density of the second TCO layer.

[0238] In this embodiment, the holes include blind holes with the above-mentioned openings and through holes penetrating the first TCO layer, wherein, taking each square centimeter of area as a calculation unit, the blind holes in a unit area account for (85±1)% of the total number of through holes and blind holes in the unit area.

[0239] In this embodiment, the ratio between the thickness H of the first TCO layer and the depth h of the blind hole is controlled to be 1:(0.7±0.05).

[0240] In this embodiment, the maximum width W of the opening of each hole that is disposed facing away from the second TCO layer is controlled to be (60±1) nm.

[0241] In this embodiment, the thickness of the first TCO layer is 40 nm, and the thickness of the second TCO layer is 80 nm.

[0242] In this embodiment, the material of the first TCO layer is AZO, and the material of the second TCO layer is IWO.

[0243] In this embodiment, the second semiconductor composite layer includes a stacked composite segment disposed in the first region.

[0244] The first doped layer is disposed on a side of the mask layer facing away from the silicon substrate, and the stacked composite section is disposed on a side of the mask layer facing away from the silicon substrate.

[0245] A avoidance hole is provided between the mask layer and the laminated composite section.

[0246] The composite TCO layer includes a first composite segment disposed in the first region and a second composite segment disposed in the second region,

[0247] The first composite section includes a first segment and a second segment, the first segment is arranged in the avoidance hole and directly contacts with the side of the first doped layer facing away from the silicon substrate, and a first electrode is arranged on the side of the first segment facing away from the silicon substrate, and the second segment is arranged on the side of the second doped extension section facing away from the silicon substrate.

[0248] A second electrode is disposed on a side of the second composite section facing away from the silicon substrate.

[0249] Among them, the material of the mask layer is SiN x .

[0250] In this embodiment, the polarity of the first doping layer is opposite to the polarity of the silicon substrate, and the polarity of the second doping layer is the same as the polarity of the silicon substrate.

[0251] In this embodiment, the refractive index of the first TCO layer is greater than the refractive index of the second TCO layer.

[0252] In this embodiment, a velvet structure is provided on the second area of ​​the backlight surface and on the light receiving surface.

[0253] In this embodiment, the silicon substrate is single crystal silicon.

[0254] In this embodiment, the tunnel passivation layer is made of silicon oxide, the first doped layer is made of polysilicon, the second doped layer is made of amorphous silicon, and the passivation contact layer is made of amorphous silicon.

[0255] In this embodiment, the light-receiving surface of the silicon substrate is provided with a front passivation layer and a front anti-reflection layer in sequence in a direction away from the silicon substrate, wherein the material of the front passivation layer is amorphous silicon with a thickness of 10nm, and the material of the front anti-reflection layer is silicon nitride with a thickness of 60nm.

[0256] The above-mentioned back contact battery is prepared by the preparation method of Example 1.

[0257] Example 5

[0258] This embodiment provides a back contact battery, comprising:

[0259] A silicon substrate, wherein a backlight surface of the silicon substrate has a plurality of first areas and second areas arranged alternately;

[0260] A first semiconductor composite layer, disposed in the first region, comprises a tunnel passivation layer and a first doping layer sequentially disposed in a direction away from the silicon substrate;

[0261] A second semiconductor composite layer, at least partially disposed in the second region, comprises a passivation contact layer and a second doping layer sequentially disposed in a direction away from the silicon substrate, wherein the polarity of the second doping layer is opposite to that of the first doping layer;

[0262] The composite TCO layer is disposed on at least a portion of the first doped layer and the second doped layer on a side facing away from the silicon substrate.

[0263] The composite TCO layer includes a first TCO layer and a second TCO layer sequentially arranged in a direction away from the silicon substrate. A plurality of holes are distributed on the first TCO layer. The holes have openings at least on one side of the first TCO layer away from the second TCO layer.

[0264] In this embodiment, the porosity of the first TCO layer is 3.00%.

[0265] In this embodiment, the density of the first TCO layer is less than the density of the second TCO layer.

[0266] In this embodiment, the holes include blind holes with the above-mentioned openings and through holes penetrating the first TCO layer, wherein, taking each square centimeter of area as a calculation unit, the blind holes in a unit area account for (85±1)% of the total number of through holes and blind holes in the unit area.

[0267] In this embodiment, the ratio between the thickness H of the first TCO layer and the depth h of the blind hole is controlled to be 1:(0.7±0.05).

[0268] In this embodiment, the maximum width W of the opening of each hole that is disposed facing away from the second TCO layer is controlled to be (20±1) nm.

[0269] In this embodiment, the thickness of the first TCO layer is 40 nm, and the thickness of the second TCO layer is 80 nm.

[0270] In this embodiment, the material of the first TCO layer is AZO, and the material of the second TCO layer is IWO.

[0271] In this embodiment, the second semiconductor composite layer includes a stacked composite segment disposed in the first region.

[0272] The first doped layer is disposed on a side of the mask layer facing away from the silicon substrate, and the stacked composite section is disposed on a side of the mask layer facing away from the silicon substrate.

[0273] A avoidance hole is provided between the mask layer and the laminated composite section.

[0274] The composite TCO layer includes a first composite segment disposed in the first region and a second composite segment disposed in the second region,

[0275] The first composite section includes a first segment and a second segment, the first segment is arranged in the avoidance hole and directly contacts with the side of the first doped layer facing away from the silicon substrate, and a first electrode is arranged on the side of the first segment facing away from the silicon substrate, and the second segment is arranged on the side of the second doped extension section facing away from the silicon substrate.

[0276] A second electrode is disposed on a side of the second composite section facing away from the silicon substrate.

[0277] Among them, the material of the mask layer is SiN x .

[0278] In this embodiment, the polarity of the first doping layer is opposite to the polarity of the silicon substrate, and the polarity of the second doping layer is the same as the polarity of the silicon substrate.

[0279] In this embodiment, the refractive index of the first TCO layer is greater than the refractive index of the second TCO layer.

[0280] In this embodiment, a velvet structure is provided on the second area of ​​the backlight surface and on the light receiving surface.

[0281] In this embodiment, the silicon substrate is single crystal silicon.

[0282] In this embodiment, the tunnel passivation layer is made of silicon oxide, the first doped layer is made of polysilicon, the second doped layer is made of amorphous silicon, and the passivation contact layer is made of amorphous silicon.

[0283] In this embodiment, the light-receiving surface of the silicon substrate is provided with a front passivation layer and a front anti-reflection layer in sequence in a direction away from the silicon substrate, wherein the material of the front passivation layer is amorphous silicon with a thickness of 10nm, and the material of the front anti-reflection layer is silicon nitride with a thickness of 60nm.

[0284] The above-mentioned back contact battery is prepared by the preparation method of Example 1.

[0285] Example 6

[0286] This embodiment provides a back contact battery, comprising:

[0287] A silicon substrate, wherein a backlight surface of the silicon substrate has a plurality of first areas and second areas arranged alternately;

[0288] A first semiconductor composite layer, disposed in the first region, comprises a tunnel passivation layer and a first doping layer sequentially disposed in a direction away from the silicon substrate;

[0289] A second semiconductor composite layer, at least partially disposed in the second region, comprises a passivation contact layer and a second doping layer sequentially disposed in a direction away from the silicon substrate, wherein the polarity of the second doping layer is opposite to that of the first doping layer;

[0290] The composite TCO layer is disposed on at least a portion of the first doped layer and the second doped layer on a side facing away from the silicon substrate.

[0291] The composite TCO layer includes a first TCO layer and a second TCO layer sequentially arranged in a direction away from the silicon substrate. A plurality of holes are distributed on the first TCO layer. The holes have openings at least on one side of the first TCO layer away from the second TCO layer.

[0292] In this embodiment, the porosity of the first TCO layer is 1.50%.

[0293] In this embodiment, the density of the first TCO layer is less than the density of the second TCO layer.

[0294] In this embodiment, the holes include blind holes with the above-mentioned openings and through holes penetrating the first TCO layer, wherein, taking each square centimeter of area as a calculation unit, the blind holes in a unit area account for (85±1)% of the total number of through holes and blind holes in the unit area.

[0295] In this embodiment, the ratio between the thickness H of the first TCO layer and the depth h of the blind hole is controlled to be 1:(0.7±0.05).

[0296] In this embodiment, the maximum width W of the opening of each hole that is disposed facing away from the second TCO layer is controlled to be (40±1) nm.

[0297] In this embodiment, the thickness of the first TCO layer is 40 nm, and the thickness of the second TCO layer is 80 nm.

[0298] In this embodiment, the material of the first TCO layer is AZO, and the material of the second TCO layer is IWO.

[0299] In this embodiment, the second semiconductor composite layer includes a stacked composite segment disposed in the first region.

[0300] The first doped layer is disposed on a side of the mask layer facing away from the silicon substrate, and the stacked composite section is disposed on a side of the mask layer facing away from the silicon substrate.

[0301] A avoidance hole is provided between the mask layer and the laminated composite section.

[0302] The composite TCO layer includes a first composite segment disposed in the first region and a second composite segment disposed in the second region,

[0303] The first composite section includes a first segment and a second segment, the first segment is arranged in the avoidance hole and directly contacts with the side of the first doped layer facing away from the silicon substrate, and a first electrode is arranged on the side of the first segment facing away from the silicon substrate, and the second segment is arranged on the side of the second doped extension section facing away from the silicon substrate.

[0304] A second electrode is disposed on a side of the second composite section facing away from the silicon substrate.

[0305] Among them, the material of the mask layer is SiN x .

[0306] In this embodiment, the polarity of the first doping layer is opposite to the polarity of the silicon substrate, and the polarity of the second doping layer is the same as the polarity of the silicon substrate.

[0307] In this embodiment, the refractive index of the first TCO layer is greater than the refractive index of the second TCO layer.

[0308] In this embodiment, a velvet structure is provided on the second area of ​​the backlight surface and on the light receiving surface.

[0309] In this embodiment, the silicon substrate is single crystal silicon.

[0310] In this embodiment, the tunnel passivation layer is made of silicon oxide, the first doped layer is made of polysilicon, the second doped layer is made of amorphous silicon, and the passivation contact layer is made of amorphous silicon.

[0311] In this embodiment, the light-receiving surface of the silicon substrate is provided with a front passivation layer and a front anti-reflection layer in sequence in a direction away from the silicon substrate, wherein the material of the front passivation layer is amorphous silicon with a thickness of 10nm, and the material of the front anti-reflection layer is silicon nitride with a thickness of 60nm.

[0312] The above-mentioned back contact battery is prepared by the preparation method of Example 1.

[0313] Example 7

[0314] This embodiment provides a back contact battery, comprising:

[0315] A silicon substrate, wherein a backlight surface of the silicon substrate has a plurality of first areas and second areas arranged alternately;

[0316] A first semiconductor composite layer, disposed in the first region, comprises a tunnel passivation layer and a first doping layer sequentially disposed in a direction away from the silicon substrate;

[0317] A second semiconductor composite layer, at least partially disposed in the second region, comprises a passivation contact layer and a second doping layer sequentially disposed in a direction away from the silicon substrate, wherein the polarity of the second doping layer is opposite to that of the first doping layer;

[0318] The composite TCO layer is disposed on at least a portion of the first doped layer and the second doped layer on a side facing away from the silicon substrate.

[0319] The composite TCO layer includes a first TCO layer and a second TCO layer sequentially arranged in a direction away from the silicon substrate. A plurality of holes are distributed on the first TCO layer. The holes have openings at least on one side of the first TCO layer away from the second TCO layer.

[0320] In this embodiment, the porosity of the first TCO layer is 4.90%.

[0321] In this embodiment, the density of the first TCO layer is less than the density of the second TCO layer.

[0322] In this embodiment, the holes include blind holes with the above-mentioned openings and through holes penetrating the first TCO layer, wherein, taking each square centimeter of area as a calculation unit, the blind holes in a unit area account for (85±1)% of the total number of through holes and blind holes in the unit area.

[0323] In this embodiment, the ratio between the thickness H of the first TCO layer and the depth h of the blind hole is controlled to be 1:(0.7±0.05).

[0324] In this embodiment, the maximum width W of the opening of each hole that is disposed facing away from the second TCO layer is controlled to be (40±1) nm.

[0325] In this embodiment, the thickness of the first TCO layer is 40 nm, and the thickness of the second TCO layer is 80 nm.

[0326] In this embodiment, the material of the first TCO layer is AZO, and the material of the second TCO layer is IWO.

[0327] In this embodiment, the second semiconductor composite layer includes a stacked composite segment disposed in the first region.

[0328] The first doped layer is disposed on a side of the mask layer facing away from the silicon substrate, and the stacked composite section is disposed on a side of the mask layer facing away from the silicon substrate.

[0329] A avoidance hole is provided between the mask layer and the laminated composite section.

[0330] The composite TCO layer includes a first composite segment disposed in the first region and a second composite segment disposed in the second region,

[0331] The first composite section includes a first segment and a second segment, the first segment is arranged in the avoidance hole and directly contacts with the side of the first doped layer facing away from the silicon substrate, and a first electrode is arranged on the side of the first segment facing away from the silicon substrate, and the second segment is arranged on the side of the second doped extension section facing away from the silicon substrate.

[0332] A second electrode is disposed on a side of the second composite section facing away from the silicon substrate.

[0333] Among them, the material of the mask layer is SiN x .

[0334] In this embodiment, the polarity of the first doping layer is opposite to the polarity of the silicon substrate, and the polarity of the second doping layer is the same as the polarity of the silicon substrate.

[0335] In this embodiment, the refractive index of the first TCO layer is greater than the refractive index of the second TCO layer.

[0336] In this embodiment, a velvet structure is provided on the second area of ​​the backlight surface and on the light receiving surface.

[0337] In this embodiment, the silicon substrate is single crystal silicon.

[0338] In this embodiment, the tunnel passivation layer is made of silicon oxide, the first doped layer is made of polysilicon, the second doped layer is made of amorphous silicon, and the passivation contact layer is made of amorphous silicon.

[0339] In this embodiment, the light-receiving surface of the silicon substrate is provided with a front passivation layer and a front anti-reflection layer in sequence in a direction away from the silicon substrate, wherein the material of the front passivation layer is amorphous silicon with a thickness of 10nm, and the material of the front anti-reflection layer is silicon nitride with a thickness of 60nm.

[0340] The above-mentioned back contact battery is prepared by the preparation method of Example 1.

[0341] Example 8

[0342] This embodiment provides a back contact battery, comprising:

[0343] A silicon substrate, wherein a backlight surface of the silicon substrate has a plurality of first areas and second areas arranged alternately;

[0344] A first semiconductor composite layer, disposed in the first region, comprises a tunnel passivation layer and a first doping layer sequentially disposed in a direction away from the silicon substrate;

[0345] A second semiconductor composite layer, at least partially disposed in the second region, comprises a passivation contact layer and a second doping layer sequentially disposed in a direction away from the silicon substrate, wherein the polarity of the second doping layer is opposite to that of the first doping layer;

[0346] The composite TCO layer is disposed on at least a portion of the first doped layer and the second doped layer on a side facing away from the silicon substrate.

[0347] The composite TCO layer includes a first TCO layer and a second TCO layer sequentially arranged in a direction away from the silicon substrate. A plurality of holes are distributed on the first TCO layer. The holes have openings at least on one side of the first TCO layer away from the second TCO layer.

[0348] In this embodiment, the porosity of the first TCO layer is 3.00%.

[0349] In this embodiment, the density of the first TCO layer is less than the density of the second TCO layer.

[0350] In this embodiment, the holes include blind holes with the above-mentioned openings and through holes penetrating the first TCO layer, wherein, taking each square centimeter of area as a calculation unit, the blind holes in a unit area account for (85±1)% of the total number of through holes and blind holes in the unit area.

[0351] In this embodiment, the ratio between the thickness H of the first TCO layer and the depth h of the blind hole is controlled to be 1:(0.7±0.05).

[0352] In this embodiment, the maximum width W of the opening of each hole that is disposed facing away from the second TCO layer is controlled to be (40±1) nm.

[0353] In this embodiment, the thickness of the first TCO layer is 40 nm, and the thickness of the second TCO layer is 80 nm.

[0354] In this embodiment, the material of the first TCO layer is AZO, and the material of the second TCO layer is IWO.

[0355] In this embodiment, the second semiconductor composite layer includes a stacked composite segment disposed in the first region.

[0356] The first doped layer is disposed on a side of the mask layer facing away from the silicon substrate, and the stacked composite section is disposed on a side of the mask layer facing away from the silicon substrate.

[0357] A avoidance hole is provided between the mask layer and the laminated composite section.

[0358] The composite TCO layer includes a first composite segment disposed in the first region and a second composite segment disposed in the second region,

[0359] The first composite section includes a first segment and a second segment, the first segment is arranged in the avoidance hole and directly contacts with the side of the first doped layer facing away from the silicon substrate, and a first electrode is arranged on the side of the first segment facing away from the silicon substrate, and the second segment is arranged on the side of the second doped extension section facing away from the silicon substrate.

[0360] A second electrode is disposed on a side of the second composite section facing away from the silicon substrate.

[0361] Among them, the material of the mask layer is SiN x .

[0362] In this embodiment, the polarity of the first doping layer is opposite to the polarity of the silicon substrate, and the polarity of the second doping layer is the same as the polarity of the silicon substrate.

[0363] In this embodiment, the refractive index of the first TCO layer is smaller than the refractive index of the second TCO layer.

[0364] In this embodiment, a velvet structure is provided on the second area of ​​the backlight surface and on the light receiving surface.

[0365] In this embodiment, the silicon substrate is single crystal silicon.

[0366] In this embodiment, the tunnel passivation layer is made of silicon oxide, the first doped layer is made of polysilicon, the second doped layer is made of amorphous silicon, and the passivation contact layer is made of amorphous silicon.

[0367] In this embodiment, the light-receiving surface of the silicon substrate is provided with a front passivation layer and a front anti-reflection layer in sequence in a direction away from the silicon substrate, wherein the material of the front passivation layer is amorphous silicon with a thickness of 10nm, and the material of the front anti-reflection layer is silicon nitride with a thickness of 60nm.

[0368] The above-mentioned back contact battery is prepared by the preparation method of Example 1.

[0369] Comparative Example 1

[0370] The difference between this comparative example and Example 2 is that no holes are provided in the first TCO layer. Accordingly, in the preparation process according to the preparation method of Example 1, the first annealing treatment is not performed in step S400.

[0371] The solar cells prepared in Examples 2 to 8 and Comparative Example 1 were subjected to performance tests, and the test results are as follows:

[0372]

[0373] It can be seen from the experimental results that, compared with comparative example 1, the conversion efficiency of examples 2 to 8 of the present invention is higher, which indicates that the arrangement of holes in the first TCO layer of the present invention can effectively improve the conversion efficiency.

[0374] By comparing Example 2, Example 3, and Example 6 to Example 7, it can be seen that the porosity of the first TCO layer can affect the conversion efficiency.

[0375] By comparing Examples 3 to 5, it can be seen that the hole opening size of the first TCO layer can affect the conversion efficiency.

[0376] Comparing Example 3 with Example 8, it can be seen that compared with the refractive index of the first TCO layer being lower than the refractive index of the second TCO layer, the first TCO layer hole design of the present invention combined with the design that the refractive index of the first TCO layer is higher than the refractive index of the second TCO layer can further improve the conversion efficiency.

[0377] In the description of this specification, the description with reference to the terms "some embodiments", "implementation", "exemplary", "example", or "for example" means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0378] The above is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with the field can make some changes or modify the technical contents suggested above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the solution of the present invention.

Claims

1. A back contact battery, characterized in that: include: A silicon substrate, wherein a backlight surface of the silicon substrate has a plurality of first areas and second areas arranged alternately; A first semiconductor composite layer, disposed in the first region, comprising a tunnel passivation layer and a first doping layer sequentially disposed in a direction away from the silicon substrate; A second semiconductor composite layer, at least partially disposed in the second region, comprises a passivation contact layer and a second doping layer sequentially disposed in a direction away from the silicon substrate, wherein the polarity of the second doping layer is opposite to that of the first doping layer; A composite TCO layer is provided in at least a portion of the first doped layer and the second doped layer on a side facing away from the silicon substrate, The composite TCO layer includes a first TCO layer and a second TCO layer sequentially arranged in a direction away from the silicon substrate, a plurality of holes are distributed on the first TCO layer, and the holes are opened at least on one side of the first TCO layer away from the second TCO layer.

2. A back contact battery according to claim 1, characterized in that: The porosity of the first TCO layer is 0.5% to 5%.

3. A back contact battery according to claim 2, characterized in that: The porosity of the first TCO layer is 1.5% to 3%.

4. A back contact battery according to claim 1, characterized in that: The density of the first TCO layer is less than the density of the second TCO layer.

5. A back contact battery according to claim 1, characterized in that: The hole includes a blind hole having the opening and / or a through hole penetrating the first TCO layer.

6. A back contact battery according to claim 5, characterized in that: Under the condition that the area per square centimeter is used as a calculation unit, the blind holes in a unit area account for at least 80% of the total amount of the through holes and the blind holes in the unit area.

7. A back contact battery according to claim 6, characterized in that: Under the condition that the area per square centimeter is used as a calculation unit, the blind holes in a unit area account for 80% to 90% of the total amount of the through holes and the blind holes in the unit area.

8. A back contact battery according to claim 1, characterized in that: The ratio between the thickness of the first TCO layer and the depth of the hole is 1:0.5-0.

8.

9. A back contact battery according to claim 1, characterized in that: In each of the holes, the maximum width of the opening disposed away from the second TCO layer is 20 nm to 60 nm.

10. A back contact battery according to claim 1, characterized in that: The thickness of the first TCO layer is 10 nm to 100 nm, and the thickness of the second TCO layer is 30 nm to 150 nm.

11. A back contact battery according to claim 1, characterized in that: The second semiconductor composite layer includes a stacked composite segment disposed in the first region, The first doped layer is disposed on a side facing away from the silicon substrate on the mask layer, and the stacked composite section is disposed on a side facing away from the silicon substrate on the mask layer. An avoidance hole is provided between the mask layer and the stacked composite section. The composite TCO layer includes a first composite section disposed in the first region and a second composite section disposed in the second region, The first composite section includes a first segment and a second segment, the first segment is arranged in the avoidance hole and directly contacts with a side of the first doped layer facing away from the silicon substrate, and a first electrode is arranged on a side of the first segment facing away from the silicon substrate, and the second segment is arranged on a side of the second doped extension section facing away from the silicon substrate. A second electrode is disposed on a side of the second composite section facing away from the silicon substrate.

12. A back contact battery according to claim 1, characterized in that: The polarity of the first doping layer is the same as that of the silicon substrate, and the polarity of the second doping layer is opposite to that of the silicon substrate.

13. A back contact battery according to claim 1, characterized in that: The refractive index of the first TCO layer is greater than the refractive index of the second TCO layer.

14. A method for preparing a back contact battery, characterized in that: include: Providing a silicon substrate, wherein a backlight surface of the silicon substrate has a plurality of first areas and second areas arranged alternately; Depositing a first semiconductor composite layer and a mask layer in sequence on the backlight surface of the silicon substrate, and removing the first semiconductor composite layer and the mask layer outside the first region, wherein the first semiconductor composite layer includes a tunnel passivation layer and a first doping layer arranged in sequence in a direction away from the silicon substrate; Depositing a second semiconductor composite layer on the mask layer and the second region, and removing a portion of the mask layer and the second semiconductor composite layer located in the first region to expose a portion of the first doped layer, wherein the second semiconductor composite layer includes a passivation contact layer and a second doped layer sequentially arranged in a direction away from the silicon substrate, and the polarity of the second doped layer is opposite to that of the first doped layer; A composite TCO layer is deposited on the second doped layer and the exposed first doped layer, wherein the composite TCO layer includes a first TCO layer and a second TCO layer sequentially arranged in a direction away from the silicon substrate, wherein a plurality of holes are distributed on the first TCO layer, and wherein the holes have openings at least on a side of the first TCO layer away from the second TCO layer.

15. The method for preparing a back contact battery according to claim 14, characterized in that: The step of depositing a composite TCO layer on the second doped layer and the exposed first doped layer comprises: Depositing a first TCO layer and performing a first annealing process; A second TCO layer is deposited and a second annealing process is performed.

16. The method for preparing a back contact battery according to claim 14, characterized in that: include: Printing ink on the composite TCO layer to form an electrode patterned structure, and then removing the composite TCO layer in the area not covered by the ink by a wet chemical process to form the composite TCO layer with an isolation area; A low-temperature paste is printed on the composite TCO layer with the isolation area to form a first electrode and a second electrode, and low-temperature annealing is performed to form an electrode structure, wherein the first electrode is electrically connected to the first doped layer through the composite TCO layer, and the second electrode is electrically connected to the second doped layer through the composite TCO layer.

17. The method for preparing a back contact battery according to claim 14, characterized in that: The porosity of the first TCO layer is 0.5% to 5%.

18. The method for preparing a back contact battery according to claim 17, characterized in that: The porosity of the first TCO layer is 1.5% to 3%.

19. The method for preparing a back contact battery according to claim 14, characterized in that: The density of the first TCO layer is less than the density of the second TCO layer.

20. A photovoltaic system, characterized in that: A back-contact battery comprising a back-contact battery according to any one of claims 1 to 13, or a back-contact battery prepared by the preparation method according to any one of claims 14 to 19.

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