Miniature light-emitting diode chip with dummy light-emitting mesa

Abstract

The invention provides an epitaxial wafer with a dummy light-emitting mesa. The epitaxial wafer comprises a temporary substrate; the light-emitting mesa is arranged on the temporary substrate and comprises a bottom transparent conductive layer which is arranged on the side, back to the temporary substrate, of the light-emitting mesa; a first epitaxial layer disposed between the bottom transparent conductive layer and the light emitting layer; a light emitting layer disposed between the first epitaxial layer and the second epitaxial layer and configured to emit light; the second epitaxial layer is arranged on the side, facing the temporary substrate, of the light-emitting mesa, and the area of the upper surface, facing the temporary substrate, of the light-emitting mesa is larger than the area of the lower surface, back to the temporary substrate, of the light-emitting mesa; the passivation layer covers the lower surface and the side face of the light-emitting table top, the light-emitting table top comprises a first light-emitting table top and a dummy light-emitting table top, the passivation layer on the first light-emitting table top is provided with a notch to expose the bottom transparent conductive layer, and the passivation layer on the dummy light-emitting table top is not provided with a notch. In addition, the invention also provides a micro light-emitting diode chip. According to the invention, the risk of delamination or gap generation between the insulating layer and the light-emitting mesa can be significantly reduced.

Description

Technical Field

[0001] The present invention generally relates to the field of micro light emitting diodes, and more particularly to a micro light emitting diode chip having a dummy light emitting mesa. Background Art

[0002] Micro Light Emitting Diode (MLD) is a new type of LED structure obtained by thin-filming, miniaturizing and arraying the original LED structure. It integrates arrayed micron-level LED units on an active addressing drive panel to realize the lighting and individual control of the LED units, thereby outputting the desired display image. The core structure of a micro-LED is a PN junction diode, which is composed of direct bandgap semiconductor materials. When the upper and lower electrodes apply a forward bias to the micro-LED to cause current to pass through, electrons and holes recombine in the active region (Active region) and emit single-color light photons at the same time.

[0003] The light-emitting mesas of a micro-LED include a regular trapezoidal light-emitting mesas and an inverted trapezoidal light-emitting mesas, wherein the upper surface of the regular trapezoidal light-emitting mesas is smaller than the lower surface, while the inverted trapezoidal light-emitting mesas are just the opposite. At present, one difficulty in manufacturing micro-LEDs based on epitaxial wafers with inverted trapezoidal light-emitting mesas is that when an insulating layer is deposited on the epitaxial wafer to cover the light-emitting mesas, the applied insulating layer is prone to delamination or gaps due to the shear stress generated parallel to the epitaxial wafer. Epitaxial wafers with delamination or gaps need to be reworked and polished multiple times through processes such as chemical mechanical polishing (CMP), which increases the complexity of the process and also brings certain uncertainties to product quality. Summary of the invention

[0004] Based on the prior art, the task of the present invention is to provide an epitaxial wafer with a dummy light-emitting mesa and a micro light-emitting diode chip, through which the risk of delamination or generation of gaps between the insulating layer and the light-emitting mesa can be significantly reduced.

[0005] In a first aspect of the present invention, the aforementioned task is achieved by a micro light emitting diode having a dummy light emitting mesa, comprising:

[0006] A plurality of light-emitting countertops, each light-emitting countertop comprising:

[0007] Bottom transparent conductive layer;

[0008] a first epitaxial layer disposed between the bottom transparent conductive layer and the light emitting layer;

[0009] a light emitting layer disposed between the first epitaxial layer and the second epitaxial layer and configured to emit light; and

[0010] A second epitaxial layer is arranged on the light emitting layer, wherein the light emitting mesa has an area near an upper surface of the second epitaxial layer greater than an area near a lower surface of the first epitaxial layer; and

[0011] A passivation layer covers the lower surface and side surfaces of the light-emitting mesas, wherein the light-emitting mesas include a first light-emitting mesas and a dummy light-emitting mesas, wherein the passivation layer on the first light-emitting mesas has a notch to expose the bottom transparent conductive layer, and the passivation layer on the dummy light-emitting mesas has no notch.

[0012] In one embodiment, the depth of the dummy light-emitting mesa is different from the depth of the first light-emitting mesa; and / or

[0013] The diameter of the upper surface of the dummy light-emitting mesa is different from the diameter of the upper surface of the first light-emitting mesa; and / or

[0014] The diameter of the lower surface of the dummy light-emitting mesa is different from the diameter of the lower surface of the first light-emitting mesa; and / or

[0015] The spacing between the dummy light-emitting mesas is different from the spacing between the first light-emitting mesas.

[0016] In one embodiment, wherein:

[0017] The depth of the dummy light-emitting mesa is the same as the depth of the first light-emitting mesa; and / or

[0018] The diameter of the upper surface of the dummy light-emitting mesa is the same as the diameter of the upper surface of the first light-emitting mesa; and / or

[0019] The diameter of the lower surface of the dummy light-emitting mesa is the same as the diameter of the upper surface of the first light-emitting mesa; and / or

[0020] The spacing between the dummy light-emitting mesas is the same as the spacing between the first light-emitting mesas.

[0021] In one embodiment, it further includes:

[0022] A substrate carries the light emitting mesa.

[0023] In one embodiment, it further includes:

[0024] The dicing streets are configured to mark the boundaries between adjacent micro-LED chips, wherein the dicing streets are arranged between the dummy light-emitting mesas.

[0025] In one embodiment,

[0026] The thickness of the buffer layer is 4000 angstroms to 8000 angstroms; and / or

[0027] The first epitaxial layer has a thickness of 2500 to 3500 angstroms; and / or

[0028] The thickness of the light emitting layer is 2000 to 4000 angstroms; and / or

[0029] The second epitaxial layer has a thickness of 4000 to 5000 angstroms; and / or

[0030] The thickness of the bottom transparent conductive layer is 800 to 1500 um; and / or

[0031] The thickness of the passivation layer is 800 angstroms to 1800 angstroms.

[0032] In one embodiment, the material of the substrate is selected from the group consisting of silicon (Si), silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), gallium nitride (GaN), glass, aluminum nitride (AlN), sapphire (α-Al2O3), and germanium (Ge).

[0033] In one embodiment, the number of dummy light-emitting mesas accounts for 40% to 50% of the total number of light-emitting mesas.

[0034] In one embodiment, the diameter of the lower surface of the light-emitting mesa is 0.8 to 1.2 μm; and / or

[0035] The diameter of the upper surface of the light-emitting mesa is 1.4 to 1.8 μm; and / or

[0036] The height of the light-emitting mesa is 0.3 to 0.7 μm.

[0037] In one embodiment, the second epitaxial layer includes:

[0038] a stepped portion in electrical contact with the light emitting layer; and

[0039] The base portion extends from the step portion to both sides.

[0040] In one embodiment, base portions of adjacent light-emitting mesas are connected to each other.

[0041] In one embodiment, the thickness of the step portion is: 400nm to 800nm; and / or

[0042] The thickness of the base portion is 4 to 4.4 um.

[0043] In one embodiment, the passivation layer covers the side surfaces of the stepped portion and the surface of the base portion.

[0044] In one embodiment, the micro light emitting diode chip further includes:

[0045] a reflector layer arranged to surround the first light emitting mesa;

[0046] A driving circuit having a metal layer, a plurality of through-hole contacts being arranged on the driving circuit, the through-hole contacts being electrically connected to the metal layer, the micro-LED array region being bonded to the driving circuit through a bottom conductive bonding layer, wherein the driving circuit further has a wiring stack under the metal layer, which is configured to lead out a first electrode;

[0047] an insulating layer configured to accommodate the first light emitting mesa, the dummy light emitting mesa, and the through-hole contact;

[0048] a first electrode electrically connected to the through-hole contact portion;

[0049] a top transparent conductive layer, which is disposed on a surface of the passivation layer and is in electrical contact with the second epitaxial layer; and

[0050] The second electrode is disposed on the surface of the top transparent conductive layer.

[0051] In order to achieve the above object, the present invention further provides a micro light emitting diode chip having a dummy light emitting mesa, comprising:

[0052] a light emitting area including a plurality of first light emitting mesas configured to emit light; and

[0053] The non-luminous area is adjacent to the luminous area and includes a plurality of dummy luminous mesas that do not emit light.

[0054] In one embodiment, the light emitting area accounts for 50% to 60% of the micro-LED chip; and / or

[0055] The non-luminous area accounts for 40% to 50% of the micro-LED chip.

[0056] In one embodiment, the first light-emitting mesa and the dummy light-emitting mesa both include:

[0057] A bottom transparent conductive layer, which faces the light-emitting side;

[0058] a first epitaxial layer disposed between the bottom transparent conductive layer and the light emitting layer;

[0059] a light emitting layer disposed between the first epitaxial layer and the second epitaxial layer and configured to emit light; and

[0060] The second epitaxial layer faces away from the light-emitting side, wherein the area of ​​the upper surface of the light-emitting mesa facing the light-emitting side is larger than the area of ​​the lower surface facing away from the light-emitting side.

[0061] In one embodiment, the first light-emitting mesa has the same size as the dummy light-emitting mesa, and the size includes: an upper surface size, a lower surface size, and a height of the light-emitting mesa.

[0062] In one embodiment, the diameter of the lower surface of the first light-emitting mesa is 0.8 to 1.2 μm; and / or

[0063] The diameter of the upper surface of the first light-emitting mesa is 1.4 to 1.8 μm; and / or

[0064] The height of the first light emitting mesa is 0.3 to 0.7 μm.

[0065] In one embodiment, the light emitting region further comprises a through-hole contact configured to electrically connect the second epitaxial layer of the first light emitting mesa to the first electrode; and

[0066] The non-light emitting region has no through-hole contact for electrically connecting the second epitaxial layer of the dummy light emitting mesa to the driving circuit.

[0067] In one embodiment, the light emitting region further comprises a top transparent conductive layer disposed on an upper surface of the light emitting mesa to electrically connect the first epitaxial layer to the second electrode; and

[0068] The non-light emitting area does not have the top transparent conductive layer.

[0069] In one embodiment, an insulating layer covers the light emitting area and the non-light emitting area.

[0070] In one embodiment, a first interval between adjacent first light-emitting mesas in the light-emitting region is equal to a second interval between adjacent dummy light-emitting mesas in the non-light-emitting region.

[0071] In one embodiment, a first interval between adjacent first light-emitting mesas in the light-emitting region is different from a second interval between adjacent dummy light-emitting mesas in the non-light-emitting region.

[0072] In one embodiment, the micro light emitting diode chip further includes:

[0073] A passivation layer covers the lower surface of the first light-emitting mesa and the lower surface of the dummy light-emitting mesa, wherein the passivation layer on the first light-emitting mesa has a notch to expose the bottom transparent conductive layer, and the passivation layer on the dummy light-emitting mesa has no notch.

[0074] In one embodiment, the micro light emitting diode chip further includes:

[0075] a reflector layer arranged to surround the first light-emitting mesa and configured to reflect light emitted by the first light-emitting mesa toward a light-emitting side;

[0076] A driving circuit having a metal layer, a plurality of through-hole contacts being arranged on the driving circuit, the through-hole contacts being electrically connected to the metal layer, the micro-LED array region being bonded to the driving circuit through a bottom conductive bonding layer, wherein the driving circuit further has a wiring stack under the metal layer, which is configured to lead out a first electrode;

[0077] an insulating layer configured to accommodate the first light emitting mesa, the dummy light emitting mesa, and the through-hole contact;

[0078] a first electrode electrically connected to the through-hole contact portion;

[0079] a top transparent conductive layer, which is disposed on a surface of the passivation layer and is in electrical contact with the second epitaxial layer; and

[0080] The second electrode is disposed on the surface of the top transparent conductive layer.

[0081] In one embodiment, in a micro light emitting diode chip, the polarity of the second electrode is opposite to that of the first electrode.

[0082] In one embodiment, the material of the second epitaxial layer is a material layer of the second conductivity type comprising two or more elements of Ga, N, As, Al, In, and P, and the first epitaxial layer is a material layer of the first conductivity type comprising two or more elements of Ga, N, As, Al, In, and P, wherein the first conductivity type is different from the second conductivity type.

[0083] In one embodiment, the light emitting layer comprises a multi-quantum well layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer, an InGaN / AlGaN multi-quantum well layer, an InGaAs / AlGaAs multi-quantum well layer, or an AlGaInP multi-quantum well layer.

[0084] In one embodiment, an electron blocking layer is disposed on a first side of the light-emitting layer, where the first side refers to a side along which electrons migrate out of the light-emitting layer.

[0085] In one embodiment, the material of the passivation layer is Si3N4 film, SiO2 film or Al2O3 film.

[0086] In one embodiment, the material of the insulating layer is selected from the group consisting of silicon dioxide (SiO2), aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon carbonitride (SiCN), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), magnesium oxide (MgO), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), or any combination thereof; and / or

[0087] The material of the metal layer is selected from the group consisting of aluminum (Al), copper (Cu), tungsten (W), silver (Ag), gold (Au), nickel (Ni), platinum (Pt), tantalum (Ta), and molybdenum (Mo).

[0088] In another embodiment of the present invention, the through-hole contact portion includes a first and a second through-hole contact portion, and the insulating layer includes a first and a second insulating layer, and the micro-light-emitting diode chip includes an upper stack and a lower stack, wherein the upper stack includes a first insulating layer, a light-emitting table and a first through-hole contact portion, and the lower stack includes a second insulating layer, a second through-hole contact portion and a driving circuit, wherein the lower stack is joined to the upper stack by hybrid bonding, so that the first through-hole contact portion is bonded to the second through-hole contact portion, and the first insulating layer is bonded to the second insulating layer.

[0089] The present invention has at least the following beneficial effects:

[0090] (1) The applicant has discovered through research that the main reason why delamination is easy to occur when an insulating layer such as silicon dioxide is coated on the light-emitting surface is that the light-emitting surface in the light-emitting area has a concave-convex structure, while the non-light-emitting area has a planar structure. Therefore, the stress generated by the insulating layer coated in the non-light-emitting area is easily transmitted to the light-emitting area, increasing the shear stress in the light-emitting area, causing the insulating layer in the light-emitting area to delaminate, wrinkle or produce gaps. The inventors of the present invention have also discovered that if the same dummy light-emitting mesa is etched in the non-light-emitting area while the light-emitting mesa is etched in the light-emitting area, on the one hand, it is easy to do in terms of process and has low additional cost, because the etching of the dummy light-emitting mesa can be achieved by simply expanding the etching range of the epitaxial wafer; on the other hand, the concave-convex structure of the dummy light-emitting mesa in the non-light-emitting area can better suppress the stress in the non-light-emitting area from being transmitted to the light-emitting area, thereby reducing the risk of delamination, wrinkling, and voids in the insulating layer in the light-emitting area when the insulating layer is coated; at the same time, according to the stress formula: σ=F / A (σ is the stress per unit area, F is the external force, and A is the force area), it can be seen that by setting a dummy light-emitting mesa in the non-light-emitting area, its concave-convex structure can increase the surface area of ​​the coated insulating layer, thereby reducing the stress per unit area, and thus also reducing the risk of delamination, wrinkling, and voids in the non-light-emitting area.

[0091] (2) In addition, the inventors have discovered through research that the best anti-delamination, wrinkling and void generation effects can be achieved when the area occupied by the dummy light-emitting mesa accounts for slightly less than 50% of the total chip area, that is, 40% to 50%, preferably 44% (at this time the light-emitting area accounts for 56%). BRIEF DESCRIPTION OF THE DRAWINGS

[0092] The present invention will be further described below in conjunction with specific embodiments with reference to the accompanying drawings.

[0093] Figure 1 A schematic diagram showing a first embodiment of an epitaxial wafer having a dummy light-emitting mesa according to the present invention is shown;

[0094] Figure 2 A schematic diagram of a light-emitting table according to the present invention is shown;

[0095] Figure 3 A schematic diagram showing a second embodiment of an epitaxial wafer having a dummy light-emitting mesa according to the present invention is shown;

[0096] Figure 4 A schematic diagram showing a third embodiment of an epitaxial wafer having a dummy light-emitting mesa according to the present invention;

[0097] Figure 5 A schematic diagram of a micro light emitting diode according to the present invention is shown;

[0098] Figure 6 A schematic diagram showing a mirror layer according to the present invention; and

[0099] Figure 7 A top view of an epitaxial wafer according to the present invention is shown. DETAILED DESCRIPTION

[0100] It should be noted that the components in the figures may be shown exaggeratedly for the sake of illustration and are not necessarily true to scale. In the figures, identical or functionally identical components are provided with the same reference numerals.

[0101] In the present invention, unless otherwise specified, "arranged on...", "arranged above..." and "arranged above..." do not exclude the existence of an intermediate between the two. In addition, "arranged on or above..." merely indicates the relative positional relationship between two components, and in certain cases, such as after reversing the product direction, it can also be converted into "arranged below or below...", and vice versa.

[0102] In the present invention, each embodiment is only intended to illustrate the aspects of the present invention and should not be construed as limiting.

[0103] In the present invention, unless otherwise specified, the quantifiers "a", "an" and "an" do not exclude the presence of a plurality of elements.

[0104] In the present invention, the term “connected” may refer to both being directly connected or being indirectly connected via an intermediate element.

[0105] In the present invention, the term "configuration" refers to the setting of the shape, structure, material and / or function of the target object to achieve the desired technical effect, wherein "configuration" includes a variety of alternative technical means for achieving the technical effect, which become obvious under the teaching of the present invention.

[0106] It should also be noted that in the embodiments of the present invention, for the sake of clarity and simplicity, only a portion of the parts or components may be shown, but those of ordinary skill in the art will understand that under the teachings of the present invention, the required parts or components may be added according to the needs of the specific scenario. In addition, unless otherwise specified, the features in different embodiments of the present invention may be combined with each other. For example, a feature in the second embodiment may be used to replace a corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment also falls within the disclosure scope or recorded scope of the present application.

[0107] It should also be noted that within the scope of the present invention, the terms "same", "equal", "equal to" and the like do not mean that the values ​​of the two are absolutely equal, but allow a certain reasonable error, that is, the terms also cover "substantially the same", "substantially equal", "substantially equal to". By analogy, in the present invention, the terms "perpendicular to", "parallel to" and the like indicating directions also cover the meanings of "substantially perpendicular to" and "substantially parallel to".

[0108] In the present invention, the term "configuration" refers to the setting of the shape, structure, material and / or function of the target object to achieve the desired technical effect, wherein "configuration" includes a variety of alternative technical means for achieving the technical effect, which become obvious under the teaching of the present invention.

[0109] In the present invention, the term "interval between adjacent light-emitting mesas" refers to the distance between the edges of adjacent light-emitting mesas in a central longitudinal section perpendicular to the bottom surface of the light-emitting mesas.

[0110] In the present invention, the term "light-emitting side of the light-emitting mesa" refers to the side of the light-emitting mesa that outputs light, that is, the side where the light generated by the light-emitting mesa leaves the light-emitting mesa and is output outward. For example, the light-emitting side of the light-emitting mesa is the side where the microlens is located. Similarly, the term "the side of the light-emitting mesa facing away from the light-emitting side" refers to the side of the light-emitting mesa opposite to the light-emitting side, for example, the side facing the drive circuit or the drive circuit.

[0111] In the present invention, the term "upward reflection" means that light is reflected so that the distance between the reflected light and the light-emitting side surface of the light-emitting mesa becomes increasingly greater. The upward direction includes directly above and obliquely above.

[0112] Figure 1 FIG. 1 is a schematic diagram showing a first embodiment of an epitaxial wafer 100 having a dummy light-emitting mesa according to the present invention.

[0113] like Figure 1As shown, the epitaxial wafer 100 includes a light-emitting area AA and a non-light-emitting area NA. The non-light-emitting area NA is adjacent to the light-emitting area AA. A first light-emitting mesa 101 for emitting light is provided in the light-emitting area AA, and a dummy light-emitting mesa 102 that does not emit light is provided in the non-light-emitting area NA. The light-emitting area AA, for example, accounts for 50% to 60% of the area of ​​the epitaxial wafer 100, preferably 56%, and the non-light-emitting area NA, for example, accounts for 40% to 50% of the area of ​​the epitaxial wafer 100, preferably 44%. In the present invention, the epitaxial wafer refers to a substrate carrying an epitaxial layer, and the epitaxial layer may be unetched or etched (in the present invention, the epitaxial layer of the epitaxial wafer has been etched to form a part of the light-emitting mesa), and the role of the epitaxial layer is to provide the basic structure of the light-emitting mesa, so that subsequent processes (photolithography, etching, deposition, electroplating, and grinding, etc.) can be performed on it to form a micro light-emitting diode chip.

[0114] In addition, the epitaxial wafer 100 also has a temporary substrate 103, a buffer layer 104 and a dicing street 107. These components are described below respectively.

[0115] Temporary substrate

[0116] The epitaxial wafer 100 with a dummy light-emitting mesa according to the present invention may have a temporary substrate 103, which is configured to grow an epitaxial layer and carry a first light-emitting mesa 101 and a dummy light-emitting mesa 102 formed by etching the epitaxial layer. The thickness of the temporary substrate 103 may be, for example, 600 to 1000 μm, preferably 800 μm. For example, the temporary substrate 103 is used for the epitaxial growth of the epitaxial layer, i.e., the first epitaxial layer 101B, the light-emitting layer 101C, and the second epitaxial layer 101D, and is used to carry the epitaxial layer and the bottom transparent conductive layer 101AA formed thereon in the subsequent process. Here, the bottom transparent conductive layer 101AA is referred to as the "bottom transparent conductive layer" because it is arranged on the side of the light-emitting mesa facing away from the light-emitting side A, that is, at the bottom of the finished chip. After the relevant process is completed, the temporary substrate 103 can be removed, for example, by debonding and grinding, such as CMP to remove the temporary substrate 103. The material of the temporary substrate 103 may include, for example, silicon (Si), silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), gallium nitride (GaN), glass, aluminum nitride (AlN), sapphire (α-Al2O3), and germanium (Ge).

[0117] Buffer layer

[0118] The epitaxial wafer 100 with a dummy light-emitting mesa according to the present invention may have a buffer layer 104, which is arranged between the second epitaxial layer 101D and the temporary substrate 103. The buffer layer 104 is used to mark the position of the second epitaxial layer 101D when removing the temporary substrate 103 to avoid damaging the second epitaxial layer 101D. For example, the buffer layer 104 may serve as an etching buffer layer or a grinding buffer layer, and its thickness is, for example, After the relevant processes are completed, the buffer layer 104 may be removed, for example, by debonding and polishing, such as CMP, to remove the buffer layer 104. The material of the buffer layer 104 may include, for example, gallium nitride, silicon nitride, and silicon dioxide.

[0119] First light-emitting surface

[0120] The epitaxial wafer 100 with dummy light-emitting mesas according to the present invention has a first light-emitting mesas 101, which is located in the light-emitting area AA and is arranged on a temporary substrate 103 or a buffer layer 104. The first light-emitting mesas 101 are arranged in the light-emitting area AA and are configured to emit light. Figure 1 It can be seen that the side inclination angle α of the light-emitting mesa 101 (see Figure 2 ) can be, for example, between 55° and 75°, especially between 60° and 70°, thereby obtaining a better aperture ratio of the micro light-emitting diode chip. The first light-emitting mesa 101 has, starting from the side facing away from the light-emitting side A, a bottom transparent conductive layer 101AA, a first epitaxial layer 101B, a light-emitting layer 101C and a second epitaxial layer 101D in sequence. The diameter of the lower surface of the light-emitting mesa 101 can be, for example, 0.8 to 1.2 μm, preferably 1.0 μm. The diameter of the upper surface of the light-emitting mesa 101 can be, for example, 1.4 to 1.8 μm, preferably 1.6 μm. The height of the light-emitting mesa can be, for example, 0.3 to 0.7 μm, preferably 0.5 μm. In addition, the first light-emitting mesa 101 also has a passivation layer 105 on its lower surface and side surfaces facing away from the light-emitting side A. These layers are described below respectively.

[0121] The bottom transparent conductive layer 101A is disposed on the side of the first light-emitting mesa 101 facing away from the light-emitting side A, that is, the side facing the driving circuit. The function of the bottom transparent conductive layer 101A is to electrically connect the first epitaxial layer 101B in the first light-emitting mesa 101 to the driving circuit, especially the first electrode, such as the anode. The material of the bottom transparent conductive layer 101A is, for example, a metal oxide, such as indium tin oxide ITO, zinc oxide ZnO, etc., and its formation method includes, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), sol-gel method, solution coating method, etc. The thickness of the bottom transparent conductive layer 101A can be, for example, 1000 Å. The width thereof may be, for example, 1.0 um. The bottom transparent conductive layer 101A and other layers of the first light-emitting mesa 101 may be etched in the same etching step or in different etching steps. The thickness of the bottom transparent conductive layer 101A may be, for example, 800 to 1500 um.

[0122] See also Figure 2 , the formation process of the first light-emitting mesa 101 is described below by taking different etching steps as examples. First, a bottom transparent conductive layer 101A is formed on the first epitaxial layer 101B, and then the bottom transparent conductive layer 101A is etched in a first etching step to form a first inclined edge 100A of the bottom transparent conductive layer 101A. Then, in a second etching step, the first epitaxial layer 101B, the light-emitting layer 101C, and the second epitaxial layer 101D are etched to form a second inclined edge 100B of the entire first light-emitting mesa 101. The inclination angle of the first inclined edge 100A can be equal to the inclination angle of the second inclined edge, for example, both are in the range of 55° to 75°, especially 60° to 70°. Alternatively, the inclination angle of the first inclined edge can be larger, for example, greater than 70°, especially greater than 75°, while the second inclined edge can be less than 75°, especially less than 70°. Since the thickness of the bottom transparent conductive layer 101A is much smaller than the sum of the thicknesses of the first epitaxial layer 101B, the light-emitting layer 101C, and the second epitaxial layer 101D, the average value of the inclination angle of the first inclined edge 100A and the second inclined edge 100B on the total height of the light-emitting mesa can still be in the range of 55° to 75°, especially 60° to 70°. For example, the first inclined edge 100A of the bottom transparent conductive layer 101A has a first inclination angle X, and the thickness of the bottom transparent conductive layer 101A is d1, while the second inclined edges 100B of the first epitaxial layer 101B, the light-emitting layer 101C, and the second epitaxial layer 101D have a second inclination angle Y, and the first epitaxial layer 101B, the light-emitting layer 101C, and the second epitaxial layer 101D have a thickness d2. Then the average value d of the inclination angle of the light-emitting mesa 101 over the entire thickness is:

[0123] d=(X*d1+Y*d2) / (d1+d2).

[0124] Here, d is in the range of 55° to 75°, especially 60° to 70°. That is to say, even if the layers etched in different etching steps have different tilt angles, as long as the average tilt angle d is in the above range, a good aperture ratio can still be guaranteed. For example, X = 85°, Y = 65°, since d1 = d2 / 10, the average tilt angle d = 66.8°.

[0125] In another case, the first inclined edge 100A and the second inclined edge 100B are not equal to each other, but their inclination angles are both in the range of 55° to 75°, especially 60° to 70°. Here, the "inclination angle of the inclined edge" refers to the angle between the inclined edge and the bottom surface of the first light-emitting mesa 101 from the cross-sectional view of the first light-emitting mesa 101, and the bottom surface direction of the first light-emitting mesa 101 can be characterized by the length extension direction of the second epitaxial layer 101D, for example. In addition, in the present embodiment, the end of the first inclined edge 100A and the end of the second inclined edge 100B are connected to each other, that is, smoothly transitioned. In other embodiments, the end of the first inclined edge 100A and the end of the second inclined edge 100B can also be a non-smooth transition, that is, there is a certain distance between the adjacent ends in the horizontal direction, and the distance is less than or equal to 0.2um. The light-emitting mesa with an inclination angle of 55° to 75°, especially 60° to 70°, can ensure a good aperture ratio on the one hand, and can also achieve a good area ratio between the first and second epitaxial layers and the light-emitting layer on the other hand.

[0126] The first epitaxial layer 101B is arranged between the bottom transparent conductive layer 101A and the light-emitting layer 101C. The light-emitting layer 101C is arranged between the first epitaxial layer 101B and the second epitaxial layer 101D and is configured to emit light. The second epitaxial layer 101D is arranged on the side of the first light-emitting mesa 101 facing the light-emitting side A, wherein the area of ​​the second epitaxial layer 101D is larger than the area of ​​the first epitaxial layer 101B, and the side surface of the first light-emitting mesa 101 has an inclined surface, and the inclination angle α of the inclined surface is 55° to 75°, preferably 60° to 70°. The thickness of the first epitaxial layer 101B can be, for example, 2500 to 3500 angstroms, the thickness of the light-emitting layer 101C can be, for example, 2000 to 4000 angstroms, and the thickness of the second epitaxial layer 101D can be, for example, 4000 to 5000 angstroms. The exemplary formation process of the first epitaxial layer 101B, the light emitting layer 101C, and the second epitaxial layer 101D can be referred to Figure 2 Detailed description of the formation process of the bottom transparent conductive layer 101A.

[0127] In addition, the second epitaxial layer 101D of the light-emitting mesa 101 includes two parts, namely, a step portion 1011 and a base portion 1012. The step portion 1011 is in electrical contact with the light-emitting layer 101C, and the base portion 1012 extends from the step portion 1011 to both sides, namely, extends beyond the step portion 1011. In one embodiment, the thickness of the step portion 1011 is The thickness of the base portion 1012 is Here, the second inclined edge 100B includes the first epitaxial layer 101B, the light emitting layer 101C, and the inclined surface of the step portion 1011. The base portion 1012 can extend to the adjacent light emitting mesa and be continuously connected to its base portion. In this embodiment, the second epitaxial layer 101D can not only increase in thickness, but also its surface area facing the light emitting side A is not limited by the slope, but can extend to the adjacent light emitting mesa, thereby improving the light emitting efficiency.

[0128] In some embodiments, the light-emitting layer is formed by a plurality of stacked quantum well layers, in particular, quantum well layers stacked in a superlattice. Preferably, the quantum well layers stacked in a superlattice include a plurality of pairs of quantum well layers stacked with quantum barrier layers. In some embodiments, the first epitaxial layer is a semiconductor material having a first conductivity type and includes a plurality of semiconductor layers. Its main matrix material may be, but is not limited to, Ga, N, As, P, In, or Al. In addition, the first epitaxial layer may include, from top to bottom, but is not limited to, a waveguide layer, a restriction layer, a transition layer, and a window layer; in addition, an ohmic contact layer may be formed below the window layer. In some embodiments, the second epitaxial layer is a semiconductor material having a second conductivity type and includes a plurality of semiconductor layers. The main matrix material of the second epitaxial layer may be, but is not limited to, Ga, N, As, P, In, or Al. In addition, the second epitaxial layer may include, from top to bottom, but is not limited to, a restriction layer and a waveguide layer; in addition, in some embodiments, an ohmic contact layer may be formed on the restriction layer. In one embodiment, the first conductivity type is different from the second conductivity type.

[0129] In one embodiment, the second epitaxial layer is an N-type GaN layer or an N-type AlGaN layer, and the first epitaxial layer is a P-type GaN layer or a P-type AlGaN layer, that is, the material of the second epitaxial layer may be a material layer of the second conductivity type comprising two or more elements of Ga, N, As, Al, In, and P, and the first epitaxial layer may be a material layer of the first conductivity type comprising two or more elements of Ga, N, As, Al, In, and P. In one embodiment, the light-emitting layer includes a multi-quantum well layer and an electron blocking layer, and the multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer or an InGaAs / AlGaAs multi-quantum well layer. In another embodiment, the first epitaxial layer may also be a P-type GaN layer or a P-type AlGaN layer, and the second epitaxial layer may be an N-type GaN layer or an N-type AlGaN layer.

[0130] In some embodiments, the light emitting layer includes at least one quantum well layer. The thickness of the quantum well layer is between 20 nm and 40 nm, for example, 30 nm. In some embodiments, the material of the quantum well layer is GaInP / (Al x Ga 1-x )y In 1-y P, wherein x ranges from 0.5 to 0.9 and y ranges from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times greater than y. In some embodiments, the light emitting layer is a multiple quantum well (MQW).

[0131] In an embodiment of the present invention, one of the first epitaxial layer and the second epitaxial layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer. In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer. The material of the N-type cladding layer is Al x In 1-x P, wherein x ranges from 0.1 to 0.5, for example, x is 0.5. In addition, in these embodiments, the thickness of the N-type cladding layer is not greater than 350 nm, for example, the thickness of the N-type cladding layer is 320 nm. The doping concentration of the N-type cladding layer is 5e 17 cm -3 To 1e 18 cm -3 In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer formed on the doped N-type contact layer. The doped N-type contact layer is configured to bond to the bonding layer. The material of the doped N-type contact layer is GaAs. In some embodiments, the thickness of the doped N-type contact layer is 10 nm to 30 nm. In some embodiments, the doping concentration of the doped N-type contact layer is 2e 18 cm -3 To 1e 19 cm -3 In some embodiments, the N-type semiconductor layer further includes an N-type spacer layer formed on the N-type cladding layer. The material of the N-type spacer layer is (Al x Ga 1-x ) y In 1-y P, wherein x ranges from 0.5 to 0.9 and y ranges from 0.1 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times greater than y. The thickness of the N-type spacer layer is 50 nm to 75 nm, for example 65 nm. In some embodiments, the P-type semiconductor layer includes a P-type cladding layer and a doped P-type contact layer. The P-type cladding layer is formed on the light-emitting layer, and the doped P-type contact layer is formed on the P-type cladding layer.

[0132] In some embodiments, the material of the P-type cladding layer is Al x In 1-x P, wherein x is 0.3 to 0.5, for example, x is 0.5. In such an embodiment, the thickness of the P-type cladding layer is not greater than 380 nm, for example, the thickness of the P-type cladding layer is 360 nm.

[0133] In some embodiments, the material of the doped P-type contact layer is GaAs. The thickness of the doped P-type contact layer is 10 nm to 30 nm, for example, 20 nm.

[0134] In some embodiments, the P-type semiconductor layer further includes a P-type spacer layer formed under the P-type cladding layer, a first doped P-type transition layer formed on the P-type cladding layer, and a second doped P-type transition layer formed on the first doped P-type transition layer. In some embodiments, the material of the P-type spacer layer is (Al x Ga 1-x ) y In 1-y P, wherein x ranges from 0.5 to 0.9 and y ranges from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times greater than y. In some embodiments, the thickness of the P-type spacer layer is 50 nm to 70 nm, for example 65 nm.

[0135] In some embodiments, the material of the first doped P-type transition layer is (Al x Ga 1-x ) y In 1-y P, wherein x ranges from 0.1 to 0.3 and y ranges from 0.3 to 0.5. For example, x is 0.17 and y is 0.5. In some embodiments, the relationship between x and y is y is 1 to 5 times x. In some embodiments, the thickness of the first doped P-type transition layer is 20 nm to 40 nm, for example 30 nm.

[0136] In some embodiments, the material of the second doped P-type transition layer is Al x Ga 1-x As, wherein x ranges from 0.5 to 0.9, for example, x is 0.6. In some embodiments, the thickness of the second doped P-type transition layer is from 10 nm to 30 nm, for example, 20 nm.

[0137] In some embodiments, the doping concentration of the second doped P-type transition layer is greater than the doping density of the first doped P-type transition layer. The doping concentration of the doped P-type contact layer is 1 to 10 times the doping concentration of the second doped P-type transition layer.

[0138] In some embodiments, the doping concentration of the doped P-type contact layer is greater than the doping concentration of the second doped P-type transition layer. In addition, in some embodiments, the doping concentration of the second doped P-type transition layer is 2 to 4 times the doping concentration of the first doped P-type transition layer.

[0139] For example, the doping concentration of the first doped P-type transition layer is greater than 1e18 cm -3 The doping density of the second doped P-type transition layer is 2e 18 cm -3 -4e 18 cm -3 In the range of 5e 18 cm -3 .

[0140] The passivation layer 105 extends on the surface and side of the light-emitting mesa 101 facing away from the light-emitting side A. The passivation layer 105 not only reduces the current leakage at the sidewall, but also passivates the sidewall defects and prevents water, oxygen, etc. from damaging the light-emitting mesa during operation, and prevents the metal in the reflector layer, cathode, etc. in the micro-LED from diffusing to the light-emitting mesa 101 or the insulating layer where it is located. The passivation layer 105 can be formed by depositing SiO2 material using a CVD process, or by depositing Al2O3 material using an ALD process.

[0141] The passivation layer 105 has a notch 106 on the first light-emitting mesa 101, and the notch 106 penetrates the passivation layer 105 to expose the bottom transparent conductive layer 101A of the first light-emitting mesa 101. The function of the notch 106 is to enable a subsequent conductive structure such as a through-hole contact to be electrically connected to the top transparent conductive layer 101A so as to be connected to an electrode or a driving circuit, thereby enabling the first light-emitting mesa 101 to emit light. In contrast, the passivation layer 105 does not have a notch 106 on the dummy light-emitting mesa 102, so the top transparent conductive layer 101A of the dummy light-emitting mesa 102 cannot be electrically connected to an electrode or a driving circuit, so that the dummy light-emitting mesa 102 does not emit light in the finished micro light-emitting diode. The passivation layer 105 may be formed, for example, as follows: first, a material layer of the passivation layer (such as silicon dioxide or aluminum oxide) is deposited on the light-emitting mesas, wherein the material layer may completely cover the first light-emitting mesas 101, the dummy light-emitting mesas 102, and the area therebetween; then, the passivation layer of the first light-emitting mesas 101 in the light-emitting area AA is photolithographically or etched to form a notch 106, wherein the notch 106 may expose at least a portion of the bottom transparent conductive layer 101A of the first light-emitting mesas 101. The size of the notch may be, for example, 30% to 90% of the width of the top transparent conductive layer 101A.

[0142] Dumb element light table

[0143] The epitaxial wafer 100 according to the present invention further has a dummy light-emitting mesa 102, which is located in the non-light-emitting area NA and is arranged on the temporary substrate 103 or the buffer layer 104. The dummy light-emitting mesa 101 is arranged in the non-light-emitting area NA and does not emit light. Figure 1It can be seen that the side inclination angle α of the dummy light-emitting mesa 102 (see Figure 2 ) can also be, for example, 55° to 75°, especially 60° to 70°. The dummy light-emitting mesa 102 has, starting from the side facing away from the light-emitting side A, a bottom transparent conductive layer 101AA, a first epitaxial layer 101B, a light-emitting layer 101C, and a second epitaxial layer 101D in sequence. In addition, the dummy light-emitting mesa 102 also has a passivation layer 105 arranged on its lower surface and side surface facing away from the light-emitting side A.

[0144] The bottom transparent conductive layer 101AA, the first epitaxial layer 101B, the light-emitting layer 101C and the second epitaxial layer 101D of the dummy light-emitting mesa 102 are the same as the first light-emitting mesa 101, except that the passivation layer 105 on the dummy light-emitting mesa 102 does not have a notch 106, so that the top transparent conductive layer 101A of the dummy light-emitting mesa 102 is not exposed, so that in the micro light-emitting diode completed in the subsequent process, the dummy light-emitting mesa 102 does not emit light. It should be noted that although in the present embodiment, the bottom transparent conductive layer 101AA, the first epitaxial layer 101B, the light-emitting layer 101C and the second epitaxial layer 101D of the dummy light-emitting mesas 102 are the same as the first light-emitting mesas 101, in other embodiments, they may be different, for example, the depth of the dummy light-emitting mesas 102 may be different from the depth of the first light-emitting mesas 101, or the upper surface diameter of the dummy light-emitting mesas 102 may be different from the upper surface diameter of the first light-emitting mesas 101, or the lower surface diameter of the dummy light-emitting mesas 102 may be different from the lower surface diameter of the first light-emitting mesas 101, or the spacing between the dummy light-emitting mesas 102 may be different from the spacing between the first light-emitting mesas 101.

[0145] The principle on which the present invention is based is explained below.

[0146] The applicant has discovered through research that the main reason why delamination is easily caused when an insulating layer such as silicon dioxide is coated on the first light-emitting mesa 101 is that the first light-emitting mesa 101 in the light-emitting area AA has a concave-convex structure, while the non-light-emitting area NA has a planar structure. Therefore, the stress generated by the insulating layer coated in the non-light-emitting area NA is easily transmitted to the light-emitting area AA, increasing the shear stress in the light-emitting area AA, causing the insulating layer in the light-emitting area AA to delaminate, wrinkle or generate gaps. The inventors have also found that if the same dummy light-emitting mesa 102 is etched in the non-light-emitting area NA while the light-emitting mesa is etched in the light-emitting area AA, on the one hand, it is easy to do in terms of process and has low additional cost, because the etching of the dummy light-emitting mesa 102 can be achieved by simply expanding the etching range of the epitaxial wafer 100; on the other hand, the concave-convex structure of the dummy light-emitting mesa 102 in the non-light-emitting area NA can better suppress the stress in the non-light-emitting area from being transmitted to the light-emitting area, thereby reducing the risk of delamination, wrinkling, and voids in the insulating layer in the light-emitting area when the insulating layer is coated; at the same time, according to the stress formula: σ=F / A (σ is the stress per unit area, F is the external force, and A is the force area), it can be seen that by setting the dummy light-emitting mesa 102 in the non-light-emitting area NA, its concave-convex structure can increase the surface area of ​​the coated insulating layer, thereby reducing the stress per unit area, and thus also reducing the risk of delamination, wrinkling, and voids in the non-light-emitting area NA. In addition, the inventors have discovered through research that when the area occupied by the dummy light-emitting mesa 102 accounts for slightly less than 50% of the total area of ​​the epitaxial wafer or chip, that is, 40% to 50%, preferably 44% (at this time the light-emitting area accounts for 56%), the best anti-delamination, wrinkling, and gap generation effects can be achieved.

[0147] Cutting Road

[0148] The epitaxial wafer 100 according to the present invention may optionally have a cutting path 107, which is arranged in the non-luminous area AA, especially between adjacent dummy light-emitting mesas 102. The cutting path 107 is used to separate adjacent light-emitting diode chips. Preferably, the cutting path is formed after the entire structure of the micro-light-emitting diode has been formed on the epitaxial wafer 100. The width of the cutting path may be, for example, 60 to 100 μm, and the depth may be, for example, 100 to 300 μm. In order to separate the chips, the cutting path may be cut by, for example, grinding wheel cutting, laser cutting, invisible cutting, etc. In order to form the cutting path, the method may include, for example, mechanical cutting, laser cutting, photolithography, etching, etc.

[0149] Figure 3 FIG. 1 is a schematic diagram showing a second embodiment of an epitaxial wafer 100 having a dummy light-emitting mesa according to the present invention.

[0150] Figure 3 The epitaxial wafer 100 in the second embodiment is Figure 1The first embodiment of the present invention is basically the same as the first embodiment in the present invention, and the main difference is that in the second embodiment, the second epitaxial layer 101D only includes a step portion but does not include a base portion, that is, the second epitaxial layer 101D is completely located within the inverted trapezoidal structure of the light-emitting mesa 101. In this embodiment, the epitaxial layer 101D of the first light-emitting mesa 101 and the dummy light-emitting mesa 102 have the same structure, that is, they do not include a base portion, that is, they are completely located within the inverted trapezoidal structure of the light-emitting mesa 101. Here, the second epitaxial layers 101D of adjacent light-emitting mesas are disconnected from each other and are not connected together. Such a light-emitting mesa structure allows a thinner light-emitting mesa thickness.

[0151] Figure 4 FIG. 1 is a schematic diagram showing a third embodiment of an epitaxial wafer 100 having a dummy light-emitting mesa according to the present invention.

[0152] Figure 4 The epitaxial wafer 100 of the third embodiment and Figure 3 The third embodiment is basically the same as the second embodiment, and the main difference is that, in the third embodiment, the depth of the dummy light-emitting mesas 102 is different from the depth of the first light-emitting mesas 101, the upper surface diameter of the dummy light-emitting mesas 102 is different from the upper surface diameter of the first light-emitting mesas 101, or the lower surface diameter of the dummy light-emitting mesas 102 is different from the lower surface diameter of the first light-emitting mesas 101, and the spacing between the dummy light-emitting mesas 102 is also different from the spacing between the first light-emitting mesas 101.

[0153] For example, the depth of the dummy light-emitting mesa 102 may be 50% to 150% of the depth of the first light-emitting mesa 101. In this embodiment, the depth of the dummy light-emitting mesa 102 is less than the depth of the first light-emitting mesa 101, but in other embodiments, the depth of the dummy light-emitting mesa 102 may also be greater than the depth of the first light-emitting mesa 101.

[0154] For example, the upper surface diameter of the dummy light-emitting mesa 102 may be 50% to 150% of the upper surface diameter of the first light-emitting mesa 101. In this embodiment, the upper surface diameter of the dummy light-emitting mesa 102 is smaller than the upper surface diameter of the first light-emitting mesa 101, but in other embodiments, the upper surface diameter of the dummy light-emitting mesa 102 may also be larger than the upper surface diameter of the first light-emitting mesa 101.

[0155] For example, the diameter of the lower surface of the dummy light-emitting mesa 102 may be 50% to 150% of the diameter of the lower surface of the first light-emitting mesa 101. In this embodiment, the diameter of the lower surface of the dummy light-emitting mesa 102 is smaller than the diameter of the lower surface of the first light-emitting mesa 101, but in other embodiments, the diameter of the lower surface of the dummy light-emitting mesa 102 may also be larger than the diameter of the lower surface of the first light-emitting mesa 101.

[0156] For example, the spacing between the dummy light-emitting mesas 102 may be 50% to 150% of the spacing between the first light-emitting mesas 101. In this embodiment, the spacing between the dummy light-emitting mesas 102 is smaller than the spacing between the first light-emitting mesas 101, but in other embodiments, the spacing between the dummy light-emitting mesas 102 may also be larger than the spacing between the first light-emitting mesas 101.

[0157] Compared with the first light-emitting mesa 101, the dummy light-emitting mesa 102 has a smaller depth, a smaller lower surface diameter, a smaller upper surface diameter or a larger spacing, which can reduce the process cost of forming the dummy light-emitting mesa 102, or reduce the area occupied by the dummy light-emitting mesa 102, or reduce the chip thickness at the dummy light-emitting mesa 102. Compared with the first light-emitting mesa 101, the dummy light-emitting mesa 102 has a larger depth, a larger lower surface diameter, a larger upper surface diameter or a smaller spacing, which can increase the area occupied by the dummy light-emitting mesa 102, thereby increasing the effect of stress removal. According to the needs of specific application occasions, the appropriate size and spacing of the dummy light-emitting mesa 101 can be selected.

[0158] Figure 5 Schematic diagram of a micro-LED chip 600 according to the present invention is shown. In this embodiment, the first light-emitting mesa or epitaxial layer of the micro-LED chip 600 has an inverted trapezoidal structure, that is, the first light-emitting mesa is a structure with a large upper surface and a small lower surface. The micro-LED chip 600 includes a light-emitting area AA and a non-light-emitting area NA, wherein the first light-emitting mesa 101 is arranged in the light-emitting area AA, and a dummy first light-emitting mesa 602 is arranged in the non-light-emitting area NA. The first light-emitting mesa is configured to emit light, while the dummy first light-emitting mesa 602 does not emit light.

[0159] The various components of the micro-LED chip 600 are described in detail below.

[0160] like Figure 5 As shown, the micro-LED chip 600 according to the present invention includes an upper stack 600A and a lower stack 600B, wherein the upper stack 600A and the upper stack 600B are hybrid-bonded at an interface A to form a complete micro-LED chip 600. It should be noted that the structure of the upper and lower stacks is merely exemplary, and in other embodiments, micro-LED chips of other structures may also be used. The structure of the upper stack 600A and the lower stack 600B and their components are described in detail below.

[0161] Upper layer

[0162] The upper stack 600A includes a first insulating layer 611A, a first light emitting mesa 101, a dummy light emitting mesa 102, a transparent conductive layer 608, a first electrode 604 (cathode), a first via contact 602, a second electrode 610 (anode), a first bonding mark 609A, and a microlens 605. Each component is described below.

[0163] A first insulating layer 611A, which is configured to accommodate at least a portion of the first light-emitting mesa 101 and provide electrical insulation therefor. Here, the first electrical insulating layer 611A has a recess 607, which is configured to accommodate the light-emitting layer and the second epitaxial layer of the first light-emitting mesa 101 and the subsidiary structure of the first light-emitting mesa 101. For a detailed description of the first light-emitting mesa 101 and its subsidiary structure (such as the passivation layer 612, the reflector layer 615, etc.), reference can be made to the first light-emitting mesa 101 and its description. Here, it should be noted that the recess 607 can be formed after the first light-emitting mesa 101, that is, the first light-emitting mesa 101 and its subsidiary structure are first formed on the temporary substrate, and then the first insulating layer 611A surrounding them is formed on the first light-emitting mesa 101 and its subsidiary structure. The material of the first insulating layer 611A can be, for example, silicon dioxide, silicon nitride, a high dielectric constant material (such as hafnium oxide, aluminum oxide, etc.), etc. The first insulating layer 611A can be formed by thermal oxidation, chemical vapor deposition (CVD), etc. The thickness of the first insulating layer 611A is, for example, 1 to 3 μm, preferably 2 μm, and more preferably 0.6 to 1.4 μm. In addition, the first insulating layer 611A may be planarized at the interface A (eg, by chemical mechanical polishing (CMP)) to promote hybrid bonding with the second insulating layer 611B.

[0164] The first insulating layer 611A is transparent to the light emitted from the first light emitting mesa 101. In some embodiments, the first insulating layer 611A is made of a dielectric material such as a solid inorganic material or a plastic material. In some embodiments, the solid inorganic material includes silicon dioxide (SiO2), aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon carbonitride (SiCN), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), magnesium oxide (MgO), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), or any combination thereof. In some embodiments, the plastic material includes a polymer such as SU-8, Permi Nex, benzocyclobutene (BCB), or a transparent plastic (resin) including spin-on glass (SOG), or an adhesive microresist BCL-1200, or any combination thereof. In some embodiments, the first insulating layer 611A can facilitate the passage of light emitted from the first light-emitting mesa 101. In some embodiments, the first insulating layer 611A can include multiple parts, such as three embedded dielectric parts and two bonding dielectric parts. The embedded dielectric part refers to the dielectric layer surrounding each light-emitting diode structure; and the bonding dielectric part refers to the dielectric layer between two light-emitting diode structures. The embedded dielectric part and the bonding dielectric part may have the same or different compositions.

[0165] Here, due to the presence of the dummy light-emitting mesa 102, the stress, especially the shear stress, of the first insulating layer 611A is significantly reduced, so that the probability of delamination, wrinkling, and gaps between the first insulating layer 611A and the light-emitting mesa is significantly reduced, thereby improving the chip quality of the micro light-emitting diode 600 and reducing the risk of failure.

[0166] A first light-emitting mesa 101, which is configured to emit light, wherein the area of ​​the top surface (i.e., the upper surface) of the first light-emitting mesa 01 is greater than the area of ​​the bottom surface (i.e., the lower surface) of the first light-emitting mesa, and is in an "inverted trapezoidal" shape. The inclination angle of the first light-emitting mesa 101 can be, for example, 10° to 85°, preferably 30° to 70°, and especially 35° to 50°. The first light-emitting mesa 101 includes a first epitaxial layer 101A, a light-emitting layer 101B, and a second epitaxial layer 101C, wherein the first epitaxial layer 101A is arranged on the top or upper surface of the first light-emitting mesa, that is, on the side facing the light-emitting surface, the light-emitting layer 101B is arranged in the recess 607 and arranged between the first epitaxial layer 101A and the second epitaxial layer 101C, and the second epitaxial layer 101C is arranged on the bottom or lower surface of the first light-emitting mesa 101, that is, on the side facing the driving backplane 606. The light-emitting layer 101B, for example, includes a multi-quantum well layer and an electron blocking layer. In one embodiment of the present invention, the first epitaxial layer 101A is an N-type GaN layer or an N-type Al GaN layer, and the second epitaxial layer 101C is a P-type GaN layer or a P-type Al GaN layer, that is, the material of the second epitaxial layer 101C can be a material layer of the second conductivity type including two or more elements of Ga, N, As, Al, In, and P, and the first epitaxial layer 101A can be a material layer of the first conductivity type including two or more elements of Ga, N, As, Al, In, and P. The multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / Al GaN multi-quantum well layer or an InGaAs / Al GaAs multi-quantum well layer. The electron blocking side is arranged on the first side of the light-emitting layer, and the first side refers to the side along which the electrons migrate out of the light-emitting layer. In another embodiment of the present invention, the first epitaxial layer can also be a P-type GaN layer or a P-type Al GaN layer, and the second epitaxial layer can be an N-type GaN layer or an N-type Al GaN layer. The top width of the first light-emitting mesa 101 is, for example, 0.5 to 3 μm, preferably 1.0 to 2.0 μm. The thickness of the first epitaxial layer 101A is, for example, 4000 to 5000 angstroms, the thickness of the light-emitting layer 101B is, for example, 2000 to 4000 angstroms, and the thickness of the second epitaxial layer 101C is, for example, 2500 to 3500 angstroms. 1 angstrom = 10^(-10) meters. Figure 3It can be seen that the first epitaxial layer 101A is located outside the recess 607, while the light-emitting layer 101B and the second epitaxial layer 101C are located inside the recess 607. In this way, the surface area of ​​the first epitaxial layer 101A is not limited by the opening area of ​​the recess 607, but can be significantly larger than the opening area of ​​the recess 607, thereby significantly increasing the area and thickness of the first epitaxial layer 101A; in addition, since the recess 607 only needs to accommodate the light-emitting layer 101B and the second epitaxial layer 101C, these two layers have a larger area and thickness compared with the structure of the prior art that needs to accommodate three layers, thereby better increasing the area and thickness of the epitaxial layer 101 and improving the light emission. It can also be seen here that the first epitaxial layer 101A passes through the first electrode 604 (here, the cathode) from below, so that the first epitaxial layers 101A of adjacent first light-emitting mesas 101 can be connected to each other, so that in the case of a common cathode structure (i.e., the first epitaxial layers of all micro-light-emitting diodes in the same array are connected to a common cathode), the conductivity between the cathode 604 and the first epitaxial layer 101A can be significantly enhanced compared to the case where the cathode 604 is connected only by the transparent conductive layer 608 covering it, thereby increasing its power supply. In addition, the contact cross section between the first epitaxial layer 101A and the cathode 604 at the edge is partially flat and partially inclined. Compared with the vertical surface, the inclined surface increases the contact area between the first epitaxial layer 101A and the cathode 604, thereby increasing the conductivity.

[0167] The first light-emitting mesa 101 further includes auxiliary structures such as passivation layers 612 and 613, a reflector layer 615, a bottom transparent conductive layer 618, etc. The passivation layer 612 is disposed between the first light-emitting mesa 101 and the reflector layer 615, and optionally extends on the upper surface of the first insulating layer 611A, while the passivation layer 613 is disposed between the inner wall of the recess 607 and the reflector layer 615, and optionally extends on the upper surface of the first insulating layer 611A. In another embodiment, only one of the passivation layers 612 and 613 extends on the upper surface of the first insulating layer 611A, or both do not extend on the upper surface of the first insulating layer 611A, instead, they only extend to the upper surface of the first insulating layer 611A, and the upper surface of the first insulating layer 611A is covered by another insulating layer or a dielectric layer. The passivation layers 612 and 613 not only reduce the current leakage at the sidewall, but also passivate the sidewall defects, prevent water, oxygen, etc. from damaging the first light-emitting mesa during operation, and prevent the metal in the reflector layer 615, cathode 604, etc. from diffusing into the first insulating layer 611 or the first light-emitting mesa 101. The passivation layers 612 and 613 can be formed by depositing SiO2 material using a CVD process, or by depositing Al2O3 material using an ALD process. The bottom transparent conductive layer 618 is arranged between the second epitaxial layer 101C and the reflector layer 615. The bottom transparent conductive layer 618 is configured to electrically connect the second epitaxial layer 101C of the first light-emitting mesa 101 to the reflector layer 615 and then to the through-hole contact 602. The material of the bottom transparent conductive layer 618 is, for example, metal oxide, such as indium tin oxide ITO, zinc oxide ZnO, etc., and its formation method includes, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), sol-gel method, solution coating method, etc.

[0168] The reflector layer 615 is configured to reflect upward the light from the first light emitting mesa 101. To this end, the reflector layer 615 has an inclined surface on the side facing the first light emitting mesa 101, and its inclination angle is, for example, the same as the inclination angle of the first light emitting mesa, which is 10° to 85°, preferably 30° to 70°, and especially 35° to 50°.

[0169] Here, the reflector layer 615 includes a side reflector layer 615A, a bottom reflector layer 615B, and an edge portion 615C, wherein the side reflector layer 615A and the bottom reflector layer 615B constitute the main body of the reflector layer 615. The side reflector layer 615A covers at least a portion of the side surface of the first light-emitting mesa 101. Both the side reflector layer 615A and the bottom reflector layer 615B are configured to reflect light from the first light-emitting mesa 101 upward, and the bottom reflector layer 615B is also configured to electrically connect the bottom transparent conductive layer 618 to the first through-hole contact portion 602. In this embodiment, the side reflector layer 615 covers the side surface of the first light-emitting mesa 101 in the recess 607, and the side reflector layer 615 is formed between the passivation layer 612 and the inner wall of the recess 607 of the insulating layer. Due to the presence of the passivation layer 612, the side reflector 615 may or may not have an atomic layer deposition layer on the side facing the first light-emitting mesa 101. In the case of having an atomic layer deposition layer, the metal in the reflector layer 615 can be further prevented from penetrating into the first light-emitting mesa 101 through the passivation layer 612. The side reflector layer 615A has an inclined surface on the side facing the first light-emitting mesa 101 to reflect the light from the first light-emitting mesa upward, and its inclination angle is, for example, the same as the inclination angle of the first light-emitting mesa 101, which is 10° to 85°, preferably 30° to 70°, and especially 35° to 50°. The bottom reflector layer 615B covers at least a portion of the bottom surface of the first light-emitting mesa 101. In this embodiment, the bottom reflector 615B covers the bottom transparent conductive layer 618 of the first light-emitting mesa 101. The bottom reflector layer 615B has an atomic layer deposition layer on the side facing the first light-emitting mesa 101. The atomic layer deposition layer is able to block the metal from the reflective metal layer to prevent its diffusion without substantially affecting the reflection of light.

[0170] See also Figure 6 The reflector layer 200 includes an atomic layer deposition layer 201, a reflective metal layer 202, a first barrier layer 203, and a second barrier layer 204 from top to bottom (i.e., from facing the first light-emitting mesa 101 to facing away from the first light-emitting mesa 101), wherein the upper side of the reflector layer 200 faces the first light-emitting mesa or epitaxial layer of the micro-light-emitting diode, and the lower side of the reflector layer 200 faces away from the first light-emitting mesa or epitaxial layer of the micro-light-emitting diode or faces the bottom transparent conductive layer.

[0171] For example, the stacked structure of the reflector layer 615 is as follows (in order from close to the first light-emitting mesa to far away from the first light-emitting mesa):

[0172] Atomic layer deposition layer 201, made of nickel, with a thickness of 5 angstroms;

[0173] The reflective metal layer 202 is made of silver and has a thickness of 1000 angstroms;

[0174] The first and second barrier layers 203A and 203B are made of titanium and platinum, respectively, and have thicknesses of 200 and 500 angstroms, respectively;

[0175] The second barrier layer 204 is made of titanium and has a thickness of 200 angstroms.

[0176] In addition, the number of layers of the first barrier layer 203 is three.

[0177] The reflector layer 615 can be formed, for example, by evaporation, sputtering, chemical vapor deposition (CVD), etc., wherein the atomic layer deposition layer 201 of the reflector layer 615 is formed by atomic layer deposition. The thickness of the passivation layer 612 between the reflector layer 612 and the first light-emitting mesa 101 is 800 to 2000 angstroms, preferably 6000 to 1600 angstroms. The thickness of the passivation layer 613 between the reflector layer 615 and the inner wall of the recess 607 is 200 to 800 angstroms, preferably 300 to 600 angstroms.

[0178] like Figure 5 As shown, the passivation layer 612 of the first light-emitting mesa 101 has a notch 620 on one side of the bottom transparent conductive layer 618 , so that the bottom transparent conductive layer 618 can be electrically connected to the first through-hole contact portion 602 through the reflector layer 615 , thereby electrically connecting the second epitaxial layer 601C to the driving circuit 606 .

[0179] A dummy light-emitting mesa 102, which is arranged in the non-light-emitting area NA and does not emit light. Figure 5 As shown, the structure of the dummy light-emitting mesa 102 is basically the same as that of the first light-emitting mesa 101, that is, it also has a first epitaxial layer 601A, a light-emitting layer 601B, a second epitaxial layer 601C, a bottom transparent conductive layer 618 and a passivation layer 612 starting from the light-emitting side. The difference between the structure of the dummy light-emitting mesa 102 and the first light-emitting mesa 101 is that the passivation layer 612 of the dummy light-emitting mesa 102 does not have a notch 620 on one side of the bottom transparent conductive layer 618, so that the second epitaxial layer 601C of the dummy light-emitting mesa 102 cannot be electrically connected to the outside, and therefore cannot emit light. In this embodiment, the dummy light-emitting mesa 102 has the same size as the first light-emitting mesa 101, but in other embodiments, the dummy light-emitting mesa 102 has a different size from the first light-emitting mesa 101, such as a different mesa height and / or a different upper surface diameter and / or a different lower surface diameter and / or a different spacing.

[0180] In addition, the dummy light-emitting mesa 102 is not provided with a reflector layer 615 or a first through-hole contact portion 602 on the side facing away from the light-emitting side. Moreover, no microlens 605 is provided above the dummy light-emitting mesa 102. Since the dummy light-emitting mesa 102 does not need to emit light, structures such as the reflector layer 615, the first through-hole contact portion 602, and the microlens 605 can be omitted. In other embodiments, in order to simplify the process or reduce the cost, one or more of the reflector layer 615, the first through-hole contact portion 602, and the microlens 605 can also be provided for the dummy light-emitting mesa 102. In addition, although the first electrode 604 is provided for the dummy light-emitting mesa 102 in the present embodiment, the first electrode 604 may not be provided for the dummy light-emitting mesa 102 in other embodiments.

[0181] Here, although the dummy light-emitting mesa 102 does not emit light, the stress, especially the shear stress, of the first insulating layer 611A is significantly reduced due to the presence of the dummy light-emitting mesa 102, so that the probability of delamination, wrinkling, and gaps between the first insulating layer 611A and the light-emitting mesa is significantly reduced, thereby improving the chip quality of the micro-light-emitting diode 600 and reducing the risk of failure. This is mainly because the concave-convex structure of the dummy light-emitting mesa 102 can prevent the stress in the non-light-emitting area NA from being transmitted to the light-emitting area AA, and at the same time, the concave-convex structure of the dummy light-emitting mesa in the non-light-emitting area increases the force-bearing area, thereby reducing the stress in the non-light-emitting area, thereby reducing the risk of delamination, wrinkling, and gaps in the insulating layer in both the light-emitting area and the non-light-emitting area.

[0182] A top transparent conductive layer 608, which is arranged on the first epitaxial layer 101A and electrically connects the first electrode 604 (cathode) to the first epitaxial layer 101A. Here, the top transparent conductive layer 608 extends on the first epitaxial layer 101A and completely covers the first epitaxial layer 101A, thereby providing a more uniform power supply for the first epitaxial layer 101A. In other embodiments, the top transparent conductive layer 608 may also only partially cover the first epitaxial layer 101A. In addition, the top transparent conductive layer 608 also extends under the first electrode 604, which is the cathode in this case, so that the transparent conductive layer 608 extends continuously on the first epitaxial layer 101A adjacent to the first light-emitting mesa 101A, thereby increasing the coverage area of ​​the first epitaxial layer 101A. The material of the top transparent conductive layer 608 is, for example, a metal oxide, such as indium tin oxide ITO, zinc oxide ZnO, etc., and its formation method includes, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), sol-gel method, solution coating method, etc.

[0183] The first electrode 604, here a cathode, is arranged to surround the first light-emitting mesa 604. The cathode 604 and its connecting parts can be made of materials such as metal (such as copper, silver or aluminum), graphene, ITO, aluminum-doped zinc oxide (AZO) or fluorine-doped tin oxide (FTO) or any combination of the above materials. In another embodiment of the present invention, the cathode 604 and its connecting parts can be made of non-transparent or transparent conductive materials, such as indium tin oxide (ITO). In a preferred embodiment, the cathode 604 is made of a reflective metal (such as copper, silver or aluminum), so that the cathode 604 can reflect light from the first light-emitting mesa 101 while optically isolating adjacent light-emitting mesas 101 from each other, for example, reflecting the light upward to the microlens 605, thereby increasing the light output. In another embodiment, a reflective layer, such as a silver layer, can be coated on the surface of the cathode 604 to provide a reflective capability. Here, the surface of the cathode 604 facing the first light-emitting mesa 101A is an inclined surface, and is inclined toward both sides (i.e., inclined toward both sides starting from the bottom surface), so that the light falling thereon can be reflected upward, i.e., toward the light-emitting side. In addition, the cathode 604 can be divided into an edge cathode 604A and a middle cathode 604B, wherein the edge cathode 604A is arranged between the second electrode 610 (here, the anode) and the first light-emitting mesa 101 at the edge, wherein a part of the edge cathode 604A is arranged on the passivation layer 612, and another part is arranged on the transparent conductive layer 608, and the middle cathode 604B is arranged between adjacent first light-emitting mesas 101, wherein the middle cathode 604B is arranged on the transparent conductive layer 608. In this way, the edge cathode 604A can completely cover the side of the first epitaxial layer 101A and be in electrical contact with it, thereby increasing the electrical contact area between the cathode 604 and the first epitaxial layer 101A.

[0184] A first through-hole contact 602, which is electrically connected to the bottom of the first light-emitting mesa 101 and passes through the first insulating layer 611A. The first through-hole contact 602 is used for hybrid bonding with the second through-hole contact 603, and thereby electrically connects the bottom of the first light-emitting mesa 101, especially the second epitaxial layer 101C, to the second electrode 610 (here, the anode). In this embodiment, no first through-hole contact 602 is provided below the dummy light-emitting mesa 102. The first through-hole contact 602 is preferably a cylindrical through-hole, and the inner wall and / or the middle space are filled with a conductor, such as metal copper. The diameter of the first through-hole contact 602 is 0.3 to 2 μm, preferably 0.6 to 1.4 μm. The first through-hole contact 602 can be planarized at the interface A (for example, by chemical mechanical polishing CMP) to facilitate hybrid bonding with the second through-hole contact 603. In addition, in order to promote the bonding strength between the first through-hole contact 602 and the second through-hole contact 603 and improve the conductivity, a first interface metal layer may be arranged at the first opening of the first through-hole contact 602, and the area of ​​the first interface metal layer is larger than the area of ​​the first opening. Similarly, a second interface metal layer may be arranged at the second opening of the second through-hole contact, and the area of ​​the second interface metal layer is larger than the area of ​​the second opening. The areas of the first interface metal layer and the second interface metal layer may be equal, or the area of ​​the first interface metal layer may be larger than or smaller than the area of ​​the second interface metal layer. When the first interface metal layer and the second interface metal layer are bonded to each other, the bonding surface formed is larger than the bonding surface formed by directly bonding the first opening of the first through-hole contact 602 and the second opening 204 of the second through-hole contact 603, thereby increasing the bonding strength and improving the conductivity between the first through-hole contact 602 and the second through-hole contact 603. The first interface metal layer 201 and the second interface metal layer 202 are made of, for example, a conductive metal, such as copper. The formation method thereof may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, chemical plating, etc. The formation method of the first through-hole contact portion 603 may be, for example, as follows: forming the first light-emitting mesa 101 and the first insulating layer 611A on a temporary substrate, then etching the first insulating layer 611A to form a through hole leading to the bottom of the first light-emitting mesa 101, then depositing metal in the through hole, and finally planarizing the opening of the through hole to form a bonding surface.

[0185] In addition, the first through-hole contact 602 is used to electrically connect the driving circuit 606 to the bottom (here, the reflector layer 607) of the epitaxial layer 101 (or the first light-emitting mesa) of the micro-LED array after bonding with the second through-hole contact 603, thereby connecting the epitaxial layer 101 to the anode 610. Here, a first metal barrier layer 617 is provided between the through-hole contact 602 and the reflector layer 607. The first metal barrier layer 617 can prevent the metal in the first through-hole contact 602 from diffusing into the epitaxial layer 101 or the insulating layer 611A or preventing it from being oxidized through the reflector layer 607 and other layers that may be arranged therebetween (e.g., the bottom transparent electrode layer). If the metal in the first through-hole contact 602 diffuses into the epitaxial layer 101, the light-emitting performance of the epitaxial layer 101 will be affected; if it diffuses into the insulating layer 611A, it will affect the insulating effect of the insulating layer 611A, thereby causing leakage current or even short circuit; if the metal in the through-hole contact 602 is oxidized, it may cause poor contact between the first through-hole contact 602 and the reflector layer 607, or even cause the electrical circuit to the epitaxial layer 101 to be broken. It can be seen that by providing the first through-hole contact 602 according to the present invention, the diffusion of the metal in the first through-hole contact 602 can be better avoided, thereby effectively preventing the risks of reduced light-emitting performance, short circuit, and open circuit of the micro-LED. The combination of the first metal barrier layer 617 and the first and second barrier layers 203 and 204 of the reflector layer can further enhance the metal barrier and anti-oxidation effects.

[0186] The second electrode 610, which is an anode in this case, is electrically connected to the driving backplane 606 through a third through-hole contact 614 that passes through the first insulating layer 611A and the second insulating layer 611B. The anode 610 can be connected to an external power source or a control source, for example, to power or control the micro-LED chip 600. Here, the third through-hole contact 614 can include a plurality of through-hole contacts, so as to connect the second epitaxial layer 101C of the plurality of first light-emitting mesas to the anode 610. Here, it is exemplarily shown that the third through-hole contact 614 includes two through-hole contacts, but this is merely exemplary, and other numbers of through-hole contacts 614 are also conceivable. The third through-hole contact 614 can be formed either before or after hybrid bonding. If the third through-hole contact 614 is formed before hybrid bonding, the upper and lower parts of the third through-hole contact 614 are first formed in the upper stack 600A and the lower stack 600B, respectively, and then the through-hole contacts on both sides are connected after hybrid bonding, and then the first insulating layer 611A is etched from above to form the anode 610 on the third through-hole contact 614. If the third through-hole contact 614 is formed after hybrid bonding, the first insulating layer 611A is etched from above to form a through hole leading to the driving backplane 606, and then metal is deposited in the through hole, and then the third through-hole contact 614 is etched to form a recess, and then metal is deposited in the recess to form the anode 610. The anode 610 and its connecting parts can be made of materials such as metal (such as copper, silver or aluminum), graphene, ITO, aluminum-doped zinc oxide (AZO) or fluorine-doped tin oxide (FTO) or any combination of the above materials.

[0187] · A first bonding mark 609A, which is disposed in the first insulating layer 611A and exposes a first mark surface, i.e., an opening of the first bonding mark. The first bonding mark 609A in the upper stack 600A serves as a mark for alignment with the second bonding mark 609B in the lower stack 600B, thereby achieving precise hybrid bonding, wherein the second bonding mark 609B is disposed in the second insulating layer 600B and exposes a second mark surface, i.e., an opening of the second bonding mark. The first bonding mark 609A and the second bonding mark 609B are aligned in such a way that, during hybrid bonding, the first mark surface is aligned and attached to the second mark surface, at which point the upper stack 600A and the lower stack 600B are aligned, and then hybrid bonding can be performed. The first bonding mark 609A and the second bonding mark 609B can be metal vias, and the two can be bonded at the interface. In addition, the first bonding mark 609A and the second bonding mark 609B may have enlarged openings and / or the openings may be coated with a metal layer to facilitate identification of their positions and increase bonding strength.

[0188] A microlens 605 is disposed above the first light-emitting mesa 101 to shape the light emitted therefrom, such as converging or collimating. In this embodiment, no microlens 605 is disposed above the dummy light-emitting mesa 102. The microlens includes a lens portion 605A and a spacer 605B. The lens portion 605A is disposed at the outermost side, i.e., the uppermost side, and is configured to shape the light from the first light-emitting mesa 101. The spacer 605B is disposed between the lens portion 605A and the first light-emitting mesa 101 to adjust the focal position of the lens portion 605A, for example, by adjusting the thickness of the spacer 605B and the curvature of the lens portion 605A and other parameters so that the focal point of the lens portion 605A is exactly located in the first light-emitting mesa 101 of the micro-LED. The width of the microlens 605 is, for example, 0.8 to 4 μm, preferably 1 to 3 μm. The distance between the lens portion 605A and the cathode 604 is, for example, 0.05 to 4 μm, preferably 0.1 to 0.3 μm. The microlenses 605 correspond to the first light-emitting mesas 101 one by one. At the same time, in this embodiment, there is a gap between adjacent microlenses 605 and their bottoms are connected to each other. The bottom of the gap is higher than the top of the first light-emitting mesas 101, or higher than the bottom of the light-emitting layer 101B of the first light-emitting mesas 101, and the lens portion 604A is located above the cathode 604. The microlenses 605 can be formed by multiple depositions. In the process of forming the microlenses, a SiO2 film layer needs to be deposited first, and then ion etching is performed. The microlenses are formed on the surface of the transparent conductive layer 608 at positions corresponding to each first light-emitting mesa 101.

[0189] Lower stack

[0190] The lower stack 600B includes a second insulating layer 611B, a second through-hole contact 603, a driving back plate 606, and a second bonding mark 609B. Each component is described below.

[0191] A second insulating layer 611B is arranged on the driving backplate 606 and is configured to accommodate the second through-hole contact 603. The material of the second insulating layer 611B can be, for example, silicon dioxide, silicon nitride, a high dielectric constant material (such as hafnium oxide, aluminum oxide, etc.), etc. The second insulating layer 611B can be formed on the driving backplate 606 by, for example, thermal oxidation, chemical vapor deposition (CVD), etc. The thickness of the second insulating layer 611B is, for example, 1 to 3 μm, preferably 2 μm, and more preferably 0.6 to 1.4 μm. In addition, the second insulating layer 611B can be planarized at the interface A (for example, by chemical mechanical polishing CMP) to promote hybrid bonding with the first insulating layer 611A.

[0192] The second insulating layer 611B may be transparent to the light emitted from the first light emitting mesa 101. In some embodiments, the second insulating layer 611B is made of a dielectric material such as a solid inorganic material or a plastic material. In some embodiments, the solid inorganic material includes silicon dioxide (SiO2), aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon carbonitride (SiCN), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), magnesium oxide (MgO), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), or any combination thereof. In some embodiments, the plastic material includes a polymer such as SU-8, PermiNex, benzocyclobutene (BCB), or a transparent plastic (resin) including spin-on glass (SOG), or an adhesive microresist BCL-1200, or any combination thereof. In some embodiments, the second insulating layer 611B can facilitate the passage of light emitted from the first light-emitting mesa 101. In some embodiments, the second insulating layer 611B may include multiple parts, such as three embedded dielectric parts and two bonding dielectric parts. The embedded dielectric part refers to the dielectric layer surrounding each light-emitting diode structure; and the bonding dielectric part refers to the dielectric layer between two light-emitting diode structures. The embedded dielectric part and the bonding dielectric part may have the same or different compositions.

[0193] A second via contact 603, which passes through the second insulating layer 611B. The second via contact 603 is configured to be hybrid bonded with the first via contact 602 at the interface A, and thereby electrically connects the bottom of the first light-emitting mesa 101, especially the second epitaxial layer 101C, to the second electrode 610 (here, the anode). The second via contact 603 is preferably a cylindrical through-hole, and the inner wall and / or the intermediate space are filled with a conductor, such as metal copper. The diameter of the second via contact 603 is 0.5 to 2.2 μm, preferably 0.8 to 1.6 μm. The second via contact 603 can be planarized at the interface A (for example, by chemical mechanical polishing CMP) to promote hybrid bonding with the first via contact 602. In addition, in order to promote the bonding strength between the second via contact 603 and the first via contact 602 and improve the conductivity, a second interface metal layer can be arranged at the second opening of the second via contact 603, and the area of ​​the second interface metal layer is larger than the area of ​​the second opening. Similarly, a first interface metal layer may be arranged at the first opening of the first through-hole contact 602, and the area of ​​the first interface metal layer is larger than the area of ​​the first opening. The areas of the first interface metal layer and the second interface metal layer may be equal, or the area of ​​the first interface metal layer may be larger than or smaller than the area of ​​the second interface metal layer. After the first interface metal layer and the second interface metal layer are bonded to each other, the bonding surface formed is larger than the bonding surface formed by directly bonding the first opening of the first through-hole contact 602 and the second opening of the second through-hole contact 603, thereby increasing the bonding strength and improving the conductivity between the first through-hole contact 602 and the second through-hole contact 603. The first interface metal layer and the second interface metal layer are, for example, made of a conductive metal, such as copper. The formation method thereof may, for example, include physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, chemical plating, and the like. The second through hole contact portion 603 may be formed, for example, as follows: providing a driving backplane 606, then forming a second insulating layer 611B on the driving backplane 606, then etching the second insulating layer 611B to form a through hole leading to the top of the driving backplane 606, then depositing metal in the through hole, and finally flattening the opening of the through hole to form a bonding surface.

[0194] In addition, the second through-hole contact 603 is used to electrically connect the driving circuit 606 to the bottom (here, the reflector layer 607) of the epitaxial layer 101 (or the first light-emitting mesa) of the micro-LED array after bonding with the first through-hole contact 603, thereby connecting the epitaxial layer 101 to the anode 610. Here, a first metal barrier layer 617 is provided between the second through-hole contact 603 and the driving circuit 607. The first metal barrier layer 617 can prevent the metal in the second through-hole contact 603 from diffusing into the driving circuit 606 or the insulating layer 611B or preventing it from being oxidized. If the metal in the second through-hole contact 602 diffuses into the driving circuit 606, the electrical performance of the driving circuit will be affected, such as a short circuit; if it diffuses into the insulating layer 611B, it will affect the insulating effect of the insulating layer 611B, thereby causing leakage current or even a short circuit; if the metal in the second through-hole contact 603 is oxidized, it may cause poor contact between the second through-hole contact 603 and the driving circuit 606, or even cause the electrical line to the driving circuit 606 to be broken. It can be seen that by providing the second through-hole contact 603 according to the present invention, the diffusion of the metal in the second through-hole contact 603 can be better avoided, thereby effectively preventing the risks of short circuit, open circuit, etc. of the driving circuit 606. The combination of the first metal barrier layer 617 and the first and second barrier layers 203 and 204 of the reflector layer can further enhance the metal barrier and anti-oxidation effects.

[0195] A driving backplane 606 (or a driving circuit), which is electrically connected to the second through-hole contact 603 so as to electrically connect the second epitaxial layer 101C of the first light-emitting mesa 101 to the anode 610. To this end, the driving backplane 606 has a conductive circuit layer for interconnecting each second through-hole contact 603 to the corresponding anode 610. The driving backplane 606 can be, for example, a thin film transistor TFT driving circuit, and can include a 2T1C driving circuit, a 3T1C driving circuit, and a 5T2C driving circuit. The driving backplane 606 is configured to drive the micro light-emitting diode, for example, to control the connection, disconnection and brightness of the micro light-emitting diode. The driving backplane 606 can include, for example, transistors, capacitors, a conductive circuit layer, an insulating layer, and a metal layer. The conductive circuit layer is formed on the substrate and is configured to supply power to the micro light-emitting diode array. The insulating layer is formed on the conductive circuit layer, wherein the insulating layer is provided with a through hole, and the through hole is provided with a through hole contact (for example, an IC copper column) for electrically connecting the conductive circuit layer to the micro light-emitting diode array. The metal layer is used for bonding and electrical contacting the micro light emitting diodes. The conductive line layer, the metal layer and the insulating layer may have been formed on the substrate 101 by deposition, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD).

[0196] A second bonding mark 609B, which is disposed in the second insulating layer 611B and exposes a second mark surface, i.e., an opening of the second bonding mark. The second bonding mark 609B in the lower stack 600B serves as a mark for alignment with the first bonding mark 609A in the upper stack 600A, thereby achieving precise hybrid bonding. The alignment method of the first bonding mark 609A and the second bonding mark 609B is that during hybrid bonding, the first mark surface is aligned and attached to the second mark surface. At this time, the upper stack 600A and the lower stack 600B have been aligned, and then hybrid bonding can be performed. The first bonding mark 609A and the second bonding mark 609B can be metal through holes, and the two can be bonded at the interface. In addition, the first bonding mark 609A and the second bonding mark 609B can have an enlarged opening and / or a metal layer can be coated at the opening to facilitate identification of their positions and increase bonding strength.

[0197] After the lower stack 600A and the upper stack 600B are formed, the lower stack 600A is bonded to the upper stack 600A by hybrid bonding, so that the first through hole contact portion 602 is bonded to the second through hole contact portion 603, and the first insulating layer 611A is bonded to the second insulating layer 611B, and optionally the first bonding mark 609A is bonded to the second bonding mark 609B, and the upper and lower parts of the third through hole between the preliminary 614 are bonded to each other. The present invention solves the technical problem encountered when manufacturing the inverted trapezoidal first light-emitting mesa with a large upper surface and a small lower surface, that is, the problem of electrical connection between the first light-emitting mesa and the driving backplane, by separately manufacturing the upper stack 600A and the lower stack 600B and then bonding the two to each other by hybrid bonding. The present invention realizes the electrical connection from the first light-emitting mesa 101 to the driving backplane 606 through hybrid bonding, so that both the upper stack 600A and the lower stack 600B can be manufactured from the surface opposite to the hybrid bonding surface, that is, the interface A, toward the hybrid bonding surface, thereby realizing a high-quality conductive structure, such as the first to third through-hole contacts (such as IC copper pillars), and the length of the conductive structure can also be flexibly selected.

[0198] An example of a hybrid bond may include the following two parts:

[0199] (1) Dielectric-to-dielectric bonding (i.e., bonding between the first insulating layer 611A and the second insulating layer 611B): At room temperature, extremely flat and smooth dielectric surfaces obtained by chemical mechanical polishing (CMP) are activated by plasma treatment or other methods and then brought into close contact at room temperature to achieve preliminary bonding.

[0200] (2) Metal-to-metal bonding (i.e., bonding between through-hole contacts): After completing dielectric-to-dielectric bonding, the upper and lower layers are heated to 200-400°C for annealing to strengthen the dielectric bonding and promote metal-to-metal bonding, thereby achieving hybrid bonding.

[0201] Figure 7 A top view of an epitaxial wafer 100 according to the present invention is shown.

[0202] like Figure 7 As shown, a portion of the light-emitting mesas on the epitaxial wafer 100 is a first light-emitting mesas 101, which has a notch 106, and the notch 106 exposes the bottom transparent conductive layer on the top of the first light-emitting mesas 101 for subsequent electrical connection; another portion of the light-emitting mesas on the epitaxial wafer 100 is a dummy light-emitting mesas 102, which has no notch 106 on the top. In this example, the non-light-emitting area NA surrounds the light-emitting area AA. In other embodiments, the non-light-emitting area NA may also only partially surround the light-emitting area AA or only be adjacent to the light-emitting area AA.

[0203] Although some embodiments of the present invention have been described in this application document, it will be appreciated by those skilled in the art that these embodiments are merely shown as examples. Those skilled in the art may conceive of numerous variations, alternatives, and improvements under the teachings of the present invention without departing from the scope of the present invention. The appended claims are intended to define the scope of the present invention and thus cover methods and structures within the scope of these claims themselves and their equivalents.

Claims

1. A micro light emitting diode having a dummy light emitting surface, comprising: A plurality of light-emitting countertops, each light-emitting countertop comprising: Bottom transparent conductive layer; a first epitaxial layer disposed between the bottom transparent conductive layer and the light emitting layer; a light emitting layer disposed between the first epitaxial layer and the second epitaxial layer and configured to emit light; and A second epitaxial layer is arranged on the light emitting layer, wherein the light emitting mesa has an area near an upper surface of the second epitaxial layer greater than an area near a lower surface of the first epitaxial layer; and A passivation layer covers the lower surface and side surfaces of the light-emitting mesas, wherein the light-emitting mesas include a first light-emitting mesas and a dummy light-emitting mesas, wherein the passivation layer on the first light-emitting mesas has a notch to expose the bottom transparent conductive layer, and the passivation layer on the dummy light-emitting mesas has no notch.

2. The micro light emitting diode according to claim 1, wherein: The depth of the dummy light-emitting mesa is different from the depth of the first light-emitting mesa; and / or The diameter of the upper surface of the dummy light-emitting mesa is different from the diameter of the upper surface of the first light-emitting mesa; and / or The diameter of the lower surface of the dummy light-emitting mesa is different from the diameter of the lower surface of the first light-emitting mesa; and / or The spacing between the dummy light-emitting mesas is different from the spacing between the first light-emitting mesas.

3. The micro light emitting diode according to claim 1, wherein: The depth of the dummy light-emitting mesa is the same as the depth of the first light-emitting mesa; and / or The diameter of the upper surface of the dummy light-emitting mesa is the same as the diameter of the upper surface of the first light-emitting mesa; and / or The diameter of the lower surface of the dummy light-emitting mesa is the same as the diameter of the upper surface of the first light-emitting mesa; and / or The spacing between the dummy light-emitting mesas is the same as the spacing between the first light-emitting mesas.

4. The micro-light emitting diode according to claim 1, further comprising: A substrate carries the light emitting mesa.

5. The micro-light emitting diode according to claim 1, further comprising: The dicing streets are configured to mark the boundaries between adjacent micro-LED chips, wherein the dicing streets are arranged between the dummy light-emitting mesas.

6. The micro light emitting diode according to claim 3, wherein: The thickness of the buffer layer is 4000 angstroms to 8000 angstroms; and / or The first epitaxial layer has a thickness of 2500 to 3500 angstroms; and / or The thickness of the light emitting layer is 2000 to 4000 angstroms; and / or The second epitaxial layer has a thickness of 4000 to 5000 angstroms; and / or The thickness of the bottom transparent conductive layer is 800 to 1500 um; and / or The thickness of the passivation layer is 800 angstroms to 1800 angstroms.

7. A micro light emitting diode according to claim 1, wherein the material of the substrate is selected from the group consisting of silicon (Si), silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), gallium nitride (GaN), glass, aluminum nitride (AlN), sapphire (α-Al2O3), and germanium (Ge). 8 . The micro light emitting diode according to claim 1 , wherein the number of dummy light emitting mesas accounts for 40% to 50% of the total number of light emitting mesas.

9. The micro light emitting diode according to any one of claims 1 to 7, wherein: The diameter of the lower surface of the light-emitting mesa is 0.8 to 1.2 μm; and / or The diameter of the upper surface of the light-emitting mesa is 1.4 to 1.8 μm; and / or The height of the light-emitting mesa is 0.3 to 0.7 μm.

10. The micro light emitting diode according to any one of claims 1 to 7, wherein the second epitaxial layer comprises: a stepped portion in electrical contact with the light emitting layer; as well as The base portion extends from the step portion to both sides. The micro light emitting diode according to claim 10 , wherein base portions of adjacent light emitting mesas are connected to each other.

12. The micro light emitting diode according to claim 10, wherein: The thickness of the step portion is: 400nm to 800nm; and / or The thickness of the base portion is 4 to 4.4 um. 13 . The micro light emitting diode according to claim 10 , wherein the passivation layer covers a side surface of the stepped portion and a surface of the base portion.

14. The micro light emitting diode chip according to any one of claims 1 to 12, further comprising: a reflector layer arranged to surround the first light emitting mesa; A driving circuit having a metal layer, a plurality of through-hole contacts being arranged on the driving circuit, the through-hole contacts being electrically connected to the metal layer, the micro-LED array region being bonded to the driving circuit through a bottom conductive bonding layer, wherein the driving circuit further has a wiring stack under the metal layer, which is configured to lead out a first electrode; an insulating layer configured to accommodate the first light emitting mesa, the dummy light emitting mesa, and the through-hole contact; a first electrode electrically connected to the through-hole contact portion; a top transparent conductive layer, which is disposed on the surface of the passivation layer and is in electrical contact with the second epitaxial layer; as well as The second electrode is disposed on the surface of the top transparent conductive layer.

15. A micro light emitting diode chip having a dummy light emitting mesa, comprising: a light emitting area including a plurality of first light emitting mesas configured to emit light; as well as The non-luminous area is adjacent to the luminous area and includes a plurality of dummy luminous mesas that do not emit light.

16. The micro light emitting diode chip according to claim 15, wherein: The light emitting area is 50% to 60% of the micro-LED chip; and / or The non-luminous area accounts for 40% to 50% of the micro-LED chip.

17. The micro-LED chip according to claim 15, wherein the first light-emitting mesa and the dummy light-emitting mesa each comprise: A bottom transparent conductive layer, which faces the light-emitting side; a first epitaxial layer disposed between the bottom transparent conductive layer and the light emitting layer; a light emitting layer disposed between the first epitaxial layer and the second epitaxial layer and configured to emit light; as well as The second epitaxial layer faces away from the light-emitting side, wherein the area of ​​the upper surface of the light-emitting mesa facing the light-emitting side is larger than the area of ​​the lower surface facing away from the light-emitting side.

18. The micro-LED chip according to claim 15, wherein the first light-emitting mesa and the dummy light-emitting mesa have the same size, and the size includes: The upper surface dimensions, lower surface dimensions and height of the light-emitting table.

19. The micro light emitting diode chip according to claim 18, wherein: The diameter of the lower surface of the first light-emitting mesa is 0.8 to 1.2 μm; and / or The diameter of the upper surface of the first light-emitting mesa is 1.4 to 1.8 μm; and / or The height of the first light emitting mesa is 0.3 to 0.7 μm.

20. The micro light emitting diode chip according to claim 17, wherein: The light emitting region further includes a via contact configured to electrically connect the second epitaxial layer of the first light emitting mesa to the first electrode; as well as The non-light emitting region has no through-hole contact for electrically connecting the second epitaxial layer of the dummy light emitting mesa to the driving circuit.

21. The micro light emitting diode chip according to claim 20, wherein: The light emitting region further includes a top transparent conductive layer disposed on an upper surface of the light emitting mesa to electrically connect the first epitaxial layer to the second electrode; as well as The non-light emitting area does not have the top transparent conductive layer.

22. The micro-LED chip according to claim 20, further comprising: An insulating layer covers the light emitting area and the non-light emitting area. 23 . The micro light emitting diode chip according to claim 15 , wherein a first interval between adjacent first light emitting mesas in the light emitting region is equal to a second interval between adjacent dummy light emitting mesas in the non-light emitting region. 24 . The micro light emitting diode chip according to claim 15 , wherein a first interval between adjacent first light emitting mesas in the light emitting region is different from a second interval between adjacent dummy light emitting mesas in the non-light emitting region.

25. The micro light emitting diode chip according to claim 17, further comprising: A passivation layer covers the lower surface of the first light-emitting mesa and the lower surface of the dummy light-emitting mesa, wherein the passivation layer on the first light-emitting mesa has a notch to expose the bottom transparent conductive layer, and the passivation layer on the dummy light-emitting mesa has no notch.

26. The micro-LED chip according to claim 25, further comprising: a reflector layer arranged to surround the first light-emitting mesa and configured to reflect light emitted by the first light-emitting mesa toward a light-exiting side; A driving circuit having a metal layer, a plurality of through-hole contacts being arranged on the driving circuit, the through-hole contacts being electrically connected to the metal layer, the micro-LED array region being bonded to the driving circuit through a bottom conductive bonding layer, wherein the driving circuit further has a wiring stack under the metal layer, which is configured to lead out a first electrode; an insulating layer configured to accommodate the first light emitting mesa, the dummy light emitting mesa, and the through-hole contact; a first electrode electrically connected to the through-hole contact portion; a top transparent conductive layer, which is disposed on the surface of the passivation layer and is in electrical contact with the second epitaxial layer; as well as The second electrode is disposed on the surface of the top transparent conductive layer.

27. The micro light emitting diode chip of claim 26, wherein the second electrode has a polarity opposite to that of the first electrode.

28. A micro-light emitting diode chip according to claim 26, wherein the material of the second epitaxial layer is a material layer of the second conductivity type comprising two or more elements of Ga, N, As, Al, In, and P, and the first epitaxial layer is a material layer of the first conductivity type comprising two or more elements of Ga, N, As, Al, In, and P, wherein the first conductivity type is different from the second conductivity type.

29. The micro-LED chip according to claim 26, wherein the light-emitting layer comprises a multi-quantum well layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer, an InGaN / AlGaN multi-quantum well layer, an InGaAs / AlGaAs multi-quantum well layer, or an AlGaInP multi-quantum well layer. 30 . The micro light emitting diode chip according to claim 29 , wherein an electron blocking layer is disposed on a first side of the light emitting layer, the first side being a side along which electrons migrate out of the light emitting layer.

31. The micro light emitting diode chip according to claim 26, wherein the material of the passivation layer is Si3N4 film, SiO2 film or Al2O3 film.

32. The micro-LED chip according to claim 26, wherein: The material of the insulating layer is selected from the group consisting of silicon dioxide (SiO2), aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon carbonitride (SiCN), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), magnesium oxide (MgO), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), or any combination thereof; and / or The material of the metal layer is selected from the group consisting of aluminum (Al), copper (Cu), tungsten (W), silver (Ag), gold (Au), nickel (Ni), platinum (Pt), tantalum (Ta), and molybdenum (Mo).

33. A micro-light emitting diode chip according to claim 26, wherein the through-hole contact portion includes a first and a second through-hole contact portion, and the insulating layer includes a first and a second insulating layer, and the micro-light emitting diode chip includes an upper stack and a lower stack, wherein the upper stack includes a first insulating layer, a light-emitting table and a first through-hole contact portion, and the lower stack includes a second insulating layer, a second through-hole contact portion and a driving circuit, wherein the lower stack is joined to the upper stack by hybrid bonding, so that the first through-hole contact portion is bonded to the second through-hole contact portion, and the first insulating layer is bonded to the second insulating layer.

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