Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device includes a light emitting element layer disposed on a substrate and including a plurality of light emitting elements; the encapsulation layer includes an organic-inorganic hybrid layer disposed on the light emitting element layer, a first inorganic encapsulation layer disposed on the organic-inorganic hybrid layer, a second inorganic encapsulation layer disposed on the first inorganic encapsulation layer, and a third inorganic encapsulation layer disposed on the second inorganic encapsulation layer. The organic-inorganic hybrid layer contains silicon, carbon, and nitrogen. The first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer each contain silicon and nitrogen. The atomic ratio of nitrogen to silicon (N / Si ratio) in the organic-inorganic hybrid layer is greater than the atomic ratio of nitrogen to silicon (N / Si ratio) in the first inorganic encapsulation layer and the atomic ratio of nitrogen to silicon (N / Si ratio) in the third inorganic encapsulation layer.

Description

Technical Field

[0001] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0002] With the development of the information society, the demand for display devices that can present images in various ways is increasing. For example, display devices are used in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device can be a flat panel display device such as a liquid crystal display (LCD) device, a field emission display device, and an organic light emitting display (OLED) device. Among the flat panel display devices, in the light emitting display device, since each of the pixels of the display panel includes a light emitting element that can emit light by itself, it is possible to display an image without the need for a backlight unit to provide light to the display panel.

[0003] The display device may further include pixels emitting predetermined light, scan lines, data lines, and power lines for driving the pixels, a scan driver outputting scan signals to the scan lines, and a display driver outputting data voltages to the data lines. Summary of the invention

[0004] The display device includes a light-emitting element layer and an encapsulation layer, the light-emitting element layer is arranged on a substrate and includes a plurality of light-emitting elements, and the encapsulation layer includes an organic-inorganic hybrid layer arranged on the light-emitting element layer, a first inorganic encapsulation layer arranged on the organic-inorganic hybrid layer, a second inorganic encapsulation layer arranged on the first inorganic encapsulation layer, and a third inorganic encapsulation layer arranged on the second inorganic encapsulation layer. The organic-inorganic hybrid layer contains silicon, carbon, and nitrogen. The first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer each contain silicon and nitrogen. The atomic ratio of nitrogen to silicon (N / Si ratio) in the organic-inorganic hybrid layer is greater than the atomic ratio of nitrogen to silicon (N / Si ratio) in the first inorganic encapsulation layer and the atomic ratio of nitrogen to silicon (N / Si ratio) in the third inorganic encapsulation layer.

[0005] The manufacturing method of the display device includes: forming a light-emitting element layer including a plurality of light-emitting elements on a substrate, forming an organic-inorganic hybrid layer on the light-emitting element layer at a first deposition rate, forming a first inorganic encapsulation layer on the organic-inorganic hybrid layer at a second deposition rate, forming a second inorganic encapsulation layer on the first inorganic encapsulation layer at a third deposition rate, and forming a third inorganic encapsulation layer on the second inorganic encapsulation layer at a fourth deposition rate. The first deposition rate is greater than the second deposition rate and the fourth deposition rate, and the third deposition rate is greater than the second deposition rate and the fourth deposition rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments thereof with reference to the accompanying drawings, in which:

[0007] Figure 1 is a perspective view of a display device according to an embodiment of the present invention;

[0008] Figure 2 It is shown Figure 1 A plan view of a display device;

[0009] Figure 3 is along Figure 2 A cross-sectional view taken along line AA';

[0010] Figure 4 is a cross-sectional view showing one sub-pixel of a display device according to an embodiment of the present invention;

[0011] Figure 5 is a schematic diagram showing an encapsulation layer of a display device according to an embodiment of the present invention;

[0012] Figure 6 is a flowchart illustrating a method for manufacturing a display device according to an embodiment of the present invention;

[0013] Figure 7 , Figure 8 , Fig. 9 , Fig.10 and Fig.11 are diagrams sequentially showing a manufacturing process of a display device according to an embodiment of the present invention;

[0014] Fig.12 is a perspective view illustrating a head mounted display according to an embodiment of the present invention;

[0015] Fig.13 It is shown Fig.12 an exploded perspective view of an example of a head mounted display; and

[0016] Fig.14 is a perspective view illustrating a head mounted display according to one embodiment. DETAILED DESCRIPTION

[0017] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. However, the present invention may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be exhaustive and comprehensive, and will fully convey the scope of the present invention to those skilled in the art.

[0018] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Throughout the specification, the same reference numerals refer to the same components.

[0019] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first element discussed below can be referred to as the second element without departing from the teachings of the present invention. Similarly, the second element may also be referred to as the first element.

[0020] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0021] Figure 1 is a perspective view of a display device according to an embodiment of the present invention.

[0022] refer to Figure 1 The display device 10 is a device for displaying a moving image or a still image. The display device 10 can be used as a display screen of various devices such as a television, a laptop computer, a monitor, a billboard, and an Internet of Things (IOT) device, and portable electronic devices such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra-portable mobile PC (UMPC).

[0023] The display device 10 may be a light-emitting display such as an organic light-emitting display including an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, or a micro-light-emitting display using a micro-light-emitting diode or a nano-light-emitting diode (LED). Hereinafter, an embodiment in which the display device 10 is an organic light-emitting display device is described, but the type of the display device 10 is not necessarily limited thereto.

[0024] In an embodiment of the present invention, the display device 10 may be a planar structure. For example, the display device 10 may be formed substantially flat on a plane defined by the first direction DR1 and the second direction DR2, and may have a predetermined thickness (or height) along the third direction DR3. In some embodiments, the display device 10 may include a curved surface in at least a portion including an edge region, etc. In addition, the display device 10 may be flexible so that it can be bent, curved, folded, or rolled.

[0025] In an embodiment of the present invention, the first direction DR1 may be a longitudinal direction, a column direction, or a vertical direction, and the second direction DR2 may be a direction intersecting the first direction DR1, for example, a transverse direction, a row direction, or a horizontal direction, relative to the image display surface of the display device 10. The third direction DR3 may be a thickness direction or a height direction of the display device 10.

[0026] The display device 10 may include a display panel 100 , a driver 200 , and a circuit board 300 .

[0027] The display panel 100 may include a main area MA including a display region DA in which an image is displayed, and a sub area SBA located on one side of the main area MA.

[0028] The main area MA may include a display area DA and a non-display area NA surrounding the display area DA. The display area DA may be located at the center of the main area MA and occupy most of the area in the main area MA. The non-display area NA may be located at an edge of the main area MA and may contact the sub-area SBA.

[0029] The display area DA may be an area in which pixels are provided, and may be an area in which an image is displayed by the pixels. In an embodiment of the present invention, the display area DA may be further provided with a sensing pattern (e.g., a touch electrode) for detecting a touch input, etc., and the display area DA may include a sensing area for detecting a touch input by the sensing pattern.

[0030] In an embodiment of the present invention, the display area DA may include long sides in the first direction DR1 and short sides in the second direction DR2, and may be formed as a plane having an approximately rectangular shape. The corners where the long sides and short sides of the display area DA intersect may be rounded or right angled. The shape of the display area DA may vary according to the embodiment. For example, the display area DA may be a polygonal shape, a circular shape, an elliptical shape, etc. in addition to a quadrilateral shape.

[0031] The non-display area NA may be directly located around the display area DA. For example, the non-display area NA may at least partially surround the display area DA. An embedded circuit may be arranged in the non-display area NA. For example, an embedded circuit including a scan driving circuit and the like may be arranged in the non-display area NA located on one side (e.g., the left side or the right side) or both sides of the display area DA.

[0032] The sub-area SBA may be located on one side of the main area MA. For example, the sub-area SBA may be an area protruding from one side of the main area MA in the first direction DR1. For example, the sub-area SBA may protrude from the lower end of the main area MA in the first direction DR1. In an embodiment of the present invention, the sub-area SBA may have a narrower width than the main area MA. For example, with respect to the second direction DR2, the sub-area SBA may have a narrower width than the main area MA.

[0033] Wiring and pads may be arranged in the sub-area SBA. For example, in the sub-area SBA, wiring and pads connected to pixels and / or embedded circuits located in the main area MA and connected to the driver 200 and / or circuit board 300 located in the sub-area SBA may be arranged. When describing an embodiment, the term "connection" may include electrical connection and / or physical connection.

[0034] In an embodiment of the present invention, the driver 200 (eg, a display driving circuit) may be mounted in the sub-area SBA. The circuit board 300 may be disposed on a portion of the sub-area SBA.

[0035] The driver 200 may include a data driving circuit for driving pixels. In an embodiment of the present invention, the driver 200 may be formed as an integrated circuit chip (IC) and arranged in the sub-area SBA. In some embodiments, the driver 200 may be arranged on a circuit board 300 arranged on the sub-area SBA, or may be arranged on another circuit board connected to the display panel 100 through the circuit board 300.

[0036] The circuit board 300 may be arranged on a portion of the sub-area SBA. For example, the circuit board 300 may be bonded to a pad located on a portion (e.g., the lower edge) of the sub-area SBA. The circuit board 300 may supply power or send a driving signal for driving the display panel 100. For example, the circuit board 300 may supply input image data (e.g., digital image data), a driving signal including a timing signal, and a driving voltage to the display panel 100. The circuit board 300 may be a flexible film such as a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a chip on film (COF), but is not necessarily limited thereto.

[0037] Figure 2 It is shown Figure 1 A plan view of a display device. Figure 3 is along Figure 2 A cross-sectional view taken along line AA'.

[0038] Figure 1 The display device 10 is shown unfolded without being bent, and Figure 2 and Figure 3 The display device 10 is illustrated as being bent in the sub-area SBA. Figure 1 A sub-area SBA is shown extending next to the main area MA, and Figure 2 and Figure 3 A portion of the sub-area SBA is shown in a bent state.

[0039] refer to Figure 2 and Figure 3, the display panel 100 may include a substrate 110, a circuit layer 120, a light emitting element layer 130, an encapsulation layer 140, and a color filter layer 150 sequentially arranged on the substrate 110, and the substrate 110 includes a main area MA and a sub-area SBA. The circuit layer 120 may also be located in the main area MA and the sub-area SBA. The light emitting element layer 130, the encapsulation layer 140, and the color filter layer 150 may be located on a portion of the substrate 110 and the circuit layer 120. For example, the light emitting element layer 130, the encapsulation layer 140, and the color filter layer 150 may be located in the main area MA.

[0040] In an embodiment of the present invention, the display device 10 may further include additional elements arranged on the display panel 100. For example, the display device 10 may further include at least one of a sensor layer (e.g., a touch sensor layer), a polarizing layer, and a protective layer (e.g., a window) arranged on the encapsulation layer 140. Each of the sensor layer, the polarizing layer, and / or the protective layer may be manufactured integrally with the display panel 100, or may be manufactured separately from the display panel 100 and attached to the display panel 100 by an adhesive layer or the like.

[0041] The main area MA may include a display area DA and a non-display area NA. The non-display area NA may be located adjacent to the display area DA. For example, the non-display area NA may be an edge area of ​​the main area MA located outside the display area DA. For example, the display area DA may be arranged between the non-display areas NA.

[0042] The substrate 110 may include an insulating material such as a polymer resin. For example, the substrate 110 may be made of polyimide or another insulating material. The substrate 110 may be a flexible substrate that can be deformed (such as bent, folded, or curled). In some embodiments, the substrate 110 may include an insulating material such as glass.

[0043] The circuit layer 120 may include pixel circuits and wiring. For example, the circuit layer 120 may include circuit elements (e.g., pixel transistors and capacitors) constituting the pixel circuit of each pixel and wiring connected to the pixel. In an embodiment of the present invention, the circuit layer 120 may further include circuit elements constituting embedded circuits (such as scan drive circuits) and wiring connected to the embedded circuits.

[0044] The light emitting element layer 130 may include a light emitting element arranged in an emission region of a pixel. For example, each of the pixels may include at least one light emitting element and a pixel circuit connected to the light emitting element. Each of the pixels may be located in a pixel region including an emission region in which the light emitting element is arranged and a pixel circuit region in which the pixel circuit is arranged. The emission region and the pixel circuit region of each pixel may overlap each other, but the present disclosure is not necessarily limited thereto.

[0045] In describing the embodiment, the circuit layer 120 and the light emitting element layer 130 are described separately, but the embodiment is not necessarily limited thereto. For example, the circuit layer 120 and the light emitting element layer 130 may be combined.

[0046] The encapsulation layer 140 may at least partially cover the light emitting element layer 130. The encapsulation layer 140 may extend from one non-display area NA toward another non-display area NA and contact the circuit layer 120. In an embodiment of the present invention, the encapsulation layer 140 may have a multi-layer structure including at least two inorganic encapsulation layers overlapping each other and at least one organic encapsulation layer between the inorganic encapsulation layers.

[0047] In an embodiment of the present invention, the display panel 100 may be bent in the bending area BA. The bending area BA may be part of the sub-area SBA and may be spaced apart from the main area MA. The non-display area NA may be interposed between the bending area BA and the display area DA.

[0048] The substrate 110 and the circuit layer 120 may be bent in the bending area BA corresponding to a partial cross-section of the sub-area SBA. Therefore, a bezel area recognized as the non-display area NA by a user may be reduced or minimized.

[0049] Figure 4 is a cross-sectional view showing one sub-pixel of a display device according to an embodiment of the present invention. Figure 4 : is a cross-sectional view showing a part of a region corresponding to one sub-pixel of the display area DA.

[0050] refer to Figure 4 , the display panel 100 may include a substrate 110 and a circuit layer 120, a light emitting element layer 130, an encapsulation layer 140, and a color filter layer 150 arranged on the substrate 110. The circuit layer 120, the light emitting element layer 130, the encapsulation layer 140, and the color filter layer 150 may be sequentially disposed or stacked on the substrate 110 along the third direction DR3.

[0051] The substrate 110 may be made of a material having a flexible property that can be bent, folded, rolled, etc. The substrate 110 may include an insulating material such as a polymer resin. For example, the substrate 110 may be made of polyimide.

[0052] The circuit layer 120 may include a pixel circuit PXC and wiring. For example, the circuit layer 120 may include circuit elements (e.g., a pixel transistor T and a capacitor Cst) constituting the pixel circuit PXC of each sub-pixel and wiring electrically connected to the sub-pixel (e.g., various power lines and signal lines including power lines, scan lines, emission control lines, and data lines).

[0053] Among the elements that may be provided on the circuit layer 120, Figure 4 The pixel circuit PXC of each sub-pixel is shown, and the pixel circuit PXC includes a first thin film transistor TFT1 (also referred to as a "first pixel transistor"), a second thin film transistor TFT2 (also referred to as a "second pixel transistor"), and a capacitor Cst. The first thin film transistor TFT1 may represent a first type of transistor (e.g., a P-type transistor) including a first semiconductor material (e.g., polysilicon) among the pixel transistors T constituting each pixel circuit PXC. Figure 4 The first thin film transistor TFT1 is shown, which is a transistor connected to the light emitting element EL through at least one connection electrode (e.g., a first connection electrode CNE1 and a second connection electrode CNE2) among the first type transistors. The second thin film transistor TFT2 may represent a second type transistor (e.g., an N-type transistor) including a second semiconductor material (e.g., an oxide semiconductor) among the pixel transistors T.

[0054] The cross section of the subpixel may vary according to the type and / or structure of each of the subpixels and the display panel 100 including the subpixel. For example, the position and order of formation of the first thin film transistor TFT1, the second thin film transistor TFT2 and the capacitor Cst may vary according to the embodiment.

[0055] The circuit layer 120 may include a semiconductor layer forming circuit elements, wiring, etc., a conductive layer, and an insulating layer arranged between the conductive layer and the semiconductor layer and / or around the conductive layer and the semiconductor layer. For example, the circuit layer 120 may include a first semiconductor layer SCL1 (e.g., a polysilicon semiconductor layer), a first insulating layer 123 (e.g., a first gate insulating layer), a first conductive layer CDL1 (e.g., a first gate conductive layer), a second insulating layer 124 (e.g., a second gate insulating layer), a second conductive layer CDL2 (e.g., a second gate conductive layer), a third insulating layer 125 (e.g., a first interlayer insulating layer), a second semiconductor layer SCL2 (e.g., an oxide semiconductor layer), a fourth insulating layer 126 (e.g., a third gate insulating layer), a third conductive layer CDL3 (e.g., a third gate conductive layer), a fifth insulating layer 127 (e.g., a second interlayer insulating layer), a fourth conductive layer CDL4 (e.g., a first source-drain conductive layer), and a sixth insulating layer 128 (e.g., a first via layer or a first planarization layer) sequentially arranged on the substrate 110 relative to the third direction DR3. In an embodiment of the present invention, the circuit layer 120 may further include a fifth conductive layer CDL5 (e.g., a second source-drain conductive layer) and a seventh insulating layer 129 (e.g., a second via layer or a second planarization layer) sequentially arranged on the sixth insulating layer 128. In an embodiment of the present invention, the circuit layer 120 may further include a lower conductive layer BCDL arranged between the substrate 110 and the first semiconductor layer SCL1, a barrier layer 121 arranged between the substrate 110 and the lower conductive layer BCDL, and a buffer layer 122 arranged between the lower conductive layer BCDL and the first semiconductor layer SCL1.

[0056] The barrier layer 121 may be disposed on the substrate 110. For example, the barrier layer 121 may be in direct contact with the substrate 110. The barrier layer 121 may protect the elements disposed on the circuit layer 120 and the light emitting element layer 130 from moisture penetrating through the substrate 110 susceptible to moisture penetration. The barrier layer 121 may include at least one inorganic layer containing an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or another inorganic insulating material). The material of the barrier layer 121 may vary according to the embodiment.

[0057] The lower conductive layer BCDL may be disposed on the barrier layer 121. The lower conductive layer BCDL may include a lower metal layer BML overlapping the active layer (eg, the first active layer ACT1 and / or the second active layer ACT2) of the at least one pixel transistor T and / or at least one wiring (or a portion of the at least one wiring). Figure 4The lower metal layer BML is illustrated as being arranged to overlap only the first active layer ACT1 of the first thin film transistor TFT1 and the capacitor electrodes CAE1 and CAE2 of the capacitor Cst, but the present disclosure is not limited thereto. For example, the lower metal layer BML may be patterned into a suitable size and / or shape as required and arranged on a portion of the pixel circuit PXC, or may be arranged on the entire surface of the pixel circuit PXC. In an embodiment of the present invention, the lower metal layer BML may also be used as a light blocking pattern and / or a back gate electrode, etc., of at least one pixel transistor T.

[0058] The buffer layer 122 may be disposed on the lower conductive layer BCDL and at least partially cover the lower conductive layer BCDL. The buffer layer 122 may include at least one inorganic layer including an inorganic insulating material.

[0059] The first thin film transistor TFT1, the second thin film transistor TFT2 and the capacitor Cst may be arranged on one surface of the substrate 110 including the buffer layer 122. The first thin film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1. The second thin film transistor TFT2 may include a second active layer ACT2 and a second gate electrode G2. In an embodiment of the present invention, the second thin film transistor TFT2 may include a back gate electrode BG. The capacitor Cst may include a first capacitor electrode CAE1 and a second capacitor electrode CAE2.

[0060] The first semiconductor layer SCL1 may be disposed on the buffer layer 122. The first semiconductor layer SCL1 may include a first active layer ACT1 of the first thin film transistor TFT1.

[0061] The first active layer ACT1 may be provided on the first semiconductor layer SCL1 and may include a first semiconductor material (e.g., polysilicon). The first active layer ACT1 may include a first channel region CH1, a first source region S1, and a first drain region D1. The first channel region CH1 may overlap with the first gate electrode G1 along the third direction DR3. The first source region S1 may be arranged on one side of the first channel region CH1, and the first drain region D1 may be arranged on the other side of the first channel region CH1. For example, the first channel region CH1 may be between the first source region S1 and the first drain region D1. The first source region S1 and the first drain region D1 may be regions formed to have conductivity by doping ions or impurities into a semiconductor used to form the first active layer ACT1. In an embodiment of the present invention, the first source region S1 may be a source electrode of a first thin film transistor TFT1. In some embodiments, the first thin film transistor TFT1 may include a separate source electrode connected to the first source region S1. In an embodiment of the present invention, the first drain region D1 may be a drain electrode of the first thin film transistor TFT1. In some embodiments, the first thin film transistor TFT1 may include a separate drain electrode connected to the first drain region D1.

[0062] The first insulating layer 123 may be disposed on the first semiconductor layer SCL1. The first insulating layer 123 may cover the first semiconductor layer SCL1.

[0063] The first conductive layer CDL1 may be arranged on the first insulating layer 123. The first conductive layer CDL1 may include a first gate electrode G1 of the first thin film transistor TFT1. The first gate electrode G1 may be arranged to overlap a portion of the first active layer ACT1 (e.g., the first channel region CH1). In an embodiment of the present invention, the first conductive layer CDL1 may further include at least one wiring (or a portion of the at least one wiring), a metal pattern (e.g., a bridge pattern), and / or a capacitor electrode. For example, the first conductive layer CDL1 may further include a first capacitor electrode CAE1 of a capacitor Cst.

[0064] In an embodiment of the present invention, the first capacitor electrode CAE1 may be integrally formed with the gate electrode G1 of at least one first thin film transistor TFT1. For example, the first capacitor electrode CAE1 and the gate electrode G1 of the first thin film transistor TFT1 may be formed as one conductive pattern, and the second capacitor electrode CAE2 may overlap the conductive pattern.

[0065] The second insulating layer 124 may be disposed on the first conductive layer CDL1. The second insulating layer 124 may at least partially cover the first conductive layer CDL1.

[0066] The second conductive layer CDL2 may be arranged on the second insulating layer 124. The second conductive layer CDL2 may include an electrode of the capacitor Cst, for example, a second capacitor electrode CAE2. In an embodiment of the present invention, the second conductive layer CDL2 may further include at least one electrode, at least one wiring (or a portion of the at least one wiring) and / or a metal pattern (for example, a bridge pattern). For example, the second conductive layer CDL2 may further include a back gate electrode BG connected to the second gate electrode G2 of the second thin film transistor TFT2.

[0067] The third insulating layer 125 may be disposed on the second conductive layer CDL2. The third insulating layer 125 may at least partially cover the second conductive layer CDL2.

[0068] The second semiconductor layer SCL2 may be disposed on the third insulating layer 125. The second semiconductor layer SCL2 may include a second active layer ACT2 of the second thin film transistor TFT2.

[0069] The second active layer ACT2 may be provided on the second semiconductor layer SCL2 and may include a second semiconductor material (e.g., an oxide semiconductor) different from the first semiconductor material. For example, the second active layer ACT2 may include IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0070] The second active layer ACT2 may include a second channel region CH2, a second source region S2, and a second drain region D2. The second channel region CH2 may overlap with the second gate electrode G2 along the third direction DR3. The second source region S2 may be arranged on one side of the second channel region CH2, and the second drain region D2 may be arranged on the other side of the second channel region CH2. For example, the second channel region CH2 may be between the second source region S2 and the second drain region D2. The second source region S2 and the second drain region D2 may be conductive regions formed by doping ions or impurities into a semiconductor for forming the second active layer ACT2. In an embodiment of the present invention, the second source region S2 may be a source electrode of a second thin film transistor TFT2. In some embodiments, the second thin film transistor TFT2 may include a separate source electrode connected to the second source region S2. In an embodiment of the present invention, the second drain region D2 may be a drain electrode of the second thin film transistor TFT2. In some embodiments, the second thin film transistor TFT2 may include a separate drain electrode connected to the second drain region D2.

[0071] The fourth insulating layer 126 may be disposed on the second semiconductor layer SCL2. The fourth insulating layer 126 may cover the second semiconductor layer SCL2.

[0072] The third conductive layer CDL3 may be disposed on the fourth insulating layer 126. The third conductive layer CDL3 may include a second gate electrode G2 of the second thin film transistor TFT2. The second gate electrode G2 may be disposed to overlap a portion of the second active layer ACT2 (e.g., the second channel region CH2). In an embodiment of the present invention, the third conductive layer CDL3 may further include at least one wiring (or a portion of the at least one wiring), a metal pattern (e.g., a bridge pattern), and / or a capacitor electrode.

[0073] In an embodiment of the present invention, each of the electrodes, conductive patterns and / or wirings provided in the lower conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may include a conductive material (e.g., at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and other metals, their alloys or other conductive materials), and each may have a single-layer or multi-layer structure. For example, each of the electrodes, conductive patterns and / or wirings provided in the lower conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may include molybdenum (Mo) or other metal materials. At least two conductive layers of the lower conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may include the same material, or may include different materials. However, the material of each of the lower conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 is not necessarily limited thereto and may vary according to the embodiment.

[0074] The fifth insulating layer 127 may be disposed on the third conductive layer CDL3. The fifth insulating layer 127 may cover the third conductive layer CDL3.

[0075] In an embodiment of the present invention, the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126 and the fifth insulating layer 127 may be an inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide or another inorganic insulating material), and each may have a single-layer or multi-layer structure. At least two insulating layers among the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126 and the fifth insulating layer 127 may include the same material, or may include different materials. The material of each of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126 and the fifth insulating layer 127 may vary according to the embodiment.

[0076] The fourth conductive layer CDL4 may be disposed on the fifth insulating layer 127. The fourth conductive layer CDL4 may include a first connection electrode CNE1 (or a drain electrode of the first thin film transistor TFT1), a first bridge electrode BE1 (or a source electrode of the second thin film transistor TFT2), and a second bridge electrode BE2 (or a drain electrode of the second thin film transistor TFT2). The first connection electrode CNE1 may be provided on the fourth conductive layer CDL4 and may be connected to the first drain region D1 of the first active layer ACT1 through a first contact hole CT1 penetrating the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127. The first bridge electrode BE1 may be provided on the fourth conductive layer CDL4 and may be connected to the second source region S2 of the second active layer ACT2 through a second contact hole CT2 penetrating the fourth insulating layer 126 and the fifth insulating layer 127. The second bridge electrode BE2 may be connected to the second drain region D2 of the second active layer ACT2 through a third contact hole CT3 penetrating the fourth insulating layer 126 and the fifth insulating layer 127. In an embodiment of the present invention, the fourth conductive layer CDL4 may further include at least one wiring (or a portion of the at least one wiring) and / or a metal pattern (e.g., a bridge pattern). For example, the fourth conductive layer CDL4 may include a portion of a power line (e.g., a first pixel power line and / or a second pixel power line) provided inside and / or outside the display area DA.

[0077] The sixth insulating layer 128 may be disposed on the fourth conductive layer CDL4. The sixth insulating layer 128 may at least partially cover the fourth conductive layer CDL4.

[0078] The fifth conductive layer CDL5 may be arranged on the sixth insulating layer 128. The fifth conductive layer CDL5 may include a second connection electrode CNE2. The second connection electrode CNE2 may be provided on the fifth conductive layer CDL5 and may be connected to the first connection electrode CNE1 through a fourth contact hole CT4 (or a first through hole) penetrating the sixth insulating layer 128. In an embodiment of the present invention, the fifth conductive layer CDL5 may further include at least one wiring (or a portion of the at least one wiring) and / or a metal pattern (e.g., a bridge pattern). For example, the fifth conductive layer CDL5 may include a portion of a power line (e.g., a first pixel power line and / or a second pixel power line) provided inside and / or outside the display area DA.

[0079] In an embodiment of the present invention, each of the electrodes, conductive patterns and / or wirings provided in the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may include a conductive material (for example, at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and other metals, their alloys or other conductive materials), and may have a single-layer or multi-layer structure. For example, each of the electrodes, conductive patterns and / or wirings provided in the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may be formed by a three-layer structure including titanium / aluminum / titanium (Ti / Al / Ti). The fourth conductive layer CDL4 and the fifth conductive layer CDL5 may include the same material, or may include different materials. The material of each of the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may vary according to the embodiment.

[0080] The seventh insulating layer 129 may be disposed on the fifth conductive layer CDL5. The seventh insulating layer 129 may at least partially cover the fifth conductive layer CDL5.

[0081] In an embodiment of the present invention, the sixth insulating layer 128 and the seventh insulating layer 129 may be an organic insulating layer including an organic insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin or other organic insulating material) that flattens the circuit layer 120, and each may have a single-layer or multi-layer structure. The sixth insulating layer 128 and the seventh insulating layer 129 may include the same material, or may include different materials. The material of each of the sixth insulating layer 128 and the seventh insulating layer 129 may vary according to the embodiment.

[0082] The light emitting element layer 130 may include a pixel defining layer 131 dividing emission areas EA of pixels and corresponding light emitting elements EL located in corresponding emission areas EA. In an embodiment of the present invention, the light emitting element layer 130 may further include a spacer disposed on a portion of the pixel defining layer 131 .

[0083] Each of the light emitting elements EL may include a first electrode ET1 connected to at least one transistor T (e.g., a first thin film transistor TFT1) included in a corresponding sub-pixel through a first connection electrode CNE1 and / or a second connection electrode CNE2, and a light emitting layer EML and a second electrode ET2 (e.g., a cathode electrode) sequentially arranged on the first electrode ET1. In an embodiment of the present invention, the light emitting element EL may further include a first intermediate layer (e.g., a hole layer including a hole transport layer) between the first electrode ET1 and the light emitting layer EML, and a second intermediate layer (e.g., an electron layer including an electron transport layer) between the light emitting layer EML and the second electrode ET2.

[0084] The first electrode ET1 of the light emitting element EL may include a conductive material and may be disposed on the circuit layer 120. For example, the first electrode ET1 may be disposed on the seventh insulating layer 129 and correspond to each emission area EA. The first electrode ET1 may be connected to the second connection electrode CNE2 through a fifth contact hole CT5 (or a second through hole) penetrating the seventh insulating layer 129.

[0085] In an embodiment of the present invention, the first electrode ET1 may include a transparent conductive metal oxide or a metal material having a high reflectivity. For example, the first electrode ET1 may have a single-layer structure including molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may have a structure including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) and a multilayer structure of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au) or nickel (Ni) (e.g., ITO / Mg, ITO / MgF, ITO / Ag and ITO / Ag / ITO).

[0086] The light-emitting layer EML of the light-emitting element EL may include a polymer material or a monomolecular material. In an embodiment of the present invention, the light-emitting layer EML of the light-emitting element EL may be arranged for each sub-pixel, and the light-emitting layer EML of each sub-pixel may emit visible light of a color corresponding to the corresponding sub-pixel. In some embodiments, the light-emitting layer EML may be a common layer shared by sub-pixels of different colors, and a wavelength conversion layer and / or a color filter corresponding to the color (or wavelength band) of light desired to be emitted from each sub-pixel may be disposed in the emission area EA of at least some of the sub-pixels.

[0087] The second electrode ET2 of the light emitting element EL includes a conductive material and can be connected to the second pixel power line. In an embodiment of the present invention, the second electrode ET2 may be a common layer formed across the entire display area DA, which at least partially covers the light emitting layer EML and the pixel defining layer 131. In an embodiment of the present invention, the second electrode ET2 may include a transparent conductive oxide (TCO) capable of transmitting light (such as indium tin oxide (ITO) or indium zinc oxide (IZO)) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag) or an alloy of magnesium (Mg) and silver (Ag)). When the second electrode ET2 includes a semi-transmissive conductive material, an improvement in light output efficiency due to the microcavity effect can be expected.

[0088] In some embodiments, the capping layer may be arranged on the second electrode ET2. The capping layer may include an organic or inorganic insulating material that at least partially covers the light-emitting element EL. The capping layer may prevent the light-emitting element EL from being damaged by external air. In an embodiment of the present invention, the capping layer may include organic materials such as α-naphthylaniline (a-NPD), N,N'-di(naphthalene-1-yl)-N,N'-diphenylbenzidine (NPB), triphenylamine-based hole transport materials (TPD), 1,3,5-tri[(3-pyridyl)-phenyl-3-yl]benzene (m-MTDATA), tri(8-hydroxyquinoline)aluminum (Alq3), lithium fluoride (LiF) and / or copper phthalocyanine (CuPc). Alternatively, it may include inorganic materials such as aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 )、zinc oxide (ZnO), silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) and / or silicon oxynitride (SiON).

[0089] The pixel defining layer 131 may have an opening corresponding to each of the emission regions EA and may at least partially surround the emission region EA. For example, the pixel defining layer 131 may cover the edge of the first electrode ET1 of the light emitting element EL and may include an opening exposing the remaining portion of the first electrode ET1. The region where the exposed first electrode ET1 overlaps with the light emitting layer EML (or the region including it) may be defined as the emission region EA of each pixel PX.

[0090] In an embodiment of the present invention, the pixel defining layer 131 may include at least one organic layer including an organic insulating material. For example, the pixel defining layer 131 may include polyacrylic resin (PAR), epoxy resin (ER), phenolic resin (PR), polyamide resin (PA), polyimide resin (PI), unsaturated polyester resin (UPR), polyphenylene ether resin (PPER), polyphenylene sulfide resin (PPSR), benzocyclobutene (BCB) or other organic insulating materials.

[0091] The spacer may be disposed on a portion of the pixel defining layer 131. The spacer may include at least one organic layer including an organic insulating material. In an embodiment of the present invention, the spacer may include the same material as the pixel defining layer 131, or may include a material different from the pixel defining layer 131. The organic insulating material constituting the spacer is not necessarily limited and varies according to the embodiment.

[0092] The encapsulation layer 140 may be disposed on the light emitting element layer 130 in the main area MA. For example, the encapsulation layer 140 may be disposed in the display area DA and the non-display area NA and at least partially cover the light emitting element layer 130. The encapsulation layer 140 may block oxygen or moisture from penetrating into the light emitting element layer 130, and may reduce electrical or physical influences on the circuit layer 120 and the light emitting element layer 130.

[0093] Figure 5 is a schematic diagram showing an encapsulation layer of a display device according to an embodiment of the present invention.

[0094] refer to Figure 5 The encapsulation layer 140 may include a light emitting element layer 130 (refer to Figure 4 ) on an organic-inorganic hybrid layer 141, a first inorganic encapsulating layer 142, a second inorganic encapsulating layer 143, and a third inorganic encapsulating layer 144. Even when a plurality of stacked layers are included, the encapsulating layer 140 can remain relatively thin.

[0095] The organic-inorganic hybrid layer 141 may include an organic group or organic part dispersed with an inorganic material. In an embodiment of the present invention, the organic-inorganic hybrid layer 141 may include silicon (Si), carbon (C), and nitrogen (N). The organic-inorganic hybrid layer 141 may include silicon oxycarbon nitride (SiO x C y N z ) or silicon carbonitride (SiC y N z ). The organic-inorganic hybrid layer 141 may include silicon (Si), carbon (C), and nitrogen (N) in one layer, thereby reducing film density while maintaining barrier properties and planarization properties.

[0096] The organic group or organic part may be randomly arranged in the organic-inorganic hybrid layer 141. In an embodiment of the present invention, the organic part may include carbon (C) and nitrogen (N), and may additionally include oxygen (O) or sulfur (S). However, the present disclosure is not necessarily limited thereto, and other elements may also be included. In an embodiment of the present invention, the organic part may include at least one of an alkyl group and an alkoxy group and an amine group. The alkyl group, alkoxy group or amine group may be derived from an organosilicon precursor and an aminosilane precursor described later in the manufacturing method.

[0097] The first inorganic encapsulation layer 142, the second inorganic encapsulation layer 143, and the third inorganic encapsulation layer 144 may include an inorganic insulating material. The inorganic insulating material may include aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 )、zinc oxide (ZnO), silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) and / or silicon oxynitride (SiON), but is not necessarily limited thereto.

[0098] In an embodiment of the present invention, the first inorganic encapsulation layer 142, the second inorganic encapsulation layer 143, and the third inorganic encapsulation layer 144 may each include silicon (Si) and nitrogen (N). The first inorganic encapsulation layer 142 to the third inorganic encapsulation layer 144 may each include silicon nitride (SiN z ) or silicon oxynitride (SiO x N z ). The nitrogen contents (z) contained in the first inorganic encapsulating layer 142, the second inorganic encapsulating layer 143, and the third inorganic encapsulating layer 144 may be the same as or different from each other.

[0099] The atomic ratio of nitrogen to silicon (N / Si ratio) in the organic-inorganic hybrid layer 141 may be greater than the atomic ratio of nitrogen to silicon (N / Si ratio) in the first inorganic encapsulating layer 142 and the atomic ratio of nitrogen to silicon (N / Si ratio) in the third inorganic encapsulating layer 144. The atomic ratio of nitrogen to silicon (N / Si ratio) in the first inorganic encapsulating layer 142 may be less than the atomic ratio of nitrogen to silicon (N / Si ratio) in the organic-inorganic hybrid layer 141 and the atomic ratio of nitrogen to silicon (N / Si ratio) in the second inorganic encapsulating layer 143. The atomic ratio of nitrogen to silicon (N / Si ratio) in the second inorganic encapsulating layer 143 may be greater than the atomic ratio of nitrogen to silicon (N / Si ratio) in the first inorganic encapsulating layer 142 and the atomic ratio of nitrogen to silicon (N / Si ratio) in the third inorganic encapsulating layer 144. The atomic ratio of nitrogen to silicon (N / Si ratio) in the third inorganic encapsulating layer 144 may be smaller than those in the organic-inorganic hybrid layer 141 and the second inorganic encapsulating layer 143 .

[0100] The atomic ratio of nitrogen to silicon (N / Si ratio) in the organic-inorganic hybrid layer 141 may be the same as or similar to the atomic ratio of nitrogen to silicon (N / Si ratio) in the second inorganic encapsulating layer 143. In an embodiment of the present invention, the atomic ratio of nitrogen to silicon (N / Si ratio) in the organic-inorganic hybrid layer 141 may be greater than the atomic ratio of nitrogen to silicon (N / Si ratio) in the second inorganic encapsulating layer 143. The atomic ratio of nitrogen to silicon (N / Si ratio) in the first inorganic encapsulating layer 142 may be the same as or similar to the atomic ratio of nitrogen to silicon (N / Si ratio) in the third inorganic encapsulating layer 144. In an embodiment of the present invention, the atomic ratio of nitrogen to silicon (N / Si ratio) in the first inorganic encapsulating layer 142 may be the same as the atomic ratio of nitrogen to silicon (N / Si ratio) in the third inorganic encapsulating layer 144.

[0101] In an embodiment of the present invention, the atomic ratio of nitrogen to silicon (N / Si ratio) in the organic-inorganic hybrid layer 141 may be greater than or equal to 0.77. The atomic ratio of nitrogen to silicon (N / Si ratio) in the first inorganic encapsulation layer 142 may be less than or equal to 0.75. The atomic ratio of nitrogen to silicon (N / Si ratio) in the second inorganic encapsulation layer 143 may be greater than or equal to 0.77. The atomic ratio of nitrogen to silicon (N / Si ratio) in the third inorganic encapsulation layer 144 may be less than or equal to 0.75. The atomic ratio of nitrogen to silicon (N / Si ratio) in the organic-inorganic hybrid layer 141 and the atomic ratio of nitrogen to silicon (N / Si ratio) in the second inorganic encapsulation layer 143 may each be less than or equal to about 1. The atomic ratio of nitrogen to silicon (N / Si ratio) in the first inorganic encapsulation layer 142 and the atomic ratio of nitrogen to silicon (N / Si ratio) in the third inorganic encapsulation layer 144 may each be greater than or equal to about 0.5.

[0102] The atomic ratio of nitrogen to silicon (N / Si ratio) can be obtained through cross-sectional analysis (TEM-EDS) and composition analysis (XPS), but the present disclosure is not necessarily limited thereto.

[0103] The organic-inorganic hybrid layer 141 and the second inorganic encapsulation layer 143 may have a lower film density than the first inorganic encapsulation layer 142 and the third inorganic encapsulation layer 144. In addition, the film density of the organic-inorganic hybrid layer 141 may be relatively low compared to other layers of the encapsulation layer 140. In other words, the film density of the organic-inorganic hybrid layer 141 may be less than the film density of the first inorganic encapsulation layer 142, the film density of the second inorganic encapsulation layer 143, and the film density of the third inorganic encapsulation layer 144.

[0104] The film density of the first inorganic encapsulating layer 142 may be greater than the film density of the organic-inorganic hybrid layer 141 and the film density of the second inorganic encapsulating layer 143. The film density of the first inorganic encapsulating layer 142 may be the same as or similar to the film density of the third inorganic encapsulating layer 144.

[0105] The film density of the second inorganic encapsulating layer 143 may be greater than the film density of the organic-inorganic hybrid layer 141 , but may be less than the film density of the first inorganic encapsulating layer 142 and the film density of the third inorganic encapsulating layer 144 .

[0106] In an embodiment of the present invention, the film density of the organic-inorganic hybrid layer 141 may be less than or equal to about 2.1 g / cm 3 The film density of the organic-inorganic hybrid layer 141 may be greater than or equal to about 1.7 g / cm 3 In some embodiments, the film density of the organic-inorganic hybrid layer 141 may be greater than or equal to about 1.9 g / cm 3 In some embodiments, the film density of the organic-inorganic hybrid layer 141 may be greater than or equal to about 2.0 g / cm 3 When the above range is satisfied, the organic-inorganic hybrid layer 141 may have enhanced planarization performance and barrier performance.

[0107] In an embodiment of the present invention, the film density of the first inorganic encapsulating layer 142 may be greater than or equal to about 2.6 g / cm 3 In some embodiments, the film density of the first inorganic encapsulating layer 142 may be greater than or equal to about 2.7 g / cm 3 In an embodiment of the present invention, the film density of the first inorganic encapsulating layer 142 may be less than or equal to about 3.0 g / cm 3 In some embodiments, the film density of the first inorganic encapsulating layer 142 may be less than or equal to about 2.9 g / cm 3 .

[0108] In an embodiment of the present invention, the film density of the second inorganic encapsulating layer 143 may be less than or equal to about 2.1 g / cm 3 The film density of the second inorganic encapsulating layer 143 may be greater than or equal to about 1.7 g / cm 3 In some embodiments, the film density of the second inorganic encapsulating layer 143 may be greater than or equal to about 1.9 g / cm 3 In some embodiments, the film density of the second inorganic encapsulating layer 143 may be greater than or equal to about 2.0 g / cm 3 .

[0109] In an embodiment of the present invention, the film density of the third inorganic encapsulating layer 144 may be greater than or equal to about 2.6 g / cm 3 In some embodiments, the film density of the third inorganic encapsulating layer 144 may be greater than or equal to about 2.7 g / cm 3 In an embodiment of the present invention, the film density of the third inorganic encapsulating layer 144 may be less than or equal to about 3.0 g / cm 3 In some embodiments, the film density of the third inorganic encapsulating layer 144 may be less than or equal to about 2.9 g / cm 3 .

[0110] The encapsulation layer 140 of the display device 10 may include a low-density organic-inorganic hybrid layer 141, a high-density first inorganic encapsulation layer 142, a low-density second inorganic encapsulation layer 143, and a high-density third inorganic encapsulation layer 144, so that the overall thickness of the encapsulation layer 140 is thinned. The first inorganic encapsulation layer 142 may have a relatively high density and a small thickness t2. The thickness t2 of the first inorganic encapsulation layer 142 may be significantly smaller than the thickness t3 of the second inorganic encapsulation layer 143. In an embodiment of the present invention, the thickness t2 of the first inorganic encapsulation layer 142 may be approximately 0.5 nm to 5 nm. Within the above range, the first inorganic encapsulation layer 142 with a high density can be formed within a short tact time.

[0111] The second inorganic encapsulation layer 143 may have a relatively low density and a thick thickness t3. The thickness t3 of the second inorganic encapsulation layer 143 may be significantly greater than the thickness t2 of the first inorganic encapsulation layer 142 and the thickness t4 of the third inorganic encapsulation layer 144. The thickness t3 of the second inorganic encapsulation layer 143 may be greater than the sum of the thickness t2 of the first inorganic encapsulation layer 142 and the thickness t4 of the third inorganic encapsulation layer 144. In an embodiment of the present invention, the thickness t3 of the second inorganic encapsulation layer 143 may be approximately 10nm to 500nm. In some embodiments, the thickness t3 of the second inorganic encapsulation layer 143 may be less than or equal to approximately 300nm. Within the above range, moisture penetration from the outside air can be prevented.

[0112] The third inorganic encapsulation layer 144 may have a relatively high density and a small thickness t4. The thickness t4 of the third inorganic encapsulation layer 144 may be significantly smaller than the thickness t3 of the second inorganic encapsulation layer 143. In an embodiment of the present invention, the thickness t4 of the third inorganic encapsulation layer 144 may be approximately 0.5 nm to 5 nm. Within the above range, the third inorganic encapsulation layer 144 having a high density may be formed within a short tact time.

[0113] The organic-inorganic hybrid layer 141 may have a planarization function and may have a different thickness for each region or location.

[0114] The thickness of the encapsulation layer 140 may be less than or equal to 2 μm. In an embodiment of the present invention, the sum of the thicknesses of the organic-inorganic hybrid layer 141, the first inorganic encapsulation layer 142, the second inorganic encapsulation layer 143, and the third inorganic encapsulation layer 144 (t1+t2+t3+t4) may be less than or equal to about 2 μm. Even when the thickness of the organic-inorganic hybrid layer 141 varies according to the region or position, the thickness of the encapsulation layer 140 including the organic-inorganic hybrid layer 141 may not exceed 2 μm. In an embodiment of the present invention, the sum of the thicknesses of the organic-inorganic hybrid layer 141, the first inorganic encapsulation layer 142, the second inorganic encapsulation layer 143, and the third inorganic encapsulation layer 144 (t1+t2+t3+t4) may be greater than or equal to about 200 nm. In some embodiments, the total thickness of the encapsulation layer 140 may become thinner. Even when the organic-inorganic hybrid layer 141 , the first inorganic encapsulating layer 142 , the second inorganic encapsulating layer 143 , and the third inorganic encapsulating layer 144 have thin thicknesses adjusted within the above range, they may have sufficient encapsulation characteristics.

[0115] The refractive index of the organic-inorganic hybrid layer 141 may be smaller than the refractive index of the first inorganic encapsulation layer 142 and the refractive index of the third inorganic encapsulation layer 144. The refractive index of the organic-inorganic hybrid layer 141 may be the same as or similar to the refractive index of the second inorganic encapsulation layer 143. In an embodiment of the present invention, the refractive index of the organic-inorganic hybrid layer 141 may be smaller than the refractive index of the second inorganic encapsulation layer 143. The refractive index of the first inorganic encapsulation layer 142 may be greater than the refractive index of the organic-inorganic hybrid layer 141 and the refractive index of the second inorganic encapsulation layer 143. The refractive index of the first inorganic encapsulation layer 142 may be the same as or similar to the refractive index of the third inorganic encapsulation layer 144. The refractive index of the second inorganic encapsulation layer 143 may be smaller than the refractive index of the first inorganic encapsulation layer 142 and the refractive index of the third inorganic encapsulation layer 144.

[0116] In an embodiment, the refractive index of the organic-inorganic hybrid layer 141 may be in the range of about 1.75 to 1.90. The refractive index of the first inorganic encapsulation layer 142 may be in the range of about 1.85 to 2.10. The refractive index of the second inorganic encapsulation layer 143 may be in the range of about 1.75 to 1.90. The refractive index of the third inorganic encapsulation layer 144 may be in the range of about 1.85 to 2.10.

[0117] Here, film density and thickness can be measured with an X-ray reflectometer (XRR) (D8 ADVANCE Plus, Bruker). In this specification, optical measuring instruments (such as ellipsometers, spectroscopic reflectometers, etc.) can be used to measure the refractive index. The ellipsometer can measure the refractive index by measuring the change in the polarization of the incident light and the reflected light relative to the inorganic layer and calculating the thickness and complex refractive index of the inorganic layer. The spectroscopic reflectometer can measure the refractive index of the inorganic layer by comparing the intensity of the light obtained by changing the wavelength. The refractive index can be a value measured at room temperature and normal pressure.

[0118] In an embodiment of the present invention, the water vapor transmission rate (WVTR) of the encapsulation layer 140 may be less than or equal to about 5*10 -5 g / m 2 The encapsulation layer 140 may have a four-layer structure, still have the small thickness described above, and have excellent barrier properties.

[0119] As used herein, water vapor transmission rate (WVTR) is a numerical value representing the moisture permeability of the amount of moisture that passes through a specific film or layer per unit area per unit time. Water vapor transmission rate (WVTR) can be measured according to the rules of ASTM F1249. Water vapor transmission rate (WVTR) can be measured using AQUATRAN 2 or AQUATRAN 3 equipment from Mocon.

[0120] The bottom surface of the first inorganic encapsulating layer 142 may be in contact with the top surface of the organic-inorganic hybrid layer 141, and the top surface of the first inorganic encapsulating layer 142 may be in contact with the bottom surface of the second inorganic encapsulating layer 143. For example, the first inorganic encapsulating layer 142 may be disposed between the organic-inorganic hybrid layer 141 and the second inorganic encapsulating layer 143. The bottom surface of the third inorganic encapsulating layer 144 may be in contact with the top surface of the second inorganic encapsulating layer 143. The organic-inorganic hybrid layer 141 may be in contact with the second electrode ET2 (reference Figure 4 ), capping layer or pixel defining layer 131 (reference Figure 4 The third inorganic encapsulation layer 144 may be in contact with the sensor layer or the color filter layer on a top surface thereof.

[0121] The encapsulation layer 140 may further include an organic encapsulation layer in addition to the organic-inorganic hybrid layer 141, the first inorganic encapsulation layer 142, the second inorganic encapsulation layer 143, and the third inorganic encapsulation layer 144. The organic encapsulation layer may include an organic material, and the organic material may include a polymer such as acrylic resin, epoxy resin, polyimide, or polyethylene, but is not necessarily limited thereto.

[0122] The display device 10 may include a color filter layer 150 (see Figure 4 ). The color filter layer 150 may include a plurality of color filters 151, 152, and 153. Each of the plurality of color filters 151, 152, and 153 may include a filter pattern region and a light blocking region. The filter pattern region may overlap with the emission region EA and may form a light exit region in which light emitted from the emission region EA exits. The light blocking region is a region through which light cannot pass due to the stacking of the plurality of color filters 151, 152, and 153.

[0123] The color filters 151, 152, and 153 may include a first color filter 151, a second color filter 152, and a third color filter 153 corresponding to different emission areas EA, respectively. The color filters 151, 152, and 153 may include a colorant (such as a dye or a pigment) that absorbs light of a wavelength band other than a specific wavelength band, and may be set to correspond to the color of the light emitted from the emission area EA. For example, the first color filter 151 may be a red color filter that transmits only the first light, which is red. The second color filter 152 may be a green color filter that transmits only the second light, which is green, and the third color filter 153 may be a blue color filter that transmits only the third light, which is blue. Figure 4 It is illustrated that only the filter pattern area of ​​the second color filter 152 overlaps the emission area EA, but emission areas of other adjacent sub-pixels may overlap the filter pattern area of ​​the first color filter 151 or the filter pattern area of ​​the third color filter 153 .

[0124] When the color filters 151, 152, and 153 are arranged in an overlapping manner, the display device 10 can reduce the intensity of the reflected light caused by the external light. The color of the reflected light caused by the external light can be controlled by adjusting the arrangement, shape, area, etc. of the color filters 151, 152, and 153 in a plan view.

[0125] Outer coating OC (reference Figure 4 ) may be disposed on the color filter layer 150 and flatten the top ends of the color filters 151, 152, and 153. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. For example, the overcoat layer OC may include a colorless light-transmitting organic material such as an acrylic resin.

[0126] Hereinafter, a method of manufacturing the display device 10 will be described with reference to other drawings.

[0127] Figure 6 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the present invention.

[0128] refer to Figure 6 , the manufacturing method of the display device 10 according to the embodiment of the present invention may include: forming a plurality of light emitting elements EL on a substrate (step S10), forming an organic-inorganic hybrid layer 141 on the light emitting element EL (step S20), forming a first inorganic encapsulation layer 142 on the organic-inorganic hybrid layer 141 (step S30), forming a second inorganic encapsulation layer 143 on the first inorganic encapsulation layer 142 (step S40), and forming a third inorganic encapsulation layer 144 on the second inorganic encapsulation layer 143 (step S50).

[0129] Figures 7 to 11 1 and 2 are views sequentially showing a manufacturing process of a display device according to an embodiment of the present invention.

[0130] refer to Figure 7 , a plurality of light emitting elements EL are formed on the substrate 110 (step S10) to form a light emitting element layer 130. A pixel defining layer 131 may be formed on the substrate 110, and a plurality of light emitting elements EL may be formed in the openings of the pixel defining layer 131. The structures of the pixel defining layer 131 and the light emitting element EL are the same as described above. Each of these formation processes may be performed by a typical patterning process, a deposition process, or the like.

[0131] refer to Figure 8 The organic-inorganic hybrid layer 141 may be formed on the light emitting element EL at a first deposition rate v1 (step S20). The step S20 of forming the organic-inorganic hybrid layer 141 may be performed using a plasma chemical vapor deposition (PECVD) process, but is not necessarily limited thereto.

[0132] The step S20 of forming the organic-inorganic hybrid layer 141 may be performed using an organosilicon precursor and / or an aminosilane precursor. Carbon (C) and nitrogen (N) may be derived from an organosilicon precursor and an aminosilane. In an embodiment of the present invention, the organosilicon precursor may include at least one of hexamethyldisiloxane (HMDSO), dimethylaminodimethylsilane (DMADMS), bis(dimethylamino)methylsilane (BDMAMS), hexamethylcyclotrisilazane, hexamethyldisilazane (HMDS), tetraethoxysilane, tetramethylsilane or tetraethylsilane. In an embodiment of the present invention, the aminosilane precursor may include at least one of cyclosilamine, trisilylamine, bis(diethylamino)silane (BDEAS), bis(tert-butylamino)silane (BTBAS), tris(dimethylamino)silane, tris(isopropylamino)silane, tetrakis(dimethylamino)silane, tris(isopropyl)cyclotrisilazane or tetramethyldisilazane, but is not necessarily limited thereto.

[0133] refer to Fig. 9 The first inorganic encapsulating layer 142 may be formed on the organic-inorganic hybrid layer 141 at a second deposition rate v2 (step S30). Step S30 of forming the first inorganic encapsulating layer 142 may be performed using a plasma atomic layer deposition (PEALD) or plasma chemical vapor deposition (PECVD) process.

[0134] refer to Fig.10 The second inorganic encapsulating layer 143 may be formed on the first inorganic encapsulating layer 142 at a third deposition rate v3 (step S40). Step S40 of forming the second inorganic encapsulating layer 143 may be performed using a plasma chemical vapor deposition (PECVD) process, but is not necessarily limited thereto.

[0135] refer to Fig.11 The third inorganic encapsulating layer 144 may be formed on the second inorganic encapsulating layer 143 at a fourth deposition rate v4 (step S50). Step S50 of forming the third inorganic encapsulating layer 144 may be performed using a plasma atomic layer deposition (PEALD) or plasma chemical vapor deposition (PECVD) process.

[0136] Steps S30 to S50 of forming the first inorganic encapsulating layer 142 to the third inorganic encapsulating layer 144 may be performed using an aminosilane precursor having a Si—N bond as a core structure. The aminosilane precursor may include the specific compound of the aminosilane precursor described above in step S20 of forming the organic-inorganic hybrid layer 141.

[0137] In an embodiment of the present invention, the first deposition rate v1 may be greater than the second deposition rate v2 and the fourth deposition rate v4. The third deposition rate v3 may be greater than the second deposition rate v2 and the fourth deposition rate v4. The first deposition rate v1 and the third deposition rate v3 may be the same or different and are greater than or equal to about 30 nm / minute. The second deposition rate v2 and the fourth deposition rate v4 may be the same or different and are less than or equal to about 30 nm / minute. Therefore, the film density of each of the first inorganic encapsulation layer 142 and the third inorganic encapsulation layer 144 may be greater than the film density of each of the organic-inorganic hybrid layer 141 and the second inorganic encapsulation layer 143.

[0138] Fig.12 is a perspective view illustrating a head-mounted display according to an embodiment of the present invention. Fig.13 It is shown Fig.12 An exploded perspective view of an example of a head-mounted display.

[0139] refer to Fig.12 and Fig.13 The head mounted display 1000 according to an embodiment of the present invention includes a first display device 11, a second display device 12, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head strap 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, a control circuit board 1600 and a connector.

[0140] The first display device 11 may provide an image to the left eye of the user, and the second display device 12 may provide an image to the right eye of the user. To the extent that elements such as the first display device 11 and the second display device 12 have not been described in detail, it can be assumed that the elements are at least similar to those already described. Figure 1 The corresponding elements described in .

[0141] The first optical member 1510 may be disposed between the first display device 11 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 12 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0142] The middle frame 1400 may be disposed between the first display device 11 and the control circuit board 1600 and between the second display device 12 and the control circuit board 1600. The middle frame 1400 may support and fix the first display device 11, the second display device 12, and the control circuit board 1600.

[0143] The control circuit board 1600 may be disposed between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 may be connected to the first display device 11 and the second display device 12 through a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data, and may transmit the digital video data to the first display device 11 and the second display device 12 through the connector.

[0144] The control circuit board 1600 may transmit digital video data corresponding to a left-eye image optimized for the user's left eye to the first display device 11, and may transmit digital video data corresponding to a right-eye image optimized for the user's right eye to the second display device 12. Alternatively, the control circuit board 1600 may transmit the same digital video data to the first display device 11 and the second display device 12.

[0145] The display device housing 1100 is used to accommodate the first display device 11, the second display device 12, the middle frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600, and the connector. The housing cover 1200 is arranged to cover one opening surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 and a second eyepiece 1220, where the user's left eye is arranged and the user's right eye is arranged. Fig.12 and Fig.13 The first eyepiece 1210 and the second eyepiece 1220 are illustrated as being separately arranged, but the present disclosure is not necessarily limited thereto. For example, the first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0146] The first eyepiece 1210 may be aligned with the first display device 11 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 12 and the second optical member 1520. Therefore, the user may view the image of the first display device 11 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and may view the image of the second display device 12 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0147] The headband 1300 is used to fix the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 remain arranged on the left eye and the right eye of the user, respectively. When the display device housing 1100 is implemented to be lightweight and compact, the head mounted display 1000 may be provided with a glasses frame instead of the headband 1300, such as Fig.14 as shown in .

[0148] In addition, the head mounted display 1000 may further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0149] Fig.14 is a perspective view illustrating a head mounted display according to an embodiment of the present invention.

[0150] refer to Fig.14 The head mounted display 1000_1 according to an embodiment of the present invention may be a glasses type display device, in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head mounted display 1000_1 according to an embodiment of the present invention may include a display device 13, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path changing member 1070, and a display device housing 1200_1.

[0151] The display device housing 1200_1 may include the display device 13, the optical member 1060, and the optical path changing member 1070. The image displayed on the display device 13 may be magnified by the optical member 1060, and the optical path may be changed by the optical path changing member 1070 to provide the image to the right eye of the user through the right eye lens 1020. As a result, the user may view an augmented reality image through the right eye, in which the virtual image displayed on the display device 13 and the real image viewed through the right eye lens 1020 are combined.

[0152] Fig.14 The display device housing 1200_1 is illustrated as being arranged at the right end of the support frame 1030, but the present disclosure is not necessarily limited thereto. For example, the display device housing 1200_1 may be arranged on the left end of the support frame 1030, and in this case, the image of the display device 13 may be provided to the left eye of the user. In some embodiments, the display device housing 1200_1 may be arranged on both the left and right ends of the support frame 1030, and in this case, the user may view the image displayed on the display device 13 through both the left eye and the right eye.

[0153] In the concluding part of the detailed description, those skilled in the art will appreciate that many variations and modifications can be made to the preferred embodiment without departing substantially from the principles of the present disclosure. Therefore, the disclosed preferred embodiments of the present invention are not intended to be limiting.

Claims

1. A display device, comprising: a light emitting element layer disposed on the substrate and including a plurality of light emitting elements; as well as an encapsulation layer, the encapsulation layer comprising an organic-inorganic hybrid layer arranged on the light-emitting element layer, a first inorganic encapsulation layer arranged on the organic-inorganic hybrid layer, a second inorganic encapsulation layer arranged on the first inorganic encapsulation layer, and a third inorganic encapsulation layer arranged on the second inorganic encapsulation layer, wherein the organic-inorganic hybrid layer comprises silicon, carbon and nitrogen, wherein the first inorganic encapsulation layer, the second inorganic encapsulation layer and the third inorganic encapsulation layer each contain silicon and nitrogen, and The atomic ratio of nitrogen to silicon in the organic-inorganic hybrid layer is greater than the atomic ratio of nitrogen to silicon in the first inorganic encapsulating layer and the atomic ratio of nitrogen to silicon in the third inorganic encapsulating layer.

2. The display device according to claim 1, The film density of the organic-inorganic hybrid layer is smaller than the film density of the first inorganic encapsulating layer, the film density of the second inorganic encapsulating layer, and the film density of the third inorganic encapsulating layer.

3. The display device according to claim 2, wherein the film density of the first inorganic encapsulation layer is greater than the film density of the second inorganic encapsulation layer, and The film density of the first inorganic encapsulating layer is the same as the film density of the third inorganic encapsulating layer.

4. The display device according to claim 1, wherein the organic-inorganic hybrid layer comprises silicon oxycarbon nitride or silicon carbonitride, and The first inorganic encapsulation layer, the second inorganic encapsulation layer and the third inorganic encapsulation layer each contain silicon nitride.

5. The display device according to claim 1, wherein the organic-inorganic hybrid layer comprises an organic portion, and The organic parts are randomly arranged in the organic-inorganic hybrid layer.

6. The display device according to claim 5, The organic part includes at least one of an alkyl group, an alkoxy group and an amine group.

7. The display device according to claim 1, The thickness of the second inorganic encapsulation layer is greater than the thickness of the first inorganic encapsulation layer and the thickness of the third inorganic encapsulation layer.

8. The display device according to claim 1, The refractive index of the organic-inorganic hybrid layer is smaller than the refractive index of the first inorganic encapsulating layer and the refractive index of the third inorganic encapsulating layer.

9. The display device according to claim 1, wherein the bottom surface of the first inorganic encapsulation layer is in contact with the organic-inorganic hybrid layer, A top surface of the first inorganic encapsulation layer contacts the second inorganic encapsulation layer, and A bottom surface of the third inorganic encapsulating layer contacts the second inorganic encapsulating layer.

10. A method for manufacturing a display device, comprising: forming a light emitting element layer including a plurality of light emitting elements on a substrate; forming an organic-inorganic hybrid layer on the light-emitting element layer at a first deposition rate; forming a first inorganic encapsulation layer on the organic-inorganic hybrid layer at a second deposition rate; forming a second inorganic encapsulation layer on the first inorganic encapsulation layer at a third deposition rate; as well as forming a third inorganic encapsulation layer on the second inorganic encapsulation layer at a fourth deposition rate, The first deposition rate is greater than the second deposition rate and the fourth deposition rate, and the third deposition rate is greater than the second deposition rate and the fourth deposition rate.

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