Display device and manufacturing method thereof

Abstract

A display device and a method of manufacturing the same are provided. The display device includes a substrate and pixels disposed on the substrate. The pixel includes a first transistor, a second transistor electrically connected to the first transistor, a third transistor electrically connected to the first transistor, and a light emitting diode element electrically connecting at least one of the first transistor and the third transistor. The first transistor includes a first semiconductor member and a first gate electrode. The first semiconductor member includes an oxide semiconductor material. The first gate electrode is disposed between the first semiconductor member and the substrate. The second transistor includes a second semiconductor member and a second gate electrode. The second semiconductor member includes the oxide semiconductor material. The second semiconductor member is disposed between the second gate electrode and the substrate. The third transistor includes a third semiconductor member including silicon.

Description

[0001] This application is a divisional application of a patent application with an application date of October 22, 2019, application number 201911004172.5, and invention name “Display device and manufacturing method thereof”. Technical Field

[0002] The technical field relates to a display device and a method for manufacturing the display device. Background Art

[0003] An organic light emitting diode (OLED) display device may include pixels for displaying an image. Each of the pixels may include an OLED. An OLED generally includes a cathode, an anode, and an emission layer disposed between the two electrodes. Electrons injected from the cathode and holes injected from the anode may combine in the emission layer to form excitons for emitting light. Each pixel of an OLED display device may include a transistor and a capacitor for driving the corresponding OLED.

[0004] The above information disclosed in this Background section is for enhancement of understanding of the background of the present application. This Background section may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art. Summary of the invention

[0005] Various embodiments may relate to a display device and a method for manufacturing the display device.The display device may include a transistor having predetermined characteristics.

[0006] Embodiments may relate to a display device. The display device may include a substrate and a pixel disposed on the substrate. The pixel may include a first transistor, a second transistor electrically connected to the first transistor, a third transistor electrically connected to the first transistor, and a light emitting diode element electrically connected to at least one of the first transistor and the third transistor. The first transistor may include a first semiconductor component and a first gate electrode. The first gate electrode may be disposed between the first semiconductor component and the substrate. The second transistor may include a second semiconductor component and a second gate electrode. The second semiconductor component may be disposed between the second gate electrode and the substrate. The oxide semiconductor material of the second semiconductor component may be the same as the oxide semiconductor material of the first semiconductor component. The third transistor may include a third semiconductor component including silicon.

[0007] The display device may further include the following elements: a data line configured to transmit a data signal; and an emission control line configured to transmit an emission control signal. The first transistor may be electrically connected to the light emitting diode element. The second transistor may be electrically connected to the data line. The third transistor may be electrically connected to the emission control line.

[0008] The display device may further include a first insulating member. The first transistor includes a first source electrode and a first drain electrode, both of which are disposed on the first semiconductor member. The first surface of the first source electrode may be disposed between the first semiconductor member and the second surface of the first source electrode. The first surface of the first drain electrode may be disposed between the first semiconductor member and the second surface of the first drain electrode. The first surface of the second gate electrode may be disposed between the substrate and the second surface of the second gate electrode. Each of the second surface of the first source electrode, the second surface of the first drain electrode, and the second surface of the second gate electrode may directly contact the first insulating member.

[0009] The light emitting diode element may be electrically connected to the first drain electrode.

[0010] The display device may further include the following elements: a first insulating layer disposed on the substrate; a second insulating layer disposed on the first insulating layer; and a third insulating layer disposed on the second insulating layer. The third transistor further includes a third gate electrode. The third semiconductor component may be disposed between the substrate and the first insulating layer. The third gate electrode may be disposed between the first insulating layer and the second insulating layer. The first face of the first semiconductor component may be disposed between the substrate and the second face of the first semiconductor component. The first face of the second semiconductor component may be disposed between the substrate and the second face of the second semiconductor component. Each of the first face of the first semiconductor component and the first face of the second semiconductor component may directly contact the third insulating layer.

[0011] The first source electrode, the first drain electrode, and the second gate electrode may be disposed between the third insulating layer and the first insulating member.

[0012] The display device may further include the following elements: a connection member connected to the first drain electrode of the first transistor through a contact hole formed in the first insulating member; and a second insulating member disposed on the connection member. The electrode of the light emitting diode element may be connected to the connection member through the contact hole formed in the second insulating member.

[0013] The display device may further include a light blocking layer overlapping the second semiconductor component and disposed between the substrate and the second semiconductor component.

[0014] The display device may further include a driving voltage line configured to transmit a driving voltage. At least one of the first transistor and the third transistor may be electrically connected to the driving voltage line.

[0015] The pixel may further include a storage capacitor electrically connected between the first gate electrode and the light emitting diode element.

[0016] The pixel may further include a fourth transistor electrically connected to the first transistor. The fourth transistor may include a fourth semiconductor component and a fourth gate electrode. The oxide semiconductor material of the fourth semiconductor component may be the same as the oxide semiconductor material of the first semiconductor component. The fourth semiconductor component may be disposed between the substrate and the fourth gate electrode.

[0017] The pixel may further include a voltage holding capacitor. The voltage holding capacitor and the light emitting diode element may be electrically connected in parallel between the first voltage source and the second voltage source.

[0018] The first transistor may be electrically connected between the light emitting diode element and the third transistor.

[0019] The light emitting diode element may be electrically connected to the third transistor.

[0020] Embodiments may relate to a method for manufacturing a display device. The display device may include a pixel. The pixel may include a first transistor, a second transistor, a third transistor, and a light emitting diode element. The method may include the following steps: forming a semiconductor component of the third transistor; forming a first insulating layer on the semiconductor component of the third transistor; forming a gate electrode of the third transistor on the first insulating layer; forming a second insulating layer on the gate electrode of the third transistor; forming a gate electrode of the first transistor on the second insulating layer; forming a third insulating layer on the gate electrode of the first transistor; forming a semiconductor component of the first transistor and a semiconductor component of the second transistor on the third insulating layer; and when forming the gate electrode of the second transistor on the semiconductor component of the second transistor, forming a source electrode of the first transistor and a drain electrode of the first transistor on the semiconductor component of the first transistor.

[0021] The first semiconductor component and the second semiconductor component each include an oxide semiconductor material. The third semiconductor component includes polysilicon.

[0022] The method may further include the following steps: forming a fourth insulating layer on the source electrode of the first transistor, the drain electrode of the first transistor and the gate electrode of the second transistor; forming a connecting member on the fourth insulating layer, wherein the connecting member is connected to the drain electrode of the first transistor through a contact hole of the fourth insulating layer; forming a fifth insulating layer on the connecting member; and forming an electrode of a light emitting diode element on the fifth insulating layer, wherein the electrode of the light emitting diode element is connected to the connecting member through the contact hole of the fifth insulating layer.

[0023] The semiconductor component of the second transistor may include a source electrode of the second transistor and a drain electrode of the second transistor. The semiconductor component of the third transistor may include a source electrode of the third transistor and a drain electrode of the third transistor. After a contact hole exposing the source electrode of the third transistor or the drain electrode of the third transistor has been formed in the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer, a contact hole exposing the source electrode of the second transistor or the drain electrode of the second transistor may be formed in the fourth insulating layer.

[0024] The method may further include: before forming a source electrode of the first transistor, a drain electrode of the first transistor, and a gate electrode of the second transistor and after forming the semiconductor member of the first transistor and the semiconductor member of the second transistor, forming an insulating member on the semiconductor member of the second transistor. The gate electrode of the second transistor may overlap the insulating member.

[0025] The first transistor may be a driving transistor. The second transistor may be a switching transistor. The third transistor may be an emission control transistor. The first transistor may be electrically connected to each of the second transistor and the third transistor. The light emitting diode element may be electrically connected to at least one of the first transistor and the third transistor.

[0026] According to an embodiment, in a pixel of a display device, a switching transistor can have a small leakage current and a high on / off ratio, a driving transistor can have a small hysteresis and a wide driving range, and an emission control transistor can have a high charge mobility and high reliability. In an embodiment, the number of masks required can be minimized when forming a heterogeneous transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a top view schematically showing a display device according to an embodiment.

[0028] Figure 2 According to the embodiment Figure 1 FIG. 4 is an equivalent circuit diagram of a pixel in a display device shown in FIG.

[0029] Figure 3 According to the embodiment along Figure 1 A schematic cross-sectional view taken along line AA' in FIG.

[0030] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 and Fig.14is a schematic diagram showing a Figure 3 0 is a cross-sectional view of a structure formed in a manufacturing process of a display device shown in FIG.

[0031] Fig.15 is a schematic cross-sectional view of a display device according to an embodiment.

[0032] Fig.16 is a schematic cross-sectional view of a display device according to an embodiment.

[0033] Fig.17 is an equivalent circuit diagram of one pixel in the display device according to the embodiment.

[0034] Fig.18 is an equivalent circuit diagram of one pixel in the display device according to the embodiment.

[0035] Fig.19 is an equivalent circuit diagram of one pixel in the display device according to the embodiment. DETAILED DESCRIPTION

[0036] Example embodiments are described with reference to the accompanying drawings. As those skilled in the art will appreciate, the described embodiments can be modified in various ways.

[0037] In the specification, the same reference numerals may denote the same elements. In the drawings, the thickness or size of layers and regions may be exaggerated or reduced to clearly illustrate arrangements and relative positions.

[0038] Although the terms "first", "second", etc. can be used here to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish one element from another element. Therefore, without departing from the teaching of one or more embodiments, the first element can be named as the second element. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used here to distinguish different categories or sets of elements. For simplicity, the terms "first", "second", etc. can respectively represent "first type (or first set)", "second type (or second set)", etc.

[0039] When a first element is referred to as being “on” a second element, the first element may be directly on the second element, or one or more intervening elements may be present between the first and second elements. When a first element is referred to as being “directly on” a second element, no intervening elements are expected to be present between the first and second elements (except for environmental elements such as air).

[0040] Unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” may imply the inclusion of stated elements but not the exclusion of any other elements.

[0041] In the drawings, reference character x is used to indicate a first direction, reference character y is used to indicate a second direction perpendicular to the first direction, and reference character z is used to indicate a third direction perpendicular to the first and second directions.

[0042] The term “connected” may mean “electrically connected”; the term “insulated” may mean “electrically isolated”; the term “grayscale” may mean “grayscale”.

[0043] Figure 1 is a top view schematically showing a display device according to an embodiment.

[0044] Reference Figure 1 , the display device includes a display panel 10, a flexible printed circuit film 20 connected to the display panel 10, a driving unit including an integrated circuit chip 30, and the like.

[0045] The display panel 10 includes a display area DA corresponding to a screen in which an image is displayed. The display panel 10 also includes a non-display area NA in which a circuit for generating a signal and / or a signal line for transmitting a signal to the display area DA is disposed. The non-display area NA may be adjacent to and / or surround the display area DA.

[0046] The pixels PX are arranged in the display area DA of the display panel 10. Signal lines such as scan lines (i.e., gate lines), emission control lines, data lines, driving voltage lines, etc. are also arranged in the display area DA. Each pixel PX is connected to the scan lines, emission control lines, data lines, and driving voltage lines, thereby receiving scan signals (i.e., gate signals), emission control signals, data signals, and driving voltages from these signal lines.

[0047] The display area DA may include a touch sensor layer for sensing a user's contact or non-contact touch. The display area DA may have a Figure 1 , but may have one or more of other shapes such as a polygonal shape, a circular shape, and an elliptical shape.

[0048] A pad portion PP (formed with a pad for receiving a signal from the outside of the display panel 10) is provided in the non-display area NA of the display panel 10. The pad portion PP may extend along one edge of the display panel 10 in the first direction x. The flexible printed circuit film 20 is bonded to the pad portion PP, and the pad of the flexible printed circuit film 20 may be electrically connected to the pad of the pad portion PP.

[0049] A driving unit for generating and / or processing various signals for driving the display panel 10 is disposed in the non-display area NA of the display panel 10. The driving unit may include the following elements: a data driver for applying a data signal to a data line; a scan driver for applying a scan signal to a scan line; an emission driver for applying an emission control signal to an emission control line; and a signal controller for controlling the data driver, the scan driver, and the emission driver. The scan driver and the emission driver may be integrated on the display panel 10 and may be disposed on opposite sides or one side of the display area DA. The data driver and the signal controller may be disposed in an integrated circuit chip (referred to as a driver IC chip) 30, and the integrated circuit chip 30 may be mounted to the non-display area NA of the display panel 10. The integrated circuit chip 30 may be mounted on a flexible printed circuit film connected to the display panel 10 to be electrically connected to the display panel 10.

[0050] The display panel 10 may include a bending region BR. The bending region BR may be disposed in a non-display region NA between the display area DA and the pad portion PP. The bending region BR may span the display panel 10 in a first direction x. The display panel 10 may be bent with a predetermined radius of curvature based on a bending axis corresponding to the bending region BR. When the display panel 10 is a top emission type, the display panel 10 may be bent so that the pad portion PP and the flexible printed circuit film 20 will be located behind the display panel 10. The bending region BR may be bent based on one bending axis or multiple bending axes. In an embodiment, the bending region BR may span the display area DA and the non-display area NA or may be disposed in the display area DA.

[0051] Figure 2 According to the embodiment Figure 1 FIG. 4 is an equivalent circuit diagram of a pixel in a display device shown in FIG.

[0052] Reference Figure 2 , the pixel PX includes a plurality of transistors (T1, T2, and T3), a storage capacitor SC, and a light emitting diode element LD. Signal lines DL, GL, EL, DVL, and CVL are connected to the pixel PX.

[0053] The signal lines DL, GL, EL and DVL may include a data line DL, a scan line GL, an emission control line EL and a driving voltage line DVL. The scan line GL may transmit a scan signal GW to the second transistor T2. The emission control line EL may transmit an emission control signal EM to the third transistor T3. The data line DL may transmit a data signal DS. The driving voltage line DVL may transmit a driving voltage ELVDD.

[0054] The transistors T1, T2 and T3 include a first transistor T1 (driving transistor), a second transistor T2 (switching transistor) and a third transistor T3 (emission control transistor). The transistors T1, T2 and T3 include gate electrodes G1, G2 and G3, respectively, source electrodes S1, S2 and S3, respectively, and drain electrodes D1, D2 and D3, respectively.

[0055] The gate electrode G1 of the first transistor T1 is connected to the first electrode E1 of the storage capacitor SC and the drain electrode D2 of the second transistor T2, the source electrode S1 of the first transistor T1 is connected to the drain electrode D3 of the third transistor T3, and the drain electrode D1 of the first transistor T1 is connected to the anode of the light emitting diode element LD. The first transistor T1 can drive the current I (depending on the size / value of the data signal DS transmitted through the second transistor T2) D is supplied to the light emitting diode element LD, and the light emitting diode element LD can be driven by a current depending on the driving current I D The brightness of the pixel PX is emitted by the size / value of the data signal DS. Therefore, the pixel PX can display the brightness in accordance with the gray scale specified by the data signal DS. The driving current I D The gate-source voltage V GS As the gate-source voltage V GS Increase, drive current I D Can be enlarged.

[0056] A gate electrode G2 of the second transistor T2 is connected to the scan line GL, a source electrode S2 of the second transistor T2 is connected to the data line DL, and a drain electrode D2 of the second transistor T2 is connected to the gate electrode G1 of the first transistor T1 and the first electrode E1 of the storage capacitor SC. The second transistor T2 is turned on according to the scan signal GW transmitted through the scan line GL, thereby performing a switching operation in which a data signal DS transmitted through the data line DL is transmitted to the gate electrode G1 of the first transistor T1 and the first electrode E1 of the storage capacitor SC.

[0057] The gate electrode G3 of the third transistor T3 is connected to the emission control line EL, the source electrode S3 of the third transistor T3 is connected to the driving voltage line DVL, and the drain electrode D3 of the third transistor T3 is connected to the source electrode S1 of the first transistor T1. The third transistor T3 is turned on according to the emission control signal EM transmitted through the emission control line EL, thereby controlling the current to flow through the first transistor T1. If the third transistor T3 is turned on, the driving current I D According to the size of the data signal DS, a driving current I D The light is supplied to the light emitting diode element LD, so that the light emitting diode element LD emits light.

[0058] A first electrode E1 of the storage capacitor SC is connected to the gate electrode G1 of the first transistor T1 and the drain electrode D2 of the second transistor T2, and a second electrode E2 of the storage capacitor SC is connected to the drain electrode D1 of the first transistor T1 and the anode of the light emitting diode element LD. During the emission period, the storage capacitor SC may continuously apply the data signal DS to the first transistor T1 to continuously activate the light emitting diode element LD. The cathode of the light emitting diode element LD may be connected to a common voltage line CVL for receiving a common voltage ELVSS.

[0059] The first transistor T1 and the second transistor T2 are NMOS (n-channel metal oxide semiconductor) transistors. The third transistor T3 is a PMOS (p-channel metal oxide semiconductor) transistor or an NMOS transistor. Each of the first transistor T1 and the second transistor T2 may include an oxide semiconductor member and may be referred to as an "oxide transistor". The oxide semiconductor may include one or more oxides of one or more metals. The one or more metals may include one or more of zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) and combinations thereof. For example, the oxide semiconductor may include at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), and indium zinc tin oxide (IZTO). The first transistor T1 may be a bottom gate oxide transistor, and the second transistor T2 may be a top gate oxide transistor. The third transistor T3 may include a polysilicon semiconductor member and may be referred to as a "silicon transistor".

[0060] According to an embodiment, a bottom-gate oxide transistor with small hysteresis and a wide driving range is used as a driving transistor. A top-gate oxide transistor with low leakage current and high on / off ratio is used as a switching transistor. A silicon transistor with high charge mobility is used as an emission control transistor. Because the driving range is large, the gate voltage VG of the first transistor T1 can be desirably changed to finely control the gray scale of the light emitted from the light-emitting diode element LD, thereby improving the display quality of the display device. Because the leakage current is small, the occurrence of flicker can be minimized even under low-frequency driving, thereby reducing power consumption. Because the driving transistor is a bottom-gate oxide transistor, the degradation of the characteristics of the driving transistor (for example, the shift of the threshold voltage Vth of the driving transistor) can be minimized because the gate electrode can block the light incident on the oxide semiconductor. Because the emission control transistor must be turned on during a relatively long emission period to stably transmit current, a silicon transistor with high reliability is advantageous.

[0061] Figure 3 According to the embodiment along Figure 1 A schematic cross-sectional view taken along line AA' in FIG.

[0062] The display panel 10 includes a substrate 110 on which wiring and elements are formed. A large number of pixels PX are arranged in a display area DA of the display panel 10. As an example, referring to Figure 1 , Figure 2 and Figure 3 One pixel PX is described and shown.

[0063] The substrate 110 may include Figure 1 The display area DA and the non-display area NA of the display panel 10 shown in FIG. 1 correspond to the display area and the non-display area. The substrate 110 may be a flexible substrate. The substrate 110 may be made of a polymer such as polyimide, polyamide, polycarbonate, or polyethylene terephthalate. The substrate 110 may be made of glass, quartz, ceramic, etc.

[0064] The barrier layer 111 for preventing moisture from penetrating from the outside is disposed on the substrate 110. The barrier layer 111 may include, for example, silicon oxide (SiO x ) or silicon nitride (SiN x ) of inorganic insulating materials.

[0065] The buffer layer 120 is disposed on the barrier layer 111. The buffer layer 120 may block impurities that may diffuse from the substrate 110 during a crystallization process for forming polysilicon and may reduce stress applied to the substrate 110. The buffer layer 120 may include an inorganic insulating material such as silicon oxide and / or silicon nitride.

[0066] The semiconductor component A3 of the third transistor T3 may be disposed on the buffer layer 120, the semiconductor component A3 including a source electrode S3, a drain electrode D3, and a channel C3 of the third transistor T3. The semiconductor component A3 includes polysilicon.

[0067] A first insulating layer 140 including an inorganic insulating material such as silicon oxide and / or silicon nitride is disposed on the semiconductor member A3. The first insulating layer 140 may be referred to as a first gate insulating layer.

[0068] A gate conductor group including a gate electrode G3 of the third transistor T3 and a second electrode E2 of the storage capacitor SC is disposed on the first insulating layer 140. The gate conductor group may include a metal such as molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), or titanium (Ti), or a metal alloy thereof. The emission control line EL may be directly disposed on the same first insulating layer 140 as the gate electrode G3.

[0069] The second insulating layer 141 is disposed on the first insulating layer 140 and the gate conductor group. The second insulating layer 141 may include an inorganic insulating material such as silicon oxide and / or silicon nitride, and may be referred to as a second gate insulating layer.

[0070] The gate electrode G1 of the first transistor T1 is disposed on the second insulating layer 141. The gate electrode G1 may also be (and / or function as) a first electrode E1 of the storage capacitor SC. The gate electrode G1 may include a metal such as molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), or titanium (Ti), or a metal alloy thereof.

[0071] The third insulating layer 160 is disposed on the second insulating layer 141 and the gate electrode G1. The third insulating layer 160 may include an inorganic insulating material such as silicon oxide and / or silicon nitride, and may be referred to as a first interlayer insulating layer.

[0072] The semiconductor component A1 of the first transistor T1 and the semiconductor component A2 of the second transistor T2 are disposed on the third insulating layer 160. In the semiconductor component A1, a portion not covered by any one of the source electrode S1 and the drain electrode D1 may form a channel C1 of the first transistor T1. The semiconductor component A2 includes a source electrode S2, a drain electrode D2, and a channel C2 of the second transistor T2. The semiconductor component A1 and the semiconductor component A2 include the same oxide semiconductor material.

[0073] The source electrode S1 and the drain electrode D1 of the first transistor T1 are (directly) disposed on the semiconductor component A1. The insulating member 142 and the gate electrode G2 of the second transistor T2 are sequentially disposed on the semiconductor component A2. The insulating member 142 may include an inorganic insulating material such as silicon oxide and / or silicon nitride. Each of the source electrode S1 of the first transistor T1, the drain electrode D1 of the first transistor T1, and the gate electrode G2 of the second transistor T2 may include at least one of molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), titanium (Ti), etc., and / or may have a multilayer structure such as a structure including titanium (Ti) and molybdenum (Mo). The titanium layer may prevent impurities (such as hydrogen) from penetrating into the semiconductor components A1 and A2 during the manufacturing process. The scanning line GL that transmits the scanning signal GW may be formed by the same (multiple) material layers as the gate electrode G2.

[0074] Semiconductor component A1 (including channel C1), source electrode S1, drain electrode D1 and gate electrode G1 form a first transistor T1. Semiconductor component A2 including channel C2, source electrode S2, drain electrode D2 and gate electrode G2 forms a second transistor T2. Semiconductor component A3 including channel C3, source electrode S3, drain electrode D3 and gate electrode G3 forms a third transistor T3. The first transistor T1 is a bottom-gate oxide transistor, the second transistor T2 is a top-gate oxide transistor, and the third transistor T3 is a top-gate silicon transistor.

[0075] If a top-gate oxide transistor is used as a driving transistor, undesirable stains due to uneven brightness may occur because the driving range is narrow. If a bottom-gate oxide transistor is used as a switching transistor, the on-current may be undesirably low due to the third insulating layer 160 which is thinner than the insulating member 142; if the width of the transistor is increased to improve the on-current, the transistor configuration may not be suitable for a high-resolution display device. For example, the thickness of the insulating member 142 may be in the range of about 1000 angstroms to about 2000 angstroms, and the thickness of the third insulating layer 160 may be about 3000 angstroms or more. According to an embodiment, a bottom-gate oxide transistor (first transistor T1) may be used as a driving transistor to widen the driving range of the driving transistor, and a top-gate oxide transistor (second transistor T2) may be used as a switching transistor to increase the on / off ratio of the switching transistor. In an embodiment, a third transistor T3 having high charge mobility and being stable is used as an emission control transistor, thereby reliably transmitting current and / or voltage from the driving voltage line DVL to the first transistor T1. The total number of masks and the total number of process steps may be reduced by forming the source electrode S1 of the first transistor T1 , the drain electrode D1 of the first transistor T1 , and the gate electrode G2 of the second transistor T2 using the same material layer.

[0076] The fourth insulating layer 161 is disposed on the source electrode S1, the drain electrode D1, and the gate electrode G2. The fourth insulating layer 161 may include an inorganic insulating material such as silicon oxide and / or silicon nitride, and may be referred to as a second interlayer insulating layer. The fourth insulating layer 161 may cover the lateral sides of the insulating member 142 and the sides of the gate electrode G2.

[0077] The connection members CM1 to CM6 are disposed on and through the fourth insulating layer 161. The connection members CM1 to CM6 may include a connection member CM1 and a connection member CM2 connected to the drain electrode D1 and the source electrode S1 through contact holes H1 and H2 formed in the fourth insulating layer 161, respectively, may include a connection member CM3 and a connection member CM4 connected to the drain electrode D2 and the source electrode S2 through contact holes H3 and H4 formed in the fourth insulating layer 161, respectively, and may include a connection member CM5 and a connection member CM6 connected to the drain electrode D3 and the source electrode S3 through contact holes H5 and H6 formed in the fourth insulating layer 161, the third insulating layer 160, the second insulating layer 141, and the first insulating layer 140, respectively.

[0078] The connection member CM1 may be electrically connected to the second electrode E2 of the storage capacitor SC, and the connection member CM2 may be electrically connected to the connection member CM5. The connection member CM3 may be electrically connected to the gate electrode G1 of the first transistor T1, and the connection member CM4 may be electrically connected to the data line DL. The connection member CM6 may be electrically connected to the driving voltage line DVL. The data line DL and / or the driving voltage line DVL may be formed of the same (multiple) material layers as the connection members CM1 to CM6.

[0079] The connection members CM1 to CM6 may include a metal or a metal alloy of at least one of aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), molybdenum (Mo), titanium (Ti), chromium (Cr), tantalum (Ta), etc. The connection members CM1 to CM6 may have a multilayer structure such as a titanium-aluminum-titanium structure, a titanium-copper-titanium structure, or a molybdenum-aluminum-titanium structure.

[0080] The fifth insulating layer 180 is disposed on the fourth insulating layer 161 and the connection members CM1 to CM6. The fifth insulating layer 180 may include an organic insulating material such as polyimide, acrylic polymer, or siloxane polymer. The fifth insulating layer 180 may be referred to as a passivation layer or a planarization layer.

[0081] The pixel electrode PE of the light emitting diode element LD is disposed on the fifth insulating layer 180. The pixel electrode PE is connected to the connection member CM1 through a contact hole H7 formed in the fifth insulating layer 180. Since the connection member CM1 is connected to the drain electrode D1 of the first transistor T1, the pixel electrode PE may be electrically connected to the drain electrode D1. The pixel electrode PE may include a metal or metal alloy of at least one of silver (Ag), nickel (Ni), gold (Au), platinum (Pt), aluminum (Al), copper (Cu), aluminum neodymium (AlNd), aluminum nickel lanthanum (AlNiLa), etc. The pixel electrode PE may include a transparent conductive material such as at least one of indium tin oxide (ITO), indium zinc oxide (IZO), etc. The pixel electrode PE may have a multilayer structure such as an ITO-silver (Ag)-ITO structure or an ITO-aluminum (Al) structure.

[0082] An insulating layer 360 having an opening exposing the pixel electrode PE is disposed on the fifth insulating layer 180. The insulating layer 360 may be referred to as a pixel defining layer, and the opening may define a pixel region. The insulating layer 360 may include an organic insulating material.

[0083] The emission layer LL is disposed on the pixel electrode PE, and the common electrode CE is disposed on the emission layer LL. The emission layer LL may be an organic emission layer including a low molecular organic material or a polymer organic material. The common electrode CE is thinly formed of one or more stacked metals having a low work function (such as one or more of calcium (Ca), barium (Ba), magnesium (Mg), aluminum (Al), silver (Ag), etc.) to have a light-transmitting property. The common electrode CE may be formed of a transparent conductive material such as ITO and / or IZO.

[0084] The pixel electrode PE, the emission layer LL and the common electrode CE of each pixel PX form a light emitting diode element LD such as an organic light emitting diode. The pixel electrode PE may be an anode (which is a hole injection electrode), and the common electrode CE may be a cathode (which is an electron injection electrode). According to a driving method of the display device, the pixel electrode PE may be a cathode and the common electrode CE may be an anode.

[0085] The encapsulation layer 400 is disposed on the common electrode CE. The encapsulation layer 400 seals the light emitting diode element LD to prevent moisture or oxygen from penetrating from the outside. The encapsulation layer 400 may include at least one inorganic layer and at least one organic layer.

[0086] A polarizing layer may be disposed on the encapsulation layer 400 to reduce external reflection, and a touch sensor layer including a touch electrode for sensing a touch may be disposed between the encapsulation layer 400 and the polarizing layer.

[0087] Parts of the barrier layer 111, the buffer layer 120, the first insulating layer 140, the second insulating layer 141, the third insulating layer 160, and the fourth insulating layer 161 (which may include one or more inorganic insulating materials) may be removed in the bending region BR. The inorganic insulating layer may be easily cracked during bending.

[0088] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 and Fig.14 is a schematic diagram showing a Figure 3 0 is a cross-sectional view of a structure formed in a manufacturing process of a display device shown in FIG.

[0089] Reference Figure 4 , one or more inorganic insulating materials are deposited on the substrate 110 by one or more chemical vapor deposition (CVD) processes to form a barrier layer 111 and a buffer layer 120. Next, amorphous silicon is deposited on the buffer layer 120 by a CVD process to form an amorphous silicon layer, the amorphous silicon layer is crystallized to form a polycrystalline silicon layer, and the polycrystalline silicon layer is patterned by a photolithography process using a first mask to form a semiconductor member A3.

[0090] Reference Figure 5 , an inorganic insulating material is deposited to form a first insulating layer 140. Next, a conductive material such as a metal is deposited on the first insulating layer 140 by a sputtering method to form a conductive layer, and the conductive layer is patterned by a photolithography process using a second mask to form a gate electrode G3 of the third transistor T3 and a second electrode E2 of the storage capacitor SC. The emission control line EL may be formed of the same material in the same process as the gate electrode G3. Then, the semiconductor member A3 is subjected to ion doping and activation treatment by using the gate electrode G3 as a mask to form a source electrode S3 and a drain electrode D3 having low resistance.

[0091] Reference Figure 6 The second insulating layer 141 is formed by depositing an inorganic insulating material. A conductive layer is formed on the second insulating layer 141 from a conductive material and patterned by a photolithography process using a third mask to form a gate electrode G1 of the first transistor T1. The gate electrode G1 may also be a first electrode E1 of the storage capacitor SC.

[0092] Reference Figure 7The third insulating layer 160 is formed by depositing an inorganic insulating material. An oxide semiconductor material is deposited on the third insulating layer 160 by a CVD process to form an oxide semiconductor layer, and the oxide semiconductor layer is patterned by a photolithography process using a fourth mask to form semiconductor components A1 and A2.

[0093] Reference Figure 8 , an inorganic insulating material is deposited to form an insulating layer, and patterning is performed using a photolithography process using a fifth mask to form the insulating member 142 .

[0094] Reference Fig. 9 , a conductive layer is formed by depositing a conductive material, and the conductive layer is patterned by a photolithography process using a sixth mask to form a source electrode S1 of the first transistor T1, a drain electrode D1 of the first transistor T1, and a gate electrode G2 of the second transistor T2. The scan line GL may be formed of the same material in the same process as the gate electrode G2. Subsequently, the exposed portion of the semiconductor component A2 that is not covered by the insulating member 142 may be processed to form the source electrode S2 and the drain electrode D2. As a processing method, at least one of a plasma treatment method, a heat treatment method in a reducing atmosphere, and the like may be used. For example, plasma treatment may be performed in a hydrogen atmosphere or a fluorine atmosphere. As a result, hydrogen or fluorine diffuses in the exposed portion of the semiconductor component A2 that is not covered by the insulating member 142, so that the exposed portion becomes conductive. The portion of the semiconductor component A2 covered by the insulating member 142 mostly retains semiconductor properties to form a channel C2. Plasma treatment may be performed using a mask (e.g., a photosensitive film pattern is formed to expose only the portion of the semiconductor component A2 designated as the source electrode S2 and the drain electrode D2), so that the semiconductor component A1 is not affected. Can be Figure 8 The step shown in FIG. 1 is performed after forming the insulating member 142 by doping the semiconductor member A2 to form the source electrode S2 and the drain electrode D2.

[0095] Reference Fig.10 , an inorganic insulating material is deposited to form a fourth insulating layer 161. Next, the first to fourth insulating layers 140, 141, 160, and 161 are patterned using a seventh mask to form contact holes H5 and H6 that expose the drain electrode D3 and the source electrode S3 of the third transistor T3. In the same process step, the fourth insulating layer 161 is patterned using the same seventh mask to form contact holes H1 and H2 that expose the drain electrode D1 and the source electrode S1 of the first transistor T1. In the same process step, portions of the first to fourth insulating layers 140, 141, 160, and 161 may be removed in the bending region BR. After the contact holes H5 and H6 are formed, an etchant may be used to remove the oxide film formed on the surface of the semiconductor component A3.

[0096] Reference Fig.11 , the fourth insulating layer 161 is patterned by a photolithography process using an eighth mask to form contact holes H3 and H4 that expose the drain electrode D2 and the source electrode S2 of the second transistor T2. In the same process step, portions of the blocking layer 111 and the buffer layer 120 can be removed from the bending region BR. The reason for forming the contact holes H3 and H4 using a separate eighth mask instead of the seventh mask (used to form the contact holes H5 and H6) is that if the contact holes H3, H4, H5, and H6 are formed in the same process step, then when the oxide layer on the surface of the semiconductor component A3 is etched through the contact holes H5 and H6, the etchant will etch or damage the semiconductor component A2 through the contact holes H3 and H4. In an embodiment, the contact holes H1 and H2 may not be formed in the same step as the contact holes H5 and H6, but may be formed in the same step as the contact holes H3 and H4.

[0097] Reference Fig.12 , a conductive layer is formed by depositing a conductive material on the fourth insulating layer 161, and the conductive layer is patterned by a photolithography process using a ninth mask to form connection members CM1 to CM6 connected to the source electrode S1 and the drain electrode D1 of the first transistor T1, the source electrode S2 and the drain electrode D2 of the second transistor T2, and the source electrode S3 and the drain electrode D3 of the third transistor T3. In this process step, the connection member CM2 and the connection member CM5 may be formed to be connected to each other. The data line DL and the driving voltage line DVL may be formed of the same material in the same process as the connection members CM1 to CM6. The connection member CM4 may be a part of the data line DL, and the connection member CM6 may be a part of the driving voltage line DVL.

[0098] Reference Fig.13 , an organic insulating material is deposited to form a fifth insulating layer 180 , and the fifth insulating layer 180 is patterned using a tenth mask to form a contact hole H7 exposing the connection member CM1 .

[0099] Reference Fig.14 A conductive layer is formed by depositing a conductive material on the fifth insulating layer 180 and patterning the conductive layer through a photolithography process using an eleventh mask to form a pixel electrode PE. The pixel electrode PE is connected to the connection member CM1 through a contact hole H7.

[0100] As a subsequent process, refer to Figure 3 , an organic insulating material is deposited on the pixel electrode PE to form an insulating layer 360, and the insulating layer 360 is patterned using a twelfth mask to form an opening exposing the pixel electrode PE. Next, an emission layer LL and a common electrode CE are formed, and then an encapsulation layer 400 is formed to manufacture Figure 3 The display device shown in FIG. Fig.15is a schematic cross-sectional view of a display device according to an embodiment. Fig.16 is a schematic cross-sectional view of a display device according to an embodiment. Fig.15 and Fig.16 The embodiment shown in FIG. Figure 3 The differences between the embodiments are described above, and the description of the same configuration may not be repeated.

[0101] Reference Fig.15 , the driving voltage line DVL is disposed on the fifth insulating layer 180, and the sixth insulating layer 181 is disposed on the driving voltage line DVL. The driving voltage line DVL may be connected to the source electrode S3 of the third transistor T3 through a contact hole H8 formed in the fifth insulating layer 180. In order to electrically connect the pixel electrode PE and the connection member CM1, the connection member CM7 is connected to the connection member CM1 through the contact hole H7 formed in the fifth insulating layer 180, and the pixel electrode PE is connected to the connection member CM7 through the contact hole H9 formed in the sixth insulating layer 181.

[0102] In order to increase the resolution of the display device, the driving voltage line DVL may overlap with the data line DL disposed on the same layer as the connection members CM1 to CM6, so that the area / area occupied by the wiring in the display device may be reduced. If the driving voltage line DVL is formed not only on the same layer as the connection members CM1 to CM6 but also on the same layer as the connection member CM7, the driving voltage line DVL may include at least two wirings in at least two different material layers, and the resistance of the driving voltage line DVL may be reduced. The driving voltage line DVL and the connection member CM7 may include a metal or metal alloy of at least one of aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), and molybdenum (Mo), may include a metal or metal alloy of at least one of tungsten (W), titanium (Ti), chromium (Cr), and tantalum (Ta), and may have a multilayer structure. The sixth insulating layer 181 may include an organic insulating material.

[0103] Reference Fig.16 The light blocking layer LB overlapped with the semiconductor component A2 of the second transistor T2 is provided between the semiconductor component A2 and the substrate 110. Since the second transistor T2 is a top gate transistor, light incident from the bottom of the display panel 10 is not blocked by the gate electrode G2. By forming the light blocking layer LB, it is possible to prevent external light from reaching the semiconductor component A2, especially the channel C2, thereby preventing the characteristics of the semiconductor component A2 from being degraded and controlling the leakage current of the second transistor T2.

[0104] The light blocking layer LB may be disposed between the second insulating layer 141 and the third insulating layer 160 as shown. In an embodiment, the light blocking layer LB may be formed of the same material in the same process as the gate electrode G1 of the first transistor T1. Alternatively or additionally, the light blocking layer LB may be disposed between the first insulating layer 140 and the second insulating layer 141; in an embodiment, the light blocking layer LB may be formed of the same material in the same process as the gate electrode G3 of the third transistor T3. In either case, no additional mask is required to form the light blocking layer LB.

[0105] Fig.17 , Fig.18 and Fig.19 Each of the diagrams shows an equivalent circuit diagram of one pixel in the display device according to the embodiment. Fig.17 , Fig.18 and Fig.19 The embodiments of the present invention mainly describe Figure 2 The differences between the embodiments are described above, and the description of the same configuration may not be repeated.

[0106] Reference Fig.17 , the structure of connecting the third transistor T3 as the emission control transistor with Figure 2 Specifically, the third transistor T3 is connected between the first transistor T1 and the light emitting diode element LD. Therefore, the first transistor T1 as a driving transistor is connected to the driving voltage line DVL. If the third transistor T3 is turned on according to the emission control signal EM during the emission period, the driving current I D (which depends on the data signal DS) is supplied to the light emitting diode element LD, and thus the light emitting diode element LD can emit light during the emission period to display a predetermined gray scale. The types and stacking structures of the first to third transistors T1, T2, and T3 can be the same as Figure 2 and Figure 3 The same or similar to those shown in .

[0107] Reference Fig.18 , pixel PX and Figure 2The embodiment of the present invention is different in that at least a fourth transistor T4 connected to the drain electrode D1 of the first transistor T1 is further included. The gate electrode G4 of the fourth transistor T4 is connected to the sensing control line CL, the source electrode S4 of the fourth transistor T4 is connected to the drain electrode D1 of the first transistor T1 and the anode of the light emitting diode element LD, and the drain electrode D4 of the fourth transistor T4 is connected to the sensing line SL. The fourth transistor T4 is a sensing transistor for sensing characteristics such as the threshold voltage Vth of the first transistor T1 that may affect the image quality. As the fourth transistor T4 is turned on in response to the sensing signal SS transmitted through the sensing control line CL, the first transistor T1 and the sensing line SL are electrically connected, and the sensing unit connected to the sensing line SL can sense the characteristic information of the first transistor T1 during the sensing period. Because the characteristic information sensed by the fourth transistor T4 during the sensing period is reflected to generate the compensation data signal, the characteristic deviation of the first transistor T1 that may be different for each pixel PX can be compensated externally.

[0108] The fourth transistor T4 may be an oxide transistor and may have Figure 3 The fourth transistor T4 may include a gate electrode disposed on a semiconductor component (the semiconductor component includes an oxide semiconductor material of the semiconductor component A2). A top-gate oxide transistor with a small leakage current and a high on / off ratio may be used as a sensing transistor to maximize sensing accuracy.

[0109] Reference Fig.19 , pixel PX and Fig.18 The embodiment of the present invention is different in that at least a capacitor RC is included. The capacitor RC and the light emitting diode element LD are electrically connected in parallel between the driving voltage line DVL (having the driving voltage ELVDD) and the common voltage line CVL (having the common voltage ELVSS). One electrode of the capacitor RC is connected to the anode of the light emitting diode element LD, and the other electrode of the capacitor RC is connected to the cathode of the light emitting diode element LD. The capacitor RC can enhance the ability to maintain the anode voltage.

[0110] Although example embodiments have been described, embodiments that can be practiced are not limited to the described embodiments. Embodiments that can be practiced are intended to cover various modifications and equivalent arrangements within the scope of the claims.

Claims

1. A display device, comprising: substrate; a driving transistor comprising a first semiconductor layer and a first gate electrode, wherein the first semiconductor layer comprises an oxide semiconductor material, and the first gate electrode is disposed between the substrate and the first semiconductor layer; a switching transistor electrically connected to the driving transistor and comprising a second semiconductor layer and a second gate electrode, the second semiconductor layer comprising an oxide semiconductor material and disposed between the substrate and the second gate electrode; as well as An emission control transistor is electrically connected to the driving transistor and includes a third semiconductor layer and a third gate electrode, the third semiconductor layer including polysilicon and disposed between the substrate and the third gate electrode.

2. The display device according to claim 1, further comprising: a driving voltage line configured to transmit a driving voltage, The emission control transistor is electrically connected between the driving transistor and the driving voltage line.

3. The display device according to claim 1, further comprising: a light emitting diode, electrically connected to the emission control transistor, Wherein, the emission control transistor is electrically connected between the driving transistor and the light emitting diode.

4. The display device according to claim 1, wherein: The driving transistor includes a first source electrode and a first drain electrode, the switching transistor includes a second source electrode and a second drain electrode, and the emission control transistor includes a third source electrode and a third drain electrode, The display device further includes a first connection member connected to one of the first source electrode and the first drain electrode, a second connection member connected to one of the second source electrode and the second drain electrode, and a third connection member connected to one of the third source electrode and the third drain electrode, and The first connection member, the second connection member, and the third connection member are formed as a same layer.

5. The display device according to claim 1, further comprising: a light blocking layer, disposed between the substrate and the second semiconductor layer, Wherein, the second semiconductor layer is stacked with the light blocking layer, and Wherein, the first gate electrode and the light blocking layer are formed as a same layer.

6. The display device according to claim 1, further comprising: a capacitor electrode disposed between the substrate and the first gate electrode, wherein the first gate electrode overlaps the capacitor electrode, and The third gate electrode and the capacitor electrode are formed in the same layer.

7. The display device according to claim 1, further comprising: A data line configured to transmit a data signal; as well as a transmission control line configured to transmit a transmission control signal, wherein the switch transistor is electrically connected to the data line, and Wherein, the emission control transistor is electrically connected to the emission control line.

8. The display device according to claim 7, further comprising: A light emitting diode is electrically connected to one of the driving transistor and the emission control transistor.

9. The display device according to claim 1, further comprising: A first insulating layer, disposed on the substrate; a second insulating layer, disposed on the first insulating layer; a third insulating layer, disposed on the second insulating layer; as well as a fourth insulating layer, disposed on the third insulating layer, Wherein, the first gate electrode is disposed between the second insulating layer and the third insulating layer, Wherein, the second gate electrode is arranged between the third insulating layer and the fourth insulating layer.

10. The display device according to claim 9, wherein: The third gate electrode is disposed between the first insulating layer and the second insulating layer.

11. The display device according to claim 9, wherein: The first semiconductor layer is disposed between the third insulating layer and the fourth insulating layer, The second semiconductor layer is disposed between the third insulating layer and the fourth insulating layer, and The third semiconductor layer is disposed between the first insulating layer and the substrate.

12. The display device according to claim 11, wherein: The first semiconductor layer and the second semiconductor layer are formed as a same layer.

13. The display device according to claim 11, further comprising: An insulating member is disposed between the second semiconductor layer and the second gate electrode and between the third insulating layer and the fourth insulating layer.

14. The display device according to claim 12, wherein: The driving transistor further includes a first source electrode and a first drain electrode contacting the first semiconductor layer, and The first source electrode, the first drain electrode, and the second gate electrode are formed as a same layer.

15. The display device according to claim 1, further comprising: A first insulating layer, disposed on the substrate; a second insulating layer, disposed on the first insulating layer; a third insulating layer, disposed on the second insulating layer; a fourth insulating layer, disposed on the third insulating layer; a first connection member connected to the driving transistor through a contact hole formed in the fourth insulating layer; a second connection member connected to the switch transistor through a contact hole formed in the fourth insulating layer; as well as A third connection member is connected to the emission control transistor through a contact hole formed in the first insulating layer to the fourth insulating layer.

16. The display device according to claim 15, wherein: The first semiconductor layer and the second semiconductor layer are formed as a same layer.

17. The display device according to claim 15, further comprising: a fifth insulating layer, disposed on the fourth insulating layer; A pixel electrode is disposed on the fifth insulating layer and connected to the first connecting member through a contact hole formed in the fifth insulating layer.

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