Display device and method for manufacturing display device

Abstract

The invention relates to a display device and a method for manufacturing the same. The display device includes a pixel electrode disposed on a substrate; a pixel defining layer disposed on the substrate and exposing the pixel electrode; a light emitting layer disposed on the pixel electrode; a common electrode disposed on the light emitting layer; a first bank disposed on the pixel defining layer; and a second bank disposed on the first bank, and the second bank having a side surface protruding from a side surface of the first bank. The second bank includes a first layer having a modulus of less than about 300 GPa and a second layer having a modulus of equal to or greater than about 300 GPa.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0156170 filed in the Korean Intellectual Property Office (KIPO) on November 13, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and a method for manufacturing the display device. Background Art

[0004] With the progress of the information age, the demand for display devices for displaying images has increased in various forms. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigators, and smart TVs. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and an organic light emitting display device. Among such flat panel display devices, the light emitting display device includes a light emitting element so that each of the plurality of pixels of the display panel can emit light by itself without providing light from a separate light emitting device providing light, thereby displaying an image.

[0005] Recently, display devices have been applied to glasses-type devices to provide virtual reality and augmented reality. In order to be applied to glasses-type devices, the display device is implemented in a very small size (e.g., 2 inches or less), but the display device should have a high pixel integration to achieve high resolution. For example, the display device may have a high pixel integration of 400 pixels per inch (PPI) or more.

[0006] As described above, the display device is implemented in a very small size, but in the case of a display device with high pixel integration, the area of ​​the light emitting region in which the light emitting element is set is reduced. Therefore, it may be difficult to implement a light emitting element separated for each light emitting region through a mask process. Summary of the invention

[0007] An object of the present disclosure is to provide a display device that can form a light emitting element separated for each light emitting region without a mask process.

[0008] Another object of the present disclosure is to provide a display device that reduces light emission deviation that may occur in each pixel.

[0009] The objects of the present disclosure are not limited to the above-mentioned objects, and additional objects of the present disclosure not mentioned herein will be clearly understood by those skilled in the art from the following description of the present disclosure.

[0010] According to an embodiment of the present disclosure, a display device may include: a pixel electrode disposed on a substrate; a pixel defining layer disposed on the substrate and exposing the pixel electrode; a light emitting layer disposed on the pixel electrode; a common electrode disposed on the light emitting layer; a first bank disposed on the pixel defining layer; and a second bank disposed on the first bank, and the second bank has a side protruding from a side of the first bank. The second bank may include a first layer having a modulus less than about 300 GPa and a second layer having a modulus equal to or greater than about 300 GPa.

[0011] A difference between the modulus of the first layer of the second bank and the modulus of the second layer of the second bank may be in a range of about 350 GPa to about 800 GPa.

[0012] A side surface of the first layer of the second bank and a side surface of the second layer of the second bank may be aligned.

[0013] The sum of the thickness of the first layer and the second layer may be less than about

[0014] A thickness of the first layer of the second bank may be about 0.5 times to about 2 times a thickness of the second layer of the second bank.

[0015] The thickness of the first layer of the second bank may be about To about and the thickness of the second layer of the second bank may be in the range of about To about within the range.

[0016] The first layer may include titanium, and the second layer may include diamond-like carbon (DLC) or tungsten carbide.

[0017] The first layer of the second bank may be disposed on the first bank, and the second layer of the second bank may be disposed on the first layer of the second bank.

[0018] The second bank may further include a third layer disposed between the first layer and the second layer and including titanium oxide.

[0019] The thickness of the third layer of the second bank may be smaller than the thickness of the first layer and the thickness of the second layer of the second bank.

[0020] The thickness of the third layer of the second bank may be about To about within the range.

[0021] The second layer of the second bank may be disposed on the first bank, and the first layer of the second bank may be disposed on the second layer of the second bank.

[0022] The display device may further include: a first inorganic layer disposed on upper and lower surfaces of the second bank and on the common electrode.

[0023] The first inorganic layer may be spaced apart from the upper surface of the second bank.

[0024] The display device may further include: an organic encapsulation layer disposed in a space between the first inorganic layer and the upper surface of the second bank.

[0025] The second bank, the organic encapsulating layer, and the first inorganic layer may be sequentially stacked in a region overlapping the second bank and the first inorganic layer in a plan view.

[0026] According to an embodiment of the present disclosure, a method for manufacturing a display device may include: forming a plurality of pixel electrodes spaced apart from each other and a pixel defining layer exposing the plurality of pixel electrodes; forming a first embankment material layer on the pixel defining layer; forming a plurality of second embankment material layers on the first embankment material layer; etching a portion of the plurality of second embankment material layers and a portion of the first embankment material layer; etching the side of the first embankment material layer to expose the lower surface of the plurality of second embankment material layers; forming a light-emitting layer on one of the plurality of pixel electrodes; forming a light-emitting pattern layer on the plurality of second embankment material layers; forming a common electrode on the light-emitting layer; forming an electrode pattern layer on the light-emitting pattern layer; forming an inorganic material layer on the electrode pattern layer; etching a portion of the inorganic material layer; and etching the light-emitting pattern layer and the electrode pattern layer to expose the plurality of second embankment material layers.

[0027] The forming of the plurality of second bank material layers on the first bank material layer may include: forming a first material layer including titanium; and forming a second material layer including diamond-like carbon (DLC) or tungsten carbide.

[0028] The etching of the portion of the multilayer second embankment material layer and the portion of the first embankment material layer may include: forming a mask pattern on the multilayer second embankment material layer; and etching the portion of the multilayer second embankment material layer not covered by the mask pattern and the portion of the first embankment material layer not covered by the mask pattern by a dry etching process.

[0029] The etching of the light emitting pattern layer and the electrode pattern layer may include removing the light emitting pattern layer and the electrode pattern layer between the plurality of second bank material layers and the inorganic material layer.

[0030] In the display device and the method for manufacturing the display device according to one embodiment, by including the multi-layered second bank, damage to the light emitting element due to an etchant or moisture can be prevented, so that the brightness difference between the light emitting elements can be reduced.

[0031] Effects according to the embodiments of the present disclosure are not limited to the above-mentioned effects, and more various effects are included in the following description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0033] Figure 1 is a perspective view showing a display device according to an embodiment;

[0034] Figure 2 It is shown Figure 1 A schematic cross-sectional view of a display device;

[0035] Figure 3 is a plan view showing a portion of a display device according to an embodiment;

[0036] Figure 4 is a schematic cross-sectional view showing a portion of a display device according to an embodiment;

[0037] Figure 5 It is shown Figure 4 An enlarged view of area A10;

[0038] Figure 6 is an enlarged view showing a region A10 according to another embodiment;

[0039] Figure 7 is a schematic cross-sectional view of a display device including a single-layer second bank;

[0040] Figure 8 is an enlarged view of area A10 according to yet another embodiment; and

[0041] Figures 9 to 16 are schematic cross-sectional views sequentially illustrating a method for manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0042] The present disclosure will now be described more fully below with reference to the accompanying drawings showing embodiments of the present disclosure. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art.

[0043] When an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, the element or layer may be directly on, directly connected to or directly coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements. In addition, when an element is referred to as being "in contact with" or "contacting" another element, etc., the element may be "electrically in contact with" or "physically in contact with" the other element, or "indirectly in contact with" or "directly in contact with" the other element.

[0044] Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be named as the second element.

[0045] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0046] For descriptive purposes, spatially relative terms such as "under," "below," "below," "down," "above," "up," "above," "higher," and "side" (e.g., as in "sidewall") may be used herein and thereby describe the relationship of one element to another element(s) as shown in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, the spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device is flipped in the accompanying drawings, an element described as "under" or "beneath" other elements or features would subsequently be oriented "above" the other elements or features. Thus, the exemplary term "under" can encompass both above and below orientations. In addition, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative terms used herein are interpreted accordingly.

[0047] In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of..." is intended to include "at least one selected from the group of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B". In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in conjunction or disjunction and can be understood to be equivalent to "and / or".

[0048] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined in the specification, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formalized meaning.

[0049] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0050] Figure 1 is a perspective view showing a display device according to one embodiment.

[0051] refer to Figure 1 According to one embodiment, the display device 10 may be included in an electronic device to provide an image displayed in the electronic device. The electronic device may refer to all electronic devices that provide a display screen. For example, a television, a laptop computer, a monitor, a billboard, an Internet of Things device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, smart glasses, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notepad, an electronic book, a portable multimedia player (PMP), a navigator, a game console, a digital camera, and a video camera that provide a display screen may be included in the electronic device.

[0052] The shape of the display device 10 may be variously modified. For example, the display device 10 may have a shape similar to a rectangular shape having short sides in the first direction DR1 and long sides in the second direction DR2 in a plan view. Corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 meet may be rounded with a curvature, but are not limited thereto, and the corners may be formed at right angles. The planar shape of the display device 10 may be similar to other polygonal shapes, a circular shape, or an elliptical shape, without being limited to a rectangular shape.

[0053] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400 (see FIG. Figure 2 ).

[0054] The display panel 100 may include a main area MA and a sub area SBA.

[0055] The main area MA may include a display area DA having pixels for displaying an image and a non-display area NDA disposed adjacent to the display area DA. The display area DA may emit light from a plurality of light emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining a light emission area or an opening area, and a self-luminous element.

[0056] For example, the self-luminous element may include at least one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED.

[0057] A plurality of pixels, a plurality of scan lines, a plurality of data lines, and a plurality of power lines may be provided in the display area DA. Each of the plurality of pixels may be a minimum unit for emitting light, and each of the self-luminous elements described above may be provided in a corresponding pixel. The scan line may supply a scan signal received from a scan driver to the pixel. The data line may supply a data voltage received from a display driver 200 to the pixel. The power line may supply a power voltage received from a display driver 200 to the pixel.

[0058] The non-display area NDA may be an outer area of ​​the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a scan driver for supplying a scan signal to a scan line and a fan-out line for connecting the display driver 200 to the display area DA.

[0059] The sub-region SBA may extend from one side of the main region MA. The sub-region SBA may include a flexible material that can withstand bending, folding, curling, etc. For example, when the sub-region SBA is bent, the sub-region SBA may overlap with the main region MA in the thickness direction DR3 (third direction DR3). The sub-region SBA may include a display driver 200 and a pad portion connected to the circuit board 300. In another embodiment, the sub-region SBA may be omitted, and the display driver 200 and the pad portion may be disposed in the non-display area NDA.

[0060] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may supply data voltages to the data lines. The display driver 200 may supply power voltages to the power lines and supply scan control signals to the scan driver. The display driver 200 may be formed by an integrated circuit (IC) and may be mounted on the display panel 100 by a chip on glass (COG) mode, a chip on plastic (COP) mode, or an ultrasonic bonding mode. For example, the display driver 200 may be disposed in a sub-region SBA and may overlap with the main region MA in the thickness direction DR3 (third direction DR3) by bending the sub-region SBA. In another embodiment, the display driver 200 may be mounted on a circuit board 300.

[0061] The circuit board 300 may be attached to the pad portion of the display panel 100 using an anisotropic conductive film (ACF). Leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0062] Figure 2 It is shown Figure 1 Detailedly, Figure 2 Involving folding Figure 1 side of the display device.

[0063] refer to Figure 2 , the display panel 100 may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, a thin film encapsulation layer TFEL, and a color filter layer CFL.

[0064] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or curled, etc. For example, the substrate SUB may include a polymer resin including polyimide (PI), but the present disclosure is not limited thereto. In another embodiment, the substrate SUB may include a glass material or a metal material.

[0065] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may also include a scan line, a data line, a power line, a scan control line, a fan-out line for connecting the display driver 200 to the data line, and a lead for connecting the display driver 200 to the pad portion. Each of the plurality of thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, in the case where a scan driver is formed at one side of the non-display area NDA of the display panel 100, the scan driver may include a thin film transistor.

[0066] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistors, scan lines, data lines, and power lines of the corresponding pixels of the thin film transistor layer TFTL may be disposed in the display area DA. The scan control lines and fan-out lines of the thin film transistor layer TFTL may be disposed in the non-display area NDA. The lead lines of the thin film transistor layer TFTL may be disposed in the sub-area SBA.

[0067] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a plurality of light emitting elements including a first electrode, a second electrode and a light emitting layer for emitting light, and a pixel defining layer defining pixels. The light emitting elements of the light emitting element layer EML may be disposed in the display area DA.

[0068] In one embodiment, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the first electrode receives a voltage from a thin film transistor of the thin film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may move to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively, and may be recombined with each other in the organic light-emitting layer to emit light.

[0069] In another embodiment, the light emitting element may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0070] The thin film encapsulation layer TFEL may cover the upper surface and side surfaces of the light emitting element layer EML and protect the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one inorganic film and at least one organic film to encapsulate the light emitting element layer EML.

[0071] The color filter layer CFL may be disposed on the thin film encapsulation layer TFEL. The color filter layer CFL may include a plurality of color filters corresponding to the plurality of light emission regions, respectively. Each of the plurality of color filters may selectively transmit light of a specific wavelength and block or absorb light of another wavelength. The color filter layer CFL may absorb a portion of light introduced from outside the display device 10 to reduce reflected light due to external light. Therefore, the color filter layer CFL may prevent color distortion caused by external light reflection.

[0072] Since the color filter layer CFL is directly disposed on the thin film encapsulation layer TFEL, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively reduced.

[0073] In some embodiments, the display device 10 may further include an optical device. The optical device may emit or receive light in an infrared band, an ultraviolet band, or a visible band. For example, the optical device may be an optical sensor (such as a proximity sensor, an illumination sensor, a camera sensor, a fingerprint sensor, or an image sensor) for sensing light incident on the display device 10.

[0074] Figure 3 is a plan view showing a portion of a display device according to an embodiment. Figure 3 is a plan view showing the arrangement of the light emitting elements ED1 , ED2 , and ED3 , the lower inorganic encapsulation layers TL1 , TL2 , and TL3 , and the second bank BN2 in the display area DA of the display device 10 .

[0075] refer to Figure 3 The second bank BN2 may expose a portion of the display area DA while covering another portion of the display area DA. An opening may be formed in the exposed area not covered by the second bank BN2. Figure 3 The lower inorganic encapsulation layers TL1, TL2, and TL3 may cover the boundary portions of the openings on the second bank BN2, and may cover the light emitting elements ED1, ED2, and ED3 in the openings.

[0076] Although in Figure 3 , the exposed area not covered by the second bank BN2 is shown as having a circular shape in a plan view, but the planar shape of the exposed area not covered by the second bank BN2 may be a polygonal shape such as a triangular shape, a quadrilateral shape, or a hexagonal shape, and the shapes of the lower inorganic encapsulation layers TL1, TL2, and TL3 covering the exposed area and its periphery may also be changed. A portion of the lower inorganic encapsulation layers TL1, TL2, and TL3 may be disposed at a higher level than the second bank BN2, and the light emitting elements ED1, ED2, and ED3 may be disposed at a lower level than the second bank BN2.

[0077] The light emitting elements ED1, ED2 and ED3 can be arranged as Type (e.g. diamond For example, the first light emitting element ED1 and the third light emitting element ED3 may be spaced apart from each other in the first direction DR1, and the first light emitting element ED1 and the third light emitting element ED3 may be alternately arranged in the first direction DR1 and the second direction DR2. The second light emitting element ED2 may be spaced apart from another adjacent second light emitting element ED2 in the first direction DR1 and the second direction DR2. The second light emitting element ED2 and the first light emitting element ED1 or the second light emitting element ED2 and the third light emitting element ED3 may be alternately arranged along a direction on a plane defined by the first direction DR1 and the second direction DR2. The shape and arrangement of the area exposed without being covered by the second embankment BN2 and the light emitting element are not limited to Figure 3 .

[0078] Figure 4 is a schematic cross-sectional view showing a portion of a display device according to an embodiment. In detail, Figure 4 It is along Figure 3 Schematic cross-sectional view taken along line II'. Figure 4 The cross sections of the substrate SUB, the thin film transistor layer TFTL, the light emitting element layer EML, the thin film encapsulation layer TFEL, and the color filter layer CFL are schematically shown.

[0079] The thin film transistor layer TFTL may include a first buffer layer BF1, a lower metal layer, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0080] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic film capable of preventing penetration of air or moisture. For example, the first buffer layer BF1 may include a plurality of inorganic films alternately stacked on each other.

[0081] The lower metal layer may be disposed on the first buffer layer BF1. For example, the lower metal layer may be formed of a single layer or multiple layers including at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0082] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer. The second buffer layer BF2 may include an inorganic film capable of preventing penetration of air or moisture. For example, the second buffer layer BF2 may include a plurality of inorganic films alternately stacked on each other.

[0083] The thin film transistor TFT may be disposed on the second buffer layer BF2 and may constitute a pixel circuit of each of the plurality of pixels. For example, the thin film transistor TFT may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0084] The semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may overlap the lower metal layer and the gate electrode GE in the thickness direction DR3, and may be insulated from the gate electrode GE by the gate insulating layer GI. A portion of the semiconductor layer ACT may form a source electrode SE and a drain electrode DE by making the material of the semiconductor layer ACT conductive.

[0085] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor layer ACT in the thickness direction DR3, and the gate insulating layer GI may be interposed between the electrode GE and the semiconductor layer ACT.

[0086] The gate insulating layer GI may be disposed on the semiconductor layer ACT. For example, the gate insulating layer GI may cover the semiconductor layer ACT and the second buffer layer BF2 and may insulate the semiconductor layer ACT from the gate electrode GE. The gate insulating layer GI may include a contact hole through which the first connection electrode CNE1 passes.

[0087] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0088] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1 , and may overlap the gate electrode GE in the thickness direction DR3 , and the capacitor electrode CPE and the gate electrode GE may form a capacitor.

[0089] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer ILD2 may be connected to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0090] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be embedded in a contact hole formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0091] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may include a contact hole through which the second connection electrode CNE2 passes.

[0092] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the pixel electrodes AE1, AE2, and AE3 of the light emitting elements ED1, ED2, and ED3. The second connection electrode CNE2 may be embedded in a contact hole formed in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0093] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include contact holes through which the pixel electrodes AE1, AE2, and AE3 of the light emitting elements ED1, ED2, and ED3 pass.

[0094] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include light emitting elements ED1, ED2, and ED3, a capping layer CAP, a pixel defining layer PDL, and a bank structure BNS. The light emitting elements ED1, ED2, and ED3 may include pixel electrodes AE1, AE2, and AE3, light emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3.

[0095] Figure 5 It is shown Figure 4 An enlarged view of area A10.

[0096] Combination Figure 4 refer to Figure 5 , the display device 10 (for example, see Figure 3) may include a plurality of emission areas EA1, EA2, and EA3 disposed in the display area DA. The emission areas EA1, EA2, and EA3 may include areas where light is emitted from the light emitting elements ED1, ED2, and ED3 to pass through the color filter layer CFL in the third direction DR3, and the pixel electrodes AE1, AE2, and AE3, the light emitting layers EL1, EL2, and EL3, and the common electrodes CE1, CE2, and CE3 may be sequentially stacked in the light emitting elements ED1, ED2, and ED3. The emission areas EA1, EA2, and EA3 may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that are spaced apart from each other and emit light of the same color or different colors.

[0097] In one embodiment, in a plan view, the areas or sizes of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be the same. For example, in the display device 10, the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have the same size, but the present disclosure is not limited thereto. In the display device 10, the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have different areas or sizes in a plan view. For example, in a plan view, the size of the second emission area EA2 may be larger than the size of each of the first emission area EA1 and the third emission area EA3, and the size of the third emission area EA3 may be larger than the size of the first emission area EA1. The intensity of light emitted from the corresponding emission areas EA1, EA2, and EA3 may vary depending on the size of the emission areas EA1, EA2, and EA3, and the size of the emission areas EA1, EA2, and EA3 may be adjusted so that the color of the image displayed in the display device 10 can be controlled. Figure 4 In the embodiment of FIG. 5 , the sizes of the emission areas EA1 , EA2 , and EA3 are shown to be the same as each other, but the present disclosure is not limited thereto.

[0098] In the display device 10, one first emission area EA1, one second emission area EA2, and one third emission area EA3 disposed adjacent to each other may form one pixel group. One pixel group may include emission areas EA1, EA2, and EA3 emitting light of different colors, thereby representing a white grayscale, but the present disclosure is not limited thereto. The combination of emission areas EA1, EA2, and EA3 constituting one pixel group may be variously changed depending on the arrangement of the emission areas EA1, EA2, and EA3 and the color of light emitted from the emission areas EA1, EA2, and EA3.

[0099] The opening formed in the embankment structure BNS of the light emitting element layer EML may be defined along the boundary of the embankment structure BNS. In a plan view, the first embankment BN1 and the second embankment BN2 of the embankment structure BNS may surround the emission areas EA1, EA2, and EA3. Each of the plurality of openings may include a corresponding one of the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0100] The display device 10 may include a plurality of light emitting elements ED1, ED2, and ED3 disposed in emission areas EA1, EA2, and EA3, respectively. The light emitting elements ED1, ED2, and ED3 may include a first light emitting element ED1 disposed in a first emission area EA1, a second light emitting element ED2 disposed in a second emission area EA2, and a third light emitting element ED3 disposed in a third emission area EA3.

[0101] The light-emitting elements ED1, ED2, and ED3 may include pixel electrodes AE1, AE2, and AE3, light-emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3, and the light-emitting elements ED1, ED2, and ED3 respectively disposed in emission areas EA1, EA2, and EA3 may emit light of different colors depending on the materials of the light-emitting layers EL1, EL2, and EL3. For example, the first light-emitting element ED1 disposed in the first emission area EA1 may emit a first light of a first color (i.e., red) having a peak wavelength in the range of about 610 nm to about 650 nm, the second light-emitting element ED2 disposed in the second emission area EA2 may emit a second light of green having a peak wavelength in the range of about 510 nm to about 550 nm, and the third light-emitting element ED3 disposed in the third emission area EA3 may emit a third light of blue having a peak wavelength in the range of about 440 nm to about 480 nm. The first emission area EA1, the second emission area EA2, and the third emission area EA3 constituting one pixel may include light emitting elements ED1, ED2, and ED3 for emitting light of different colors to achieve a white grayscale. In another embodiment, since the light emitting layers EL1, EL2, and EL3 may include two or more materials for emitting light of different colors, one light emitting layer may emit mixed light. For example, the light emitting layers EL1, EL2, and EL3 may include a material for emitting red light and a material for emitting green light at the same time to emit yellow light, or may include a material for emitting red light, a material for emitting green light, and a material for emitting blue light to emit white light.

[0102] The pixel electrodes AE1, AE2, and AE3 may be disposed on the second passivation layer PAS2. The pixel electrodes AE1, AE2, and AE3 may be disposed in emission areas EA1, EA2, and EA3, respectively. The pixel electrodes AE1, AE2, and AE3 may include a first pixel electrode AE1 disposed in the first emission area EA1, a second pixel electrode AE2 disposed in the second emission area EA2, and a third pixel electrode AE3 disposed in the third emission area EA3. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be spaced apart from each other on the second passivation layer PAS2.

[0103] The pixel electrodes AE1, AE2, and AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first and second connection electrodes CNE1 and CNE2. Edges of the pixel electrodes AE1, AE2, and AE3 may be covered by a pixel defining layer PDL so that the first, second, and third pixel electrodes AE1, AE2, and AE3 may be insulated from each other.

[0104] The pixel electrodes AE1, AE2 and AE3 may include a transparent electrode material and / or a conductive metal material. For example, the pixel electrodes AE1, AE2 and AE3 may include metals such as silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), lanthanum (La), titanium (Ti), titanium nitride (TiN) and combinations thereof. For example, the pixel electrodes AE1, AE2 and AE3 may include electrode materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO) and combinations thereof. The pixel electrodes AE1, AE2 and AE3 may have a multilayer structure including a transparent electrode material and a conductive metal material.

[0105] The pixel defining layer PDL may be disposed on the second passivation layer PAS2, the residual pattern RP, and the pixel electrodes AE1, AE2, and AE3. The pixel defining layer PDL may be disposed on the second passivation layer PAS2, and may cover the sides of the pixel electrodes AE1, AE2, and AE3 and the residual pattern RP to expose a portion of the upper surface of the pixel electrodes AE1, AE2, and AE3. For example, the pixel defining layer PDL may expose a portion of the first pixel electrode AE1 in the first emission area EA1 in a plan view, and the first light emitting layer EL1 may be directly disposed on the first pixel electrode AE1.

[0106] The pixel defining layer PDL may include an inorganic insulating material. The pixel defining layer PDL may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, a tantalum oxide layer, a hafnium oxide layer, a zinc oxide (ZnO x , which can be ZnO or ZnO 2 ) layer and at least one of an amorphous silicon layer, but the present disclosure is not limited thereto.

[0107] According to one embodiment, the pixel defining layer PDL may be disposed on the pixel electrodes AE1, AE2, and AE3, and may be spaced apart from the upper surfaces of the pixel electrodes AE1, AE2, and AE3. The pixel defining layer PDL may not be in direct contact with the upper surfaces of the pixel electrodes AE1, AE2, and AE3, while partially overlapping with the upper surfaces of the pixel electrodes AE1, AE2, and AE3 in the thickness direction DR3 of the substrate SUB, and a residual pattern RP may be disposed between the pixel defining layer PDL and the pixel electrodes AE1, AE2, and AE3. However, the pixel defining layer PDL may be in direct contact with the sides of the pixel electrodes AE1, AE2, and AE3. The sides of the pixel defining layer PDL may protrude toward the emission areas EA1, EA2, and EA3 more than the sides of the second bank BN2.

[0108] The residual pattern RP may be disposed on the edge of each of the pixel electrodes AE1, AE2, and AE3. Due to the residual pattern RP, the pixel defining layer PDL may not be in direct contact with the upper surface of the pixel electrodes AE1, AE2, and AE3. In the manufacturing process of the display device 10, a portion of the sacrificial layer disposed on the pixel electrodes AE1, AE2, and AE3 may be removed so that the residue may form a residual pattern RP. The residual pattern RP may include a metal or oxide semiconductor material. In the accompanying drawings, the side of the residual pattern RP facing the light emission areas EA1, EA2, and EA3 is shown as being aligned with the side of the pixel defining layer PDL, but the present disclosure is not limited thereto. In another embodiment, the side of the residual pattern RP may protrude toward the light emission areas EA1, EA2, and EA3 than the side of the pixel defining layer PDL, or may be recessed than the side of the pixel defining layer PDL. The side of the pixel defining layer PDL may be the outermost side facing the light emission areas EA1, EA2, and EA3.

[0109] The light-emitting layers EL1, EL2 and EL3 may be disposed on the pixel electrodes AE1, AE2 and AE3. The light-emitting layers EL1, EL2 and EL3 may be organic light-emitting layers made of organic materials, and the light-emitting layers EL1, EL2 and EL3 may be formed on the pixel electrodes AE1, AE2 and AE3, respectively, by a deposition process. The light-emitting layers EL1, EL2 and EL3 may have a multilayer structure, and each of the hole injection material, the hole transport material, the light-emitting material, the electron transport material and / or the electron injection material may constitute a layer. When the thin film transistor TFT applies a voltage to the pixel electrodes AE1, AE2 and AE3 of the light-emitting elements ED1, ED2 and ED3 and the common electrodes CE1, CE2 and CE3 of the light-emitting elements ED1, ED2 and ED3 receive a common voltage or a cathode voltage, holes and electrons may be injected and transported, and holes and electrons may be recombined with each other in the light-emitting layers EL1, EL2 and EL3 to emit light.

[0110] The light-emitting layers EL1, EL2, and EL3 may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3, which are respectively arranged in different emission areas EA1, EA2, and EA3. The first light-emitting layer EL1 may be arranged on the first pixel electrode AE1 in the first emission area EA1, the second light-emitting layer EL2 may be arranged on the second pixel electrode AE2 in the second emission area EA2, and the third light-emitting layer EL3 may be arranged on the third pixel electrode AE3 in the third emission area EA3. The light-emitting layers EL1, EL2, and EL3 may emit light of different colors, respectively, or one of the light-emitting layers EL1, EL2, and EL3 may emit mixed light. In one embodiment, the first light-emitting layer EL1 may emit red light, the second light-emitting layer EL2 may emit green light, and the third light-emitting layer EL3 may emit blue light. In another embodiment, the first light-emitting layer EL1 may emit yellow light as a mixture of red light and green light, and the second light-emitting layer EL2 may emit blue light. In another embodiment, the first light-emitting layer EL1 may emit white light as a mixture of red light, green light, and blue light.

[0111] The light emitting layers EL1, EL2, and EL3 may be disposed on an upper surface of the pixel defining layer PDL. In one embodiment, the light emitting layers EL1, EL2, and EL3 may be disposed in a space between the pixel electrodes AE1, AE2, and AE3 and the pixel defining layer PDL. In one embodiment, the light emitting layers EL1, EL2, and EL3 may contact the pixel defining layer PDL, the residual pattern RP, and the pixel electrodes AE1, AE2, and AE3.

[0112] The common electrodes CE1, CE2, and CE3 may be disposed on the light emitting layers EL1, EL2, and EL3. The common electrodes CE1, CE2, and CE3 may include a transparent conductive material so that light generated from the light emitting layers EL1, EL2, and EL3 may be emitted. The common electrodes CE1, CE2, and CE3 may receive a common voltage or a low potential voltage. In the case where the pixel electrodes AE1, AE2, and AE3 receive a voltage corresponding to the data voltage and the common electrodes CE1, CE2, and CE3 receive a low potential voltage, a potential difference may be formed between the pixel electrodes AE1, AE2, and AE3 and the common electrodes CE1, CE2, and CE3, and the light emitting layers EL1, EL2, and EL3 may emit light.

[0113] The common electrodes CE1, CE2, and CE3 may include a first common electrode CE1, a second common electrode CE2, and a third common electrode CE3 respectively disposed in different light emission areas EA1, EA2, and EA3. The first common electrode CE1 may be disposed on the first light emitting layer EL1 in the first emission area EA1, the second common electrode CE2 may be disposed on the second light emitting layer EL2 in the second emission area EA2, and the third common electrode CE3 may be disposed on the third light emitting layer EL3 in the third emission area EA3. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be spaced apart from each other.

[0114] The coating layers CAP1, CAP2, and CAP3 may be disposed on the common electrodes CE1, CE2, and CE3. The coating layers CAP1, CAP2, and CAP3 may include an organic material or an inorganic insulating material, and the coating layers CAP1, CAP2, and CAP3 cover the light emitting elements ED1, ED2, and ED3. The coating layers CAP1, CAP2, and CAP3 may prevent the light emitting elements ED1, ED2, and ED3 from being damaged by external air. In an embodiment, the coating layers CAP1, CAP2, and CAP3 may include an organic material such as a-NPD, NPB, TPD, m-MTDATA, Alq3, LiF, and / or CuPc, or an organic material such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide (ZnO x , which can be ZnO or ZnO 2 ), inorganic materials of silicon oxide, silicon nitride and / or silicon oxynitride.

[0115] The cladding layers CAP1, CAP2, and CAP3 may include first, second, and third cladding layers CAP1, CAP2, and CAP3 disposed in different emission areas EA1, EA2, and EA3, respectively. The first, second, and third cladding layers CAP1, CAP2, and CAP3 may be spaced apart from each other.

[0116] The display device 10 may include a multilayer dam structure BNS disposed on the pixel defining layer PDL. The dam structure BNS may have a structure in which dams BN1 and BN2 including different materials are sequentially stacked, the dams BN1 and BN2 include a plurality of openings including emission areas EA1, EA2, and EA3, and the dams BN1 and BN2 are arranged to overlap with a light blocking layer to be described later in a third direction DR3. The light emitting elements ED1, ED2, and ED3 of the display device 10 may overlap with the openings of the dam structure BNS in the third direction DR3.

[0117] The bank structure BNS may include a first bank BN1 and a second bank BN2 sequentially stacked on the pixel defining layer PDL.

[0118] The first bank BN1 may be disposed on the pixel defining layer PDL. The side of the first bank BN1 may be recessed in a direction opposite to the direction facing the emission regions EA1, EA2, and EA3 than the side of the pixel defining layer PDL. The side of the first bank BN1 may be recessed in a direction opposite to the direction facing the emission regions EA1, EA2, and EA3 than the side of the second bank BN2 as described below.

[0119] According to one embodiment, the first bank BN1 may include a metal material. In an embodiment, the first bank BN1 may include aluminum (Al), an oxide of aluminum (Al), or an alloy of aluminum (Al).

[0120] According to one embodiment, the common electrodes CE1, CE2, and CE3 may be in direct contact with the side of the first bank BN1. One end and the other end of the common electrodes CE1, CE2, and CE3 may be in direct contact with the side of the first bank BN1. The common electrodes CE1, CE2, and CE3 of different light emitting elements ED1, ED2, and ED3 may each be in direct contact with the first bank BN1, and the first bank BN1 may include a metal material so that each of the common electrodes CE1, CE2, and CE3 may be electrically connected to each other through the first bank BN1.

[0121] The light emitting layers EL1, EL2, and EL3 may be in direct contact with the side of the first bank BN1. The area in which the common electrodes CE1, CE2, and CE3 contact the side of the first bank BN1 may be larger than the area in which the light emitting layers EL1, EL2, and EL3 contact the side of the first bank BN1. The common electrodes CE1, CE2, and CE3 may be disposed on the side of the first bank BN1 to cover a larger area or a higher position than the light emitting layers EL1, EL2, and EL3 on the side of the first bank BN1. Since the common electrodes CE1, CE2, and CE3 of the light emitting elements ED1, ED2, and ED3 are electrically connected to each other through the first bank BN1, it may be advantageous for the common electrodes CE1, CE2, and CE3 to contact the first bank BN1 in a larger area.

[0122] The first bank BN1 may have a top surface higher than the common electrodes CE1, CE2, and CE3 and the capping layers CAP1, CAP2, and CAP3. A height from the substrate SUB to the top surface of the first bank BN1 may be greater than a height from the substrate SUB to the common electrodes CE1, CE2, and CE3.

[0123] The second bank BN2 may be disposed on the first bank BN1. The second bank BN2 may include a tip TIP which is a region protruding from the first bank BN1. A side of the second bank BN2 may protrude toward the emission areas EA1, EA2, and EA3 from a side of the first bank BN1.

[0124] Since the side surface of the second bank BN2 has a shape protruding toward the emission areas EA1 , EA2 , and EA3 than the side surface of the first bank BN1 , an undercut structure of the first bank BN1 may be formed under the tip end TIP of the second bank BN2 .

[0125] In the display device 10 according to one embodiment, the embankment structure BNS may include a tip TIP protruding toward the emission areas EA1, EA2, and EA3, so that the light-emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 spaced apart from each other may be formed by a deposition process and an etching process instead of a mask process. In addition, different layers may also be formed separately in different emission areas EA1, EA2, and EA3 by a deposition process. For example, although the light-emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 of the light-emitting elements ED1, ED2, and ED3 are formed by a deposition process without using a mask, the deposited material may be disconnected from the embankment structure BNS between the light emission areas EA1, EA2, and EA3 by the tip TIP of the second embankment BN2, and not connected in the light emission areas EA1, EA2, and EA3. After the material for forming a specific layer is formed on the entire surface of the display device 10, different layers may be formed separately in different emission areas EA1, EA2, and EA3 by a process of removing the layer formed in the unnecessary area by etching. In the display device 10, different light emitting elements ED1, ED2 and ED3 can be respectively formed for the emission areas EA1, EA2 and EA3 through deposition processes and etching processes without using a mask process, unnecessary elements in the display device 10 can be omitted, and the size of the non-display area NDA can be minimized.

[0126] The second bank BN2 may include first layers BN210 and BN211 having a modulus less than or equal to about 300 GPa and second layers BN220 and BN221 having a modulus greater than or equal to about 300 GPa. In this specification, the modulus may refer to Young's modulus and may be a value measured by ASTM E 11-97.

[0127] Figure 6 FIG. 1 is an enlarged view showing area A10 according to another embodiment. Figure 5 As shown in , the first layer BN210 of the second bank BN2 may be disposed on the first bank BN1, and the second layer BN220 of the second bank BN2 may be disposed on the first layer BN210 of the second bank BN2. Figure 6 As shown in , the second layer BN221 of the second bank BN2 may be disposed on the first bank BN1 , and the first layer BN211 of the second bank BN2 may be disposed on the second layer BN221 of the second bank BN2 .

[0128] In an embodiment, the difference between the modulus of the first layer BN210 and BN211 of the second bank BN2 and the modulus of the second layer BN220 and BN221 of the second bank BN2 may be in the range of about 350 GPa to about 800 GPa. When the difference in modulus between the two layers is within the above range, the tip TIP of the second bank BN2 may be prevented from bending or breaking.

[0129] In one embodiment, the modulus of the first layer BN210 and BN211 of the second bank BN2 may be less than or equal to about 200 GPa. For example, the modulus of the first layer BN210 and BN211 of the second bank BN2 may be less than or equal to about 150 GPa. In one embodiment, the modulus of the first layer BN210 and BN211 of the second bank BN2 may be greater than or equal to about 50 GPa. For example, the modulus of the first layer BN210 and BN211 of the second bank BN2 may be greater than or equal to about 100 GPa. The first layer BN210 and BN211 of the second bank BN2 may include titanium (Ti). The modulus of the first layer BN210 and BN211 of the second bank BN2 including titanium may be about 116 GPa.

[0130] In one embodiment, the modulus of the second layer BN220 and BN221 of the second bank BN2 may be greater than or equal to about 400 GPa. For example, the modulus of the second layer BN220 and BN221 of the second bank BN2 may be greater than or equal to about 500 GPa. In one embodiment, the modulus of the second layer BN220 and BN221 of the second bank BN2 may be less than or equal to about 1000 GPa. For example, the modulus of the second layer BN220 and BN221 of the second bank BN2 may be less than or equal to about 900 GPa. The second layer BN220 and BN221 of the second bank BN2 may include diamond-like carbon (DLC) or tungsten carbide. The modulus of the second layers BN220 and BN221 including DLC ​​of the second bank BN2 may be in the range of about 500 GPa to about 900 GPa, and the modulus of the second layers BN220 and BN221 including tungsten carbide of the second bank BN2 may be in the range of about 530 GPa to about 700 GPa.

[0131] Figure 7 is a schematic cross-sectional view of a display device including a single-layer second bank BN2 ′. Figure 7 , the second bank BN2' containing only titanium (Ti) may have a low modulus, so the tip TIP may be bent during a cleaning process or an etching process. Due to the deformation of the tip TIP, the second bank BN2' may fall off from the lower inorganic encapsulation layer TL1, or moisture penetration may occur. This may cause damage to the light emitting element ED1.

[0132] Return to reference Figure 5 and Figure 6 Since the second bank BN2 includes the second layers BN220 and BN221 having a relatively large modulus value, the tip TIP can be robust against mechanical deformation. The second bank BN2 may include the first layers BN210 and BN211 having a relatively small modulus value, so that the second bank BN2 may have a certain degree of ductility. By including the first layers BN210 and BN211 and the second layers BN220 and BN221, the second bank BN2 may be resistant to deformation and cracking.

[0133] The side surfaces of the first layers BN210 and BN211 of the second bank BN2 and the side surfaces of the second layers BN220 and BN221 of the second bank BN2 may be aligned to form a flat surface. Although the side surfaces of the first layers BN210 and BN211 and the second layers BN220 and BN221 of the second bank BN2 are only perpendicular to the substrate SUB in the drawings, the side surfaces may be inclined relative to the substrate SUB.

[0134] The sum of the thicknesses t10+t20 and t11+t21 of the first layers BN210 and BN211 and the second layers BN220 and BN221 of the second bank BN2 may be less than about The second bank BN2 may include first layers BN210 and BN211 and second layers BN220 and BN221 having different moduli, and may have high strength and thin thickness. In one embodiment, the sum of the thicknesses t10+t20 and t11+t21 of the first layers BN210 and BN211 and the second layers BN220 and BN221 of the second bank BN2 may be approximately To about within the range.

[0135] The thickness t10 and t11 of the first layer BN210 and BN211 of the second bank BN2 and the thickness t20 and t21 of the second layer BN220 and BN221 may be appropriately adjusted as needed. In one embodiment, the thickness t10 and t11 of the first layer BN210 and BN211 of the second bank BN2 may be about 0.5 times to about 2 times the thickness t20 and t21 of the second layer BN220 and BN221. In another embodiment, the thickness t10 and t11 of the first layer BN210 and BN211 of the second bank BN2 may be equal to or greater than the thickness t20 and t21 of the second layer BN220 and BN221.

[0136] In one embodiment, the thickness of each of the first layers BN210 and BN211 of the second bank BN2 may be about To about In another embodiment, the thickness of each of the first layers BN210 and BN211 of the second bank BN2 may be about To about In one embodiment, the thickness of each of the second layers BN220 and BN221 of the second bank BN2 may be about To about In another embodiment, the thickness of each of the second layers BN220 and BN221 of the second bank BN2 may be approximately To about within the range.

[0137] Figure 8 is an enlarged view of area A10 according to yet another embodiment. Figure 5 Compared with the display device in Figure 8 The display device in the embodiment may further include a third layer BN230 between the first layer BN212 and the second layer BN222. In addition to the third layer BN230, other configurations are similar to Figure 5 Same as described in .

[0138] Combination Figures 4 to 6 refer to Figure 8 , the third layer BN230 of the second bank BN2 may be disposed between the first layer BN210 and BN211 and the second layer BN220 and BN221 of the second bank BN2, and defects caused by arcs that may occur while forming the first layer BN210 and BN211 and the second layer BN220 and BN221 may be prevented. The third layer BN230 of the second bank BN2 may include a high resistance material. In one embodiment, the third layer BN230 of the second bank BN2 may include titanium oxide (TiO x ).

[0139] The thickness t30 of the third layer BN230 of the second bank BN2 may be smaller than the thickness t12 of the first layer BN212 and the thickness t22 of the second layer BN222. In one embodiment, the thickness t30 of the third layer BN230 of the second bank BN2 may be about To about Within the above range, the first light emitting element ED1 may not be damaged due to heat generation.

[0140] The thin film encapsulation layer TFEL may be disposed on the light emitting elements ED1, ED2, and ED3 and the embankment structure BNS, and may cover the light emitting elements ED1, ED2, and ED3 and the embankment structure BNS. The thin film encapsulation layer TFEL may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one organic film to protect the light emitting element layer EML from particles such as dust.

[0141] In an embodiment, the thin film encapsulation layer TFEL may include a lower inorganic encapsulation layer TFE1 , an organic encapsulation layer TFE2 , and an upper inorganic encapsulation layer TFE3 , which are sequentially stacked.

[0142] Each of the lower inorganic encapsulation layer TFE1 and the upper inorganic encapsulation layer TFE3 may include an inorganic insulating material. For example, each of the lower inorganic encapsulation layer TFE1 and the upper inorganic encapsulation layer TFE3 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and may include, for example, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide (ZnO x , which can be ZnO or ZnO 2 ), silicon oxide, silicon nitride and silicon oxynitride.

[0143] The organic encapsulation layer TFE2 may include a polymer-based material. For example, the organic encapsulation layer TFE2 may include at least one of an acrylic resin, an epoxy resin, a polyimide, and polyethylene. For example, the organic encapsulation layer TFE2 may include an acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.). The organic encapsulation layer TFE2 may be formed by hardening a monomer or coating a polymer.

[0144] The lower inorganic encapsulation layer TFE1 may be disposed on the light emitting elements ED1, ED2, and ED3 and the embankment structure BNS. The lower inorganic encapsulation layer TFE1 may include a first inorganic layer TL1, a second inorganic layer TL2, and a third inorganic layer TL3 disposed corresponding to the light emission areas EA1, EA2, and EA3, respectively. Each of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may include an inorganic insulating material and cover the light emitting elements ED1, ED2, and ED3. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may prevent the light emitting elements ED1, ED2, and ED3 from being damaged due to external air.

[0145] The lower inorganic encapsulation layer TFE1 (including inorganic layers TL1, TL2, and TL3) can be formed by a chemical vapor deposition (CVD) method, and thus can be formed along the step difference of the deposition layer. For example, due to the tip of the bank structure BNS, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can also form a thin film under the undercut structure. The lower inorganic encapsulation layers TL1, TL2, and TL3 can be arranged along the upper surface of the second bank BN2, the side surface (i.e., the side) of the first bank BN1, and the upper surface of the common electrodes CE1, CE2, and CE3.

[0146] The lower inorganic encapsulation layer TFE1 may include a plurality of spaced-apart inorganic layers TL1, TL2, and TL3, and each of the inorganic layers TL1, TL2, and TL3 may be disposed in a corresponding one of the emission areas EA1, EA2, and EA3. The first inorganic layer TL1 may not overlap with the second light-emitting element ED2 and the third light-emitting element ED3 in the third direction DR3, but may be disposed only on the first light-emitting element ED1 and the embankment structure BNS in the periphery of the first light-emitting element ED1. The second inorganic layer TL2 may not overlap with the first light-emitting element ED1 and the third light-emitting element ED3 in the third direction DR3, but may be disposed only on the second light-emitting element ED2 and the embankment structure BNS in the periphery of the second light-emitting element ED2. The third inorganic layer TL3 may not overlap with the first light-emitting element ED1 and the second light-emitting element ED2 in the third direction DR3, but may be disposed only on the third light-emitting element ED3 and the embankment structure BNS in the periphery of the third light-emitting element ED3.

[0147] The first inorganic layer TL1 may be formed after the first common electrode CE1 is formed, the second inorganic layer TL2 may be formed after the second common electrode CE2 is formed, and the third inorganic layer TL3 may be formed after the third common electrode CE3 is formed. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may be spaced apart from each other on the bank structure BNS.

[0148] The lower inorganic encapsulation layers TL1, TL2, and TL3 may be disposed on the upper surfaces of the light-emitting elements ED1, ED2, and ED3 and on the lower surface of the second bank BN2 in the periphery of the light-emitting elements ED1, ED2, and ED3, but may be separated from the upper surface of the second bank BN2. For example, the lower inorganic encapsulation layers TL1, TL2, and TL3 may have an undercut structure on the second bank BN2. The space between the lower inorganic encapsulation layers TL1, TL2, and TL3 and the upper surface of the second bank BN2 may be a space from which the materials of the light-emitting layers EL1, EL2, and EL3, the common electrodes CE1, CE2, and CE3, and the encapsulation layers CAP1, CAP2, and CAP3 deposited on the upper surface of the second bank BN2 are removed.

[0149] The organic encapsulation layer TFE2 may be disposed on the second bank BN2 and the lower inorganic encapsulation layers TL1, TL2, and TL3. A portion of the organic encapsulation layer TFE2 may be disposed in a space between the lower inorganic encapsulation layers TL1, TL2, and TL3 and the upper surface of the second bank BN2. In an area where the second bank BN2 and the lower inorganic encapsulation layers TL1, TL2, and TL3 overlap, the second bank BN2, the organic encapsulation layer TFE2, and the lower inorganic encapsulation layers TL1, TL2, and TL3 may be sequentially disposed. In the tip TIP area, the organic encapsulation layer TFE2 and the lower inorganic encapsulation layers TL1, TL2, and TL3 may be sequentially arranged on the second bank BN2, and the organic encapsulation layer TFE2 may be disposed on top of the lower inorganic encapsulation layers TL1, TL2, and TL3. In other words, a portion of the organic encapsulation layer TFE2 may be disposed between the upper surface of the second embankment BN2 and the lower inorganic encapsulation layers TL1, TL2, and TL3 on the tip TIP of the second embankment BN2, and another portion of the organic encapsulation layer TFE2 may be disposed on top of the lower inorganic encapsulation layers TL1, TL2, and TL3.

[0150] In one embodiment, the entire upper surface of the second bank BN2 may be in contact with the organic encapsulation layer TFE2. The first lower surfaces of the lower inorganic encapsulation layers TL1, TL2, and TL3 may be surfaces opposite to the upper surface of the second bank BN2, and the first lower surfaces of the lower inorganic encapsulation layers TL1, TL2, and TL3 may be in contact with the organic encapsulation layer TFE2.

[0151] The upper inorganic encapsulation layer TFE3 may be disposed on the organic encapsulation layer TFE2. The upper inorganic encapsulation layer TFE3 may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide (ZnO x , which can be ZnO or ZnO 2 ), silicon oxide, silicon nitride and / or silicon oxynitride.

[0152] A light blocking layer (not shown) may be disposed on the thin film encapsulation layer TFEL, but the present disclosure is not limited thereto. The light blocking layer may be located between the light emission areas EA1, EA2, and EA3. The light blocking layer may include a light absorbing material. For example, the light blocking layer may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perolefin black, and aniline black, but the present disclosure is not limited thereto. The light blocking layer may prevent color mixing due to penetration of visible light between the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3, thereby improving the display device 10 (e.g., see Figure 3 )’s color reproduction rate.

[0153] The display device 10 may include a plurality of color filters CF1, CF2, and CF3 disposed on the light emission areas EA1, EA2, and EA3. Each of the color filters CF1, CF2, and CF3 may include a filter pattern area and a light blocking area. The filter pattern area may overlap with the light emission areas EA1, EA2, and EA3 or the opening of the dike structure BNS in the third direction DR3, and may form a light output area, and light emitted from the light emission areas EA1, EA2, and EA3 is output from the light output area. The light blocking area may be an area where the color filters CF1, CF2, and CF3 are stacked so that light cannot be transmitted therethrough.

[0154] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3, and the first color filter CF1, the second color filter CF2, and the third color filter CF3 are arranged to correspond to the light emission areas EA1, EA2, and EA3, respectively. The color filters CF1, CF2, and CF3 may include a colorant such as a dye or a pigment for absorbing light of another wavelength band other than the light of a specific wavelength band, and may be arranged to correspond to the color of the light emitted from the light emission areas EA1, EA2, and EA3. For example, the first color filter CF1 may be a red color filter arranged to overlap with the first emission area EA1 in the third direction DR3, and the first color filter CF1 transmits only the red first light. The second color filter CF2 may be a green color filter arranged to overlap with the second emission area EA2 in the third direction DR3, and the second color filter CF2 transmits only the green second light. The third color filter CF3 may be a blue color filter arranged to overlap with the third emission area EA3 in the third direction DR3, and the third color filter CF3 transmits only the blue third light.

[0155] Since the color filters CF1, CF2, and CF3 are arranged to overlap each other in the third direction DR3, the display device 10 can reduce the intensity of the reflected light due to the external light. In addition, the color sense of the reflected light due to the external light can be controlled by adjusting the layout, shape, and area of ​​the color filters CF1, CF2, and CF3 in a plan view.

[0156] An overcoat layer OC may be disposed on the color filters CF1, CF2, and CF3, and the upper ends of the color filters CF1, CF2, and CF3 may be flattened. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. For example, the overcoat layer OC may include a colorless light-transmitting organic material such as an acrylic-based resin.

[0157] Hereinafter, a manufacturing process of the display device 10 according to one embodiment will be described with reference to the accompanying drawings.

[0158] Figures 9 to 16are schematic cross-sectional views sequentially illustrating a method for manufacturing a display device according to an embodiment. Figures 9 to 16 Schematically showing a display device 10 (for example, see Figure 3 ) of the embankment structure BNS of the light emitting element layer EML, the light emitting element ED and the thin film encapsulation layer TFEL. Hereinafter, the process of forming each layer in the manufacturing process of the display device 10 will be omitted, and the formation order of each layer will be described.

[0159] refer to Fig. 9 , a plurality of pixel electrodes AE1 , AE2 , and AE3 completely spaced apart from each other, a sacrificial layer SFL, a pixel defining material layer PDLL, and a plurality of bank material layers BNL1 , BNL210 , and BNL220 may be formed on the second passivation layer PAS2 .

[0160] The second bank material layers BNL210 and BNL220 may have a multi-layer structure and include a first material layer BNL210 and a second material layer BNL220. After the process, the first material layer BNL210 and the second material layer BNL220 may form a second bank BN2 (see FIG. Figure 4 ). Forming the multi-layer second bank material layers BNL210 and BNL220 on the first bank material layer BNL1 may include forming the first material layer BNL210 including titanium and forming the second material layer BNL220 including diamond-like carbon (DLC) or tungsten carbide. Figures 9 to 16 It is shown that the second material layer BNL220 is formed after the first material layer BNL210 is formed, but the present disclosure is not limited thereto, and in another embodiment, the first material layer BNL210 may be formed after the second material layer BNL220 is formed. In one embodiment, the first material layer BNL210 including titanium may be formed using a chemical vapor deposition (CVD) method, the second material layer BNL220 including diamond-like carbon (DLC) may be formed using a sputtering process, and the second material layer BNL220 including tungsten carbide may be formed using a chemical vapor deposition (CVD) method.

[0161] Although not shown, the substrate SUB (see Figure 4 ) is provided with a thin film transistor layer TFTL (see Figure 4 ), and the structure of the thin film transistor layer TFTL is the same as that of the above reference Figure 4 The structures described are the same. A detailed description of the thin film transistor layer TFTL will be omitted.

[0162] Then, refer to Fig.10, a first etching process of forming a photoresist (not shown) on the second bank material layers BNL210 and BNL220 and etching a portion of the first bank material layer BNL1 and a portion of the second bank material layers BNL210 and BNL220 using the photoresist as a mask pattern may be performed. Through the first etching process, a hole may be formed in an area not covered by the mask pattern, and a portion of the pixel defining material layer PDLL may be exposed. The photoresists may be arranged to be spaced apart from each other on the second bank material layers BNL210 and BNL220, and may be arranged to expose an area overlapping with the pixel electrodes AE1, AE2, and AE3 in a plan view.

[0163] In an embodiment, the first etching process may be performed by anisotropic dry etching. A hole may be formed in a region overlapping with the pixel electrodes AE1, AE2, and AE3 in a plan view, and the hole may form a bank structure BNS (see FIG. Fig.11 ) opening.

[0164] refer to Fig.11 , an undercut structure of the first bank BN1 may be formed by the second etching process. The first bank material layer BNL1 may have a faster etching rate than the second bank material layer BNL2, and the side of the second bank BN2 may be formed in a structure protruding more than the side of the first bank BN1. The side of the second bank BN2 may protrude toward the hole more than the side of the first bank BN1 to form a tip TIP (see Figure 5 ), and an undercut structure may be formed at the bottom.

[0165] In one embodiment, the second etching process may be an isotropic wet etching process. The second etching process may use an alkaline etchant. The bank structure BNS including the first bank BN1 and the second bank BN2 may be obtained by the second etching process.

[0166] Then, if Fig.12 As shown in FIG. 1 , the pixel definition material layer PDLL (see FIG. 1 ) can be removed by the third etching process. Fig.11 ), and the sacrificial layer SFL can also be removed (see Fig.11 ). The third etching process may include etching to remove the pixel definition material layer PDLL and etching to remove the sacrificial layer SFL.

[0167] The sacrificial layer SFL may protect the pixel electrodes AE1, AE2, and AE3 from the influence of plasma in the etching process. In the sacrificial layer SFL, the portion exposed by the hole and the portion between the first bank material layer BNL1 and the pixel electrodes AE1, AE2, and AE3 may be removed. However, the sacrificial layer SFL may not be completely removed, and a portion of the sacrificial layer SFL as a residual pattern RP may be retained between the pixel defining layer PDL and the pixel electrodes AE1, AE2, and AE3. The pixel electrodes AE1, AE2, and AE3 may be exposed by the third etching process.

[0168] pass Figures 9 to 12 By the process, pixel electrodes AE1, AE2 and AE3 spaced apart from each other, a pixel defining layer PDL exposing the pixel electrodes, a first bank BN1 disposed on the pixel defining layer PDL, and a second bank BN2 protruding from a side of the first bank BN1 can be formed on a substrate.

[0169] Then, if Fig.13 As shown in , the first light emitting element ED1 may be formed by sequentially stacking a first light emitting layer EL1 and a first common electrode CE1 on the first pixel electrode AE1, and a first cladding layer CAP1 may be formed on the first common electrode CE1. Since the first light emitting layer EL1, the first common electrode CE1, and the first cladding layer CAP1 are formed on the entire surface of the substrate, a first light emitting pattern layer ELP1, a first electrode pattern layer CEP1, and a first cladding pattern layer CPP1 may be formed. The first light emitting pattern layer ELP1 and the first light emitting layer EL1 may include the same material, the first electrode pattern layer CEP1 and the first common electrode CE1 may include the same material, and the first cladding pattern layer CPP1 and the first cladding layer CAP1 may include the same material.

[0170] The first light emitting layer EL1 and the first light emitting pattern layer ELP1 can be separated, the first common electrode CE1 and the first electrode pattern layer CEP1 can be separated, and the tip TIP (see FIG. 1 ) of the second bank BN2 can be Figure 5 ) The first cladding layer CAP1 and the first cladding pattern layer CPP1 may be separated. The first light emitting layer EL1 may be formed on the first pixel electrode AE1, and the first light emitting pattern layer ELP1 may be formed on the second bank BN2. The first common electrode CE1 may be formed on the first light emitting layer EL1, and the first electrode pattern layer CEP1 may be formed on the first light emitting pattern layer ELP1.

[0171] The first light emitting layer EL1 and the first common electrode CE1 may be formed by a thermal deposition process. Due to the tip TIP of the second bank BN2, the deposition of the material in the opening may not be smooth. However, since the material of the first light emitting layer EL1 and the first common electrode CE1 is deposited in an inclined direction rather than a direction perpendicular to the upper surface of the substrate, the deposition may also occur in the area covered by the tip TIP of the second bank BN2.

[0172] The deposition process for forming the common electrodes CE1, CE2, and CE3 may be performed obliquely to be relatively closer to the horizontal direction than the deposition process for forming the light emitting layers EL1, EL2, and EL3. Therefore, the common electrodes CE1, CE2, and CE3 may have a larger contact area with the side of the first bank BN1 than the light emitting layers EL1, EL2, and EL3. In an embodiment, the common electrodes CE1, CE2, and CE3 may be deposited to a higher position on the side of the first bank BN1 than the light emitting layers EL1, EL2, and EL3. Different common electrodes CE1, CE2, and CE3 may be electrically connected to each other by contacting the first bank BN1 having high conductivity.

[0173] Subsequently, a first inorganic material layer TLL1 covering the first cladding layer CAP1 and the first cladding pattern layer CPP1 may be formed. In one embodiment, the first inorganic material layer TLL1 may be formed by a chemical vapor deposition (CVD) method.

[0174] refer to Fig.14 , a fourth etching process may be performed to remove the first inorganic material layer TLL1 (see Fig.13 ) to expose the first electrode pattern layer CEP1. A photoresist (not shown) as a mask may be formed in a region overlapping with the first emission region EA1 and an edge region in the periphery of the region in a plan view, and the first inorganic material layer TLL1 not covered by the mask may be removed. Through the fourth etching process, the first inorganic material layer TL1 may remain in a region overlapping with the first emission region EA1 and an edge region in the periphery of the region. In an embodiment, the fourth etching process may be anisotropic dry etching.

[0175] refer to Fig.15 , by removing Fig.14The first cladding pattern layer CPP1, the first electrode pattern layer CEP1 and the first light emitting pattern layer ELP1 are removed to expose the second bank BN2, and a fifth etching process may be performed to expose the second bank BN2. In an embodiment, the fifth etching process may include an isotropic wet etching step. Not only the first cladding pattern layer CPP1, the first electrode pattern layer CEP1 and the first light emitting pattern layer ELP1 disposed on the second bank BN2 may be removed, but also the first light emitting pattern layer ELP1, the first electrode pattern layer CEP1 and the first cladding pattern layer CPP1 of the second emission area EA2 and the third emission area EA3 not covered by the first inorganic material layer TLL1 may be removed. Therefore, the first light emitting pattern layer ELP1, the first electrode pattern layer CEP1 and the first cladding pattern layer CPP1 disposed between the first inorganic layer TL1 and the second bank BN2 may be removed, and an undercut structure of the first inorganic layer TL1 may be formed.

[0176] Combination Figure 4 refer to Fig.16 , by executing Figures 13 to 15 According to the process shown in FIG. 1 , a second light emitting element ED2 and a second inorganic layer TL2 may be formed on the second emission area EA2 , and a third light emitting element ED3 and a third inorganic layer TL3 may be formed on the third emission area EA3 .

[0177] Subsequently, although not shown in the drawings, the display device 10 may be manufactured by forming an organic encapsulation layer TFE2 of a thin film encapsulation layer TFEL, an upper inorganic encapsulation layer TFE3, a color filter layer CFL, and an overcoat layer OC on the light emitting elements ED1, ED2, and ED3 and the dam structure BNS. The structures of the thin film encapsulation layer TFEL, the color filter layer CFL, and the overcoat layer OC are the same as those described above, and a detailed description of the structures of the thin film encapsulation layer TFEL, the color filter layer CFL, and the overcoat layer OC will be omitted.

[0178] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure belongs will be able to make various modifications and changes thereto.Therefore, the embodiments of the disclosure described above may be implemented individually or in combination with each other.

[0179] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but are used to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be interpreted by the attached claims, and should be interpreted as all technical spirits within the equivalent scope are included in the scope of the present disclosure.

Claims

1. A display device, wherein: The display device comprises: A pixel electrode is disposed on the substrate; A pixel defining layer, disposed on the substrate and exposing the pixel electrode; A light-emitting layer is disposed on the pixel electrode; A common electrode, disposed on the light-emitting layer; A first bank is disposed on the pixel defining layer; and a second bank provided on the first bank, and having a side surface protruding from a side surface of the first bank, The second embankment includes a first layer having a modulus less than 300 GPa and a second layer having a modulus equal to or greater than 300 GPa.

2. The display device according to claim 1, wherein: A difference between the modulus of the first layer of the second bank and the modulus of the second layer of the second bank is in a range of 350 GPa to 800 GPa.

3. The display device according to claim 1, wherein: A side surface of the first layer of the second bank is aligned with a side surface of the second layer of the second bank.

4. The display device according to claim 1, wherein: The sum of the thickness of the first layer and the second layer is less than 5. The display device according to claim 1, wherein: A thickness of the first layer of the second bank is 0.5 to 2 times a thickness of the second layer of the second bank.

6. The display device according to claim 1, wherein: The thickness of the first layer of the second bank is to within the range of The thickness of the second layer of the second bank is to within the range.

7. The display device according to claim 1, wherein: The first layer comprises titanium, and The second layer includes diamond-like carbon or tungsten carbide.

8. The display device according to claim 1, wherein: The first layer of the second bank is disposed on the first bank, and The second layer of the second bank is disposed on the first layer of the second bank.

9. The display device according to claim 8, wherein: The second bank further includes a third layer disposed between the first layer and the second layer and including titanium oxide.

10. The display device according to claim 9, wherein: A thickness of the third layer of the second bank is smaller than a thickness of the first layer and a thickness of the second layer of the second bank.

11. The display device according to claim 9, wherein: The thickness of the third layer of the second bank is to within the range.

12. The display device according to claim 1, wherein: The second layer of the second bank is disposed on the first bank, and The first layer of the second bank is disposed on the second layer of the second bank.

13. The display device according to claim 1, wherein: The display device further includes: A first inorganic layer is disposed on the upper and lower surfaces of the second bank and on the common electrode.

14. The display device according to claim 13, wherein: The first inorganic layer is spaced apart from the upper surface of the second bank.

15. The display device according to claim 14, wherein: The display device further includes: An organic encapsulation layer is disposed in a space between the first inorganic layer and the upper surface of the second bank.

16. The display device according to claim 15, wherein: The second bank, the organic encapsulating layer, and the first inorganic layer are sequentially stacked in a region overlapping the second bank and the first inorganic layer in a plan view.

17. A method for manufacturing a display device, wherein: The method comprises: forming a plurality of pixel electrodes spaced apart from each other and a pixel defining layer exposing the plurality of pixel electrodes; forming a first bank material layer on the pixel defining layer; forming a plurality of second bank material layers on the first bank material layer; etching a portion of the multilayer second bank material layer and a portion of the first bank material layer; etching the side surfaces of the first bank material layer to expose the lower surfaces of the multi-layer second bank material layer; forming a light emitting layer on one of the plurality of pixel electrodes; forming a light emitting pattern layer on the multi-layer second bank material layer; forming a common electrode on the light-emitting layer; forming an electrode pattern layer on the light-emitting pattern layer; forming an inorganic material layer on the electrode pattern layer; etching a portion of the inorganic material layer; and The light emitting pattern layer and the electrode pattern layer are etched to expose the multi-layer second bank material layer.

18. The method according to claim 17, wherein: The forming of the plurality of second bank material layers on the first bank material layer comprises: forming a first material layer including titanium; and A second material layer including diamond-like carbon or tungsten carbide is formed.

19. The method according to claim 18, wherein: The etching the portion of the multilayer second bank material layer and the portion of the first bank material layer comprises: forming a mask pattern on the multi-layer second bank material layer; and The portion of the multi-layered second bank material layer not covered by the mask pattern and the portion of the first bank material layer not covered by the mask pattern are etched by a dry etching process.

20. The method according to claim 18, wherein: The etching of the light emitting pattern layer and the electrode pattern layer includes removing the light emitting pattern layer and the electrode pattern layer between the plurality of second bank material layers and the inorganic material layer.

Images