Display device

Abstract

Disclosed is a display device including: a plurality of pixels each including a plurality of emission areas and a non-emission area adjacent to the plurality of emission areas; and a pixel defining layer that overlaps the non-emission region. The pixel defining layer includes a plurality of trenches surrounding respective emission regions and spaced apart from each other. A corner of each of the plurality of grooves is chamfered.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0156656, filed on November 13, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between users and information has been emphasized. Due to the importance of display devices, the use of various display devices such as liquid crystal display devices and organic light emitting display devices has increased. Summary of the invention

[0005] Embodiments may provide a display device capable of preventing lateral leakage current, disconnection of a cathode electrode, and defects in an encapsulation layer.

[0006] An embodiment of a display device includes a plurality of pixels each including a plurality of emission regions and a non-emission region adjacent to the plurality of emission regions, and a pixel defining layer overlapping the non-emission region, the pixel defining layer including a plurality of grooves surrounding the corresponding emission regions and spaced apart from each other. A corner of each of the plurality of grooves may be chamfered.

[0007] Inner and outer corners of each of the plurality of grooves may be chamfered.

[0008] A width of an edge of each of the plurality of grooves may coincide with a width of a corner of each of the plurality of grooves.

[0009] A width of an edge of each of the plurality of trenches and a width of a corner of each of the plurality of trenches may range from 80 nm to 150 nm.

[0010] The thickness of each of the plurality of trenches may range from 300 nm to 1000 nm.

[0011] The distance between the plurality of trenches may range from 100 nm to 300 nm.

[0012] A corner of each of the plurality of emission areas may be chamfered.

[0013] A corner of each of the plurality of emission areas may be a right angle.

[0014] An inner corner of each of the plurality of grooves may be a right angle, and an outer corner of each of the plurality of grooves may be chamfered.

[0015] A width of an edge of each of the plurality of grooves may coincide with a width of a corner of each of the plurality of grooves.

[0016] A width of an edge of each of the plurality of grooves may be smaller than a maximum width between an inner corner and an outer corner of each of the plurality of grooves.

[0017] A width of an edge of each of the plurality of grooves may be different from a width of a corner of each of the plurality of grooves.

[0018] A width of an edge of each of the plurality of grooves may be greater than a width of a corner of each of the plurality of grooves.

[0019] The width of the edge of each of the plurality of grooves may coincide with a maximum width between an inner corner and an outer corner of each of the plurality of grooves.

[0020] The plurality of emission regions may include a first emission region configured to emit light of a first color, a second emission region configured to emit light of a second color, and a third emission region configured to emit light of a third color.

[0021] The first emission region and the second emission region may be arranged in a first direction, and the third emission region may be arranged in a second direction relative to the first emission region and the second emission region.

[0022] The display device may further include an anode electrode, an emission structure and a cathode electrode, the opening of the pixel defining layer extends to the anode electrode, the emission structure is disposed on the anode electrode and the pixel defining layer, and the cathode electrode is disposed on the emission structure.

[0023] The emission structure may include: a first emission component, the first emission component including a first hole transport component, a first electron transport component, and a first emission layer disposed between the first hole transport component and the first electron transport component; a second emission component, the second emission component including a second hole transport component, a second electron transport component, and a second emission layer disposed between the second hole transport component and the second electron transport component; and a charge generation layer disposed between the first emission component and the second emission component.

[0024] The charge generation layer may include a discontinuous portion overlapping at least a portion of each of the plurality of trenches.

[0025] The cathode electrode may be disposed continuously on the emitting structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other features of the embodiments of the present disclosure will become more apparent by describing the embodiments of the present disclosure in further detail with reference to the accompanying drawings.

[0027] Figure 1 is a block diagram schematically showing a display device according to an embodiment.

[0028] Figure 2 is a block diagram schematically illustrating a sub-pixel according to an embodiment.

[0029] Figure 3 is a plan view schematically showing a display panel according to an embodiment.

[0030] Figure 4 It is shown Figure 3 An exploded perspective view of a portion of a display panel.

[0031] Figure 5 is a cross-sectional view schematically showing an emission structure according to an embodiment.

[0032] Figure 6 is a cross-sectional view schematically showing an emission structure according to an embodiment.

[0033] Figure 7 is a plan view schematically showing a pixel according to an embodiment.

[0034] Figure 8 It is schematically shown that Figure 7 A plan view of a pixel display device.

[0035] Fig. 9 It is schematically shown Figure 8 A cross-sectional view of a display device.

[0036] Fig.10 is a plan view schematically showing a pixel according to an embodiment.

[0037] Fig.11 It is schematically shown that Fig.10 A plan view of a pixel display device.

[0038] Fig.12 yes Fig.11 Magnified view of the intersection area.

[0039] Fig.13 is along Fig.11 A cross-sectional view taken along line II'.

[0040] Fig.14 It is schematically shown Fig.11 A cross-sectional view of a display device.

[0041] Fig.15 It is schematically shown that Figure 7 A plan view of a pixel display device.

[0042] Fig.16 According to the embodiment Fig.15 Magnified view of the intersection area.

[0043] Fig.17 According to the embodiment Fig.15 Magnified view of the intersection area.

[0044] Fig.18 is a block diagram showing a display system according to an embodiment.

[0045] Fig.19 It is shown Fig.18 A perspective view showing an application example of the display system.

[0046] Fig. 20 It shows the device worn by the user. Fig.19 FIG. 1 is a diagram of a head mounted display device. DETAILED DESCRIPTION

[0047] The embodiments will be described more fully below with reference to the accompanying drawings in which various embodiments are shown. However, the inventive concept can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the inventive concept to those skilled in the art.

[0048] Throughout the specification, the same reference numerals refer to the same elements. In the accompanying drawings, for clarity, the thickness of certain lines, layers, components, elements or features may be exaggerated. It should be understood that although the terms "first", "second", etc. may be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, the "first" element discussed below may also be referred to as the "second" element.

[0049] The term used herein is only for the purpose of describing a particular embodiment, and is not intended to limit. Unless otherwise clearly indicated in the context, "a", "an", "the" and "at least one" as used herein do not represent the limitation of quantity, and are intended to include both the singular and the plural. For example, unless otherwise clearly indicated in the context, "element" has the same meaning as "at least one element". "At least one" should not be understood to limit "one" or "one". As used herein, word "or" means logical "or", so unless otherwise indicated in the context, expression "A, B or C" means "A and B and C", "A and B but not C", "A and C but not B", "B and C but not A", "A but not B and non-C", "B but not A and non-C" and "C but not A and non-B".

[0050] It will also be understood that the terms “comprise,” “comprising,” “include,” and “including” when used in this specification specify the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or clusters thereof.

[0051] Throughout the specification, when an element is referred to as being “connected” or “coupled” to another element, the element can be directly connected or coupled to the other element or indirectly connected or coupled to the other element with one or more intervening elements interposed therebetween.

[0052] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the figures. It should be understood that, in addition to the orientations depicted in the figures, relative terms are intended to include different orientations of the device. For example, if the device in one of the figures is turned over, the element described as being on the "lower" side of the other elements will then be oriented on the "upper" side of the other elements. Therefore, the term "lower" can include both the orientations of "lower" and "upper", depending on the specific orientation of the figure. Similarly, if the device in one of the figures is turned over, the element described as being "below" or "beneath" the other elements will then be oriented to be "above" the other elements. Therefore, the term "lower" or "under" can include both the orientations of the upper and lower parts.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that, unless explicitly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and will not be interpreted in an idealized or overly formal sense.

[0054] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0055] Figure 1 is a block diagram schematically showing a display device 100 according to an embodiment.

[0056] Reference Figure 1 , the display device 100 may include a display panel 110 , a gate driver 120 , a data driver 130 , a voltage generator 140 , and a controller 150 .

[0057] The display panel 110 may include a plurality of sub-pixels SP. The plurality of sub-pixels SP may be connected to the gate driver 120 through first to m-th gate lines GL1 to GLm. The plurality of sub-pixels SP may be connected to the data driver 130 through first to n-th data lines DL1 to DLn. Each of m and n may be an integer greater than 1.

[0058] Each of the plurality of sub-pixels SP may include at least one light emitting element configured to generate light. Accordingly, each of the plurality of sub-pixels SP may generate light of a specific color (such as red, green, blue, cyan, magenta, or yellow). Two or more sub-pixels among the plurality of sub-pixels SP may form one pixel PXL. For example, Figure 1 As shown in FIG. 1 , three sub-pixels SP may form one pixel PXL.

[0059] The gate driver 120 may be connected to the sub-pixels SP arranged in the row direction through the first gate line GL1 to the m-th gate line GLm. The gate driver 120 may output a gate signal to the first gate line GL1 to the m-th gate line GLm in response to a gate control signal GCS. In an embodiment, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting a gate signal in synchronization with a timing of applying a data signal, and the like.

[0060] In an embodiment, first to m-th emission control lines EL1 to ELm connected to the sub-pixels SP in the row direction may also be provided. In this case, the gate driver 120 may include an emission control driver configured to control the first to m-th emission control lines EL1 to ELm. The emission control driver may operate under the control of the controller 150.

[0061] The gate driver 120 may be disposed on one side of the display panel 110. However, the embodiment is not limited to the above example. For example, the gate driver 120 may be divided into two or more drivers that are physically and / or logically distinguished from each other. The driver may be disposed on a first side of the display panel 110 and a second side of the display panel 110 opposite to the first side. Thus, the gate driver 120 may be disposed around the display panel 110 in various forms according to the embodiment.

[0062] The data driver 130 may be connected to the sub-pixels SP arranged in the column direction through the first data line DL1 to the nth data line DLn. The data driver 130 may receive the image data DATA and the data control signal DCS from the controller 150. The data driver 130 may operate in response to the data control signal DCS. In an embodiment, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, and the like.

[0063] The data driver 130 may apply a data signal having a grayscale voltage corresponding to the image data DATA to the first to n-th data lines DL1 to DLn using a voltage from the voltage generator 140. When a gate signal is applied to each of the first to m-th gate lines GL1 to GLm, a data signal corresponding to the image data DATA may be applied to the first to n-th data lines DL1 to DLn. Therefore, the corresponding sub-pixel SP may generate light corresponding to the data signal. As a result, an image may be displayed on the display panel 110.

[0064] In an embodiment, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0065] The voltage generator 140 may operate in response to a voltage control signal VCS provided from the controller 150. The voltage generator 140 is configured to generate a plurality of voltages and provide the generated voltages to components of the display device 100. For example, the voltage generator 140 may receive an input voltage from an external device provided outside the display device 100, adjust the received voltage, and regulate the adjusted voltage, thereby generating the plurality of voltages.

[0066] The voltage generator 140 may generate a first power supply voltage VDD and a second power supply voltage VSS. The generated first power supply voltage VDD and the second power supply voltage VSS may be provided to the sub-pixel SP. The first power supply voltage VDD may have a relatively high voltage level. The second power supply voltage VSS may have a voltage level lower than that of the first power supply voltage VDD. In other embodiments, the first power supply voltage VDD or the second power supply voltage VSS may be provided by an external device of the display device 100.

[0067] In addition, the voltage generator 140 may generate various voltages. For example, the voltage generator 140 may generate an initialization voltage to be applied to the sub-pixel SP. For example, during a sensing operation for sensing electrical characteristics of a transistor and / or a light-emitting element of the sub-pixel SP, a certain reference voltage may be applied to each of the first to n-th data lines DL1 to DLn. The voltage generator 140 may generate a reference voltage.

[0068] The controller 150 may control the overall operation of the display device 100. The controller 150 may receive input image data IMG and a control signal CTRL for controlling an operation of displaying the input image data IMG from an external device. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0069] The controller 150 may convert the input image data IMG to be suitable for the display device 100 or the display panel 110 and thus output the image data DATA. In an embodiment, the controller 150 may align the input image data IMG by row to be suitable for the sub-pixels SP and then output the image data DATA.

[0070] Two or more components of the data driver 130, the voltage generator 140, and the controller 150 may be mounted into a single integrated circuit. Figure 1 As shown in , the data driver 130, the voltage generator 140 and the controller 150 may be included in the driving integrated circuit DIC. In this case, the data driver 130, the voltage generator 140 and the controller 150 may be components functionally separated from each other in a single driving integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140 and the controller 150 may be provided as a component separated from the driving integrated circuit DIC.

[0071] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 is configured to sense ambient temperature and generate temperature data TEP indicating the sensed temperature. In an embodiment, the temperature sensor 160 may be disposed adjacent to the display panel 110 and / or the driving integrated circuit DIC.

[0072] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. In an embodiment, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may control components such as the data driver 130 and / or the voltage generator 140 to adjust the data signal and the first and second power voltages VDD and VSS.

[0073] Figure 2 is a block diagram schematically showing a sub-pixel SPij according to an embodiment. Figure 2 , a sub-pixel SPij disposed in an i-th row (where i is an integer greater than or equal to 1 and less than or equal to m) and a j-th column (where j is an integer greater than or equal to 1 and less than or equal to n) is shown.

[0074] Reference Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0075] The light emitting element LD is connected between the first power supply voltage node VDDN and the second power supply voltage node VSSN. Here, the first power supply voltage node VDDN can be provided as a transmission Figure 1 The second power supply voltage node VSSN can be provided as a transmission node. Figure 1 A node of a second power supply voltage VSS.

[0076] The anode electrode AE ​​of the light emitting element LD may be connected to the first power supply voltage node VDDN through the sub-pixel circuit SPC. The cathode electrode CE of the light emitting element LD may be connected to the second power supply voltage node VSSN. For example, the anode electrode AE ​​of the light emitting element LD may be connected to the first power supply voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0077] The sub-pixel circuit SPC can be connected to Figure 1 The i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm, Figure 1 The i-th emission control line ELi among the first emission control line EL1 to the m-th emission control line ELm and Figure 1 The sub-pixel circuit SPC is configured to control the light emitting element LD in response to a signal received through the above-mentioned signal line.

[0078] The sub-pixel circuit SPC may operate in response to a gate signal received through the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. Figure 2 As shown in , the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC may operate in response to a gate signal received through the first sub-gate line SGL1 and the second sub-gate line SGL2. Thus, in the case where the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC may operate in response to a gate signal received through the corresponding sub-gate line.

[0079] The sub-pixel circuit SPC may operate in response to an emission control signal received through the i-th emission control line ELi. In an embodiment, the i-th emission control line ELi may include one or more sub-emission control lines. In the case where the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC may operate in response to an emission control signal received through the corresponding sub-emission control line.

[0080] The sub-pixel circuit SPC may receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC may store a voltage corresponding to the data signal in response to at least one of the gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. The sub-pixel circuit SPC may adjust a current flowing from the first power supply voltage node VDDN through the light emitting element LD to the second power supply voltage node VSSN according to the stored voltage in response to the emission control signal received through the i-th emission control line ELi. Therefore, the light emitting element LD may emit light at a brightness corresponding to the data signal.

[0081] Figure 3 is a plan view schematically showing a display panel DP according to an embodiment.

[0082] Reference Figure 3 , Figure 1 The embodiment of the display panel 110 depicted in FIG. 1 may include a display panel DP including a display area DA and a non-display area NDA. The display panel DP may display an image through the display area DA. The non-display area NDA may be disposed around the display area DA.

[0083] The display panel DP may include a substrate SUB, sub-pixels SP, and pads PD.

[0084] In the case where the display panel DP is used as a display screen of a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, and the like, the display panel DP may be positioned very close to the user's eyes. In this case, a relatively high density of sub-pixels SP may be required. In order to increase the pixel density of the sub-pixels SP, the substrate SUB may be provided as a silicon substrate. The sub-pixels SP may be formed on a substrate SUB which is a silicon substrate. A display device 100 (refer to FIG. 1 ) including a display panel DP having a substrate SUB which is a silicon substrate Figure 1 ) can be called a silicon-based OLED (OLEDoS) display device.

[0085] A plurality of sub-pixels SP may be disposed in a display area DA on a substrate SUB. The plurality of sub-pixels SP may be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiment is not limited to the above example. For example, the plurality of sub-pixels SP may be arranged in a zigzag pattern in the first direction DR1 and the second direction DR2. For example, the plurality of sub-pixels SP may be arranged in a zigzag pattern in the first direction DR1 and the second direction DR2. The first direction DR1 may refer to a row direction, and the second direction DR2 may refer to a column direction.

[0086] Two or more sub-pixels among the plurality of sub-pixels SP may form one pixel PXL.

[0087] A component for controlling the sub-pixel SP may be disposed in the non-display area NDA on the substrate SUB. For example, a line (such as Figure 1 The first to m-th gate lines GL1 to GLm and the first to n-th data lines DL1 to DLn) may be disposed in the non-display area NDA.

[0088] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, the controller 150, and the temperature sensor 160 of the display panel DP may be integrated in the non-display area NDA. In an embodiment, Figure 1 The gate driver 120 may be mounted on the display panel DP and positioned in the non-display area NDA. In other embodiments, the gate driver 120 may be implemented as an integrated circuit separated from the display panel DP. In an embodiment, the temperature sensor 160 may be positioned in the non-display area NDA to sense the temperature of the display panel DP.

[0089] The pad PD may be disposed in the non-display area NDA on the substrate SUB. The pad PD may be electrically connected to the sub-pixel SP through a line. For example, the pad PD may be connected to the sub-pixel SP through the first to nth data lines DL1 to DLn.

[0090] The pad PD can connect the display panel DP and the display device 100 (see Figure 1 In an embodiment, voltages and signals required for the operation of components included in the display panel DP may be obtained from Figure 1 The gate control signal GCS may be provided to the driver integrated circuit DIC through the pad PD. For example, the first data line DL1 to the nth data line DLn may be connected to the driver integrated circuit DIC through the pad PD. For example, the first power supply voltage VDD and the second power supply voltage VSS may be received from the driver integrated circuit DIC through the pad PD. For example, in the case where the gate driver 120 is mounted on the display panel DP, the gate control signal GCS may be transmitted from the driver integrated circuit DIC to the gate driver 120 through the pad PD.

[0091] In an embodiment, the circuit board may be electrically connected to the pad PD by a conductive adhesive member such as an anisotropic conductive film. Here, the circuit board may be a flexible circuit board or a flexible film made of a flexible material. The driving integrated circuit DIC may be mounted on the circuit board and electrically connected to the pad PD.

[0092] In an embodiment, the display area DA may have various shapes. The display area DA may have a closed loop shape including straight and / or curved edges. For example, the display area DA may have a shape such as a polygon, a circle, a semicircle, an ellipse, and the like.

[0093] In an embodiment, the display panel DP may have a flat display surface. In an embodiment, the display panel DP may have a display surface that is at least partially rounded. In an embodiment, the display panel DP may be bendable, foldable, or rollable. In the above case, the display panel DP and / or the substrate SUB may include a material having a flexible property.

[0094] Figure 4 It is shown Figure 3 An exploded perspective view of a portion of the display panel DP. Figure 4 In the figure, for the sake of clarity and concise explanation, the display panel DP is schematically shown. Figure 3 The remaining portions of the display panel DP corresponding to other pixels may also be configured in the same manner.

[0095] Reference Figure 3 and Figure 4 , each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, the embodiment is not limited to the above example. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels, or may include two sub-pixels.

[0096] exist Figure 4 2 shows a case where the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 have a rectangular shape and have the same size when viewed in a third direction DR3 intersecting the first direction DR1 and the second direction DR2. However, the embodiment is not limited to the above example. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be modified to have various shapes.

[0097] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, an encapsulation layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0098] In an embodiment, the substrate SUB may include a silicon wafer substrate formed by a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming a circuit element. For example, the semiconductor material may include silicon, germanium and / or silicon-germanium. The substrate SUB may be provided from a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, or the like. In an embodiment, the substrate SUB may include a glass substrate. In an embodiment, the substrate SUB may include a polyimide (PI) substrate.

[0099] The pixel circuit layer PCL may be disposed on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layers. The conductive pattern of the pixel circuit layer PCL may be used as at least some of circuit elements, lines, and the like. The conductive pattern may include copper, but the embodiment is not limited thereto.

[0100] The circuit element may include corresponding sub-pixel circuits SPC of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 (refer to Figure 2 ). The sub-pixel circuit SPC may include a plurality of transistors and one or more capacitors. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. In an embodiment, in the case where the substrate SUB is formed of a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In an embodiment, in the case where the substrate SUB is formed of a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other on a plane defined by a first direction DR1 and a second direction DR2. For example, each capacitor may include electrodes spaced apart from each other in a third direction DR3 with an insulating layer interposed therebetween.

[0101] The lines of the pixel circuit layer PCL may include signal lines connected to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, for example, a gate line, an emission control line, and a data line. The lines may also include signal lines connected to Figure 2 In addition, the line may also include a line connected to the first power supply voltage node VDDN. Figure 2 A line to the second power supply voltage node VSSN.

[0102] The light emitting element layer LDL may include an anode electrode AE, a pixel defining layer PDL, an emission structure EMS, and a cathode electrode CE.

[0103] The anode electrode AE ​​may be disposed on the pixel circuit layer PCL. The anode electrode AE ​​may contact a circuit element of the pixel circuit layer PCL. The anode electrode AE ​​may include an opaque conductive material capable of reflecting light, but the embodiment is not limited thereto.

[0104] The pixel defining layer PDL may be disposed on the anode electrode AE. The pixel defining layer PDL may include an opening OP extending to and exposing a corresponding portion of the anode electrode AE. The opening OP in the pixel defining layer PDL may be understood as a corresponding emission region corresponding to the first to third subpixels SP1 to SP3.

[0105] In an embodiment, the pixel defining layer PDL may include an inorganic material. In this case, the pixel defining layer PDL may include a plurality of inorganic layers stacked one above the other. For example, the pixel defining layer PDL may include silicon oxide (SiO x ) and silicon nitride (SiN x In an embodiment, the pixel defining layer PDL may include an organic material. However, the material of the pixel defining layer PDL is not limited to the above examples.

[0106] The emission structure EMS may be disposed on the anode electrode AE ​​exposed through the opening OP in the pixel defining layer PDL. The emission structure EMS may include an emission layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes.

[0107] In an embodiment, the emission structure EMS may fill the opening OP in the pixel defining layer PDL and be disposed on the entire surface of the upper portion of the pixel defining layer PDL. In other words, the emission structure EMS may extend over the first sub-pixel SP1 to the third sub-pixel SP3. In this case, at least some of the multiple layers in the emission structure EMS may be interrupted or bent on the boundaries between the first sub-pixel SP1 to the third sub-pixel SP3. However, the embodiments are not limited to the above examples. For example, portions of the emission structure EMS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 may be separated from each other, and each may be disposed in a corresponding opening OP in the pixel defining layer PDL.

[0108] The cathode electrode CE may be disposed on the emission structure EMS. The cathode electrode CE may extend throughout the first sub-pixel SP1 to the third sub-pixel SP3. Thus, the cathode electrode CE may be provided as a common electrode of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0109] The cathode electrode CE may be a thin film metal layer having a thickness that allows light emitted from the emission structure EMS to pass through. The cathode electrode CE may be made of a metal material or a transparent conductive material having a relatively small thickness. In an embodiment, the cathode electrode CE may include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. In an embodiment, the cathode electrode CE may include at least one of silver (Ag), magnesium (Mg), and a compound thereof. However, the material of the cathode electrode CE is not limited to the above examples.

[0110] Any one of the anode electrodes AE, the portion of the emission structure EMS overlapping with the any one of the anode electrodes AE, and the portion of the cathode electrode CE overlapping with the portion of the emission structure EMS can be understood as constituting one light emitting element LD (refer to Figure 2). In other words, each of the light-emitting elements of the first subpixel SP1 to the third subpixel SP3 may include an anode electrode AE, a portion of the emission structure EMS overlapping with the anode electrode AE, and a portion of the cathode electrode CE overlapping with the portion of the emission structure EMS. In each of the first subpixel SP1 to the third subpixel SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE are transferred to the emission layer of the emission structure EMS, thereby forming excitons. When the excitons transition from an excited state to a ground state, light can be generated. The brightness of the light can be determined based on the amount of current flowing through the emission layer. The wavelength range of the light to be generated can be determined based on the configuration of the emission layer.

[0111] The encapsulation layer TFE may be disposed on the cathode electrode CE. The encapsulation layer TFE may cover the light emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE may be configured to prevent oxygen and / or water or the like from penetrating into the light emitting element layer LDL. In an embodiment, the encapsulation layer TFE may include a structure formed by alternately stacking one or more inorganic layers and one or more organic layers. For example, the inorganic layer may include silicon nitride, silicon oxide, silicon oxynitride (SiO x N y ) or the like. For example, the organic layer may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the encapsulation layer TFE are not limited to the above examples.

[0112] The encapsulation layer TFE may also include aluminum oxide (AlO x ) film to improve the encapsulation efficiency of the encapsulation layer TFE. The film containing aluminum oxide may be positioned on the upper surface of the encapsulation layer TFE facing the optical function layer OFL and / or under the lower surface of the encapsulation layer TFE facing the light emitting element layer LDL.

[0113] The thin film including aluminum oxide may be formed by an atomic layer deposition (ALD) method. However, the embodiment is not limited to the above example. The encapsulation layer TFE may also include a thin film formed of at least one of various materials suitable for improving encapsulation efficiency.

[0114] The optical function layer OFL may be disposed on the encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0115] The color filter layer CFL may be disposed between the encapsulation layer TFE and the lens array LA. The color filter layer CFL may be configured to filter the light emitted from the emission structure EMS to selectively output light of a wavelength range or color corresponding to each sub-pixel. The color filter layer CFL may include a plurality of color filters CF corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively. Each of the plurality of color filters CF allows light within a wavelength range corresponding to the associated sub-pixel to pass through. For example, the color filter corresponding to the first sub-pixel SP1 allows red light to pass through, the color filter corresponding to the second sub-pixel SP2 allows green light to pass through, and the color filter corresponding to the third sub-pixel SP3 allows blue light to pass through. Depending on the light emitted from the emission structure EMS of each sub-pixel, at least some of the plurality of color filters CF may be omitted.

[0116] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include a plurality of lenses LS corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the plurality of lenses LS may output and guide the light emitted from the emission structure EMS along a desired path, thereby improving light output efficiency. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a refractive index higher than that of the overcoat layer OC. In an embodiment, the lens LS may include an organic material. In an embodiment, the lens LS may include an acrylic material. However, the material of the lens LS is not limited to the above examples.

[0117] In an embodiment, compared to the opening OP of the pixel defining layer PDL, at least some of the plurality of color filters CF of the color filter layer CFL and at least some of the plurality of lenses LS of the lens array LA may be displaced in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2. Specifically, in the central area of ​​the display area DA, the center of each color filter and the center of each lens may be aligned or overlapped with the center of the corresponding opening OP of the pixel defining layer PDL. For example, in the central area of ​​the display area DA, each opening OP of the pixel defining layer PDL may completely overlap with the corresponding color filter of the color filter layer CFL and the corresponding lens of the lens array LA. In the area of ​​the display area DA adjacent to the non-display area NDA, when viewed in the third direction DR3, the center of the color filter CF and the center of the lens LS may be displaced in a plane direction from the center of the corresponding opening OP of the pixel defining layer PDL. For example, in the area adjacent to the non-display area NDA in the display area DA, each opening OP of the pixel defining layer PDL may partially overlap with the corresponding color filter of the color filter layer CFL and the corresponding lens of the lens array LA. Accordingly, light emitted from the emission structure EMS in the central portion of the display area DA can be effectively output in the normal direction of the display surface. Light emitted from the emission structure EMS around the periphery of the display area DA can be effectively output in a direction inclined at a certain angle relative to the normal direction of the display surface.

[0118] An outer coating OC may be disposed on the lens array LA. The outer coating OC may cover the optical function layer OFL, the encapsulation layer TFE, the emission structure EMS and / or the pixel circuit layer PCL. The outer coating OC may include various materials suitable for protecting the underlying layers from foreign matter such as dust, water or the like. For example, the outer coating OC may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the outer coating OC may include an epoxy resin, but is not limited thereto. The outer coating OC may have a refractive index lower than that of the lens array LA.

[0119] The cover window CW may be disposed on the outer coating layer OC. The cover window CW may be configured to protect the lower layer. The cover window CW may have a refractive index higher than that of the outer coating layer OC. The cover window CW may include glass, but the embodiment is not limited thereto. For example, the cover window CW may be an encapsulation glass layer configured to protect components disposed thereunder. In other embodiments, the cover window CW may be omitted.

[0120] Figure 5 is a cross-sectional view schematically showing an emission structure EMS according to an embodiment.

[0121] Reference Figure 5, the emission structure EMS may have a tandem structure in which the first emission part EU1 and the second emission part EU2 are stacked.

[0122] Each of the first emission component EU1 and the second emission component EU2 may include at least one emission layer configured to generate light in response to a current applied thereto. The first emission component EU1 may include a first emission layer EML1, a first electron transport component ETU1, and a first hole transport component HTU1. The first emission layer EML1 may be disposed between the first electron transport component ETU1 and the first hole transport component HTU1. The second emission component EU2 may include a second emission layer EML2, a second electron transport component ETU2, and a second hole transport component HTU2. The second emission layer EML2 may be disposed between the second electron transport component ETU2 and the second hole transport component HTU2.

[0123] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, and the like as needed. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same configuration or different configurations.

[0124] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, and the like as needed. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same configuration or different configurations.

[0125] A connection layer that can be provided in the form of a charge generation layer CGL may be provided between the first emission component EU1 and the second emission component EU2 to connect the first emission component EU1 and the second emission component EU2 to each other. In an embodiment, the charge generation layer CGL may have a stacked structure including a p-dopant layer and an n-dopant layer. For example, the p-dopant layer may include a p-type dopant such as HAT-CN, TCNQ, or NDP-9, and the n-dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof. However, the embodiments are not limited to the above examples.

[0126] In an embodiment, the first emission layer EML1 and the second emission layer EML2 may generate light of different colors. The light emitted from the first emission layer EML1 and the second emission layer EML2 may be mixed into visible white light. For example, the first emission layer EML1 may generate blue light, and the second emission layer EML2 may generate yellow light. In an embodiment, the second emission layer EML2 may include a stacked structure including a first sub-emission layer configured to generate red light and a second sub-emission layer configured to generate green light. The red light and the green light may be mixed to provide yellow light. In this case, an intermediate layer configured to perform the function of transporting holes and / or blocking electron transport may also be provided between the first sub-emission layer and the second sub-emission layer.

[0127] In an embodiment, the first emission layer EML1 and the second emission layer EML2 may generate light of the same color.

[0128] The emission structure EMS may be formed through a scheme such as vacuum deposition, inkjet printing, or the like, but the embodiment is not limited thereto.

[0129] Figure 6 is a cross-sectional view schematically showing an emission structure EMS according to an embodiment.

[0130] Reference Figure 6 , the emission structure EMS may have a series structure in which the first to third emission parts EU1 to EU3 are stacked.

[0131] Each of the first emission component EU1 to the third emission component EU3 may include an emission layer configured to generate light in response to a current applied thereto. The first emission component EU1 may include a first emission layer EML1, a first electron transport component ETU1, and a first hole transport component HTU1. The first emission layer EML1 may be disposed between the first electron transport component ETU1 and the first hole transport component HTU1. The second emission component EU2 may include a second emission layer EML2, a second electron transport component ETU2, and a second hole transport component HTU2. The second emission layer EML2 may be disposed between the second electron transport component ETU2 and the second hole transport component HTU2. The third emission component EU3 may include a third emission layer EML3, a third electron transport component ETU3, and a third hole transport component HTU3. The third emission layer EML3 may be disposed between the third electron transport component ETU3 and the third hole transport component HTU3.

[0132] Each of the first to third hole transport components HTU1 to HTU3 may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, and the like as needed. The first to third hole transport components HTU1 to HTU3 may have the same configuration or different configurations.

[0133] Each of the first to third electron transport units ETU1 to ETU3 may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, and the like as needed. The first to third electron transport units ETU1 to ETU3 may have the same configuration or different configurations.

[0134] The first charge generation layer CGL1 may be disposed between the first emission part EU1 and the second emission part EU2. The second charge generation layer CGL2 may be disposed between the second emission part EU2 and the third emission part EU3.

[0135] In an embodiment, the first emission layer EML1 to the third emission layer EML3 may generate light of different colors. The light emitted from the first emission layer EML1 to the third emission layer EML3 may be mixed into visible white light. For example, the first emission layer EML1 may generate blue light, the second emission layer EML2 may generate green light, and the third emission layer EML3 may generate red light.

[0136] In other embodiments, two or more emission layers among the first to third emission layers EML1 to EML3 may generate light of the same color.

[0137] and Figure 5 and Figure 6 Unlike the situation shown in , the emitting structure EMS may comprise a single emitting component.

[0138] Figure 7 is a plan view schematically showing a pixel PXL according to an embodiment.

[0139] Reference Figure 7 , the pixel PXL may include first to third sub-pixels SP1 to SP3.

[0140] The first subpixel SP1 may include a first emission area EMA1 and a non-emission area NEA formed around the first emission area EMA1. The second subpixel SP2 may include a second emission area EMA2 and a non-emission area NEA formed around the second emission area EMA2. The third subpixel SP3 may include a third emission area EMA3 and a non-emission area NEA formed around the third emission area EMA3.

[0141] The first emission area EMA1 may be a region where the emission structure EMS (see Figure 4) may be an area where light is emitted from a portion of the emission structure EMS corresponding to the first sub-pixel SP1. The second emission area EMA2 may be an area where light is emitted from a portion of the emission structure EMS corresponding to the second sub-pixel SP2. The third emission area EMA3 may be an area where light is emitted from a portion of the emission structure EMS corresponding to the third sub-pixel SP3. Figure 4 As described above, each emission region may be understood as an opening OP of the pixel defining layer PDL corresponding to each of the first to third sub-pixels SP1 to SP3 .

[0142] Each of the first to third emission areas EMA1 to EMA3 may have a quadrilateral shape. For example, each corner of the first to third emission areas EMA1 to EMA3 may be a right angle. The term “quadrilateral shape” may mean a rectangular or square shape.

[0143] The first sub-pixel SP1 and the second sub-pixel SP2 may be arranged in the first direction DR1. The third sub-pixel SP3 may be disposed in the second direction DR2 relative to each of the first sub-pixel SP1 and the second sub-pixel SP2. However, the embodiment is not limited to the above example. For example, the first sub-pixel SP1 to the third sub-pixel SP3 may be arranged in the first direction DR1.

[0144] The first sub-pixel SP1 may have a surface area larger than that of the second sub-pixel SP2. The third sub-pixel SP3 may have a surface area larger than that of the first sub-pixel SP1. Therefore, the first emission area EMA1 may have a surface area larger than that of the second emission area EMA2. The third emission area EMA3 may have a surface area larger than that of the first emission area EMA1. However, the embodiments are not limited to the above examples. For example, the first sub-pixel SP1 and the second sub-pixel SP2 may have substantially the same surface area. The third sub-pixel SP3 may have a surface area larger than that of each of the first sub-pixel SP1 and the second sub-pixel SP2. Thus, the surface areas of the first to third sub-pixels SP1 to SP3 may be changed in various ways depending on the embodiments.

[0145] Figure 8 It is schematically shown that Figure 7 1 is a plan view of a display device 100 having a pixel PXL.

[0146] Reference Figure 8 The display device 100 may include a non-emission area NEA (refer to Figure 7 ) overlapped with a pixel defining layer PDL. The pixel defining layer PDL may include a trench TRCH integrally formed to surround the first to third emission areas EMA1 to EMA3. Fig. 9The trench TRCH may refer to a structure formed in the pixel defining layer PDL and partially penetrating the pixel defining layer PDL, but the embodiment is not limited thereto.

[0147] The groove TRCH may be patterned by etching a portion of the pixel defining layer PDL between the first emission area EMA1 to the third emission area EMA3. Therefore, the groove TRCH may be positioned between the first emission area EMA1 to the third emission area EMA3. For example, the groove TRCH may be positioned between the first emission area EMA1 and the second emission area EMA2. For example, the groove TRCH may be positioned between the first emission area EMA1 and the third emission area EMA3. For example, the groove TRCH may be positioned between the second emission area EMA2 and the third emission area EMA3. For example, the groove TRCH may be positioned between the adjacent third emission area EMA3. In other words, one groove TRCH may be positioned between the first emission area EMA1 to the third emission area EMA3 separated by a space from the first emission area EMA1 to the third emission area EMA3.

[0148] The trench TRCH may be patterned along the periphery of the first to third emission areas EMA1 to EMA3 to surround the first to third emission areas EMA1 to EMA3. For example, the trench TRCH having a certain width w may be patterned along the periphery of the first to third emission areas EMA1 to EMA3 each having a right angle corner. In this case, an intersection area CA may be formed in which portions of the trench TRCH intersect each other. For convenience of explanation, in Figure 8 , the intersection area CA of the trench TRCH formed in the center portion is shown as a representative example, and reference numerals for other intersection areas are omitted.

[0149] Ideally, the pixel defining layer PDL adjacent to the intersection region CA of the trench TRCH may have a rectangular shape. However, referring to the enlarged view of the intersection region CA, since it is difficult to achieve right-angle patterning in the manufacturing process, the pixel defining layer PDL adjacent to the intersection region CA has a substantially rounded shape. Accordingly, the oblique line width w of the trench TRCH in the intersection region CA is d Can be increased.

[0150] Fig. 9 It is schematically shown Figure 8 1 is a cross-sectional view of a display device 100 .

[0151] Reference Fig. 9Due to the trench TRCH, a discontinuous portion such as a gap VD may be formed in the emission structure EMS. Some of the multiple layers stacked in the emission structure EMS may be interrupted or bent by the gap VD. For example, the charge generation layer CGL included in the emission structure EMS may be interrupted by the gap VD. Therefore, the lateral leakage current may be prevented from flowing through the charge generation layer CGL in the adjacent sub-pixel SP (refer to Figure 1 ) flows between.

[0152] As the width of the trench TRCH increases, the length l of the gap VD may increase. For example, as the cross region CA (refer to Figure 8 ) in the trench TRCH has a diagonal width w d In this case, unlike the above-described embodiment, the charge generation layer CGL extends as a whole without interruption. Therefore, a lateral leakage current may flow between adjacent sub-pixels SP. In addition, the gap VD may grow and reach the cathode electrode CE, thereby causing a disconnection in the cathode electrode CE. In addition, the gap VD may grow and reach the encapsulation layer TFE, thereby causing a disconnection in the encapsulation layer TFE, or a defect such as a seam may appear in the encapsulation layer TFE.

[0153] Fig.10 is a plan view schematically showing a pixel PXL' according to an embodiment.

[0154] about Fig.10 ,and Figure 7 Explanation of overlapping content is simplified or omitted.

[0155] Reference Fig.10 , the pixel PXL' may include first to third sub-pixels SP1' to SP3'.

[0156] The first subpixel SP1' may include a first emission area EMA1' and a non-emission area NEA' formed around the first emission area EMA1'. The second subpixel SP2' may include a second emission area EMA2' and a non-emission area NEA' formed around the second emission area EMA2'. The third subpixel SP3' may include a third emission area EMA3' and a non-emission area NEA' formed around the third emission area EMA3'.

[0157] Each of the first to third emission areas EMA1' to EMA3' may have an octagonal shape. For example, each corner of the first to third emission areas EMA1' to EMA3' may be chamfered. Thus, Fig.10 The sizes of the first emission area EMA1' to the third emission area EMA3' shown in FIG. Figure 7The sizes of the first emission area EMA1 to the third emission area EMA3 are shown in FIG. Fig.10 The size of the non-emission area NEA′ shown in FIG. 4 may be larger than Figure 7 The size of the non-emitting area NEA is shown in .

[0158] Fig.11 It is schematically shown that includes Fig.10 1 is a plan view of a display device 100 ′ having pixels.

[0159] Reference Fig.11 The display device 100' may include a non-emitting area NEA' (refer to Fig.10 The pixel defining layer PDL' may include a plurality of trenches TRCH' separately formed to surround the first to third emission areas EMA1' to EMA3', respectively.

[0160] The plurality of trenches TRCH' may be divided into a first trench TRCH1', a second trench TRCH2', and a third trench TRCH3' according to the position. For example, each of the first trenches TRCH1' may surround a corresponding first emission area EMA1'. For example, each of the second trenches TRCH2' may surround a corresponding second emission area EMA2'. For example, each of the third trenches TRCH3' may surround a corresponding third emission area EMA3'.

[0161] The groove TRCH' may be patterned by etching a portion of the pixel defining layer PDL' between the first emission area EMA1' to the third emission area EMA3'. Therefore, the groove TRCH' may be positioned between the first emission area EMA1' to the third emission area EMA3'. For example, each of the first groove TRCH1' and each of the second groove TRCH2' may be positioned between the first emission area EMA1' and the second emission area EMA2'. For example, each of the first groove TRCH1' and each of the third groove TRCH3' may be positioned between the first emission area EMA1' and the third emission area EMA3'. For example, each of the second groove TRCH2' and each of the third groove TRCH3' may be positioned between the second emission area EMA2' and the third emission area EMA3'. For example, each of the third groove TRCH3' may be positioned between the adjacent third emission areas EMA3'. In other words, the two grooves TRCH' may be positioned between the first emission area EMA1' to the third emission area EMA3' separated by a space from the first emission area EMA1' to the third emission area EMA3'.

[0162] The corners of the trench TRCH' may be chamfered. For example, each corner of the first trench TRCH1' to the third trench TRCH3' may be chamfered. Fig.11 As shown in FIG. 1 , each of the first to third trenches TRCH1 ′ to TRCH3 ′ may be patterned in an octagonal shape on outer and inner surfaces thereof.

[0163] The grooves TRCH' may be patterned along the periphery of the first to third emission areas EMA1' to EMA3' to surround the first to third emission areas EMA1' to EMA3'. For example, each of the first grooves TRCH1' may be patterned along the periphery of the corresponding first emission area EMA1' having a chamfered corner. For example, each of the second grooves TRCH2' may be patterned along the periphery of the corresponding second emission area EMA2' having a chamfered corner. For example, each of the third grooves TRCH3' may be patterned along the periphery of the corresponding third emission area EMA3' having a chamfered corner.

[0164] In this case, a crossing area CA' may be formed in which portions of the pixel defining layer PDL' cross each other. Fig.11 , the intersection area CA′ formed in the center portion is shown as a representative example, and reference numerals for other intersection areas are omitted.

[0165] Fig.12 yes Fig.11 Magnified view of the intersection area CA'.

[0166] Reference Fig.12 , groove TRCH' (refer to Fig.11 ) may include an inner corner IC' and an outer corner OC'. In an embodiment, the inner corner IC' and the outer corner OC' of the trench TRCH' may be chamfered. Therefore, the corner and the edge EG' of the trench TRCH' may have a uniform width w'. Thus, as each of the trenches TRCH' surrounds a corresponding emission region and has a chamfered inner corner IC' and a chamfered outer corner OC', an intersection region CA' of a pixel defining layer may be formed instead of an intersection region CA of the trenches (refer to Figure 8 ). Therefore, each of the trenches TRCH' may have a uniform width w' along the periphery of the corresponding emission region.

[0167] Fig.13 is along Fig.11 A cross-sectional view taken along line II'.

[0168] Reference Fig.13 The pixel circuit layer PCL may be disposed on the substrate SUB. The via layer VIAL may be disposed on the pixel circuit layer PCL.

[0169] The via layer VIAL may cover the pixel circuit layer PCL and have an overall flat surface. The via layer VIAL is configured to flatten the step portion on the pixel circuit layer PCL. The via layer VIAL may include silicon oxide (SiO x ), silicon nitride (SiN x ) and at least one of silicon carbonitride (SiCN), but the embodiment is not limited thereto.

[0170] The reflective electrode RE may be disposed on the via layer VIAL. Each of the reflective electrodes RE may be used as a source for transmitting light from the emission structure EMS (refer to Figure 4 ) is a total reflection mirror that reflects light emitted by the display surface. The reflective electrode RE may include a metal material suitable for reflecting light. For example, the reflective electrode RE may include at least one of the following: aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected from the above materials, but the embodiment is not limited thereto.

[0171] In order to planarize the step portion between the reflective electrodes RE, a planarization layer PLNL may be disposed on the via layer VIAL and the reflective electrode RE. The planarization layer PLNL may cover the entire surface of the reflective electrode RE and the via layer VIAL and may have a flat surface. In an embodiment, the planarization layer PLNL may be omitted.

[0172] On the planarization layer PLNL, an anode electrode AE ​​may be provided for the corresponding reflective electrode RE. The anode electrode AE ​​may be connected to the corresponding reflective electrode RE through via holes (not shown). In an embodiment, the anode electrode AE ​​may include an indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO). However, the material of the anode electrode AE ​​is not limited to the above examples. For example, the anode electrode AE ​​may include titanium nitride.

[0173] The pixel defining layer PDL' may be disposed on the anode electrode AE ​​and portions of the planarization layer PLNL. The pixel defining layer PDL' may be disposed in the non-emission area NEA' and define each emission area.

[0174] In an embodiment, the pixel defining layer PDL' may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include silicon oxide (SiO x ) and silicon nitride (SiN x). For example, the pixel defining layer PDL' may include first to third inorganic insulating layers PDL1' to PDL3' which are stacked in series. The first to third inorganic insulating layers PDL1' to PDL3' may include silicon nitride, silicon oxide, and silicon nitride, respectively, but the embodiment is not limited thereto. The first to third inorganic insulating layers PDL1' to PDL3' may have a stepped cross-section.

[0175] In an embodiment, the groove TRCH' may pass through the pixel defining layer PDL' and partially penetrate the planarization layer PLNL. However, the embodiment is not limited to the above example. In an embodiment, the groove TRCH' may pass through the pixel defining layer PDL' and the planarization layer PLNL, and partially penetrate the via layer VIAL. For example, the groove TRCH' may partially penetrate the pixel defining layer PDL'.

[0176] In an embodiment, the width w' of the trench TRCH' may range from 80 nm to 150 nm. The thickness t of the trench TRCH' may range from 300 nm to 1000 nm. The distance d between the trenches TRCH' may range from 100 nm to 300 nm.

[0177] Fig.14 It is schematically shown Fig.11 1 is a cross-sectional view of a display device 100'.

[0178] Reference Fig.14 Due to the trench TRCH', a discontinuous portion such as a void VD' may be formed in the emission structure EMS'. Since the trench TRCH' has a uniform width w' along the periphery of each emission region, the intersection area CA' (refer to Fig.11 ) does not increase the width (or diagonal width) of each corner of the trench TRCH' in the emission structure EMS'. Therefore, the length l' of the gap VD' does not increase. Therefore, the charge generation layer CGL' included in the emission structure EMS' may have a discontinuous portion overlapping at least a portion of the trench TRCH'. In other words, the charge generation layer CGL' is interrupted by the gap VD' instead of extending as a whole. As a result, it is possible to prevent the lateral leakage current from flowing through the charge generation layer CGL' in the adjacent sub-pixel SP (refer to Figure 1 ) between. In addition, since the length l' of the gap VD' is relatively short, the gap VD' does not grow to reach the cathode electrode CE'. Therefore, the cathode electrode CE' can be continuously formed on the emission structure EMS' without being disconnected. In addition, the gap VD' does not grow to reach the encapsulation layer TFE'. Therefore, the encapsulation layer TFE' is not interrupted and can be uniformly formed without defects such as seams in the encapsulation layer TFE'.

[0179] Fig.15It is schematically shown that includes Figure 7 1 is a plan view of a display device 100 having a pixel PXL.

[0180] Reference Fig.15 The display device 100 may include a non-emitting area NEA (refer to Figure 7 ) overlapping the pixel defining layer PDL. The pixel defining layer PDL may include a plurality of trenches TRCH" which are separately formed to respectively surround the first to third emission areas EMA1 to EMA3. Fig.15 As shown in FIG. 1 , the display device 100 ″ may include first to third emission areas EMA1 to EMA3 each having a right-angled corner, thereby resulting in an increase in aperture ratio, thereby improving emission efficiency.

[0181] The grooves TRCH” may be divided into a first groove TRCH1”, a second groove TRCH2” and a third groove TRCH3” according to the position. For example, each of the first grooves TRCH1” may surround a corresponding first emission area EMA1. For example, each of the second grooves TRCH2” may surround a corresponding second emission area EMA2. For example, each of the third grooves TRCH3” may surround a corresponding third emission area EMA3.

[0182] The groove TRCH" may be patterned by etching a portion of the pixel defining layer PDL" between the first emission area EMA1 to the third emission area EMA3. Therefore, the groove TRCH" may be positioned between the first emission area EMA1 to the third emission area EMA3. For example, each of the first groove TRCH1" and each of the second groove TRCH2" may be positioned between the first emission area EMA1 and the second emission area EMA2. For example, each of the first groove TRCH1" and each of the third groove TRCH3" may be positioned between the first emission area EMA1 and the third emission area EMA3. For example, each of the second groove TRCH2" and each of the third groove TRCH3" may be positioned between the second emission area EMA2 and the third emission area EMA3. For example, each of the third groove TRCH3" may be positioned between adjacent third emission areas EMA3. In other words, the two grooves TRCH" may be positioned between the first emission area EMA1 to the third emission area EMA3 with a space therebetween.

[0183] The corners of the trench TRCH" may be chamfered. For example, each corner of the first trench TRCH1" to the third trench TRCH3" may be chamfered. Fig.15 As shown in FIG. 1 , the outer side of each of the first to third trenches TRCH1 ″ to TRCH3 ″ may be patterned in an octagonal shape, and the inner side thereof may be patterned in a quadrangular shape.

[0184] The grooves TRCH” may be patterned along the periphery of the first to third emission areas EMA1 to EMA3 to surround the first to third emission areas EMA1 to EMA3. For example, each of the first grooves TRCH1” may be patterned along the periphery of the corresponding first emission area EMA1 having a right-angle corner. For example, each of the second grooves TRCH2” may be patterned along the periphery of the corresponding second emission area EMA2 having a right-angle corner. For example, each of the third grooves TRCH3” may be patterned along the periphery of the corresponding third emission area EMA3 having a right-angle corner.

[0185] In this case, a crossing area CA" in which portions of the pixel defining layer PDL" cross each other may be formed. For convenience of explanation, Fig.15 , an intersection area CA" formed in the center portion is shown as a representative example, and reference numerals for other intersection areas are omitted.

[0186] Fig.16 According to the embodiment Fig.15 Magnified view of the intersection area CA”.

[0187] Reference Fig.16 , groove TRCH" (reference Fig.15 ) corners may include internal corners IC” and external corners OC”.

[0188] In embodiments, an outer corner OC" of each of the trenches TRCH" may be chamfered, and an inner corner IC" may be patterned into a right angle shape.

[0189] In an embodiment, the corners and edges EG of the trench TRCH" may have a uniform width w". In this case, the width w" of the edge EG" of each of the trenches TRCH" may be smaller than the maximum width w between the inner corner IC" and the outer corner OC". m Thus, as each of the trenches TRCH" surrounds the corresponding emission region and has a chamfered outer corner OC", a cross region CA" of the pixel defining layer may be formed instead of the cross region CA of the trenches (refer to Figure 8 ). Accordingly, the width (or oblique line width) of each corner of the trench TRCH" in the intersection area CA" does not increase, and each corner of the trench TRCH" may have the same width w" as the width of the edge EG". Therefore, the above-mentioned lateral leakage current can be prevented from flowing, and the cathode electrode CE (refer to Figure 4 ) can not be disconnected, and the encapsulation layer TFE (refer to Figure 4 ) may not have defects such as seams.

[0190] Fig.17 According to the embodiment Fig.15 A magnified view of the intersection area CA". Fig.17 ,and Fig.16 Explanation of overlapping content is simplified or omitted.

[0191] Reference Fig.17 , the width (or diagonal width) of each corner of the trench TRCH" may be smaller than the width w of the edge EG". In this case, the width w" of the edge EG" of each of the trenches TRCH" may be the same as the maximum width w" between the inner corner IC" and the outer corner OC". Fig.16 Compared with the above, the width (or diagonal width) of each corner of the trench TRCH" can be further reduced. Therefore, the above-mentioned lateral leakage current can be more effectively prevented from flowing, and the cathode electrode CE (refer to Figure 4 ) can not be disconnected, and the encapsulation layer TFE (refer to Figure 4 ) may not have defects such as seams.

[0192] Fig.18 is a block diagram showing a display system 1000 according to an embodiment.

[0193] Reference Fig.18 , the display system 1000 may include a processor 1100, and one or more display devices (eg, a first display device 1210 and a second display device 1220).

[0194] The processor 1100 may perform various tasks and operations. In an embodiment, the processor 1100 may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 may be connected to other components of the display system 1000 through a bus system to control the components.

[0195] exist Fig.18 2 shows a case where the display system 1000 includes a first display device 1210 and a second display device 1220. The processor 1100 may be connected to the first display device 1210 through a first channel CH1, and may be connected to the second display device 1220 through a second channel CH2.

[0196] The processor 1100 may transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210 through the first channel CH1. The first display device 1210 may display an image based on the first image data IMG1 and the first control signal CTRL1. Figure 1 In this case, the first image data IMG1 and the first control signal CTRL1 may be provided as Figure 1 Input image data IMG and control signal CTRL.

[0197] The processor 1100 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220 through the second channel CH2. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. Figure 1 In this case, the second image data IMG2 and the second control signal CTRL2 may be provided as Figure 1 Input image data IMG and control signal CTRL.

[0198] The display system 1000 may include a computing system that provides an image display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (tablet PC), a smart watch, a watch phone, a portable multimedia player, a navigation system, and an ultra mobile personal computer (UMPC). In addition, the display system 1000 may include at least one of a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0199] Fig.19 It is shown Fig.18 1000 is a perspective view of an application example of the display system 1000.

[0200] Reference Fig.19 , Fig.18 The display system 1000 may be applied to a head mounted display device 2000. The head mounted display device 2000 may be a wearable electronic device that can be worn on the head of a user.

[0201] The head mounted display device 2000 may include a head mounting band 2100 and a display device housing 2200. The head mounting band 2100 may be connected to the display device housing 2200. The head mounting band 2100 may include a transverse band and / or a longitudinal band to fasten the head mounted display device 2000 to the user's head. The transverse band may surround the sides of the user's head, and the longitudinal band may surround the top of the user's head. However, embodiments are not limited to the above examples. For example, the head mounting band 2100 may be implemented in the form of a glasses frame, a helmet, etc.

[0202] The display device receiving case 2200 can receive Fig.18 The first display device 1210 and the second display device 1220. The display device receiving case 2200 may also receive Fig.18 Processor 1100.

[0203] Fig. 20 It shows the device worn by the user. Fig.19FIG. 2 is a diagram of a head mounted display device 2000 .

[0204] Reference Fig. 20 , the first display panel DP1 of the first display device 1210 and the second display panel DP2 of the second display device 1220 are disposed in the head mounted display device 2000. The head mounted display device 2000 may further include one or more lenses (eg, a left eye lens LLNS and a right eye lens RLNS).

[0205] In the display device receiving container 2200, the right eye lens RLNS may be positioned between the first display panel DP1 and the right eye of the user. In the display device receiving container 2200, the left eye lens LLNS may be positioned between the second display panel DP2 and the left eye of the user.

[0206] The image output from the first display panel DP1 may be viewed by the right eye of the user through the right eye lens RLNS. The right eye lens RLNS may refract light emitted from the first display panel DP1 toward the right eye of the user. The right eye lens RLNS may perform an optical function to adjust the viewing distance between the first display panel DP1 and the right eye of the user.

[0207] The image output from the second display panel DP2 may be viewed by the user's left eye through the left eye lens LLNS. The left eye lens LLNS may refract light emitted from the second display panel DP2 toward the user's left eye. The left eye lens LLNS may perform an optical function to adjust the viewing distance between the second display panel DP2 and the user's left eye.

[0208] In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pancake-shaped cross-section. In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-regions having different optical characteristics. In this case, each display panel may output images corresponding to the sub-regions of the multi-channel lens, respectively. The output images may be viewed by a user through the corresponding sub-regions.

[0209] According to an embodiment, a groove having a chamfered corner may be formed in the pixel defining layer, thereby reducing the size (or length) of the gap formed during the stacking process of the emission structure. Accordingly, the undesired connection of the charge generation layer may be prevented, thereby preventing the lateral leakage current from flowing between the sub-pixels. In addition, the disconnection of the cathode electrode and defects in the encapsulation layer may be prevented. As a result, the reliability of the display device may be enhanced.

[0210] However, the effects of the present disclosure are not limited to the above-described effects, and various modifications may be made without departing from the spirit and scope of the present disclosure.

[0211] Although specific embodiments and application examples have been described, it should be noted that other embodiments and modifications may be derived from the disclosure provided. Accordingly, the concept of the present disclosure is not limited to the foregoing embodiments, but rather to the broader scope of the claims presented and various obvious modifications and equivalent arrangements.

[0212] The embodiments described in detail above are provided to explain the present disclosure, but it should be noted that the embodiments are not intended to limit the scope of the present disclosure. It should be understood by those skilled in the art that various changes, substitutions and modifications may be made herein without departing from the scope of the present disclosure as defined by the appended claims.

[0213] The scope of the present disclosure is not limited by the detailed description of this specification, but should be defined by the appended claims. In addition, all changes or modifications of the present disclosure derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present disclosure.

Claims

1. A display device, comprising: a plurality of pixels, each of the plurality of pixels comprising a plurality of emission regions and a non-emission region adjacent to the plurality of emission regions; as well as a pixel defining layer, the pixel defining layer overlapping the non-emitting area, the pixel defining layer comprising a plurality of grooves surrounding the corresponding emitting area and spaced apart from each other, Wherein, a corner of each of the plurality of grooves is chamfered.

2. The display device according to claim 1, wherein: Inner and outer corners of each of the plurality of grooves are chamfered.

3. The display device according to claim 1, wherein: A width of an edge of each of the plurality of grooves is consistent with a width of the corner of each of the plurality of grooves.

4. The display device according to claim 3, wherein: The width of the edge of each of the plurality of trenches and the width of the corner of each of the plurality of trenches range from 80 nm to 150 nm.

5. The display device according to claim 1, wherein: A thickness of each of the plurality of trenches ranges from 300 nm to 1000 nm.

6. The display device according to claim 1, wherein: The distance between the plurality of grooves ranges from 100 nm to 300 nm.

7. The display device according to claim 1, wherein: A corner of each of the plurality of emission areas is chamfered.

8. The display device according to claim 1, wherein: A corner of each of the plurality of emission areas is a right angle.

9. The display device according to claim 8, wherein: An inner angle of each of the plurality of grooves is a right angle, and an outer angle of each of the grooves is chamfered.

10. The display device according to claim 9, wherein: A width of an edge of each of the plurality of grooves is consistent with a width of the corner of each of the plurality of grooves.

11. The display device according to claim 10, wherein: The width of the edge of each of the plurality of grooves is smaller than a maximum width between the inner corner and the outer corner of each of the plurality of grooves.

12. The display device according to claim 9, wherein: A width of an edge of each of the plurality of grooves is different from a width of the corner of each of the plurality of grooves.

13. The display device according to claim 12, wherein: The width of the edge of each of the plurality of grooves is greater than the width of the corner of each of the plurality of grooves.

14. The display device according to claim 12, wherein: The width of the edge of each of the plurality of grooves coincides with a maximum width between the inner corner and the outer corner of each of the plurality of grooves.

15. The display device according to claim 1, wherein: The plurality of emission regions include a first emission region configured to emit light of a first color, a second emission region configured to emit light of a second color, and a third emission region configured to emit light of a third color.

16. The display device according to claim 15, wherein: The first emission region and the second emission region are arranged in a first direction, and the third emission region is arranged in a second direction relative to the first emission region and the second emission region.

17. The display device according to claim 1, further comprising: an anode electrode, the opening of the pixel defining layer extending to the anode electrode; an emission structure, wherein the emission structure is disposed on the anode electrode and the pixel defining layer; as well as A cathode electrode is disposed on the emitting structure.

18. The display device according to claim 17, wherein: The transmitting structure comprises: a first emission component, the first emission component including a first hole transport component, a first electron transport component, and a first emission layer disposed between the first hole transport component and the first electron transport component; a second emission component including a second hole transport component, a second electron transport component, and a second emission layer disposed between the second hole transport component and the second electron transport component; and A charge generation layer is provided between the first emission component and the second emission component.

19. The display device according to claim 18, wherein: The charge generation layer includes a discontinuous portion overlapping at least a portion of each of the plurality of trenches.

20. The display device according to claim 17, wherein: The cathode electrode is continuously disposed on the emitting structure.

Images