Light-emitting element, display device, method for manufacturing light-emitting element, and method for manufacturing display device

Abstract

The invention provides a light-emitting element, a display device, a method for manufacturing the light-emitting element, and a method for manufacturing the display device. The light emitting element may include: a first portion including a first contact electrode, a first semiconductor layer, an active layer, and a second semiconductor layer in this order; the second part sequentially comprises a second contact electrode, a second semiconductor layer and a third semiconductor layer; and a protective layer disposed on a portion of an upper portion and a side surface of the first portion and a portion of an upper portion and a side surface of the second portion, where the first portion may be disposed on the second portion, and a diameter of the first portion may be smaller than a diameter of the second portion.

Description

Technical Field

[0001] The present invention relates to a light emitting element, a display device and a manufacturing method thereof. Background Art

[0002] With the development of the information society, the demand for display devices for displaying images has increased in various forms. The display device may be a flat panel display device such as a liquid crystal display device (Liquid Crystal Display), a field emission display device (Field Emission Display), a light emitting display device (Light Emitting Display), etc. The light emitting display device may include an organic light emitting display device including an organic light emitting diode element as a light emitting element and an ultra-small light emitting display device including an ultra-small light emitting diode element (micro light emitting diode element, hereinafter referred to as a micro light emitting element) as a light emitting element.

[0003] When manufacturing an ultra-small light-emitting display device, micro light-emitting elements are contacted without a separate electrode between a common electrode and the light-emitting elements, so that a resistance problem may occur. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a vertical light-emitting element including a first contact electrode in contact with a pixel electrode and a second contact electrode in contact with a common electrode, and to provide a display device and a manufacturing method thereof in which the pixel electrode and the common electrode are arranged up and down with the light-emitting element separated, so as to easily cope with high-resolution.

[0005] The technical problems of the present invention are not limited to the technical problems mentioned above, and those skilled in the art can clearly understand other technical problems not mentioned through the following description.

[0006] According to one embodiment, a light-emitting element for solving the above-mentioned technical problems may include: a first part, including a first contact electrode, a first semiconductor layer, an active layer, and a second semiconductor layer in sequence; a second part, including a second contact electrode, a second semiconductor layer, and a third semiconductor layer in sequence; and a protective layer, arranged on a part of the upper part and a side surface of the first part and a part of the upper part and a side surface of the second part, wherein the first part may be arranged on the second part, and the diameter of the first part may be smaller than the diameter of the second part.

[0007] The second semiconductor layer of the second portion may be connected to the second semiconductor layer of the first portion.

[0008] The first portion and the second portion may be in a cylindrical shape, and the second portion may surround the first portion in a plane.

[0009] In a plane, the second contact electrode may surround the first portion.

[0010] The first portion and the second portion may be in a rectangular parallelepiped shape, and one side surface of the first portion and the second portion may be aligned and consistent with each other.

[0011] A display device according to an embodiment for solving the above technical problems may include: a substrate; a common electrode arranged on the substrate; an organic pattern layer arranged on the common electrode; a light-emitting element arranged on the organic pattern layer and having a first contact electrode and a second contact electrode; a pixel electrode arranged on the first contact electrode; and a connecting electrode connecting the second contact electrode and the common electrode, wherein the light-emitting element includes: a first part, including the first contact electrode, a first semiconductor layer, an active layer, and a second semiconductor layer in sequence; a second part, including the second contact electrode, a second semiconductor layer, and a third semiconductor layer in sequence; and a protective layer, arranged on a portion of the upper part and the side surface of the first part and a portion of the upper part and the side surface of the second part, wherein the first part may be arranged on the second part, and the diameter of the first part may be smaller than the diameter of the second part.

[0012] The display device may further include: an organic layer covering an upper surface of the connection electrode and a side surface of the light emitting element.

[0013] The connection electrode may have a higher reflectivity than the pixel electrode.

[0014] The common electrode and the connection electrode may include a metal substance, and the pixel electrode may include a transparent conductive oxide.

[0015] The common electrode may be a common layer formed in common in a plurality of sub-pixels.

[0016] The second semiconductor layer of the second portion may be connected to the second semiconductor layer of the first portion.

[0017] The first portion and the second portion may be in a cylindrical shape, and the second portion may surround the first portion in a plane.

[0018] On the plane, the second contact electrode may surround the first portion.

[0019] The display device may further include: a first organic layer covering the second contact electrode; a second organic layer arranged on the first organic layer; and a functional layer arranged between the first organic layer and the second organic layer, wherein the functional layer may include one or more of a protective layer including an inorganic film and a reflective layer including a reflective material with high reflectivity.

[0020] The first portion and the second portion may be in a rectangular parallelepiped shape, and one side surface of the first portion and the second portion may be aligned and consistent with each other.

[0021] A method for manufacturing a light-emitting element according to an embodiment for solving the above-mentioned technical problem may include the following steps: forming a plurality of semiconductor material layers on a base substrate; etching the plurality of semiconductor material layers to form a light-emitting element including a third semiconductor layer, a second semiconductor layer, an active layer and a first semiconductor layer; etching the first semiconductor layer, the active layer and a portion of the second semiconductor layer to form a first part and a second part; forming a protective layer arranged on a portion of the upper part and the side surface of the first part and a portion of the upper part and the side surface of the second part; and forming a first contact electrode on the upper part of the first part and a second contact electrode on the upper part of the second part, wherein the first part may be arranged on the second part and the diameter of the first part may be smaller than the diameter of the second part.

[0022] In the step of forming the first portion and the second portion, the peripheries of the first semiconductor layer, the active layer, and the second semiconductor layer may be etched so that the first portion is arranged in a plane at the center of the second portion to expose the second semiconductor layer on the upper surface of the second portion.

[0023] In the steps of forming the first contact electrode on the upper part of the first part and forming the second contact electrode on the upper part of the second part, the first contact electrode can be formed to contact the first semiconductor layer of the first part, and the second contact electrode can be formed to contact the second semiconductor layer of the second part.

[0024] A manufacturing method of a display device according to an embodiment for solving the above-mentioned technical problem may include the following steps: forming a thin film transistor layer and a common electrode on a substrate; forming a dummy adhesion layer on the common electrode and aligning a light-emitting element; fixing the light-emitting element on the dummy adhesion layer, and removing a portion of the dummy adhesion layer to form an organic pattern layer; forming a connecting electrode connecting the common electrode and a second contact electrode of the light-emitting element; forming an organic layer covering the connecting electrode and a portion of the light-emitting element; and forming a pixel electrode on the first contact electrode of the light-emitting element, wherein the light-emitting element includes: a first part, which includes the first contact electrode, a first semiconductor layer, an active layer, and a second semiconductor layer in sequence; and a second part, which includes the second contact electrode, a second semiconductor layer, and a third semiconductor layer in sequence, wherein the first part may be arranged on the second part, and a diameter of the first part may be smaller than a diameter of the second part.

[0025] In the manufacturing method of the display device, the step of fixing the light-emitting element to the dummy adhesive layer may include the following steps: curing the dummy adhesive layer at a first temperature; inserting a portion of each of the light-emitting elements into the dummy adhesive layer; and curing the dummy adhesive layer at a second temperature higher than the first temperature.

[0026] The manufacturing method of the display device may also include the following steps: forming a shading layer arranged on a covering layer arranged on the pixel electrode and the organic layer and defining a light-emitting area; in the area divided by the shading layer, forming a first light conversion layer in an area corresponding to the first sub-pixel, forming a second light conversion layer in an area corresponding to the second sub-pixel, and forming a light transmission layer in an area corresponding to the third sub-pixel; and forming a first color filter on the first light conversion layer, forming a second color filter on the second light conversion layer, and forming a third color filter on the light transmission layer.

[0027] Details of other embodiments are included in the detailed description and drawings.

[0028] According to the light emitting element, the display device and the manufacturing method thereof of the embodiment, the contact resistance between the pixel electrode and the common electrode and the light emitting element can be reduced.

[0029] The effects according to the embodiments are not limited to the above-exemplified contents, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a perspective view showing a display device according to an embodiment.

[0031] Figure 2 is a layout diagram showing a display device according to an embodiment.

[0032] Figure 3 is a block diagram showing a display device according to an embodiment.

[0033] Figure 4 is an equivalent circuit diagram showing a sub-pixel according to an embodiment.

[0034] Figure 5 is an equivalent circuit diagram showing a sub-pixel according to still another embodiment.

[0035] Figure 6 is a perspective view showing the structure of a light emitting element according to an embodiment.

[0036] Figure 7 is a cross-sectional view showing the structure of a light emitting element according to an embodiment.

[0037] Figure 8 is a diagram showing a layout of pixels of a display area according to an embodiment.

[0038] Fig. 9 is shown corresponding to Figure 8 FIG. 1 is a cross-sectional view of an example of a cross-section of a display panel taken along line I1 - I1 ′.

[0039] Fig.10 It is shown in detail Fig. 9 A cross-sectional view of an example of region A.

[0040] Fig.11 is shown corresponding to Figure 8 FIG. 1 is a cross-sectional view showing another example of a cross-section of a display panel taken along line I1 - I1 ′.

[0041] Fig.12 It is shown in detail Fig.11 A cross-sectional view of an example of region B.

[0042] Fig.13 is a perspective view showing the structure of a light emitting element according to another embodiment.

[0043] Fig.14 is a cross-sectional view showing the structure of a light emitting element according to an embodiment.

[0044] Fig.15 is a diagram showing a layout of pixels of a display area according to an embodiment.

[0045] Fig.16 is shown corresponding to Fig.15 FIG. 1 is a cross-sectional view of an example of a cross-section of a display panel taken along line I2 - I2 ′.

[0046] Fig.17 It is shown in detail Fig.16 A cross-sectional view of an example of the C region.

[0047] Fig.18 is a flowchart showing a method for manufacturing a light emitting element according to an embodiment.

[0048] Figures 19 to 24 is a cross-sectional view for explaining a method for manufacturing a light emitting element according to an embodiment.

[0049] Fig.25 is a flowchart illustrating a method for manufacturing a display device according to an embodiment.

[0050] Figure 26 to Figure 36 is a cross-sectional view for explaining a method for manufacturing a display device according to an embodiment.

[0051] Fig.37 FIG. 4 is an exemplary diagram showing a virtual reality device including a display device according to an embodiment.

[0052] Fig.38 is an exemplary diagram showing a smart watch including a display device according to an embodiment.

[0053] Fig.39 is an exemplary diagram showing a vehicle instrument panel and a center instrument panel including a display device according to an embodiment.

[0054] Fig.40 is an exemplary diagram showing a transparent display device including a display device according to an embodiment.

[0055] Description of Reference Numerals

[0056] 10: Display device 100: Display panel

[0057] SUB: Substrate PXE1: First pixel electrode

[0058] PXE2: second pixel electrode PXE3: third pixel electrode

[0059] BOL: organic pattern layer CTE: contact electrode

[0060] LE: light emitting element BE: connecting electrode

[0061] SEM1: first semiconductor layer SEM2: second semiconductor layer

[0062] SEM3: Third semiconductor layer MQW: Active layer

[0063] CE: common electrode 190: third organic layer

[0064] BM1: first light shielding layer BM2: second light shielding layer

[0065] QDL1: first light conversion layer QDL2: second light conversion layer

[0066] TFL: Light transmission layer CF1: First color filter

[0067] CF2: Second color filter CF3: Third color filter

[0068] CTE1: first contact electrode CTE2: second contact electrode

[0069] LEP1: Part 1 LEP2: Part 2 DETAILED DESCRIPTION

[0070] The advantages and features of the present invention and the methods for achieving the same may be clearly understood by referring to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present invention may be implemented in various forms different from each other, and is not limited to the embodiments disclosed below, and the purpose of providing the present embodiments is only to complete the disclosure of the present invention and to fully inform the scope of the invention to those with ordinary knowledge in the technical field to which the present invention belongs. The present invention is defined only by the scope of the claims.

[0071] When an element or layer is referred to as being "on" another element or layer, this includes all situations where the element or layer is immediately above or sandwiched between other layers or other elements. Throughout the specification, the same reference numerals refer to the same constituent elements. Since the shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings used to illustrate the embodiments are exemplary, the present invention is not limited to the matters illustrated.

[0072] The various features of the various embodiments of the present invention may be partially or completely combined or combined with each other, and various linkages and drives may be performed technically. The various embodiments may be implemented independently of each other, or may be implemented together in a related relationship.

[0073] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0074] Figure 1 is a perspective view showing a display device according to an embodiment.

[0075] Reference Figure 1The display device 10 is a device for displaying moving images or still images, and can be used not only as a display screen for portable electronic devices such as mobile phones, smart phones, tablet personal computers, smart watches, watch phones, mobile communication terminals, electronic notepads, electronic books, portable multimedia players (PMP: portable multimedia player), navigators, ultra mobile PCs (UMPC: UltraMobile PC), etc., but also as a display screen for a variety of products such as televisions, notebook computers, monitors, billboards, Internet of Things (IOT: internet of things) devices, etc.

[0076] The display device 10 may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and an ultra-small light-emitting display device using an ultra-small light-emitting diode (micro light-emitting diode (micro LED) or nano-type light-emitting diode (nano LED)). The following description is centered on the case where the display device 10 is an ultra-small light-emitting display device, but the present invention is not limited to this. In addition, for the sake of convenience, the ultra-small light-emitting diode is described as a light-emitting element.

[0077] The display device 10 includes a display panel 100 , a display driving circuit 250 , a circuit board 300 and a power supply circuit 500 .

[0078] The display panel 100 may be formed as a plane having a rectangular shape having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. The corners where the short sides in the first direction DR1 meet the long sides in the second direction DR2 may be formed in an arc shape with a predetermined curvature or at a right angle. The plane shape of the display panel 100 is not limited to a quadrilateral, and may be formed as other polygons, a circle, or an ellipse. The display panel 100 may be formed flat, but is not limited thereto. For example, the display panel 100 may include a curved portion formed at the left and right ends and having a constant curvature or a varying curvature. In addition, the display panel 100 may be formed flexibly so that the display panel 100 may be bent, curved, folded, folded, or curled.

[0079] The substrate SUB of the display panel 100 (see Fig. 9 ) may include a main area MA and a sub-area SBA.

[0080] The main area MA may include a display area DA that displays an image and a non-display area NDA that is a surrounding area of ​​the display area DA. The display area DA may include a plurality of pixels that display an image. For example, a pixel may include a first sub-pixel that emits a first light, a second sub-pixel that emits a second light, and a third sub-pixel that emits a third light.

[0081] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. Figure 1 The case where the sub-region SBA is expanded is exemplarily shown, but the sub-region SBA may be curved, in which case the sub-region SBA may be arranged on the lower surface of the display panel 100. When the sub-region SBA is curved, the sub-region SBA may overlap the main region MA in the third direction DR3 which is the thickness direction of the display panel 100. A display driving circuit 250 may be arranged in the sub-region SBA.

[0082] The display driving circuit 250 may generate signals and voltages for driving the display panel 100. The display driving circuit 250 may be formed as an integrated circuit (IC) and attached to the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit 250 may be attached to the circuit board 300 by a chip on film (COF) method.

[0083] The circuit board 300 may be attached to one end of the sub-area SBA of the display panel 100. Therefore, the circuit board 300 may be electrically connected to the display panel 100 and the display driving circuit 250. The display panel 100 and the display driving circuit 250 may receive digital video data, timing signals, and driving voltages through the circuit board 300. The circuit board 300 may be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip on film.

[0084] The power supply circuit 500 may generate a plurality of panel driving voltages according to a power supply voltage from the outside. The power supply circuit 500 may be formed as an integrated circuit (IC) and attached to the circuit board 300 by a COF method.

[0085] Figure 2 is a layout diagram showing a display device according to an embodiment. Figure 2The case where the sub-area SBA is expanded but not bent is exemplarily shown.

[0086] Reference Figure 2 , the display panel 100 may include a main area MA and a sub-area SBA.

[0087] The main area MA may include a display area DA displaying an image and a non-display area NDA as a surrounding area of ​​the display area DA. The display area DA may occupy most of the main area MA. The display area DA may be arranged at the center of the main area MA.

[0088] The display area DA includes a plurality of pixels PX for displaying an image, and each of the plurality of pixels PX may include a plurality of sub-pixels SPX. The pixel PX may be defined as a sub-pixel group that is a minimum unit capable of expressing a white grayscale.

[0089] The non-display area NDA may be arranged adjacent to the display area DA. The non-display area NDA may be an outer area of ​​the display area DA. The non-display area NDA may be arranged to surround the display area DA. The non-display area NDA may be an edge area of ​​the display panel 100.

[0090] The first scan driver SDC1 and the second scan driver SDC2 may be arranged in the non-display area NDA. The first scan driver SDC1 may be arranged on one side (e.g., the left side) of the display panel 100, and the second scan driver SDC2 may be arranged on the other side (e.g., the right side) of the display panel 100, but is not limited thereto. Each of the first scan driver SDC1 and the second scan driver SDC2 may be electrically connected to the display driver circuit 250 through a scan fan-out wiring. Each of the first scan driver SDC1 and the second scan driver SDC2 may receive a scan control signal from the display driver circuit 250, generate a scan signal according to the scan control signal, and output the scan signal to the scan wiring.

[0091] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. The length of the sub-region SBA in the second direction DR2 may be less than the length of the main region MA in the second direction DR2. The length of the sub-region SBA in the first direction DR1 may be less than the length of the main region MA in the first direction DR1, or the length of the sub-region SBA in the first direction DR1 may be substantially the same as the length of the main region MA in the first direction DR1. The sub-region SBA may be curved and may be arranged at a lower portion of the display panel 100. In this case, the sub-region SBA may overlap with the main region MA in the third direction DR3.

[0092] The sub-area SBA may include a connection area CA, a pad area PA, and a bending area BA.

[0093] The connection area CA is a region protruding from one side of the main area MA in the second direction DR2 . One side of the connection area CA may be connected to the non-display area NDA of the main area MA, and the other side of the connection area CA may be connected to the bending area BA.

[0094] The pad area PA is an area where the pad PD and the display driving circuit 250 are arranged. The display driving circuit 250 may be attached to the driving pad of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be attached to the pad PD in the pad area PA using a conductive adhesive member such as an anisotropic conductive film. One side of the pad area PA may be connected to the bending area BA.

[0095] The bending area BA is a curved area. When the bending area BA is curved, the pad area PA may be arranged at a lower portion of the connection area CA and a lower portion of the main area MA. The bending area BA may be arranged between the connection area CA and the pad area PA. One side of the bending area BA may be connected to the connection area CA, and the other side of the bending area BA may be connected to the pad area PA.

[0096] Figure 3 is a block diagram showing a display device according to an embodiment.

[0097] Reference Figure 3 , the display area DA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of light emitting control lines EL and a plurality of data lines DL.

[0098] The plurality of pixels PX may be arranged in a matrix in a first direction DR1 and a second direction DR2. The plurality of scan lines SL and the plurality of light emitting control lines EL may extend along the first direction DR1 and may be arranged along the second direction DR2. The plurality of data lines DL may extend along the second direction DR2 and may be arranged along the first direction DR1. The plurality of scan lines SL include a plurality of write scan lines GWL, a plurality of control scan lines GCL, a plurality of initialization scan lines GIL, and a plurality of bias scan lines GBL.

[0099] Each of the plurality of sub-pixels SPX may be connected to one of the plurality of write scan lines GWL, one of the plurality of control scan lines GCL, one of the plurality of initialization scan lines GIL, one of the plurality of bias scan lines GBL, one of the plurality of light emission control lines EL, and one of the plurality of data lines DL. Each of the plurality of sub-pixels SPX may receive a data voltage of the data line DL according to a write scan signal of the write scan line GWL, and may cause the light emitting element to emit light according to the data voltage.

[0100] The non-display area NDA includes a first scan driving part SDC1 , a second scan driving part SDC2 , and a display driving circuit 250 .

[0101] Each of the first scan driving part SDC1 and the second scan driving part SDC2 includes a write scan signal output part 611, a control scan signal output part 612, an initialization scan signal output part 613, a bias scan signal output part 614, and a light emitting signal output part 615. Each of the write scan signal output part 611, the control scan signal output part 612, the initialization scan signal output part 613, the bias scan signal output part 614, and the light emitting signal output part 615 can receive a scan timing control signal SCS from the timing control circuit 251. The write scan signal output part 611 can generate a write scan signal according to the scan timing control signal SCS of the timing control circuit 251 and output it to the write scan line GWL in sequence. The control scan signal output part 612 can generate a control scan signal according to the scan timing control signal SCS and output it to the control scan line GCL in sequence. The initialization scan signal output part 613 can generate an initialization scan signal according to the scan timing control signal SCS and output it to the initialization scan line GIL in sequence. The bias scan signal output unit 614 may generate a bias scan signal according to the scan timing control signal SCS and sequentially output it to the bias scan line GBL. The light emission signal output unit 615 may generate a light emission control signal according to the scan timing control signal SCS and sequentially output it to the light emission control line EL.

[0102] The display driving circuit 250 includes a timing control circuit 251 and a data driving circuit 252 .

[0103] The data driving circuit 252 may receive the digital video data DATA and the data timing control signal DCS from the timing control circuit 251. The data driving circuit 252 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs it to the data line DL. In this case, the sub-pixel SPX may be selected by the write scan signal of the first scan driving part SDC1 and the second scan driving part SDC2, and the data voltage may be supplied to the selected sub-pixel SPX.

[0104] The timing control circuit 251 may receive digital video data DATA and a timing signal from the outside. The timing control circuit 251 may generate a scan timing control signal SCS and a data timing control signal DCS for controlling the display panel 100 according to the timing signal. The timing control circuit 251 may output the scan timing control signal SCS to the first scan driving part SDC1 and the second scan driving part SDC2. The timing control circuit 251 may output the digital video data DATA and the data timing control signal DCS to the data driving circuit 252.

[0105] The power supply circuit 500 may generate a plurality of panel driving voltages according to a power supply voltage from the outside. For example, the power supply circuit 500 may generate a first driving voltage VDD, a second driving voltage VSS, and a third driving voltage VINT and supply them to the display panel 100.

[0106] Figure 4 is an equivalent circuit diagram showing a sub-pixel according to an embodiment.

[0107] Reference Figure 4 According to an embodiment, the sub-pixel SPX may be connected to the scan lines GWL, GIL, GCL, GBL, the emission control line EL, and the data line DL. For example, the sub-pixel SPX may be connected to the write scan line GWL, the initialization scan line GIL, the control scan line GCL, the bias scan line GBL, the emission control line EL, and the data line DL.

[0108] The subpixel SPX according to an embodiment includes a driving transistor DT, a switching element, a capacitor C1 and a light emitting element LE. The switching element includes a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5 and a sixth transistor ST6.

[0109] The driving transistor DT includes a gate electrode, a first electrode, and a second electrode, and controls a drain-source current (hereinafter referred to as a “driving current”) flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode.

[0110] The light emitting element LE may be a micro light emitting diode.

[0111] The light emitting element LE emits light according to the driving current. The light emission amount of the light emitting element LE may be proportional to the driving current. The anode electrode of the light emitting element LE may be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode electrode may be connected to the second power line VSL to which the second power voltage is applied.

[0112] The capacitor C1 is formed between the gate electrode of the driving transistor DT and the first power line VDL to which the first power voltage is applied. The first power voltage may be a voltage having a level higher than that of the second power voltage. One electrode of the capacitor C1 may be connected to the gate electrode of the driving transistor DT, and the other electrode may be connected to the first power line VDL.

[0113] like Figure 4 As shown, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6 and the driving transistor DT can all be formed using p-type MOSFETs. In this case, the active layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6 and the driving transistor DT can be formed using polysilicon.

[0114] The gate electrode of the second transistor ST2 can be connected to the write scan line GWL, and the gate electrode of the first transistor ST1 can be connected to the control scan line GCL. The gate electrode of the third transistor ST3 can be connected to the initialization scan line GIL, and the gate electrode of the fourth transistor ST4 can be connected to the bias scan line GBL. Since the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5 and the sixth transistor ST6 are all formed using p-type MOSFETs, when a scan signal of a gate low voltage and a light emitting signal are applied to the control scan line GCL, the initialization scan line GIL, the write scan line GWL, the bias scan line GBL and the light emitting control line EL, respectively, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5 and the sixth transistor ST6 can be turned on. One electrode of the third transistor ST3 and one electrode of the fourth transistor ST4 can be connected to the initialization voltage line VIL.

[0115] Figure 5 is an equivalent circuit diagram showing a sub-pixel according to still another embodiment.

[0116] Reference Figure 5, the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5 and the sixth transistor ST6 may be formed using a p-type MOSFET, and the first transistor ST1 and the third transistor ST3 may be formed using an n-type MOSFET. The active layer of each of the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5 and the sixth transistor ST6 formed using a p-type MOSFET may be formed using polysilicon, and the active layer of each of the first transistor ST1 and the third transistor ST3 formed using an n-type MOSFET may be formed using an oxide semiconductor. In this case, the transistor formed using polysilicon and the transistor formed using an oxide semiconductor may be arranged in layers different from each other.

[0117] Since the first transistor ST1 and the third transistor ST3 are formed using n-type MOSFETs, the first transistor ST1 can be turned on when a control scan signal with a gate high voltage is applied to the control scan line GCL, and the third transistor ST3 can be turned on when an initialization scan signal with a gate high voltage is applied to the initialization scan line GIL. In contrast, since the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed using p-type MOSFETs, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 can be turned on when a scan signal with a gate low voltage and a light emitting signal are applied to the write scan line GWL, the bias scan line GBL, and the light emitting control line EL, respectively.

[0118] Or, in Figure 4 In the embodiment, the fourth transistor ST4 can be formed using an n-type MOSFET. In this case, the active layer of each fourth transistor ST4 can be formed using an oxide semiconductor. When the fourth transistor ST4 is formed using an n-type MOSFET, when the bias scan line GBL is applied with a bias scan signal of a gate high voltage, the fourth transistor ST4 can be turned on.

[0119] Or, despite Figure 4 and Figure 5 Although not shown in the figure, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6 and the driving transistor DT can all be formed using n-type MOSFETs. In this case, the active layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6 and the driving transistor DT can be formed using an oxide semiconductor.

[0120] Figure 6is a perspective view showing the structure of a light emitting element according to an embodiment, Figure 7 is a cross-sectional view showing the structure of a light emitting element according to an embodiment.

[0121] Reference Figure 6 and Figure 7 , the light emitting element LE may be a vertical type micro LED extending along the third direction DR3. The vertical type micro LED refers to an LED having a structure in which the third semiconductor layer SEM3, the second semiconductor layer SEM2, the active layer MQW and the first semiconductor layer SEM1 are sequentially arranged in the third direction DR3 as a vertical direction.

[0122] Each of the plurality of light emitting elements LE may be formed using an inorganic material such as gallium nitride (GaN). The length of each of the plurality of light emitting elements LE in the first direction DR1, the length in the second direction DR2, and the length in the third direction DR3 may be several μm to several hundred μm, respectively. For example, the length of each of the plurality of light emitting elements LE in the first direction DR1, the length in the second direction DR2, and the length in the third direction DR3 may be approximately 100 μm or less, respectively.

[0123] Each of the plurality of light emitting elements LE may be formed by being grown on a semiconductor substrate such as a silicon substrate or a sapphire substrate.

[0124] The light emitting element LE may include a third semiconductor layer SEM3, a second semiconductor layer SEM2, an active layer MQW, a first semiconductor layer SEM1, a first contact electrode CTE1, a second contact electrode CTE2, and a protective layer INS0.

[0125] The third semiconductor layer SEM3 may include an undoped semiconductor and may be a substance not doped to an n-type or p-type. In an exemplary embodiment, the third semiconductor layer SEM3 may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto.

[0126] The second semiconductor layer SEM2 may be doped with a second conductive type dopant such as Si, Ge, Se, Sn, etc. For example, the second semiconductor layer SEM2 may be n-GaN doped with n-type Si.

[0127] The active layer MQW may be disposed on the second semiconductor layer SEM2 and may emit light by recombination of electron-hole pairs according to an electrical signal applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2.

[0128] The active layer MQW may include a material of a single quantum well structure or a multi-quantum well structure. In the case where the active layer MQW includes a material of a multi-quantum well structure, it may also be a structure in which multiple well layers (well layers) and barrier layers (barrier layers) are alternately stacked with each other. In this case, the well layer may be formed using InGaN, and the barrier layer may be formed using GaN or AlGaN, but is not limited thereto. Alternatively, the active layer MQW may have a structure in which semiconductor materials of a type with a high energy band gap and semiconductor materials of a type with a low energy band gap are alternately stacked with each other, or may include different III-group semiconductor materials to V-group semiconductor materials according to the wavelength band of the emitted light.

[0129] In the case where the active layer MQW includes InGaN, the color of the emitted light may be different depending on the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer MQW may move toward the red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer MQW may move toward the blue wavelength band. For example, the content of indium (In) of the active layer MQW of the light emitting element LE that emits the third light (light in the blue wavelength band) may be about 10 wt% to 20 wt%.

[0130] The first semiconductor layer SEM1 may be disposed on the active layer MQW. The first semiconductor layer SEM1 may be formed of GaN doped with a first conductive type dopant such as Mg, Zn, Ca, Ba, or the like.

[0131] The electron blocking layer may be arranged between the first semiconductor layer SEM1 and the active layer MQW. The electron blocking layer may be a layer for suppressing or preventing excessive electrons from flowing into the active layer MQW. For example, the electron blocking layer may be AlGaN or p-AlGaN doped with p-type Mg. The electron blocking layer may be omitted.

[0132] The superlattice layer may be disposed between the active layer MQW and the second semiconductor layer SEM2. The superlattice layer may be a layer for relieving stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer may be formed using InGaN or GaN. The superlattice layer may be omitted.

[0133] The light emitting element LE includes a first portion LEP1 and a second portion LEP2. The first portion LEP1 may be arranged on the second portion LEP2. The first portion LEP1 and the second portion LEP2 may be cylindrical in shape. On a plane, the second portion LEP2 may be arranged to surround the first portion LEP1.

[0134] The first portion LEP1 includes a first contact electrode CTE1, a first semiconductor layer SEM1, an active layer MQW, a second semiconductor layer SEM2, and a protective layer INS0. The second portion LEP2 includes a second contact electrode CTE2, a second semiconductor layer SEM2, a third semiconductor layer SEM3, and a protective layer INS0. The second semiconductor layer SEM2 of the first portion LEP1 may be connected to the second semiconductor layer SEM2 of the second portion LEP2. The diameter of the first portion LEP1 may be narrower than the diameter of the second portion LEP2. The second portion LEP2 that does not overlap with the first portion LEP1 may be exposed to the outside.

[0135] The first contact electrode CTE1 may be disposed on the first semiconductor layer SEM1 of the first portion LEP1. The first contact electrode CTE1 may be disposed on an upper surface of the first semiconductor layer SEM1.

[0136] The second contact electrode CTE2 may be disposed on an upper surface of the second semiconductor layer SEM2 of the second portion LEP2 not overlapping the first portion LEP1. In a plane, the second contact electrode CTE2 may be disposed around the first portion LEP1.

[0137] The first contact electrode CTE1 and the second contact electrode CTE2 may include one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0138] The protective layer INS0 may be disposed on the upper surface of the first portion LEP1 and the second portion LEP2 where the first contact electrode CTE1 and the second contact electrode CTE2 are not disposed and the side surfaces of the first portion LEP1 and the second portion LEP2. The protective layer INS0 may be a film for protecting the side surface of the light emitting element LE. The protective layer INS0 may be formed using an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

[0139] Figure 8 is a diagram showing a layout of pixels of a display area according to an embodiment.

[0140] Reference Figure 8 , each of the plurality of pixels PX of the display area DA may include a first sub-pixel SPX1 , a second sub-pixel SPX2 , and a third sub-pixel SPX3 .

[0141] The plurality of pixels PX may be arranged in a matrix form. In each of the plurality of pixels PX, a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3 may be arranged along a first direction DR1.

[0142] The first sub-pixel SPX1 may emit the first light, the second sub-pixel SPX2 may emit the second light, and the third sub-pixel SPX3 may emit the third light. Here, the first light may be light of a blue wavelength band, the second light may be light of a green wavelength band, and the third light may be light of a red wavelength band. For example, the blue wavelength band refers to a wavelength band in which the main peak wavelength of light is included in a wavelength band of about 370nm to 460nm, the green wavelength band refers to a wavelength band in which the main peak wavelength of light is included in a wavelength band of about 480nm to 560nm, and the red wavelength band may refer to a wavelength band in which the main peak wavelength of light is included in a wavelength band of about 600nm to 750nm.

[0143] The first sub-pixel SPX1 includes a common electrode CE, a plurality of light emitting elements LE, a first pixel electrode PXE1, and a first light conversion layer QDL1. The second sub-pixel SPX2 includes a common electrode CE, a plurality of light emitting elements LE, a second pixel electrode PXE2, and a second light conversion layer QDL2. The third sub-pixel SPX3 includes a common electrode CE, a plurality of light emitting elements LE, a third pixel electrode PXE3, and a light transmission layer TPL.

[0144] The common electrode CE may be a common layer commonly formed in the first sub-pixel SPX1 , the second sub-pixel SPX2 , and the third sub-pixel SPX3 arranged along the same first direction DR1 .

[0145] For the plurality of light emitting elements LE, the same number of light emitting elements LE may be arranged in each sub-pixel. For example, two light emitting elements LE may be arranged in the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The plurality of light emitting elements LE may emit the third light (i.e., light in the blue wavelength band). The plurality of light emitting elements LE may be circular in a plane, but are not limited thereto.

[0146] Pixel electrodes PXE1, PXE2, and PXE3 may be disposed on the light emitting elements LE included in the respective subpixels. The areas of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may be set according to the light conversion efficiency of the first light conversion layer QDL1 and the second light conversion layer QDL2.

[0147] The first pixel electrode PXE1 can be connected to the fourth transistor ST4 ( Figure 4 and Figure 5 ) and the second electrode of the sixth transistor ST6 ( Figure 4 and Figure 5 ) is electrically connected to the second electrode of the second pixel electrode PXE2. The second pixel electrode PXE2 can be electrically connected to the fourth transistor ST4 ( Figure 4 and Figure 5) and the second electrode of the sixth transistor ST6 ( Figure 4 and Figure 5 ) is electrically connected to the second electrode of the third pixel electrode PXE3. The third pixel electrode PXE3 can be electrically connected to the fourth transistor ST4 ( Figure 4 and Figure 5 ) and the second electrode of the sixth transistor ST6 ( Figure 4 and Figure 5 ) is electrically connected to the second electrode.

[0148] The first light conversion layer QDL1 may completely overlap the first pixel electrode PXE1 and the plurality of light emitting elements LE of the first sub-pixel SPX1. The area of ​​the first light conversion layer QDL1 may be greater than the area of ​​the first pixel electrode PXE1. The first light conversion layer QDL1 may convert or shift the peak wavelength of the incident light into light having another specific peak wavelength and emit it. For example, the first light conversion layer QDL1 may convert or shift the third light emitted from the plurality of light emitting elements LE of the first sub-pixel SPX1 into the first light.

[0149] The second light conversion layer QDL2 may completely overlap with the second pixel electrode PXE2 and the plurality of light emitting elements LE of the second sub-pixel SPX2. The area of ​​the second light conversion layer QDL2 may be greater than the area of ​​the second pixel electrode PXE2. The second light conversion layer QDL2 may convert or shift the peak wavelength of the incident light into light having another specific peak wavelength and emit it. For example, the second light conversion layer QDL2 may convert or shift the third light emitted from the plurality of light emitting elements LE of the second sub-pixel SPX2 into the second light.

[0150] The light transmission layer TPL may completely overlap the third pixel electrode PXE3 and the plurality of light emitting elements LE of the third sub-pixel SPX3. The light transmission layer TPL may directly transmit the incident light. For example, the light transmission layer TPL may directly transmit the third light emitted from the plurality of light emitting elements LE of the third sub-pixel SPX3.

[0151] Fig. 9 is shown corresponding to Figure 8 FIG. 1 is a cross-sectional view of an example of a cross-section of a display panel taken along line I1 - I1 ′. Fig.10 It is shown in detail Fig. 9 A cross-sectional view of an example of region A.

[0152] Reference Fig. 9 and Fig.10The substrate SUB can be made of insulating materials such as glass and polymer resin. When the substrate SUB is made of polymer resin, it can be a stretchable flexible substrate. The polymer resin can be acryl resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0153] A barrier film BR may be disposed on the substrate SUB. The barrier film BR is a film for protecting the transistors of the thin film transistor layer TFTL and the light-emitting layer of the light-emitting element layer EML from the influence of moisture penetrating through the moisture-permeable substrate SUB. The barrier film BR may be formed by a plurality of inorganic films stacked alternately. For example, the barrier film BR may be formed by a plurality of films in which one or more inorganic films selected from silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked.

[0154] A first thin film transistor TFT1 may be disposed on the barrier film BR. The first thin film transistor TFT1 may be Figure 5 One of the fourth transistor ST4 and the sixth transistor ST6 is shown. The first thin film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1.

[0155] A first active layer ACT1 of the first thin film transistor TFT1 may be disposed on the barrier film BR. The first active layer ACT1 of the first thin film transistor TFT1 may include polycrystalline silicon, single crystalline silicon, low temperature polycrystalline silicon, or amorphous silicon.

[0156] The first active layer ACT1 may include a first channel region CHA1, a first source region S1, and a first drain region D1. The first channel region CHA1 may be a region overlapping with the first gate electrode G1 in a third direction DR3 that is a thickness direction of the substrate SUB. The first source region S1 may be arranged on one side of the first channel region CHA1, and the first drain region D1 may be arranged on the other side of the first channel region CHA1. The first source region S1 and the first drain region D1 may be regions that do not overlap with the first gate electrode G1 in the third direction DR3. The first source region S1 and the first drain region D1 may be regions that are doped with ions in a silicon semiconductor and have conductivity.

[0157] A first gate insulating film 131 may be disposed on the first channel region CHA1, the first source region S1, and the first drain region D1 of the first thin film transistor TFT1. The first gate insulating film 131 may be formed using an inorganic film (eg, silicon nitride layer, silicon oxynitride layer, silicon oxide layer, titanium oxide layer, or aluminum oxide layer).

[0158] A first gate metal layer GTL1 may be disposed on the first gate insulating film 131. The first gate metal layer GTL1 may include a first gate electrode G1 of the first thin film transistor TFT1 and a first capacitor electrode CAE1. The first gate electrode G1 may overlap the first active layer ACT1 in the third direction DR3. Fig. 9 , the first gate electrode G1 and the first capacitor electrode CAE1 are arranged apart from each other, but the first gate electrode G1 and the first capacitor electrode CAE1 may be connected to each other. The first gate metal layer GTL1 may be formed as a single layer or multiple layers using one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0159] A second gate insulating film 132 may be disposed on the first gate electrode G1 of the first thin film transistor TFT1 and the first capacitor electrode CAE1. The second gate insulating film 132 may be formed using an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0160] A second gate metal layer GTL2 may be disposed on the second gate insulating film 132. The second gate metal layer GTL2 may include a second capacitor electrode CAE2. The second capacitor electrode CAE2 may overlap with the first capacitor electrode CAE1 of the first gate metal layer GTL1 in the third direction DR3. Since the second gate insulating film 132 has a predetermined dielectric constant, a capacitor C1 ( Figure 5 The second gate metal layer GTL2 may be formed as a single layer or multiple layers using one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof.

[0161] A first interlayer insulating film 141 may be disposed on the second capacitor electrode CAE2. The first interlayer insulating film 141 may be formed using an inorganic film (eg, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

[0162] A second thin film transistor TFT2 may be disposed on the first interlayer insulating film 141. The second thin film transistor TFT2 may be Figure 5 The second thin film transistor TFT2 may include a second active layer ACT2 and a second gate electrode G2.

[0163] A second active layer ACT2 of a second thin film transistor TFT2 may be disposed on the first interlayer insulating film 141. The second active layer ACT2 may include an oxide semiconductor. For example, the second active layer ACT2 may include IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0164] The second active layer ACT2 may include a second channel region CHA2, a second source region S2, and a second drain region D2. The second channel region CHA2 may be a region overlapping with the second gate electrode G2 in the third direction DR3. The second source region S2 may be arranged on one side of the second channel region CHA2, and the second drain region D2 may be arranged on the other side of the second channel region CHA2. The second source region S2 and the second drain region D2 may be regions that do not overlap with the second gate electrode G2 in the third direction DR3. The second source region S2 and the second drain region D2 may be regions that are doped with ions in the oxide semiconductor and have conductivity.

[0165] A third gate insulating film 133 may be disposed on the second active layer ACT2 of the second thin film transistor TFT2. The third gate insulating film 133 may be formed using an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0166] A third gate metal layer GTL3 may be disposed on the third gate insulating film 133. The third gate metal layer GTL3 may include a second gate electrode G2 of the second thin film transistor TFT2. The second gate electrode G2 may overlap the second active layer ACT2 in the third direction DR3. The third gate metal layer GTL3 may be formed as a single layer or multiple layers using one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0167] A second interlayer insulating film 142 may be disposed on the second gate electrode G2 of the second thin film transistor TFT2. The second interlayer insulating film 142 may be formed using an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0168] A first data metal layer DTL1 may be disposed on the second interlayer insulating film 142. The first data metal layer DTL1 may include a first source connection electrode SBE3, a second source connection electrode SBE1, and a third source connection electrode SBE2. The first source connection electrode SBE3 may be connected to the first drain region D1 of the first active layer ACT1 through a first source contact hole PCT1 penetrating the first gate insulating film 131, the second gate insulating film 132, the first interlayer insulating film 141, the third gate insulating film 133, and the second interlayer insulating film 142. The second source connection electrode SBE1 may be connected to the second source region S2 of the second active layer ACT2 through a second source connection contact hole BCT1 penetrating the third gate insulating film 133 and the second interlayer insulating film 142. The third source connection electrode SBE2 may be connected to the second drain region D2 of the second active layer ACT2 through a third source connection contact hole BCT2 penetrating the third gate insulating film 133 and the second interlayer insulating film 142. The first data metal layer DTL1 may be formed as a single layer or multiple layers using one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof. For example, the first data metal layer DTL1 may include a first layer using titanium (Ti), a second layer using aluminum (Al), and a third layer using titanium (Ti).

[0169] A first organic layer 160 for planarizing a step difference caused by the first thin film transistor TFT1 and the second thin film transistor TFT2 may be disposed on the first source connection electrode SBE3, the second source connection electrode SBE1, and the third source connection electrode SBE2. The first organic layer 160 may be formed using an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0170] A second data metal layer DTL2 may be disposed on the first organic layer 160. The second data metal layer DTL2 may include a fourth source connection electrode SBE4. The fourth source connection electrode SBE4 may be connected to the first source connection electrode SBE3 through a second source contact hole PCT2 penetrating the first organic layer 160. The second data metal layer DTL2 may be formed as a single layer or multiple layers using one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. For example, the second data metal layer DTL2 may include a first layer using titanium (Ti), a second layer using aluminum (Al), and a third layer using titanium (Ti).

[0171] A second organic layer 180 may be disposed on the fourth source connection electrode SBE4 and may be formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0172] A light emitting element layer EML may be disposed on the second organic layer 180 . The light emitting element layer EML may include a common electrode CE, a light emitting element LE, pixel electrodes PXE1 , PXE2 , and PXE3 , and a third organic layer 190 .

[0173] A common electrode CE may be disposed on the second organic layer 180. The common electrode CE may be a common layer formed in the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The common electrode CE may be formed as a single layer or multiple layers using one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. For example, in order to reduce the resistance of the common electrode CE, the common electrode CE may be formed using copper (Cu) having a low surface resistance.

[0174] An organic pattern layer BOL may be arranged on the common electrode CE. The organic pattern layer BOL serves to temporarily fix or adhere the plurality of light emitting elements LE to prevent the plurality of light emitting elements LE from tilting and falling down during the process of transferring the plurality of light emitting elements LE to the display panel 100. That is, the organic pattern layer BOL may be a film for pseudo-adhering the plurality of light emitting elements LE on the common electrodes CE of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The thickness of the organic pattern layer BOL may be greater than the thickness of the common electrode CE, and may be greater than the thickness of the first contact electrode CTE1 and the second contact electrode CTE2, so as to facilitate pseudo-adherence.

[0175] The organic pattern layer BOL may be a photosensitive organic layer such as a photoresist, or may be formed using acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0176] The detailed description of the organic pattern layer BOL will be combined with Figure 26 to Figure 36 This will be described later.

[0177] A plurality of light emitting elements LE may be arranged on the organic pattern layer BOL.

[0178] The plurality of light emitting elements LE may be directly transferred from the semiconductor substrate to the common electrode CE of the display panel 100. Alternatively, the plurality of light emitting elements LE may be transferred to the common electrode CE of the display panel 100 by an electrostatic method using an electrostatic head or a stamp method using a high molecular material having elasticity such as PDMS or silicon as a transfer substrate.

[0179] The third semiconductor layer SEM3 of the light emitting element LE may be in direct contact with the organic pattern layer BOL. The light emitting element LE may completely overlap with the organic pattern layer BOL. The organic pattern layer BOL may protrude from the light emitting element LE to the outside, but is not limited thereto.

[0180] The light emitting element LE may be a reference Figure 6 and Figure 7 A light emitting element LE is described.

[0181] Pixel electrodes PXE1, PXE2, and PXE3 may be arranged on the first contact electrode CTE1 of the light emitting element LE. For example, the first pixel electrode PXE1 may be arranged on the first contact electrode CTE1 of the light emitting element LE of the first sub-pixel SPX1. The second pixel electrode PXE2 may be arranged on the first contact electrode CTE1 of the light emitting element LE of the second sub-pixel SPX2. The third pixel electrode PXE3 may be arranged on the first contact electrode CTE1 of the light emitting element LE of the third sub-pixel SPX3. The first contact electrode CTE1 of the light emitting element LE may overlap with the pixel electrodes PXE1, PXE2, and PXE3.

[0182] The pixel electrodes PXE1 , PXE2 , and PXE3 can be formed using a transparent metal material (TCO: Transparent Conductive Material) such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide) that can transmit light, or a transparent conductive oxide.

[0183] The connection electrode BE plays a role of connecting the second contact electrode CTE2 of the light emitting element LE to the common electrode CE. To this end, the connection electrode BE may be connected to the second contact electrode CTE2 and the common electrode CE. The connection electrode BE may overlap at least a portion of the second contact electrode CTE2. The connection electrode BE may overlap at least a portion of the organic pattern layer BOL and at least a portion of the common electrode CE. The connection electrode BE may surround at least a portion of the side surface of the light emitting element LE. For example, the connection electrode BE may be arranged on a portion of the protection layer INS0 of the light emitting element LE. The connection electrode BE may surround the side surface of the second portion LEP2 of the light emitting element LE.

[0184] The connection electrode BE may include one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). Alternatively, the connection electrode BE may also be formed of a transparent metal material (TCO: Transparent Conductive Material) such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide) that can transmit light.

[0185] When the connection electrode BE is formed of a metal material with high reflectivity such as aluminum (Al), among the light emitted from the active layer MQW of the light emitting element LE, the light traveling toward the side surface of the light emitting element LE can be reflected by the connection electrode BE and travel toward the upper part of the light emitting element LE. Therefore, the light loss of the light emitting element LE can be reduced, and thus the light efficiency of the light emitting element LE can be improved.

[0186] In addition, in the first sub-pixel SPX1, the first pixel electrode PXE1 can be connected to the second organic layer 180 through the first connection hole CT1 ( Figure 8 ) is connected to the fourth source connection electrode SBE4. In the second sub-pixel SPX2, the second pixel electrode PXE2 can be connected to the second organic layer 180 through the second connection hole CT2 ( Figure 8 ) is connected to the fourth source connection electrode SBE4. In the third sub-pixel SPX3, the third pixel electrode PXE3 can be connected through the third connection hole CT3 ( Figure 8) is connected to the fourth source connection electrode SBE4.

[0187] In the first subpixel SPX1, the first pixel electrode PXE1 may be connected to the first source region S1 or the first drain region D1 of the first thin film transistor TFT1 through the first source connection electrode SBE3 and the fourth source connection electrode SBE4. Therefore, a voltage controlled by the first thin film transistor TFT1 may be applied to the first pixel electrode PXE1 in the first subpixel SPX1.

[0188] Furthermore, in the second sub-pixel SPX2, the second pixel electrode PXE2 can be connected to the first source region S1 or the first drain region D1 of the first thin film transistor TFT1 through the first source connection electrode SBE3 and the fourth source connection electrode SBE4. Therefore, a voltage controlled by the first thin film transistor TFT1 can be applied to the second pixel electrode PXE2 in the second sub-pixel SPX2.

[0189] Furthermore, in the third subpixel SPX3, the third pixel electrode PXE3 may be connected to the first source region S1 or the first drain region D1 of the first thin film transistor TFT1 through the first source connection electrode SBE3 and the fourth source connection electrode SBE4. Therefore, a voltage controlled by the first thin film transistor TFT1 may be applied to the third pixel electrode PXE3 in the third subpixel SPX3.

[0190] The third organic layer 190 may be arranged to cover a portion of the side surfaces of the connection electrode BE and the plurality of light emitting elements LE. For example, the third organic layer 190 may be arranged to cover the connection electrode BE. Also, the third organic layer 190 may be arranged to cover the upper surface of the second portion LEP2 and the side surface of the first portion LEP1 that are not covered by the connection electrode BE. The third organic layer 190 may be formed using an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0191] The third organic layer 190 is a layer for planarizing a step difference caused by the plurality of light emitting elements LE The third organic layer 190 may be provided to expose the first contact electrode CTE1 of each of the plurality of light emitting elements LE.

[0192] In addition, the pixel electrodes PXE1 , PXE2 , PXE3 may be referred to as anode electrodes or first electrodes, and the common electrode CE may be referred to as cathode electrode or second electrode.

[0193] The first capping layer CAP1 may be disposed on the pixel electrodes PXE1, PXE2, PXE3. The first capping layer CAP1 may be formed using an inorganic film (eg, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

[0194] A light shielding layer BM, a first light conversion layer QDL1, a second light conversion layer QDL2, and a light transmission layer TPL may be arranged on the first cover layer CAP1. The first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL may be formed by dividing the light shielding layer BM. Therefore, in the first sub-pixel SPX1, the first light conversion layer QDL1 may be arranged on the first cover layer CAP1, in the second sub-pixel SPX2, the second light conversion layer QDL2 may be arranged on the first cover layer CAP1, and in the third sub-pixel SPX3, the light transmission layer TPL may be arranged on the first cover layer CAP1. The light shielding layer BM may overlap with the third organic layer 190 in the third direction DR3, and may not overlap with the plurality of light emitting elements LE.

[0195] The first light conversion layer QDL1 may convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element LE into the first light (light in the red wavelength band). The first light conversion layer QDL1 may include a first base resin BRS1 and first wavelength conversion particles WCP1. The first base resin BRS1 may include a light-transmitting organic substance. For example, the first base resin BRS1 may include an epoxy resin, an acrylic resin, a cardo resin, or an imide resin, etc. The first wavelength conversion particles WCP1 may convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element LE into the first light (light in the red wavelength band). The first wavelength conversion particles WCP1 may be quantum dots (QD: quantum dot), quantum rods, fluorescent substances, or phosphorescent substances.

[0196] The second light conversion layer QDL2 can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element LE into a second light (light in the green wavelength band). The second light conversion layer QDL2 may include a second base resin BRS2 and second wavelength conversion particles WCP2. The second base resin BRS2 may include a light-transmitting organic substance. For example, the second base resin BRS2 may include an epoxy resin, an acrylic resin, a Cardo resin, or an imide resin, etc. The second wavelength conversion particles WCP2 may convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element LE into a second light (light in the green wavelength band). The second wavelength conversion particles WCP2 may be quantum dots (QD: quantum dot), quantum rods, fluorescent substances, or phosphorescent substances.

[0197] The light transmission layer TPL may include a light-transmitting organic material, such as an epoxy resin, an acrylic resin, a cardo resin, or an imide resin.

[0198] The light shielding layer BM may include a first light shielding layer BM1 and a second light shielding layer BM2 stacked in sequence. The length of the first light shielding layer BM1 in the first direction DR1 or the length of the second direction DR2 may be greater than the length of the second light shielding layer BM2 in the first direction DR1 or the length of the second direction DR2. The first light shielding layer BM1 and the second light shielding layer BM2 may be formed using organic layers such as acryl resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. The first light shielding layer BM1 and the second light shielding layer BM2 may include a light shielding substance to prevent the light of the light emitting element LE of one sub-pixel from traveling to the sub-pixel adjacent thereto. For example, the first light shielding layer BM1 and the second light shielding layer BM2 may include an inorganic black pigment such as carbon black or an organic black pigment.

[0199] The second cover layer CAP2 may be disposed on the first cover layer CAP1 and the light shielding layer BM. The second cover layer CAP2 may be disposed on the side surface and the upper surface of the light shielding layer BM. That is, the second cover layer CAP2 may be disposed on the side surface of the first light shielding layer BM1, the side surface and the upper surface of the second light shielding layer BM2.

[0200] The reflective layer RF may be arranged between the light shielding layer BM and the first light conversion layer QDL1, between the light shielding layer BM and the second light conversion layer QDL2, and between the light shielding layer BM and the light transmission layer TPL. The reflective layer RF may be arranged on the second cover layer CAP2 arranged on the side surface of the first light shielding layer BM1 and the side surface of the second light shielding layer BM2. The reflective layer RF is used to reflect light traveling from the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL toward the side surface direction.

[0201] The reflective layer RF may include a metal substance having high reflectivity such as aluminum (Al). The thickness of the reflective layer RF may be about 0.1 μm.

[0202] Alternatively, the reflective layer RF may include M (M is an integer greater than 2) pairs of first and second layers having different refractive indices in order to function as a distributed Bragg reflector (DBR). In this case, the M first layers and the M second layers may be arranged alternately. The first and second layers may be formed using an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

[0203] The third cover layer CAP3 may be disposed on the second cover layer CAP2, the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL. The third cover layer CAP3 may be formed using an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer). The first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL may be encapsulated by the first cover layer CAP1, the second cover layer CAP2, and the third cover layer CAP3.

[0204] A fifth organic layer 193 may be disposed on the third capping layer CAP3. The fifth organic layer 193 may be formed using acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0205] A plurality of color filters CF1, CF2, CF3 may be disposed on the fifth organic layer 193. The plurality of color filters CF1, CF2, CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

[0206] The first color filter CF1 arranged in the first sub-pixel SPX1 can transmit the first light (light in the red wavelength band) and can absorb or block the third light (light in the blue wavelength band). Therefore, the first color filter CF1 can transmit the first light (light in the red wavelength band) converted by the first light conversion layer QDL1 among the third light (light in the blue wavelength band) emitted from the light emitting element LE, and can absorb or block the third light (light in the blue wavelength band) not converted by the first light conversion layer QDL1. Therefore, the first sub-pixel SPX1 can emit the first light (light in the red wavelength band).

[0207] The second color filter CF2 arranged in the second sub-pixel SPX2 can transmit the second light (light in the green wavelength band) and absorb or block the third light (light in the blue wavelength band). Therefore, the second color filter CF2 can transmit the second light (light in the green wavelength band) converted by the second light conversion layer QDL2 among the third light (light in the blue wavelength band) emitted from the light emitting element LE, and can absorb or block the third light (light in the blue wavelength band) not converted by the second light conversion layer QDL2. Therefore, the second sub-pixel SPX2 can emit the second light (light in the green wavelength band).

[0208] The third color filter CF3 arranged in the third sub-pixel SPX3 can transmit the third light (light in the blue wavelength band). Therefore, the third color filter CF3 can transmit the third light (light in the blue wavelength band) emitted from the light-emitting element LE through the light-transmitting layer TPL. Therefore, the third sub-pixel SPX3 can emit the third light (light in the blue wavelength band).

[0209] The first, second, and third color filters CF1, CF2, and CF3 overlapped in the third direction DR3 may overlap the third organic layer 190 and the light blocking layer BM in the third direction DR3.

[0210] A sixth organic layer 194 for planarization may be disposed on the plurality of color filters CF1, CF2, CF3. The sixth organic layer 194 may be formed using acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0211] according to Fig. 9 and Fig.10 The light emitting element LE includes a first portion LEP1 and a second portion LEP2 of a multi-level structure, and may include a first contact electrode CTE1 arranged in the first portion LEP1 and a second contact electrode CTE2 arranged in the second portion LEP2. The first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 may be arranged on the upper surface of the light emitting element LE, and the common electrode CE may be arranged on the lower surface of the light emitting element LE. The pixel electrodes PXE1, PXE2, and PXE3 are arranged on the first contact electrode CTE1, and the second contact electrode CTE2 is connected to the common electrode CE through the connecting electrode BE.

[0212] Fig.11 is shown corresponding to Figure 8 FIG. 1 is a cross-sectional view showing another example of a cross-section of a display panel taken along line I1 - I1 ′. Fig.12 It is shown in detail Fig.11A cross-sectional view of an example of region B.

[0213] Reference Fig.11 and Fig.12 ,and Fig. 9 and Fig.10 The difference of the embodiment is that the organic layer covering the light emitting element LE is formed into multiple layers, and a functional layer FUL is added between the stacked organic layers 190 and 191. Fig.11 and Fig.12 In the embodiment of Figures 8 to 10 The description of the embodiment is repeated.

[0214] Reference Fig.11 and Fig.12 The light emitting element layer EML further includes a plurality of stacked organic layers 190 and 191 and a functional layer FUL disposed between the stacked organic layers 190 and 191 .

[0215] The third organic layer 190 and the fourth organic layer 191 may be disposed in order to planarize the light emitting element LE.

[0216] The third organic layer 190 may be arranged to cover at least a portion of the side surface of the light emitting element LE including the second contact electrode CTE2 . The third organic layer 190 may be arranged to be increasingly higher from the center of the sub-pixels SPX1 , SPX2 , SPX3 toward the side surface.

[0217] A fourth organic layer 191 may be disposed on the third organic layer 190 . The fourth organic layer 191 may be disposed not higher than the light emitting element LE. For example, the first contact electrode CTE1 of the light emitting element LE may be exposed through the fourth organic layer 191 .

[0218] The fourth organic layer 191 may be formed using an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0219] A functional layer FUL may be disposed between the third organic layer 190 and the fourth organic layer 191 .

[0220] The functional layer FUL may be a reflective layer including a metal substance with high reflectivity, such as aluminum (Al). When the functional layer FUL includes a metal substance with high reflectivity, the light extraction efficiency of the light emitting element LE may be improved.

[0221] The functional layer FUL may be a protective layer formed using an inorganic film (eg, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer). When the functional layer FUL includes an inorganic film, the reliability of the light emitting element LE may be improved.

[0222] Fig.13 is a perspective view showing the structure of a light emitting element according to another embodiment, Fig.14 is a cross-sectional view showing the structure of a light emitting element according to an embodiment.

[0223] Reference Fig.13 and Fig.14 ,and Figure 6 and Figure 7 The difference of the embodiment is that the first part LEP1 and the one side surface of the second part LEP2 are arranged in a straight line and aligned. Fig.13 and Fig.14 In the embodiment of Figure 6 and Figure 7 The description of the embodiment is repeated.

[0224] Reference Fig.13 and Fig.14 , the light emitting element LE may be a vertical type micro LED extending along the third direction DR3. The vertical type micro LED refers to an LED having a structure in which the third semiconductor layer SEM3, the second semiconductor layer SEM2, the active layer MQW and the first semiconductor layer SEM1 are sequentially arranged in the third direction DR3 as a vertical direction.

[0225] The light emitting element LE includes a first portion LEP1 and a second portion LEP2. The first portion LEP1 may be disposed on the second portion LEP2. The first portion LEP1 and the second portion LEP2 may be in a rectangular parallelepiped shape. One side surface of the first portion LEP1 and the second portion LEP2 are aligned on a straight line.

[0226] The first portion LEP1 includes a first contact electrode CTE1, a first semiconductor layer SEM1, an active layer MQW, a second semiconductor layer SEM2, and a protective layer INS0. The second portion LEP2 includes a second contact electrode CTE2, a second semiconductor layer SEM2, a third semiconductor layer SEM3, and a protective layer INS0. The second semiconductor layer SEM2 of the first portion LEP1 may be connected to the second semiconductor layer SEM2 of the second portion LEP2. The diameter of the first portion LEP1 may be narrower than the diameter of the second portion LEP2. The second portion LEP2 that does not overlap with the first portion LEP1 may be exposed to the outside.

[0227] A first contact electrode CTE1 may be disposed on the first semiconductor layer SEM1 of the first portion LEP1. The first contact electrode CTE1 may be disposed on an upper surface of the first semiconductor layer SEM1.

[0228] The second contact electrode CTE2 may be disposed on an upper surface of the second semiconductor layer SEM2 of the second portion LEP2 not overlapping the first portion LEP1.

[0229] A protective layer INS0 may be disposed on the upper surface of the first portion LEP1 and the second portion LEP2 where the first contact electrode CTE1 and the second contact electrode CTE2 are not disposed and the side surfaces of the first portion LEP1 and the second portion LEP2. The protective layer INS0 may be a film for protecting the side surface of the light emitting element LE. The protective layer INS0 may be formed using an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

[0230] The common electrode CE may be a common layer commonly formed in the first sub-pixel SPX1 , the second sub-pixel SPX2 , and the third sub-pixel SPX3 arranged along the same first direction DR1 .

[0231] Fig.15 is a diagram showing a layout of pixels of a display area according to an embodiment. Fig.16 is shown corresponding to Fig.15 FIG. 1 is a cross-sectional view of an example of a cross-section of a display panel taken along line I2 - I2 ′. Fig.17 It is shown in detail Fig.16 A cross-sectional view of an example of the C region.

[0232] Reference Figures 15 to 17 ,and Fig. 9 and Fig.10 The embodiment is different in that the light emitting element LE includes reference Fig.13 and Fig.14 The light emitting element LE shown in the figure includes a plurality of stacked organic layers 190 and 191. Figures 15 to 17 In the embodiment of Figures 8 to 10 The description of the embodiment is repeated.

[0233] The connection electrode BE plays a role of connecting the second contact electrode CTE2 and the common electrode CE of the light emitting element LE. To this end, the connection electrode BE may be connected to the second contact electrode CTE2 and the common electrode CE. The connection electrode BE may overlap with at least a portion of the second contact electrode CTE2. The connection electrode BE may overlap with at least a portion of the organic pattern layer BOL and at least a portion of the common electrode CE. The connection electrode BE may surround at least a portion of the side surface of the light emitting element LE. For example, the connection electrode BE may be arranged on a portion of the protection layer INS0 of the light emitting element LE. The connection electrode BE may surround the side surface of the second portion LEP2 of the light emitting element LE. The connection electrode BE may be arranged to be lower than the active layer MQW.

[0234] The third organic layer 190 may surround the second portion LEP2. The third organic layer 190 may cover the connection electrode BE. The fourth organic layer 191 may surround the first portion LEP1. The fourth organic layer 191 may be formed to completely cover the light emitting element LE. In the case where the fourth organic layer 191 is formed to completely cover the light emitting element LE, an opening portion OP_C exposing the first contact electrode CTE1 may be included.

[0235] Pixel electrodes PXE1, PXE2, and PXE3 may be arranged on the first contact electrode CTE1 of the light emitting element LE. For example, the first pixel electrode PXE1 may be arranged on the first contact electrode CTE1 of the light emitting element LE of the first sub-pixel SPX1. The second pixel electrode PXE2 may be arranged on the first contact electrode CTE1 of the light emitting element LE of the second sub-pixel SPX2. The third pixel electrode PXE3 may be arranged on the first contact electrode CTE1 of the light emitting element LE of the third sub-pixel SPX3. The first contact electrode CTE1 of the light emitting element LE may overlap with the pixel electrodes PXE1, PXE2, and PXE3.

[0236] The width of the organic pattern layer BOL may be equal to or greater than the width of the light emitting element LE.

[0237] Each of the plurality of pixels PX of the display area DA may include a first sub-pixel SPX1 , a second sub-pixel SPX2 , and a third sub-pixel SPX3 .

[0238] Fig.18 is a flowchart showing a method for manufacturing a light emitting element according to an embodiment. Figures 19 to 24 is a cross-sectional view for explaining a method for manufacturing a light emitting element according to an embodiment. Figures 19 to 24 Shown with reference Figure 6 An example of a cross-section and a plane of a light-emitting element on a growth substrate corresponding to the light-emitting element.

[0239] Reference Fig.19, prepare a base substrate BSUB. The base substrate BSUB may be a sapphire substrate (Al 2 O 3 ) or a silicon wafer including silicon. However, not limited thereto, in one embodiment, a case where the base substrate BSUB is a sapphire substrate is exemplified and described.

[0240] A plurality of semiconductor material layers SEM3L, SEM2L, MQWL, SEM1L are formed on the base substrate BSUB. Fig.18 S10). The plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L grown by the epitaxial method may be formed by growing a seed crystal. Here, the method for forming the semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L may be electron beam deposition, physical vapor deposition (PVD: Physical vapor deposition), chemical vapor deposition (CVD: Chemical vapor deposition), plasma laser deposition (PLD: Plasma laser deposition), dual-type thermal evaporation, sputtering, metal-organic chemical vapor deposition (MOCVD: Metal organic chemical vapor deposition), etc. Preferably, they may be formed by metal-organic chemical vapor deposition (MOCVD). However, it is not limited thereto.

[0241] The precursor material for forming the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L is not particularly limited within a range that can be generally selected for forming the target material. As an example, the precursor material may be a metal precursor containing an alkyl group such as a methyl group or an ethyl group. For example, it may be a precursor such as trimethylgallium (Ga(CH 3 ) 3 ), trimethylaluminum (Al(CH 3 ) 3 ), triethyl phosphate ((C 2 H 5 ) 3 PO 4 ) and the like, but not limited thereto.

[0242] Specifically, a third semiconductor material layer SEM3L is formed on the base substrate BSUB. Although the drawings show a situation where one layer of the third semiconductor material layer SEM3L is stacked, it is not limited thereto, and multiple layers may also be formed. The third semiconductor material layer SEM3L may be arranged in order to reduce the lattice constant difference between the second semiconductor material layer SEM2L and the base substrate BSUB. As an example, the third semiconductor material layer SEM3L may include an undoped semiconductor, which may be a material that is not doped to n-type or p-type. In an exemplary embodiment, the third semiconductor material layer SEM3L may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto.

[0243] By using the above method, the second semiconductor material layer SEM2L, the active material layer MQWL and the first semiconductor material layer SEM1L are sequentially formed on the third semiconductor material layer SEM3L.

[0244] Next, the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L are etched to form a light emitting element LE ( Fig.18 S20).

[0245] Specifically, a plurality of first mask patterns MP1 are formed on the first semiconductor material layer SEM1L. The first mask pattern MP1 may be a hard mask containing inorganic matter or a photoresist mask containing organic matter. The first mask pattern MP1 prevents the lower plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L from being etched. Next, using the plurality of first mask patterns MP1 as masks, a portion of the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L is first etched (1 st etch).

[0246] The plurality of semiconductor material layers SEM3L, SEM2L, MQWL, SEM1L not overlapping the first mask pattern MP1 may be etched and removed on the base substrate BSUB, and the portions overlapping the first mask pattern MP1 and not etched may be formed into a plurality of semiconductor materials SEM3, SEM2, MQW, SEM1.

[0247] Reference Fig.21 , a portion of the plurality of semiconductor materials SEM3, SEM2, MQW, SEM1 that have been etched for the first time is etched for the second time. The second etching forms a first portion LEP1 with a narrow width and a second portion LEP2 with a relatively wide width ( Fig.18The processes used for the second etching include dry etching, wet etching, reactive ion etching (RIE), deep reactive ion etching (DRIE), inductively coupled plasma reactive ion etching (ICP-RIE), etc.

[0248] Reference Fig. 22 and Fig.23 , an insulating material layer INSL is formed on the base substrate BSUB on which the light emitting element LE is formed.

[0249] Specifically, an insulating layer INSL is formed on the outer surface of the plurality of light emitting elements LE. The insulating layer INSL may be formed on the entire surface of the base substrate BSUB, and may be formed not only on the light emitting elements LE but also on the upper surface of the base substrate BSUB exposed by the light emitting elements LE.

[0250] Next, a third etching step (3 rd etch) to form a protective layer INS0 ( Fig.18 S40).

[0251] Specifically, an etching process of partially removing a portion of the insulating substance layer INSL so that the insulating substance layer INSL exposes the upper surface of the light emitting element LE and surrounds the side surface of the light emitting element LE may be performed. Specifically, in this process, the insulating substance layer INSL may define a first opening portion OP1 by removing at least a portion of the upper surface of the first semiconductor layer SEM1 of the light emitting element LE. Also, the insulating substance layer INSL may define a second opening portion OP2 by removing at least a portion of the second semiconductor layer SEM2 of the light emitting element LE. The process of partially removing the insulating substance layer INSL may be performed by an etching process using a mask.

[0252] Next, refer to Fig.24 , a first contact electrode CTE1 and a second contact electrode CTE2 may be formed on the light emitting element LE to form the light emitting element LE ( Fig.18 S50).

[0253] For example, a contact electrode material layer is stacked on the base substrate BSUB. Then, etching is performed by an etching process to form a first contact electrode CTE1 covering the first opening OP1 of the light emitting element LE and a second contact electrode CTE2 covering the second opening OP2. The contact electrode material layer can be formed using a transparent conductive material. For example, the contact electrode material layer can be a transparent conductive oxide such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide).

[0254] then, Fig.25 is a flowchart illustrating a method for manufacturing a display device according to an embodiment. Figure 26 to Figure 36 is a cross-sectional view for explaining a method for manufacturing a display device according to an embodiment. Figure 26 to Figure 36 Shown with Figure 8 An example of a cross section of a display panel corresponding to line I1-I1'.

[0255] First, as Fig.26 As shown, a thin film transistor layer TFTL and a common electrode CE ( Fig.25 S110).

[0256] A barrier film BR is formed on the substrate SUB, and a first channel region CHA1 , a first source region S1 , and a first drain region D1 of the first thin film transistor TFT1 are formed on the barrier film BR by a photolithography process.

[0257] Then, a first gate insulating film 131 is formed on the first channel region CHA1, the first source region S1, and the first drain region D1 of the first thin film transistor TFT1, and a first gate electrode G1 and a first capacitor electrode CAE1 of the first thin film transistor TFT1 are formed on the first gate insulating film 131. The first channel region CHA1, the first source region S1, and the first drain region D1 of the first thin film transistor TFT1 may include polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, or amorphous silicon.

[0258] Then, a second gate insulating film 132 is formed on the first gate electrode G1 of the first thin film transistor TFT1 and the first capacitor electrode CAE1 , and a second capacitor electrode CAE2 is formed on the second gate insulating film 132 by a photolithography process.

[0259] Then, a first interlayer insulating film 141 is formed on the second capacitor electrode CAE, and a second channel region CHA2, a second source region S2, and a second drain region D2 of the second thin film transistor TFT2 are formed on the first interlayer insulating film 141 using a photolithography process. The second channel region CHA2, the second source region S2, and the second drain region D2 of the second thin film transistor TFT2 may include an oxide semiconductor including indium (In), gallium (Ga), and oxygen (O).

[0260] Then, a third gate insulating film 133 is formed on the second channel region CHA2 , the second source region S2 , and the second drain region D2 of the second thin film transistor TFT2 , and a second gate electrode G2 of the second thin film transistor TFT2 is formed on the third gate insulating film 133 by photolithography.

[0261] Then, a second interlayer insulating film 142 is formed on the second gate electrode G2 of the second thin film transistor TFT2. Furthermore, a first source contact hole PCT1 penetrating the first gate insulating film 131, the second gate insulating film 132, the first interlayer insulating film 141, the third gate insulating film 133, and the second interlayer insulating film 142, a second source connection contact hole BCT1 penetrating the third gate insulating film 133 and the second interlayer insulating film 142, and a third source connection contact hole BCT2 penetrating the third gate insulating film 133 and the second interlayer insulating film 142 are formed by a photolithography process. Furthermore, a first source connection electrode SBE3, a second source connection electrode SBE1, and a third source connection electrode SBE2 are formed on the second interlayer insulating film 142 by a photolithography process.

[0262] Then, a first organic layer 160 is formed on the first source connection electrode SBE3 , the second source connection electrode SBE1 , and the third source connection electrode SBE2 , and a fourth source connection electrode SBE4 is formed on the first organic layer 160 using a photolithography process.

[0263] Then, a second organic layer 180 is formed on the fourth source connection electrode SBE4 , and a common electrode CE is formed on the second organic layer 180 using a photolithography process.

[0264] Second, if Fig. 27 and Fig.28 As shown, a dummy adhesive layer BOL_1 (or a temporary adhesive layer or a temporary fixing layer) is formed on the common electrode CE and aligned with the light emitting element LE ( Fig.25 S120).

[0265] The dummy adhesive layer BOL_1 temporarily fixes or adheres the plurality of light emitting elements LE to prevent the plurality of light emitting elements LE from tilting and falling down during the process of transferring the plurality of light emitting elements LE to the display panel 100. To this end, the thickness of the dummy adhesive layer BOL_1 may be within about 2 μm, but the embodiments of the present specification are not limited thereto.

[0266] The dummy adhesion layer BOL_1 may be a photosensitive organic layer such as a photoresist, or may be formed using acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0267] In order to transfer the plurality of light emitting elements LE grown on the base substrate BSUB to the display panel 100 , a support film SPF1 is attached on the plurality of light emitting elements LE.

[0268] Specifically, a support film SPF1 is attached on the plurality of light emitting elements LE. The support film SPF1 may be aligned on the plurality of light emitting elements LE and may be attached to the first contact electrodes CTE1 of the plurality of light emitting elements LE. Since the plurality of light emitting elements LE are arranged in a large number, they may be attached to the support film SPF1 without being separated from the support film SPF1.

[0269] The support film SPF1 may be formed using a support layer SP2 and an adhesive layer SP1 arranged on the support layer SP2. The support layer SP2 may be formed using a material that is transparent and mechanically stable in a manner that allows light to be transmitted. For example, the support layer SP2 may include a transparent polymer such as polyester, polyacrylic acid, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, and the like. The adhesive layer SP1 may include an adhesive substance for bonding the light-emitting element LE. For example, the adhesive substance may include polyurethane acrylate, epoxy acrylate, polyester acrylate, and the like. The adhesive substance may be a substance whose adhesive force changes with the application of ultraviolet rays (UV) or heat, whereby the adhesive layer SP1 may be easily separated from the light-emitting element LE.

[0270] Next, the base substrate BSUB is irradiated with laser light to separate the light emitting elements LE from the base substrate BSUB. The base substrate BSUB is separated from each of the third semiconductor layers SEM3 of the plurality of light emitting elements LE.

[0271] The base substrate BSUB can be separated by a laser lift off (LLO) process. The laser lift off process uses laser, and a KrF excimer laser (248 nm wavelength) can be used as a source. The energy density of the excimer laser is about 550 mJ / cm 2 Up to 950mJ / cm 2 Range irradiation, the irradiation area (incident area) can be 50×50μm 2 Up to 1×1cm 2 By irradiating laser light to the base substrate BSUB, the base substrate BSUB can be separated from the light emitting element LE.

[0272] Third, if Fig.29 As shown, a plurality of light emitting elements LE are fixed to the dummy adhesive layer BOL_1 ( Fig.25 S130).

[0273] A portion of each of the plurality of light emitting elements LE may be embedded in the dummy adhesive layer BOL_1 and temporarily fixed. For example, the third semiconductor layer SEM3 of each of the plurality of light emitting elements LE may be embedded in the dummy adhesive layer BOL_1 and fixed.

[0274] In the case where the dummy adhesion layer BOL_1 is a photosensitive organic layer such as a photoresist, after the dummy adhesion layer BOL_1 is cured at a first temperature, a portion of each of the plurality of light emitting elements LE is fixed to the dummy adhesion layer BOL_1. Thereafter, the dummy adhesion layer BOL_1 may be completely cured at a second temperature higher than the first temperature. The first temperature may be about 150 degrees, and the second temperature may be about 250 degrees, but the embodiments of the present specification are not limited thereto.

[0275] The plurality of light emitting elements LE can be separated from the support film SPF1 by a laser lift-off process.

[0276] Fourth, if Fig.30 As shown, a portion of the dummy adhesive layer BOL_1 is removed to form an organic pattern layer BOL ( Fig.25 S140).

[0277] The organic pattern layer BOL is formed by removing a portion of the dummy adhesion layer BOL_1 using the light emitting element LE as a mask. That is, the organic pattern layer BOL may be a residue of the dummy adhesion layer BOL_1.

[0278] In the case where the dummy adhesion layer BOL_1 is a photosensitive organic layer such as a photoresist, it may be removed by an ashing process.

[0279] Fifth, if Fig.31 and Fig.32 As shown, a connection electrode BE ( Fig.25 S150).

[0280] To this end, first, a connection electrode layer BEL is formed to cover the common electrode CE, the organic pattern layer BOL and the plurality of light emitting elements LE.

[0281] After that, after forming a photoresist covering the entire connection electrode layer BEL, the photoresist overlapping the opening of the mask is removed to expose the connection electrode layer BEL, and then the exposed connection electrode layer BEL is etched to form the connection electrode BE. The photoresist can be removed by an ashing process.

[0282] Sixth, if Fig.33 As shown, a third organic layer 190 ( Fig.25 S160).

[0283] The third organic layer 190 may be disposed to cover the common electrode CE, a portion of the side surface and the upper surface of the organic pattern layer BOL, and a portion of the side surface of each of the plurality of light emitting elements LE.

[0284] The third organic layer 190 may be formed to be lower than a height of the light emitting element LE so that the first contact electrode CTE1 of the light emitting element LE is exposed.

[0285] Seventh, such as Fig.34 and Fig.35 As shown, pixel electrodes PXE1, PXE2, PXE3 ( Fig.25 S170).

[0286] For example, after forming a pixel electrode layer PXEL covering all first contact electrodes CTE1 of a plurality of light emitting elements LE and the entire third organic layer 190, and forming a photoresist covering the entire pixel electrode layer PXEL, the photoresist overlapping the opening of the mask is removed to expose the pixel electrode layer PXEL, and then the exposed pixel electrode layer PXEL is etched to form pixel electrodes PXE1, PXE2, and PXE3. The photoresist may be removed by an ashing process.

[0287] Eighth, such as Fig.36 As shown, a cover layer CPA1, a light shielding layer BM, a first light conversion layer QDL1 and a second light conversion layer QDL2, and color filters CF1, CF2, and CF3 are formed. Fig.25 S180).

[0288] A first capping layer CAP1 is formed on the pixel electrodes PXE1, PXE2, PXE3 and the third organic layer 190, a first light shielding layer BM1 is formed on the first capping layer CAP1, and a second light shielding layer BM2 is formed on the first light shielding layer BM1. The first light shielding layer BM1 and the second light shielding layer BM2 may overlap with the third organic layer 190 in the third direction DR3, and may not overlap with the plurality of light emitting elements LE. The length of the first light shielding layer BM1 in the first direction DR1 or the length in the second direction DR2 may be greater than the length of the second light shielding layer BM2 in the first direction DR1 or the length in the second direction DR2.

[0289] Then, the second cover layer CAP2 is formed on the first cover layer CAP1 and the light shielding layer BM, and the reflective layer RF is formed on the second cover layer CAP2 arranged on side surfaces of the first light shielding layer BM1 and the second light shielding layer BM2.

[0290] Then, in the area divided by the first light-shielding layer BM1 and the second light-shielding layer BM2, a first light conversion layer QDL1 is formed in the area corresponding to the first sub-pixel SPX1, a second light conversion layer QDL2 is formed in the area corresponding to the second sub-pixel SPX2, and a light-transmitting layer TPL is formed in the area corresponding to the third sub-pixel SPX3.

[0291] Then, a third capping layer CAP3 is formed on the second capping layer CAP2 , the first light conversion layer QDL1 , the second light conversion layer QDL2 , and the light transmitting layer TPL, and a fifth organic layer 193 is formed on the third capping layer CAP3 .

[0292] Then, a plurality of color filters CF1 , CF2 , and CF3 are formed on the fifth organic layer 193 , and a sixth organic layer 194 is formed on the plurality of color filters CF1 , CF2 , and CF3 .

[0293] Fig.37 FIG. 4 is an exemplary diagram showing a virtual reality device including a display device according to an embodiment. Fig.37 A virtual reality device 1 to which a display device 10_1 according to an embodiment is applied is shown.

[0294] Reference Fig.37 According to an embodiment, the virtual reality device 1 may be a device in the form of glasses. According to an embodiment, the virtual reality device 1 includes: a display device 10_1, a left-eye lens 10a, a right-eye lens 10b, a support frame 20, glasses frame legs 30a, 30b, a reflective component 40, and a display device storage portion 50.

[0295] Fig.37The virtual reality device 1 including the glasses frame legs 30a and 30b is exemplarily shown, but the virtual reality device 1 according to an embodiment can also be applied to a head mounted display including a headband that can be worn on the head instead of the glasses frame legs 30a and 30b. That is, the virtual reality device 1 according to an embodiment is not limited to Fig.37 The contents shown can be applied to various electronic devices in various forms, among others.

[0296] The display device storage portion 50 may include a display device 10_1 and a reflective component 40. The image displayed on the display device 10_1 may be reflected by the reflective component 40 and provided to the right eye of the user through the right eye lens 10b. Therefore, the user may view the virtual reality image displayed on the display device 10_1 through the right eye.

[0297] Fig.37 The case where the display device storage portion 50 is arranged at the right end of the support frame 20 is exemplified, but the embodiments of the present specification are not limited thereto. For example, the display device storage portion 50 may be arranged at the left end of the support frame 20, in which case the image displayed on the display device 10_1 may be reflected from the reflective component 40 and provided to the left eye of the user through the left eye lens 10a. Therefore, the user can view the virtual reality image displayed on the display device 10_1 through the left eye. Alternatively, the display device storage portion 50 may be arranged at both the left end and the right end of the support frame 20, in which case the user can view the virtual reality image displayed on the display device 10_1 through both the left eye and the right eye.

[0298] Fig.38 is an exemplary diagram showing a smart watch including a display device according to an embodiment.

[0299] Reference Fig.38 According to one embodiment, the display device 10_2 can be applied to a smart watch 2 which is one of the smart devices.

[0300] Fig.39 is an exemplary diagram showing a vehicle instrument panel and a center instrument panel including a display device according to an embodiment. Fig.39 A vehicle to which display devices 10_a, 10_b, 10_c, 10_d, 10_e according to an embodiment are applied is shown.

[0301] Reference Fig.39According to an embodiment, the display devices 10_a, 10_b, and 10_c can be applied to a dashboard of a car, or to a center fascia of a car, or to a center information display (CID: Center Information Display) arranged on a dashboard of a car. Furthermore, the display devices 10_d and 10_e according to an embodiment can be applied to a room mirror display (room mirror display) that replaces a side mirror of a car.

[0302] Fig.40 is an exemplary diagram showing a transparent display device including a display device according to an embodiment.

[0303] Reference Fig.40 According to an embodiment, the display device 10_3 can be applied to a transparent display device. The transparent display device can transmit light while displaying an image IM. Therefore, a user located in front of the transparent display device can not only view the image IM displayed on the display device 10_3, but also see the object RS or background located on the back of the transparent display device. In the case where the display device 10_3 is applied to a transparent display device, the substrate of the display device 10_3 may include a light-transmitting portion capable of transmitting light, or may be formed using a material capable of transmitting light.

[0304] The embodiments of the present invention are described above with reference to the accompanying drawings, but a person with ordinary knowledge in the technical field to which the present invention belongs can understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all aspects and are not restrictive.

Claims

1. A light emitting element, comprising: The first part includes, in sequence, a first contact electrode, a first semiconductor layer, an active layer, and a second semiconductor layer; The second part includes a second contact electrode, a second semiconductor layer and a third semiconductor layer in sequence; as well as a protective layer disposed on a portion of the upper portion and a side surface of the first portion and a portion of the upper portion and a side surface of the second portion, wherein the first portion is arranged on the second portion, The diameter of the first portion is smaller than the diameter of the second portion.

2. The light-emitting element according to claim 1, wherein The second semiconductor layer of the second portion is connected to the second semiconductor layer of the first portion.

3. The light-emitting element according to claim 2, wherein The first part and the second part are cylindrical in shape, In a plane, the second portion surrounds the first portion.

4. The light-emitting element according to claim 3, wherein In a plane, the second contact electrode surrounds the first portion.

5. The light emitting element according to claim 2, wherein The first part and the second part are in the shape of a cuboid, One side surfaces of the first portion and the second portion are aligned and consistent with each other.

6. A display device, comprising: substrate; A common electrode is arranged on the substrate; an organic pattern layer, arranged on the common electrode; a light emitting element, arranged on the organic pattern layer and having a first contact electrode and a second contact electrode; A pixel electrode, arranged on the first contact electrode; as well as a connecting electrode connecting the second contact electrode and the common electrode, Wherein, the light emitting element comprises: The first part includes the first contact electrode, the first semiconductor layer, the active layer, and the second semiconductor layer in sequence; The second part includes the second contact electrode, the second semiconductor layer and the third semiconductor layer in sequence; and a protective layer disposed on a portion of the upper portion and a side surface of the first portion and a portion of the upper portion and a side surface of the second portion, wherein the first portion is arranged on the second portion, The diameter of the first portion is smaller than the diameter of the second portion.

7. The display device according to claim 6, further comprising: The organic layer covers the upper surface of the connecting electrode and the side surface of the light emitting element.

8. The display device according to claim 6, wherein: The connection electrode has a higher reflectivity than the pixel electrode.

9. The display device according to claim 8, wherein: The common electrode and the connection electrode include metal substances, The pixel electrode includes a transparent conductive oxide.

10. The display device according to claim 9, wherein: The common electrode is formed on a common layer of a plurality of sub-pixels.

11. The display device according to claim 6, wherein: The second semiconductor layer of the second portion is connected to the second semiconductor layer of the first portion.

12. The display device according to claim 11, wherein: The first part and the second part are cylindrical in shape, On a plane, the second portion surrounds the first portion, In a plane, the second contact electrode surrounds the first portion.

13. The display device according to claim 12, further comprising: a first organic layer, covering the second contact electrode; a second organic layer disposed on the first organic layer; a functional layer disposed between the first organic layer and the second organic layer, The functional layer includes at least one of a protective layer including an inorganic film and a reflective layer including a reflective material with high reflectivity.

14. The display device according to claim 11, wherein: The first part and the second part are in the shape of a cuboid, One side surfaces of the first portion and the second portion are aligned and consistent with each other.

15. A method for manufacturing a light emitting element, comprising the following steps: forming a plurality of semiconductor material layers on a base substrate; Etching the plurality of semiconductor material layers to form a light emitting element including a third semiconductor layer, a second semiconductor layer, an active layer and a first semiconductor layer; Etching the first semiconductor layer, the active layer, and a portion of the second semiconductor layer to form a first portion and a second portion; forming a protective layer disposed on a portion of an upper portion and a side surface of the first portion and a portion of an upper portion and a side surface of the second portion; as well as forming a first contact electrode on an upper portion of the first portion, and forming a second contact electrode on an upper portion of the second portion, The first part is arranged on the second part, and a diameter of the first part is smaller than a diameter of the second part.

16. The method for manufacturing a light emitting element according to claim 15, wherein: In the step of forming the first part and the second part, The peripheries of the first semiconductor layer, the active layer, and the second semiconductor layer are etched so that the first portion is arranged in a plane at the center of the second portion to expose the second semiconductor layer on the upper surface of the second portion.

17. The method for manufacturing a light emitting element according to claim 16, wherein: In the steps of forming the first contact electrode on the upper portion of the first portion and forming the second contact electrode on the upper portion of the second portion, The first contact electrode is formed to contact the first semiconductor layer of the first portion, The second contact electrode is formed to contact the second semiconductor layer of the second portion.

18. A method for manufacturing a display device, comprising the following steps: forming a thin film transistor layer and a common electrode on a substrate; forming a dummy adhesion layer on the common electrode and aligning the light emitting element; fixing the light emitting element on the dummy adhesive layer, and removing a portion of the dummy adhesive layer to form an organic pattern layer; forming a connection electrode connecting the common electrode and a second contact electrode of the light emitting element; forming an organic layer covering the connection electrode and a portion of the light emitting element; as well as forming a pixel electrode on the first contact electrode of the light emitting element, Wherein, the light emitting element comprises: The first part includes the first contact electrode, the first semiconductor layer, the active layer, and the second semiconductor layer in sequence; and The second part includes the second contact electrode, the second semiconductor layer and the third semiconductor layer in sequence, The first part is arranged on the second part, and a diameter of the first part is smaller than a diameter of the second part.

19. The method for manufacturing a display device according to claim 18, wherein: The step of fixing the light emitting element to the dummy adhesive layer comprises the following steps: curing the dummy adhesive layer at a first temperature; inserting a portion of each of the light emitting elements into the dummy adhesive layer; and The dummy adhesion layer is cured at a second temperature higher than the first temperature.

20. The method for manufacturing a display device according to claim 18, further comprising the following steps: forming a light shielding layer disposed on the cover layer disposed on the pixel electrode and the organic layer and defining a light emitting area; In the regions divided by the light shielding layer, a first light conversion layer is formed in a region corresponding to the first sub-pixel, a second light conversion layer is formed in a region corresponding to the second sub-pixel, and a light transmission layer is formed in a region corresponding to the third sub-pixel; and A first color filter is formed on the first light conversion layer, a second color filter is formed on the second light conversion layer, and a third color filter is formed on the light transmission layer.

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