Display apparatus and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device includes: a substrate; a first semiconductor layer disposed on the substrate and including a first active portion, a second active portion, and a first doped portion; a first conductive layer including a first conductive pattern overlapping the first active portion; a second conductive layer including a second conductive pattern and a third conductive pattern, the second conductive pattern overlapping the first conductive pattern, and the third conductive pattern being connected to the first doped portion through a first contact hole; a second semiconductor layer disposed on the second conductive layer and including an upper first active portion and a second doped portion; a third conductive layer including a first conductive line overlapping the upper first active portion; and a fourth conductive layer including a fourth conductive pattern electrically connecting the third conductive pattern to the second doped portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0155723 filed in the Korean Intellectual Property Office on November 10, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to a display device and a method of manufacturing the display device. Background Art

[0004] In general, a display device includes a light emitting diode and a thin film transistor that controls the brightness of the light emitting diode, etc. The thin film transistor controls the corresponding light emitting diode to emit light of a preset color by using a data signal, a driving voltage, and a common voltage transmitted thereto. Summary of the invention

[0005] One or more embodiments include a display device that provides a high-quality image and a method of manufacturing the display device. However, such technical goals are only examples, and the embodiments are not limited thereto.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the embodiments.

[0007] According to one or more embodiments, a display device may include: a substrate; a first semiconductor layer, which is arranged on the substrate and includes a first active portion, a second active portion, and a first doped portion between the first active portion and the second active portion; a first conductive layer, which is arranged on the first semiconductor layer and includes a first conductive pattern overlapping the first active portion; a second conductive layer, which is arranged on the first conductive layer and includes a second conductive pattern and a third conductive pattern, the second conductive pattern overlapping the first conductive pattern, and the third conductive pattern is connected to the first doped portion through a first contact hole exposing a portion of the first doped portion; a second semiconductor layer, which is arranged on the second conductive layer and includes an upper first active portion and a second doped portion extending from the upper first active portion; a third conductive layer, which is arranged on the second semiconductor layer and includes a first conductive line overlapping the upper first active portion; and a fourth conductive layer, which is arranged on the third conductive layer and includes a fourth conductive pattern electrically connecting the third conductive pattern to the second doped portion.

[0008] The first semiconductor layer may further include a fourth active portion and a third doped portion between the first and fourth active portions, and the first conductive layer may further include a second conductive line extending in the first direction and overlapping the second and fourth active portions.

[0009] The first semiconductor layer may further include a fifth active portion extending from the third doped portion to be farther from the fourth active portion, and the first conductive layer may further include a third conductive line extending in the first direction and overlapping the fifth active portion.

[0010] The first semiconductor layer may further include a fourth doped portion extending from the fifth active portion to be further away from the third doped portion, and the fourth doped portion may be electrically connected to the data line.

[0011] The second conductive layer may further include a fourth conductive line extending in the first direction and overlapping the upper first active portion.

[0012] The first conductive line and the fourth conductive line may overlap each other.

[0013] The first semiconductor layer may further include a sixth active portion and a fifth doped portion and a sixth doped portion respectively arranged at both sides of the sixth active portion, and

[0014] The first conductive layer may further include a fifth conductive line extending in the first direction and overlapping the sixth active portion.

[0015] The second semiconductor layer may further include an upper second active portion and a seventh doped portion between the upper first active portion and the upper second active portion, and the third conductive layer may further include a sixth conductive line extending in the first direction and overlapping the upper second active portion.

[0016] The first semiconductor layer may include a silicon semiconductor material, and the second semiconductor layer may include an oxide-based semiconductor material.

[0017] The fourth conductive pattern may be connected to the third conductive pattern through a second contact hole exposing a portion of the third conductive pattern, the first contact hole may be spaced apart from the second contact hole by a first distance, and the first distance may be in a range of about 1 μm to about 2 μm.

[0018] According to one or more embodiments, a method for manufacturing a display device may include: forming a first semiconductor layer on a substrate; forming a first insulating layer on the first semiconductor layer; forming a first conductive layer including a first gate electrode overlapping the first semiconductor layer on the first insulating layer and doping the first semiconductor layer; forming a second insulating layer on the first conductive layer; forming a first contact hole exposing a portion of the first semiconductor layer, and heat treating the first semiconductor layer; forming a second conductive layer including a capacitor electrode overlapping the first gate electrode and a first connecting electrode overlapping the first contact hole on the second insulating layer; forming a third insulating layer on the second conductive layer; and forming a second semiconductor layer on the third insulating layer.

[0019] The first semiconductor layer may include a first active region and a first doped region and a second doped region respectively arranged on both sides of the first active region, wherein the first active region may overlap with the first gate electrode, and during the formation of the first contact hole and the heat treatment of the first semiconductor layer, the first contact hole may be formed to overlap with the first doped region.

[0020] The method may also include: forming a fourth insulating layer on the second semiconductor layer; forming a third conductive layer including a second gate electrode overlapping the second semiconductor layer on the fourth insulating layer; forming a fifth insulating layer on the third conductive layer; forming a second contact hole, a third contact hole and a fourth contact hole, the second contact hole exposing a portion of the first connection electrode, the third contact hole exposing a portion of the second doping region of the first semiconductor layer, and the fourth contact hole exposing a portion of the second semiconductor layer; and forming a fourth conductive layer including a first source / drain electrode overlapping the second contact hole, a second source / drain electrode overlapping the third contact hole, and a third source / drain electrode overlapping the fourth contact hole on the fifth insulating layer.

[0021] The forming of the second contact hole, the third contact hole, and the fourth contact hole may include simultaneously forming the second contact hole and the third contact hole, and forming the fourth contact hole after the forming of the second contact hole and the third contact hole.

[0022] The second contact hole, the third contact hole, and the fourth contact hole may be formed simultaneously.

[0023] The first contact hole may be spaced apart from the second contact hole by a first distance, and the first distance may be about 1 μm to about 2 μm.

[0024] In the formation of the first contact hole and the heat treatment of the first semiconductor layer, a fifth contact hole overlapping the second doping region may be formed simultaneously with the first contact hole, and in the formation of the second conductive layer, the second conductive layer may further include a second connecting electrode overlapping the fifth contact hole.

[0025] The method may also include: forming a fourth insulating layer covering the second semiconductor layer; forming a third conductive layer including a second gate electrode overlapping the second semiconductor layer on the fourth insulating layer; forming a fifth insulating layer on the third conductive layer; forming a second contact hole exposing a portion of the first connection electrode, a third contact hole exposing a portion of the second connection electrode, and a fourth contact hole exposing a portion of the second semiconductor layer; and forming a fourth conductive layer including a first source / drain electrode overlapping the second contact hole, a second source / drain electrode overlapping the third contact hole, and a third source / drain electrode overlapping the fourth contact hole on the fifth insulating layer.

[0026] The second contact hole, the third contact hole, and the fourth contact hole may be formed simultaneously.

[0027] The first semiconductor layer may include a silicon semiconductor material, and the second semiconductor layer may include an oxide-based semiconductor material.

[0028] These and / or other aspects will become apparent and more readily appreciated from the following detailed description of the embodiments, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects, features and advantages of certain embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 is a schematic plan view of a display device according to an embodiment;

[0031] Figure 2 is a schematic diagram of an equivalent circuit of a pixel of a display device according to an embodiment;

[0032] Figure 3 is a schematic cross-sectional view of a display device according to an embodiment;

[0033] Figure 4 is a schematic cross-sectional view of a display device according to another embodiment;

[0034] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E and Fig. 5F is a schematic cross-sectional view for explaining some operations of a method of manufacturing a display device according to an embodiment;

[0035] Figure 6 It is shown Figure 1 A schematic layout diagram of a display device according to an embodiment of the present invention in an area B;

[0036] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 7F and Figure 7G It is shown Figure 1 A schematic layout diagram of each layer of a display device according to an embodiment of the present invention in a region B; and

[0037] Figure 8 is a schematic cross-sectional view of a display device according to an embodiment. DETAILED DESCRIPTION

[0038] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words as non-limiting examples of the apparatus or method disclosed herein. However, it is apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments do not have to be exclusive, nor do they have to limit the present disclosure. For example, the specific shape, configuration, and characteristics of an embodiment can be used or implemented in another embodiment.

[0039] Unless otherwise specified, the embodiments shown should be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments, etc. (hereinafter, individually or collectively referred to as "elements") can be combined, separated, interchanged and / or rearranged without departing from the scope of the present invention.

[0040] The use of cross hatching and / or shading in the drawings is generally provided to make the boundaries between adjacent elements clear. Therefore, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material performance, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, performance, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the embodiment can be implemented differently, a specific process sequence can be performed in a different order from that described. For example, two processes described in succession can be performed substantially simultaneously, or in an order opposite to that described. In addition, the same reference numerals refer to the same elements.

[0041] When an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, the element or layer may be directly on, connected to or coupled to the other element or layer, or there may be an intervening element or intervening layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intervening element or intervening layer. For this reason, the term "connection" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without an intervening element. The x-axis direction, the y-axis direction, and the z-axis direction are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-axis direction, the y-axis direction, and the z-axis direction may be perpendicular to each other, or may represent different orientations that are not perpendicular to each other. For the purposes of this disclosure, "at least one of A and B" may be understood as only A, only B, or any combination of A and B. Furthermore, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0042] Although the terms "first" and "second" etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0043] Spatially relative terms (such as "under", "below", "below", "down", "above", "up", "above", "higher", and "side" (e.g., as in "sidewall"), etc.) may be used herein for descriptive purposes and, thereby, to describe the relationship of one element to another element (or elements) as shown in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is turned over, then an element described as "under" or "under" other elements or features will then be oriented "above" the other elements or features. Therefore, the term "under" can cover both above and below orientations. In addition, the device can be oriented in other ways (e.g., rotated 90 degrees or at other orientations) and, therefore, the spatially relative terms used herein should be interpreted accordingly.

[0044] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the context clearly states otherwise, the singular forms "one", "one (kind / person)" and "the (the)" are also intended to include plural forms. In addition, when used in this specification, the term "comprises, comprising, includes and / or including" indicates the presence of stated features, integral bodies, steps, operations, elements, components and / or their groups, but does not exclude the presence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or their groups. It is also noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms, rather than as terms of degree, and are therefore used to explain the inherent deviations in the measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0045] Various embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic illustrations of embodiments and / or intermediate structures. Therefore, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, the embodiments disclosed herein should not necessarily be interpreted as limited to the specific illustrated shapes of the regions, but should include shape deviations due to, for example, manufacturing. In this way, the regions shown in the drawings may be schematic in nature and the shapes of these regions may not reflect the actual shapes of the regions of the device, and therefore are not necessarily intended to be limiting.

[0046] According to the practice in the art, some embodiments are described and shown in the accompanying drawings from the perspective of functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connections, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also considered that each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and associated circuits) for performing other functions. In addition, without departing from the scope of the present invention, each block, unit and / or module of some embodiments can be physically divided into two or more interacting and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the invention.

[0047] In the description, the term "about" or "approximately" includes the stated value and may indicate a range of allowable deviations relative to the stated value determined by taking into account errors associated with a manufacturing method or a measurement method. As an example, in the description, the term "about" may mean within ±20%, ±10%, or ±5% of a specified value.

[0048] Where a particular embodiment may be implemented differently, a particular process sequence may be performed in a different order than described. As an example, two processes described in succession may be performed substantially simultaneously and in a reverse order.

[0049] For the convenience of explanation, the size of the elements in the drawings may be exaggerated or reduced. As an example, for the convenience of description, the size and thickness of each element shown in the drawings are arbitrarily represented, and therefore, the present disclosure is not necessarily limited thereto.

[0050] Figure 1 is a schematic plan view of a display device 10 according to the embodiment.

[0051] refer to Figure 1 , the display device 10 may include a display area DA displaying an image and a peripheral area PA arranged around the display area DA.

[0052] The display device 10 may include a substrate 100. In the description, in the case where the substrate 100 includes a display area DA and a peripheral area PA, it means that the substrate 100 may include a region overlapping the display area DA and a region overlapping the peripheral area PA.

[0053] The substrate 100 may include a rigid material (such as a glass material, a ceramic material, a metal material, a plastic material), or a flexible material or a bendable material. When the substrate 100 is flexible or bendable, the substrate 100 may include a polymer resin including polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP).

[0054] A plurality of pixels P each including a display element such as a light emitting diode may be arranged in the display area DA of the substrate 100. The light emitting diode may include an organic light emitting diode including an organic emission layer. In another example, the light emitting diode may be an inorganic light emitting diode including an inorganic emission layer. The size of the light emitting diode may be micrometer-scale or nanometer-scale.

[0055] Each pixel P may include a pixel circuit electrically connected to a light emitting diode. The pixel circuit may include a transistor and a storage capacitor. A plurality of pixel circuits may be electrically connected to a peripheral circuit arranged in the peripheral area PA. As an example, the pixel circuit may be connected to a scan line SL, a data line DL intersecting the scan line SL, and a drive voltage line PL. The scan line SL may extend in a first direction (e.g., an x-axis direction), and the data line DL and the drive voltage line PL may extend in a second direction (e.g., a y-axis direction) intersecting the first direction (e.g., the x-axis direction).

[0056] The display device 10 can display an image by using light emitted from the pixels P. Each pixel P can emit, for example, red light, green light, or blue light. The pixels P can be arranged in various configurations (such as stripe configuration, configuration and mosaic configuration, etc.) are arranged in the display area DA to display an image.

[0057] The peripheral area PA may be an area in which no pixels P are arranged and may be an area in which no image is displayed. The peripheral area PA may be arranged outside the display area DA to surround the display area DA. A printed circuit board and terminal components, etc. may be arranged in the peripheral area PA. The printed circuit board may include a built-in driving circuit, a power line, and a driving circuit for driving the pixels P, and a driver integrated circuit (IC) may be connected to the terminal components.

[0058] In an embodiment, the display area DA may have a rectangular shape in which the length in the first direction (e.g., the x-axis direction) is smaller than the length in the second direction (e.g., the y-axis direction). In another embodiment, the display area DA may be formed in a polygonal shape (such as a triangle, a pentagon, and a hexagon, etc.), a circular shape, an elliptical shape, or an irregular shape, etc. The display area DA may have rounded corners.

[0059] The display device 10 may be a device for displaying a moving image or a still image, and may include a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer, a mobile communication terminal, an electronic notepad, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra-mobile personal computer (UMPC). In another example, the display device 10 may be used as a display screen for various products including a television, a notebook computer, a monitor, a billboard, and an Internet of Things (IoT) device. For example, the display device 10 according to the embodiment may be used in a wearable device including a smart watch, a watch phone, a glasses-type display, and a head-mounted display (HMD). For example, the display device 10 according to the embodiment may be used as an instrument panel for a car, a central dashboard for a car, or a central information display (CID) arranged on the dashboard of a car, an indoor rearview mirror display instead of a side mirror of a car, and a display arranged on the back of the front seat of a car as entertainment for the rear seat.

[0060] Figure 2 is a display device 10 according to an embodiment (see Figure 1 ) is a schematic diagram of the equivalent circuit of a pixel P.

[0061] refer to Figure 2 , the pixel P may include an organic light emitting diode OLED as a display element and a pixel circuit PC electrically connected to the organic light emitting diode OLED. The pixel circuit PC may include seven transistors and at least one capacitor. As an example, the pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a storage capacitor Cst, and a boost capacitor Cbt. In another embodiment, the pixel circuit PC may not include the boost capacitor Cbt.

[0062] Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, the storage capacitor Cst, and the boost capacitor Cbt may be connected to a signal line, a first initialization voltage line VIL1, a second initialization voltage line VIL2, a drive voltage line PL, and a common voltage line VSL. The signal line may include a data line DL, a first scan line GWL, a second scan line GCL, a third scan line GIL, a fourth scan line GBL, and an emission control line EML. The first scan line GWL may transmit a first scan signal GW, the second scan line GCL may transmit a second scan signal GC, the third scan line GIL may transmit a third scan signal GI, the fourth scan line GBL may transmit a fourth scan signal GB, and the emission control line EML may transmit an emission control signal EM. In an embodiment, the signal line, the first initialization voltage line VIL1, the second initialization voltage line VIL2, the drive voltage line PL, and the common voltage line VSL may be shared by adjacent pixel circuits.

[0063] The driving voltage line PL may transmit a first power voltage ELVDD to the first transistor T1. The first initialization voltage line VIL1 may transmit a first initialization voltage Vint to the pixel circuit PC. The first initialization voltage Vint may initialize the first transistor T1. The second initialization voltage line VIL2 may transmit a second initialization voltage Vaint to the pixel circuit PC. The second initialization voltage Vaint may initialize the organic light emitting diode OLED. The common voltage line VSL may transmit a second power voltage ELVSS to an opposite electrode (e.g., a cathode) of the organic light emitting diode OLED.

[0064] Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may include a gate electrode, a first terminal and a second terminal, and one of the first terminal and the second terminal may be used as a source, and the other of the first terminal and the second terminal may be used as a drain.

[0065] The first transistor T1 may be a driving transistor. The first gate electrode of the first transistor T1 may be connected to the storage capacitor Cst, the first terminal of the first transistor T1 may be electrically connected to the driving voltage line PL through the fifth transistor T5, and the second terminal of the first transistor T1 may be electrically connected to the pixel electrode (e.g., anode) of the organic light emitting diode OLED through the sixth transistor T6. The first transistor T1 may supply a driving current I to the organic light emitting diode OLED according to the switching operation of the second transistor T2. d .

[0066] The second transistor T2 may be a data write transistor. The second gate electrode of the second transistor T2 may be connected to the first scan line GWL, the first terminal of the second transistor T2 may be connected to the data line DL, and the second terminal of the second transistor T2 may be connected to the first terminal of the first transistor T1. The second transistor T2 may be turned on according to the first scan signal GW transmitted through the first scan line GWL and may perform a switching operation to transmit the data signal Dm to the first terminal of the first transistor T1. The data signal Dm may be transmitted through the data line DL.

[0067] The third transistor T3 may be a compensation transistor for compensating for the threshold voltage of the first transistor T1. The third gate electrode of the third transistor T3 may be connected to the second scan line GCL. The first terminal of the third transistor T3 may be connected to the first capacitor electrode CE1 of the storage capacitor Cst and the first gate electrode of the first transistor T1 through the node connection line 166. The first terminal of the third transistor T3 may be connected to the fourth transistor T4. The second terminal of the third transistor T3 may be connected to the second terminal of the first transistor T1 and electrically connected to the pixel electrode (e.g., anode) of the organic light emitting diode OLED through the sixth transistor T6. The third transistor T3 may be turned on according to the second scan signal GC transmitted through the second scan line GCL, and the first transistor T1 may be diode-connected by electrically connecting the first gate electrode of the first transistor T1 to the second terminal (e.g., drain electrode).

[0068] The fourth transistor T4 may be a first initialization transistor that initializes the first gate electrode of the first transistor T1. The fourth gate electrode of the fourth transistor T4 may be connected to the third scan line GIL. The first terminal of the fourth transistor T4 may be connected to the first initialization voltage line VIL1. The second terminal of the fourth transistor T4 may be connected to the first capacitor electrode CE1 of the storage capacitor Cst, the first terminal of the third transistor T3, and the first gate electrode of the first transistor T1. The fourth transistor T4 may be turned on according to the third scan signal GI transmitted through the third scan line GIL and may perform an initialization operation to initialize the voltage of the first gate electrode of the first transistor T1 by transmitting the first initialization voltage Vint to the first gate electrode of the first transistor T1.

[0069] The fifth transistor T5 may be an operation control transistor. A fifth gate electrode of the fifth transistor T5 may be connected to the emission control line EML, a first terminal of the fifth transistor T5 may be connected to the driving voltage line PL, and a second terminal of the fifth transistor T5 may be connected to the first terminal of the first transistor T1 and the second terminal of the second transistor T2.

[0070] The sixth transistor T6 may be an emission control transistor. A sixth gate electrode of the sixth transistor T6 may be connected to the emission control line EML, a first terminal of the sixth transistor T6 may be connected to the second terminal of the first transistor T1 and the second terminal of the third transistor T3, and a second terminal of the sixth transistor T6 may be electrically connected to the second terminal of the seventh transistor T7 and a pixel electrode (e.g., an anode) of the organic light emitting diode OLED.

[0071] The fifth transistor T5 and the sixth transistor T6 may be turned on at the same time according to the emission control signal EM transmitted through the emission control line EML, the first power voltage ELVDD may be transmitted to the organic light emitting diode OLED, and the driving current I d It can flow through an organic light emitting diode OLED.

[0072] The seventh transistor T7 may be a second initialization transistor for initializing a pixel electrode (e.g., an anode) of the organic light emitting diode OLED. The seventh gate electrode of the seventh transistor T7 may be connected to the fourth scan line GBL. The first terminal of the seventh transistor T7 may be connected to the second initialization voltage line VIL2. The second terminal of the seventh transistor T7 may be connected to the second terminal of the sixth transistor T6 and the pixel electrode (e.g., an anode) of the organic light emitting diode OLED. The seventh transistor T7 may be turned on according to the fourth scan signal GB transmitted through the fourth scan line GBL, and the pixel electrode (e.g., an anode) of the organic light emitting diode OLED is initialized by transmitting the second initialization voltage Vaint to the pixel electrode (e.g., an anode) of the organic light emitting diode OLED.

[0073] The fourth scan signal GB may be substantially synchronized with the first scan signal GW. In an embodiment, the fourth scan signal GB may be substantially synchronized with the first scan signal GW of the pixels in the next row. As an example, the fourth scan line GBL may be substantially the same as the first scan line GWL of the pixels in the next row.

[0074] The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor electrode CE1 of the storage capacitor Cst may be connected to the first gate electrode of the first transistor T1, and the second capacitor electrode CE2 of the storage capacitor Cst may be connected to the driving voltage line PL. In an embodiment, the first capacitor electrode CE1 of the storage capacitor Cst may be integral with the first gate electrode of the first transistor T1. The storage capacitor Cst may store a charge corresponding to a difference between a voltage of the first gate electrode of the first transistor T1 and the first power voltage ELVDD.

[0075] The boost capacitor Cbt may include a third capacitor electrode CE3 and a fourth capacitor electrode CE4. The third capacitor electrode CE3 may be connected to the second gate electrode of the second transistor T2 and the first scan line GWL, and the fourth capacitor electrode CE4 may be connected to the first terminal of the third transistor T3 and the node connection line 166. In the case where the first scan signal GW supplied to the first scan line GWL is a cut-off voltage, the boost capacitor Cbt may increase the voltage of the first node N1 to clearly express a black grayscale. The first node N1 may be a region where the first gate electrode of the first transistor T1, the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the fourth capacitor electrode CE4 of the boost capacitor Cbt are connected to each other.

[0076] A pixel electrode (e.g., an anode) of the organic light emitting diode OLED may be electrically connected to the first transistor T1 through the sixth transistor T6. An opposite electrode (e.g., a cathode) of the organic light emitting diode OLED may be electrically connected to a common voltage line VSL and may receive a voltage corresponding to the second power voltage ELVSS through the common voltage line VSL.

[0077] In an embodiment, some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be n-channel metal oxide semiconductor field effect transistors (MOSFETs), and the rest of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be p-channel MOSFETs. Figure 2 As shown in , the third transistor T3 and the fourth transistor T4 may be n-channel MOSFETs, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be p-channel MOSFETs.

[0078] A transistor including a silicon semiconductor layer (or a silicon-like semiconductor layer) may have high electron mobility and excellent reliability. Therefore, since the first transistor T1 directly affecting the brightness of the organic light emitting diode OLED includes a silicon semiconductor layer, a high-resolution display device 10 may be implemented.

[0079] The transistor including the oxide semiconductor layer can have a low off current and can be driven at a low frequency. Therefore, since at least one of the remaining second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7 except the first transistor T1 includes an oxide semiconductor layer, the power consumption of the display device 10 can be reduced.

[0080] Figure 3 is a schematic cross-sectional view of a display device 10 according to the embodiment. Figure 4 is a schematic cross-sectional view of a display device 10 according to another embodiment. Figure 3 Shown along Figure 1 The display device 10 is taken along the line AA' in FIG. Figure 1 An embodiment of a cross section of a display device 10 is shown in FIG. Figure 4 Shown along Figure 1 The display device 10 is taken along the line AA' in FIG. Figure 1 A modified embodiment of a cross section of the display device 10 is shown in FIG.

[0081] refer to Figure 3 The substrate 100 may include a rigid material (such as a glass material, a ceramic material, a metal material, a plastic material), or a flexible material or a bendable material.

[0082] The substrate 100 may have a single layer structure or a multilayer structure formed of the above-mentioned materials, and in the case of a multilayer structure, may further include an inorganic layer. As an example, the substrate 100 may include a first organic matrix layer 101, a first inorganic barrier layer 103, a second organic matrix layer 105, and a second inorganic barrier layer 107. The first organic matrix layer 101 and the second organic matrix layer 105 may each include a polymer resin. The first inorganic barrier layer 103 and the second inorganic barrier layer 107 may be used as a barrier layer to prevent penetration of external foreign matter, and may include a single layer or multiple layers containing an inorganic insulating material such as silicon nitride and / or silicon oxide.

[0083] The bottom metal layer BM may be disposed between the second organic matrix layer 105 and the second inorganic barrier layer 107. In another embodiment, the bottom metal layer BM may be disposed between the second inorganic barrier layer 107 and the buffer layer 201. The bottom metal layer BM may include at least one material of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In an embodiment, the bottom metal layer BM may have a single layer of molybdenum, a double layer of molybdenum and titanium, or a triple layer of a titanium layer, an aluminum layer, and a titanium layer.

[0084] The buffer layer 201 may be disposed on the bottom metal layer BM. The buffer layer 201 may include an inorganic insulating layer including an inorganic insulating material (such as silicon nitride and / or silicon oxide) and include a single-layer structure or a multi-layer structure including the above-mentioned material. The buffer layer 201 may increase the flatness of the upper surface of the substrate 100 and prevent or reduce impurities from the substrate 100, etc. from penetrating (or permeating) into the semiconductor layer.

[0085] The silicon-based semiconductor layer of the silicon-based transistor may be disposed on the buffer layer 201. Figure 3 The first active region A1, the first source region S1, and the first drain region D1 of the first thin film transistor TFT1 corresponding to a portion of the silicon-based semiconductor layer are shown. The first thin film transistor TFT1 may be used as a driving transistor and may have a first active region A1, a first source region S1, and a first drain region D1 corresponding to a portion of the silicon-based semiconductor layer. Figure 2 The configuration of the first transistor T1 is described. The first source region S1 and the first drain region D1 may be disposed at both sides (eg, opposite sides) of the first active region A1 and may be doped regions doped with impurities.

[0086] The first gate insulating layer 203 (or first insulating layer) may be disposed on the silicon-based semiconductor layer. The first gate insulating layer 203 may include an inorganic insulating layer including an inorganic insulating material (such as silicon oxide, silicon nitride and / or silicon oxynitride), and may include a single layer structure or a multilayer structure including the above materials.

[0087] The first gate electrode G1 and / or the first capacitor electrode CE1 may be disposed on the first gate insulating layer 203. The first gate electrode G1 may be arranged to overlap with the first active region A1. In the doping process of forming the first source region S1 and the first drain region D1, the first active region A1 overlapping with the first gate electrode G1 may not be doped. In an embodiment, the first gate electrode G1 and / or the first capacitor electrode CE1 may be integral with each other. The first gate electrode G1 and / or the first capacitor electrode CE1 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and include a single layer or multiple layers containing the above materials.

[0088] The second gate insulating layer 205 (or second insulating layer) may be disposed on the first gate electrode G1 and / or the first capacitor electrode CE1. The second gate insulating layer 205 may include an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may include a single layer structure or a multilayer structure including the above materials.

[0089] The second capacitor electrode CE2, the first connection electrode CM1, and the second lower gate electrode G2b may be disposed on the second gate insulating layer 205. The second capacitor electrode CE2 may be arranged to overlap the first gate electrode G1 and / or the first capacitor electrode CE1. The first capacitor electrode CE1 and the second capacitor electrode CE2 may form a storage capacitor Cst.

[0090] The first connection electrode CM1 may be connected (e.g., electrically connected) to the first source region S1 through the first contact hole. As an example, the first connection electrode CM1 may contact (e.g., directly contact) the first source region S1 through the first contact hole that passes through the first gate insulating layer 203 and the second gate insulating layer 205 and exposes a portion of the first source region S1 of the first thin film transistor TFT1.

[0091] The second capacitor electrode CE2, the first connection electrode CM1, and the second lower gate electrode G2b may each include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and include a single layer or a plurality of layers containing the above materials.

[0092] The first interlayer insulating layer 207 (or the third insulating layer) may be disposed on the second capacitor electrode CE2, the first connection electrode CM1, and the second lower gate electrode G2b. The first interlayer insulating layer 207 may include an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may include a single-layer structure or a multi-layer structure including the above-mentioned material.

[0093] An oxide-based semiconductor layer may be provided on the first interlayer insulating layer 207. For this, Figure 3 The second active region A2, the second source region S2, and the second drain region D2 of the second thin film transistor TFT2 corresponding to a portion of the oxide-based semiconductor layer are shown. The second thin film transistor TFT2 may be a portion corresponding to the reference Figure 2 The second source region S2 and the second drain region D2 may be disposed on both sides (eg, opposite sides) of the second active region A2 and may be doped regions doped with impurities. The second active region A2 may be arranged to overlap with the second lower gate electrode G2b.

[0094] The third gate insulating layer 209 (or the fourth insulating layer) may be disposed on the oxide-based semiconductor layer. Figure 3 2 shows that the third gate insulating layer 209 is formed to completely cover the substrate 100, but the embodiment is not limited thereto. In the embodiment, the third gate insulating layer 209 may be disposed only between the second upper gate electrode G2a and the second active region A2.

[0095] The third gate insulating layer 209 may include an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and include a single-layer structure or a multi-layer structure including the above-mentioned materials.

[0096] The second upper gate electrode G2a may be disposed on the third gate insulating layer 209. The second upper gate electrode G2a may be arranged to overlap with the second active region A2. The second upper gate electrode G2a and the second lower gate electrode G2b may be disposed to face each other, and the second active region A2 is between the second upper gate electrode G2a and the second lower gate electrode G2b, and the width of the second upper gate electrode G2a may be smaller than the width of the second lower gate electrode G2b. In an embodiment, one of the second upper gate electrode G2a and the second lower gate electrode G2b may be omitted.

[0097] The second upper gate electrode G2a may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and include a single layer or multiple layers containing the above materials.

[0098] The second interlayer insulating layer 211 (or the fifth insulating layer) may be disposed on the second upper gate electrode G2a. The second interlayer insulating layer 211 may include an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may include a single layer structure or a multilayer structure including the above materials.

[0099] The source / drain electrodes may be disposed on the second interlayer insulating layer 211. The source / drain electrodes may be connected (e.g., electrically connected) to a portion of the silicon-based semiconductor layer and / or a portion of the oxide-based semiconductor layer. The source / drain electrodes may include: a first source electrode SE1 connected (e.g., electrically connected) to a first source region S1 of a first thin film transistor TFT1; a first drain electrode DE1 connected (e.g., electrically connected) to a first drain region D1 of the first thin film transistor TFT1; a second source electrode SE2 connected (e.g., electrically connected) to a second source region S2 of a second thin film transistor TFT2; and a second drain electrode DE2 connected (e.g., electrically connected) to a second drain region D2 of a second thin film transistor TFT2. For example, the source electrode of one thin film transistor may be used as the drain electrode of an adjacent thin film transistor. As an example, the first source electrode SE1 of the first thin film transistor TFT1 may be used as the drain electrode of another thin film transistor that shares the first source region S1 with the first thin film transistor TFT1. In an embodiment, at least one of the first source electrode SE1 , the first drain electrode DE1 , the second source electrode SE2 , and the second drain electrode DE2 may be omitted.

[0100] The first source electrode SE1 of the first thin film transistor TFT1 may be connected (e.g., electrically connected) to the first source region S1 of the first thin film transistor TFT1 through the first connection electrode CM1. As an example, the first source electrode SE1 may contact (e.g., directly contact) the first connection electrode CM1 through a second contact hole that passes through the first interlayer insulating layer 207, the third gate insulating layer 209, and the second interlayer insulating layer 211 and exposes a portion of the first connection electrode CM1.

[0101] A first contact hole for electrically connecting the first connection electrode CM1 to the first source region S1 and a second contact hole for electrically connecting the first source electrode SE1 to the first connection electrode CM1 may be spaced apart from each other by a first distance d1. When viewed in a direction perpendicular to the substrate 100 (e.g., in a plan view), the first distance d1 may be the minimum distance between the first contact hole and the second contact hole on a straight virtual line. The first distance d1 may be about 1.0 μm to about 2.0 μm. In an embodiment, the first distance d1 may be about 1.8 μm. In the case where the first distance d1 is less than about 1.0 μm, defects due to alignment errors may occur during the manufacturing process of the contact hole, and in the case where the first distance d1 is greater than about 2.0 μm, the area of ​​the pixel circuit may increase and the resolution of the display device may decrease.

[0102] The source / drain electrodes may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and include a single layer or multiple layers containing the above materials.

[0103] The first planarization layer 213 may be disposed on the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2. The driving voltage line PL may be disposed on the first planarization layer 213. The driving voltage line PL may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), titanium (Ti), and / or tungsten (W). In an embodiment, the driving voltage line PL may have a three-layer structure of a titanium layer, an aluminum layer, and a titanium layer.

[0104] The second planarization layer 215 may be disposed on the driving voltage line PL. The first planarization layer 213 and the second planarization layer 215 may each include an organic insulating material such as benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0105] The organic light emitting diode OLED may be disposed on the second planarization layer 215. The organic light emitting diode OLED may include a pixel electrode 310 on the second planarization layer 215, an opposite electrode 330, and an intermediate layer 320 between the pixel electrode 310 and the opposite electrode 330.

[0106] The pixel electrode 310 may be a reflective electrode. In an embodiment, the pixel electrode 310 may include a reflective layer and a transparent electrode layer or a semi-transparent electrode layer on the reflective layer, and the reflective layer includes silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. The transparent electrode layer or the semi-transparent electrode layer may include at least one of indium tin oxide, indium zinc oxide, zinc oxide, indium oxide, indium gallium oxide and aluminum zinc oxide. In an embodiment, the pixel electrode 310 may have a three-layer structure of an indium tin oxide (ITO) layer, an Ag layer and an ITO layer.

[0107] The pixel defining layer PDL may be disposed on the pixel electrode 310 to cover the edge portion of the pixel electrode 310. The pixel defining layer PDL may define an opening that exposes a portion of the upper surface of each of the plurality of pixel electrodes 310. The opening of the pixel defining layer PDL may define an emission region of the organic light emitting diode OLED. The pixel defining layer PDL may cover the edge portion of the pixel electrode 310 and prevent arcing, etc. from occurring at the edge portion of the pixel electrode 310 by increasing the distance between the edge portion of the pixel electrode 310 and the edge portion of the opposing electrode 330. The pixel defining layer PDL may be formed by spin coating, etc., using an organic insulating material such as a polyimide resin, a polyamide resin, an acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), and a phenolic resin, etc.

[0108] In an embodiment, the pixel defining layer PDL may include a light-blocking material and be formed in black. The light-blocking material may include carbon black, nanotubes, a resin or paste containing a black dye, metal particles (e.g., nickel particles, aluminum particles, molybdenum particles, and alloy particles thereof), metal oxide particles (e.g., chromium oxide particles), or metal nitride particles (e.g., chromium nitride particles). In the case where the pixel defining layer PDL includes a light-blocking material, external light reflection caused by a metal structure arranged below the pixel defining layer PDL may be reduced.

[0109] The intermediate layer 320 may include an emission layer patterned to correspond to the pixel electrode 310. The emission layer may include a low molecular weight organic material or a polymer organic material. The first common layer and / or the second common layer may be disposed below and above the emission layer. The first common layer may be disposed below the emission layer and may include, for example, a hole transport layer (HTL), or include an HTL and a hole injection layer (HIL). The second common layer may be disposed above the emission layer and may include an electron transport layer (ETL) and / or an electron injection layer (EIL). In an embodiment, a second common layer may not be provided. The emission layer may be patterned to correspond to the pixel electrode 310, and the first common layer and the second common layer may be common layers formed integrally throughout the organic light emitting diode OLED.

[0110] The opposite electrode 330 may be a cathode as an electron injection electrode. A metal, an alloy, a conductive compound, or any combination thereof having a low work function may be used as the opposite electrode 330. The opposite electrode 330 may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0111] The counter electrode 330 may include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum lithium (Al-Li), calcium (Ca), magnesium indium (Mg-In), magnesium silver (Mg-Ag), ytterbium (Yb), silver ytterbium (Ag-Yb), ITO, indium zinc oxide (IZO), or any combination thereof. The counter electrode 330 may have a single-layer structure having a single layer, or a multi-layer structure having a plurality of layers.

[0112] For example, the pixel electrode 310 may be formed for each organic light emitting diode OLED, and the opposing electrode 330 may be formed integrally throughout the organic light emitting diode OLED. For example, a plurality of organic light emitting diodes OLED may share the opposing electrode 330.

[0113] In an embodiment, a coating layer may also be provided on the relative electrode 330. The coating layer may improve the external light emission efficiency of the organic light emitting element based on the principle of constructive interference. The coating layer may include a material having a refractive index of about 1.6 (at about 589 nm). The coating layer may be an organic coating layer including an organic material, an inorganic coating layer including an inorganic material, or a composite coating layer including an organic material and an inorganic material.

[0114] The encapsulation layer may be disposed on the organic light emitting diode OLED. The encapsulation layer may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. The inorganic encapsulation layer may include silicon oxide, silicon nitride and / or silicon oxynitride, and the organic encapsulation layer may include an organic insulating material.

[0115] Before forming the first connection electrode CM1 and the second connection electrode CM2, the display device 10 according to the embodiment may be manufactured by heat-treating the silicon-based semiconductor layer (e.g., the first semiconductor layer) after forming the first contact hole. The characteristics of the first thin film transistor TFT1 may be controlled by removing hydrogen atoms coupled to dangling bonds in a region adjacent to the first contact hole through heat treatment. As an example, the driving range of the gate voltage of the first thin film transistor TFT1 may be improved through heat treatment.

[0116] In the case where the oxide-based semiconductor layer is exposed to a heat treatment process, hydrogen atoms may penetrate the oxide-based semiconductor layer, and the threshold voltage of the second thin film transistor TFT2 may shift (shift) in the negative direction. Therefore, in order to prevent the threshold voltage of the second thin film transistor TFT2 from shifting (or shifting) due to the heat treatment process, before forming the oxide-based semiconductor layer, the display device 10 according to the embodiment may form a first contact hole through the first gate insulating layer 203 and the second gate insulating layer 205 and then perform heat treatment on the first source region S1 through the first contact hole. Therefore, the second thin film transistor TFT2 may be formed to have a thickness of 30 cm 2 / V·s or more high mobility.

[0117] Despite Figure 3 2 shows that the first connection electrode CM1 is formed on the first source region S1 of the first thin film transistor TFT1, but the embodiment is not limited thereto. The first connection electrode CM1 may contact (e.g., directly contact) the first drain region D1 through a contact hole that passes through the first gate insulating layer 203 and the second gate insulating layer 205 and exposes a portion of the first drain region D1 of the first thin film transistor TFT1. For example, the first source electrode SE1 may be connected (e.g., electrically connected) to the first source region S1 of the first thin film transistor TFT1, and the first drain electrode DE1 may be connected (e.g., electrically connected) to the first drain region D1 through the first connection electrode CM1.

[0118] refer to Figure 4 , the second connection electrode CM2 may also be disposed between the second gate insulating layer 205 and the first interlayer insulating layer 207 of the display device 10. The second connection electrode CM2 may be connected (e.g., electrically connected) to the first drain region D1 through a third contact hole. As an example, the second connection electrode CM2 may be in contact (e.g., directly in contact) with the first drain region D1 through a third contact hole that passes through the first gate insulating layer 203 and the second gate insulating layer 205 and exposes a portion of the first drain region D1 of the first thin film transistor TFT1. The second connection electrode CM2, the second capacitor electrode CE2, the first connection electrode CM1, and the second lower gate electrode G2b may be disposed on the same layer and may include the same material.

[0119] The first drain electrode DE1 of the first thin film transistor TFT1 may be connected (e.g., electrically connected) to the first drain region D1 of the first thin film transistor TFT1 through the second connection electrode CM2. As an example, the first drain electrode DE1 may contact (e.g., directly contact) the second connection electrode CM2 through a fourth contact hole that passes through the first interlayer insulating layer 207, the third gate insulating layer 209, and the second interlayer insulating layer 211 and exposes a portion of the second connection electrode CM2.

[0120] The third contact hole for electrically connecting the second connection electrode CM2 to the first drain region D1 and the fourth contact hole for electrically connecting the first drain electrode DE1 to the second connection electrode CM2 may be spaced apart from each other by a second distance d2. When viewed in a direction perpendicular to the substrate 100, the second distance d2 may be the minimum distance between the third contact hole and the fourth contact hole on a straight virtual line. The second distance d2 may be about 1.0 μm to about 2.0 μm. In an embodiment, the second distance d2 may be about 1.8 μm.

[0121] Before forming the first connection electrode CM1 and the second connection electrode CM2, in the display device 10 according to the embodiment, the first source region S1 and the first drain region D1 may be subjected to heat treatment after forming the first contact hole and the third contact hole. The characteristics of the first thin film transistor TFT1 may be improved by removing hydrogen atoms of dangling bonds coupled to the first source region S1 and the first drain region D1 through the heat treatment. Since the oxide-based semiconductor layer is formed after the heat treatment of the silicon-based semiconductor layer, the threshold voltage transition (or shift) of the second thin film transistor TFT2 due to the heat treatment may be reduced.

[0122] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E and Fig. 5F 2 are schematic cross-sectional views for explaining some operations of a method of manufacturing a display device according to an embodiment.

[0123] refer to Figure 5A , a silicon-based semiconductor layer (or a first semiconductor layer) may be formed on a substrate 100. The substrate 100 may have a single-layer structure or a multi-layer structure. As an example, the substrate 100 may include a first organic matrix layer 101, a first inorganic barrier layer 103, a second organic matrix layer 105, and a second inorganic barrier layer 107.

[0124] In an embodiment, a bottom metal layer BM may be formed between the second organic matrix layer 105 and the second inorganic barrier layer 107. In another embodiment, the bottom metal layer BM may be formed between the second inorganic barrier layer 107 and the buffer layer 201. The bottom metal layer BM may be arranged to overlap the silicon-based semiconductor layer. As an example, when viewed in a direction perpendicular to the substrate 100, the first active region A1 of the silicon-based semiconductor layer may be positioned inside the bottom metal layer BM.

[0125] A first gate insulating layer 203 may be formed on the silicon-based semiconductor layer, and a first conductive layer may be formed on the first gate insulating layer 203. The first conductive layer may include a first gate electrode G1 overlapping the silicon-based semiconductor layer. After forming the first gate electrode G1, a first active region A1, a first source region S1, and a first drain region D1 of the first thin film transistor TFT1 may be formed by doping the silicon-based semiconductor layer. The first active region A1 may be an undoped region disposed below the first gate electrode G1 (e.g., directly below the first gate electrode G1). One of the multiple doped regions formed on both sides (e.g., opposite sides) of the first active region A1 may be the first source region S1, and another of the multiple doped regions may be the first drain region D1.

[0126] A second gate insulating layer 205 may be formed on the first gate electrode G1 .

[0127] refer to Figure 5B , a first contact hole CH1 may be formed through the first gate insulating layer 203 and the second gate insulating layer 205 and expose a portion of the silicon-based semiconductor layer. The exposed portion of the silicon-based semiconductor layer may be a portion of the first source region S1 of the first thin film transistor TFT1. In another embodiment, the first contact hole CH1 may expose a portion of the first drain region D1 of the first thin film transistor TFT1.

[0128] After forming the first contact hole CH1, the silicon-based semiconductor layer may be heat-treated. The heat treatment temperature may be about 280°C to about 370°C. The electrical characteristics of the first thin film transistor TFT1 may be controlled by curing the first active area A1 through the heat treatment and removing hydrogen atoms coupled to the dangling bonds to form the intended defects. As an example, the range of the gate voltage may be improved. The gate voltage may be changed when the current flowing through the first thin film transistor TFT1 is changed from 1pA to about 10nA through the heat treatment.

[0129] refer to Figure 5C , a second conductive layer may be formed on the second gate insulating layer 205. The second conductive layer may include a first connection electrode CM1, a second lower gate electrode G2b, and a second capacitor electrode CE2. The first connection electrode CM1 may be connected to the first contact hole CH1 (see Figure 5B ) overlaps with the first source region S1 and contacts (eg, directly contacts) the first source region S1 through the first contact hole CH1.

[0130] The second capacitor electrode CE2 may overlap the first gate electrode G1. The first gate electrode G1 may be integral with the first capacitor electrode CE1. Therefore, the first capacitor electrode CE1 and the second capacitor electrode CE2 may form a storage capacitor Cst. The storage capacitor Cst may overlap the first active area A1 of the first thin film transistor TFT1.

[0131] refer to Figure 5D , a first interlayer insulating layer 207 may be formed on the second conductive layer, and an oxide-based semiconductor layer (e.g., a second semiconductor layer) may be formed on the first interlayer insulating layer 207. A third gate insulating layer 209 may be formed on the oxide-based semiconductor layer, and a third conductive layer may be formed on the third gate insulating layer 209. The third conductive layer may include a second upper gate electrode G2a overlapping the oxide-based semiconductor layer. A second interlayer insulating layer 211 may be formed on the third conductive layer.

[0132] Despite Figure 5D 100 is shown in FIG. 104 as being formed to completely cover the substrate 100, but the embodiment is not limited thereto. In an embodiment, by forming the second upper gate electrode G2a and then etching a portion of the third gate insulating layer 209, the third gate insulating layer 209 may be disposed only between the second upper gate electrode G2a and the second active region A2 of the oxide-based semiconductor layer.

[0133] After forming the second upper gate electrode G2a, the second active region A2, the second source region S2, and the second drain region D2 of the second thin film transistor TFT2 may be formed by doping the oxide-based semiconductor layer. The second active region A2 may be an undoped region disposed below the second upper gate electrode G2a (e.g., directly below the second upper gate electrode G2a). One of the plurality of doped regions formed on both sides (e.g., opposite sides) of the second active region A2 may be the second source region S2, and another of the plurality of doped regions may be the second drain region D2.

[0134] The second upper gate electrode G2a and the second lower gate electrode G2b may be arranged to face each other, and the second active area A2 of the second thin film transistor TFT2 is located between the second upper gate electrode G2a and the second lower gate electrode G2b. The second thin film transistor TFT2 may have a dual gate electrode structure in which gate electrodes are arranged above and below the second active area A2. In an embodiment, the width of the second lower gate electrode G2b may be greater than the width of the second upper gate electrode G2a.

[0135] A second interlayer insulating layer 211 may be formed, and then a second contact hole CH2 may be formed through the first interlayer insulating layer 207, the third gate insulating layer 209, and the second interlayer insulating layer 211 and exposing a portion of the first connection electrode CM1, and a third contact hole CH3 may be formed through the first gate insulating layer 203, the second gate insulating layer 205, the first interlayer insulating layer 207, the third gate insulating layer 209, and the second interlayer insulating layer 211 and exposing a portion of the first drain region D1 of the first thin film transistor TFT1. In an embodiment, the second contact hole CH2 and the third contact hole CH3 may be formed simultaneously.

[0136] refer to Figure 5E , a fourth contact hole CH4 and a fifth contact hole CH5 that pass through the third gate insulating layer 209 and the second interlayer insulating layer 211 and expose a portion of the oxide-based semiconductor layer may be formed. The fourth contact hole CH4 may expose a portion of the second source region S2 of the second thin film transistor TFT2, and the fifth contact hole CH5 may expose a portion of the second drain region D2 of the second thin film transistor TFT2. For example, in order to reduce defects caused by alignment errors of the contact holes, the first contact hole CH1 (see Figure 5B ) and the second contact hole CH2 (see Figure 5D ) may be formed to be spaced apart from each other. As an example, the distance between the first contact hole CH1 and the second contact hole CH2 may be about 1.0 μm to about 2.0 μm. In an embodiment, the distance between the first contact hole CH1 and the second contact hole CH2 may be about 1.8 μm.

[0137] Despite Figure 5D and Figure 5E 2 shows that the operation of forming the fourth contact hole CH4 and the fifth contact hole CH5 is performed after the operation of forming the second contact hole CH2 and the third contact hole CH3, but the embodiment is not limited thereto. In the embodiment, the second contact hole CH2, the third contact hole CH3, the fourth contact hole CH4, and the fifth contact hole CH5 may be formed simultaneously. In the case where the second contact hole CH2, the third contact hole CH3, the fourth contact hole CH4, and the fifth contact hole CH5 are formed simultaneously, the number of masks required is reduced, and therefore, the manufacturing cost may be reduced.

[0138] refer to Fig. 5F A fourth conductive layer including source / drain electrodes may be formed on the second interlayer insulating layer 211. The source / drain electrodes may include a first source electrode SE1 and a first drain electrode DE1 of the first thin film transistor TFT1, and a second source electrode SE2 and a second drain electrode DE2 of the second thin film transistor TFT2.

[0139] The first source electrode SE1 may contact the second contact hole CH2 (see Figure 5E ) and is connected (eg, electrically connected) to the first connection electrode CM1 through the second contact hole CH2. The first drain electrode DE1 may be connected to the third contact hole CH3 (see Figure 5E ) and is connected (eg, electrically connected) to the first drain region D1 of the first thin film transistor TFT1 through the third contact hole CH3. The second source electrode SE2 may be connected to the fourth contact hole CH4 (see Figure 5E ) and is connected (eg, electrically connected) to the second source region S2 of the second thin film transistor TFT2 through the fourth contact hole CH4. The second drain electrode DE2 may be connected to the fifth contact hole CH5 (see Figure 5E ) overlaps and is connected (eg, electrically connected) to the second drain region D2 of the second thin film transistor TFT2 through the fifth contact hole CH5.

[0140] A first planarization layer 213 may be formed on the fourth conductive layer, and a driving voltage line PL may be formed on the first planarization layer 213. A second planarization layer 215 may be formed on the driving voltage line PL, and an organic light emitting diode OLED and a pixel defining layer PDL may be formed on the second planarization layer 215. The organic light emitting diode OLED may include a pixel electrode 310, an intermediate layer 320, and an opposing electrode 330.

[0141] Despite FIG. 5B to FIG. 5F 1 shows that the first contact hole CH1 is formed to expose the first source region S1 of the first thin film transistor TFT1, but the embodiment is not limited thereto. The first contact hole CH1 may be formed to expose the first drain region D1 of the first thin film transistor TFT1, and, for example, the first connection electrode CM1 overlapping the first contact hole CH1 may be connected (e.g., electrically connected) to the first drain electrode DE1.

[0142] For example, as referenced Figure 4 As described above, when forming the first contact hole CH1 (see Figure 5B ), a sixth contact hole may be formed simultaneously. The sixth contact hole may expose the first drain region D1 of the first thin film transistor TFT1. For example, the second conductive layer may further include a second connection electrode overlapping the sixth contact hole, and the first drain electrode DE1 may be connected (e.g., electrically connected) to the second connection electrode.

[0143] Figure 6 It is shown Figure 1 A schematic layout diagram of a display device 10 according to an embodiment of the present invention is shown in FIG. Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 7F and Figure 7G It is shown Figure 1 A schematic layout diagram of a display device 10 according to an embodiment of the present invention is shown in FIG. Figure 8 is a schematic cross-sectional view of a display device 10 according to the embodiment. Figure 8 Shown along Figure 6 The line C-C' intercepts Figure 6 An embodiment of a cross section of a display device 10 is shown in FIG.

[0144] refer to Figure 6 and FIG. 7A to FIG. 7G , the pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 and a storage capacitor Cst. The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2, and the first capacitor electrode CE1 may be used as a gate electrode of the first transistor T1 (e.g., Figure 3 The first transistor T1 may be a first gate electrode G1 corresponding to the reference Figure 3 The first thin film transistor TFT1 is described as an element. As an example, the first transistor T1 may be a driving transistor.

[0145] Active areas AR1 , AR2 , AR5 , AR6 , and AR7 of the first, second, fifth, sixth, and seventh transistors T1 , T2 , T5 , T6 , and T7 may be arranged along a first semiconductor pattern Act1 included in the first semiconductor layer 1200 . Figure 6 The seventh transistor T7 shown in FIG. 1 is included in the pixel circuit PC positioned in the (n+1)th row (see FIG. 1 ). Figure 2 ), and Figure 7B It is shown that the seventh active area AR7 (or the sixth active portion) is arranged along the second semiconductor pattern Act2 included in the pixel circuit PC in the (n+1)th row. Since pixel circuits having the same shape are repeatedly arranged, the seventh transistor T7 included in the pixel circuit PC positioned in the nth row may be arranged in the first semiconductor pattern Act1. Here, n is a natural number greater than zero.

[0146] The emission control line EML (or the second conductive line) may extend in the first direction (e.g., the x-axis direction) and may overlap the fifth active area AR5 (or the fourth active portion) and the sixth active area AR6 (or the second active portion) of the first semiconductor pattern Act1. In an embodiment, a portion of the emission control line EML overlapping the fifth active area AR5 may be used as a gate electrode of the fifth transistor T5, and a portion of the emission control line EML overlapping the sixth active area AR6 may be used as a gate electrode of the sixth transistor T6.

[0147] The first scan line GWL (or the third conductive line) may extend in the first direction (eg, the x-axis direction) and may overlap the second active region AR2 (or the fifth active portion) of the first semiconductor pattern Act1 and the seventh active region AR7 of the second semiconductor pattern Act2. The first scan line GWL may transmit a first scan signal GW (see Figure 2 ). A portion of the first scan line GWL overlapping the second active area AR2 may be used as a gate electrode of the second transistor T2. The first scan line GWL passing through the pixel circuit PC in the nth row may be used as a fourth scan line GBL (or a fifth conductive line) passing through the pixel circuit PC in the (n+1)th row. A portion of the fourth scan line GBL overlapping the seventh active area AR7 may be used as a gate electrode of the seventh transistor T7.

[0148] The third transistor T3 and the fourth transistor T4 may be arranged along the third semiconductor pattern Act3 included in the second semiconductor layer 1500 .

[0149] The second scanning line GCL (see Figure 2 ) may include a second first scan line GCL1 (or a fourth conductive line) and a second second scan line GCL2 (or a first conductive line) overlapping each other, and a third active area AR3 (or an upper first active portion) of the third semiconductor pattern Act3 is between the second first scan line GCL1 and the second second scan line GCL2. The second first scan line GCL1 and the second second scan line GCL2 may extend in a first direction (e.g., an x-axis direction) and transmit a second scan signal GC (see Figure 2 ).

[0150] A portion of the second first scan line GCL1 may be used as a lower gate electrode of the third transistor T3, and a portion of the second second scan line GCL2 may be used as an upper gate electrode of the third transistor T3. In a region adjacent to the third transistor T3, a width of the second first scan line GCL1 in the second direction (e.g., y-axis direction) may be greater than a width of the second second scan line GCL2 in the second direction (e.g., y-axis direction).

[0151] The third scanning line GIL (see Figure 2 ) may include a third first scan line GIL1 and a third second scan line GIL2 (or a sixth conductive line) overlapping each other, and a fourth active area AR4 (or an upper second active portion) of the third semiconductor pattern Act3 is between the third first scan line GIL1 and the third second scan line GIL2. The third first scan line GIL1 and the third second scan line GIL2 may extend in a first direction (e.g., an x-axis direction) and transmit a third scan signal GI (see Figure 2 ).

[0152] A portion of the third first scan line GIL1 may be used as a lower gate electrode of the fourth transistor T4, and a portion of the third second scan line GIL2 may be used as an upper gate electrode of the fourth transistor T4. In a region adjacent to the fourth transistor T4, a width of the third first scan line GIL1 in the second direction (e.g., y-axis direction) may be greater than a width of the third second scan line GIL2 in the second direction (e.g., y-axis direction).

[0153] The first initialization voltage line VIL1 may extend in the first direction (e.g., the x-axis direction) and be connected (e.g., electrically connected) to the tenth doping region 1505 of the third semiconductor pattern Act3. The second initialization voltage line VIL2 may extend in the first direction (e.g., the x-axis direction) to overlap the third second scan line GIL2, and then be bent to be connected (e.g., electrically connected) to the seventh doping region 1213 of the second semiconductor pattern Act2.

[0154] refer to Figure 6 , Fig. 7A and Figure 8 , the substrate 100 may include a first organic matrix layer 101, a first inorganic barrier layer 103, a second organic matrix layer 105, and a second inorganic barrier layer 107. The bottom metal layer 1100 may be disposed between the second organic matrix layer 105 and the second inorganic barrier layer 107. The bottom metal layer 1100 may include a main portion 1110 disposed below the first active region AR1 (or the first active portion). The main portion 1110 may be connected to branch portions extending in a first direction (e.g., an x-axis direction) and a second direction (e.g., a y-axis direction).

[0155] The bottom metal layer 1100 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and may include a single layer or multiple layers containing the above materials. The bottom metal layer 1100 may be, for example, a single layer of molybdenum, a double layer of molybdenum and titanium, or a triple layer of a titanium layer, an aluminum layer, and a titanium layer.

[0156] refer to Figure 6 , Figure 7B and Figure 8 , the buffer layer 201 may be disposed on the second inorganic barrier layer 107 and the first semiconductor layer 1200 may be disposed on the buffer layer 201. The first semiconductor layer 1200 may include a first semiconductor pattern Act1 and a second semiconductor pattern Act2. The first semiconductor layer 1200 may be a silicon-based semiconductor layer. The first semiconductor pattern Act1 may be a pixel circuit PC corresponding to the nth row (see Figure 2), and the second semiconductor pattern Act2 may be a semiconductor pattern corresponding to the pixel circuit PC in the (n+1)th row. The first semiconductor layer 1200 may include a first active region AR1, a second active region AR2, a fifth active region AR5, a sixth active region AR6, and a seventh active region AR7, and doped regions may be disposed on both sides (e.g., opposite sides) of each active region.

[0157] The first active region AR1 may be an active region of the first transistor T1, and may have a curved shape. Because the first active region AR1 has a curved shape (e.g., an omega (Ω)-shaped curved shape) in a plan view, the first active region AR1 may form a long channel length in a narrow space. Therefore, the first transistor T1 may more accurately control the grayscale of light emitted from the organic light emitting diode OLED. The first active region AR1 may be connected to the bottom metal layer 1100 (see Fig. 7A ) overlaps with the main part 1110.

[0158] The first doping region 1201 (or the first doping portion) and the second doping region 1203 (or the third doping portion) may be arranged on both sides (e.g., opposite sides) of the first active region AR1. The first doping region 1201 may be arranged between the first active region AR1 and the sixth active region AR6, and the second doping region 1203 may be arranged between the first active region AR1 and the fifth active region AR5. The first doping region 1201 may be the drain region of the first transistor T1 and the source region of the sixth transistor T6. The second doping region 1203 may be the source region of the first transistor T1 and the drain region of the fifth transistor T5.

[0159] The second active region AR2 may be an active region of the second transistor T2. The second doping region 1203 and the fifth doping region 1209 (or the fourth doping portion) may be arranged on both sides (e.g., opposite sides) of the second active region AR2. For example, the second doping region 1203 may be arranged between the first active region AR1 and the second active region AR2. The fifth doping region 1209 may be an end portion of the first semiconductor pattern Act1 and may be connected (e.g., electrically connected) to the data line DL (see Figure 2 ).

[0160] The fifth active region AR5 may be an active region of the fifth transistor T5. The second doped region 1203 and the fourth doped region 1207 may be arranged on both sides (e.g., opposite sides) of the fifth active region AR5. The second doped region 1203 may be arranged between the first active region AR1 and the fifth active region AR5. The fourth doped region 1207 may be connected to a pixel circuit adjacent in a first direction (e.g., an x-axis direction).

[0161] The sixth active region AR6 may be an active region of the sixth transistor T6. The first doping region 1201 and the third doping region 1205 may be arranged on both sides (e.g., opposite sides) of the sixth active region AR6. The third doping region 1205 may have the same configuration as the sixth doping region 1211 of the second semiconductor pattern Act2. For example, the third doping region 1205 may be arranged between the sixth active region AR6 and the seventh active region AR7 of the first semiconductor pattern Act1.

[0162] The seventh active region AR7 may be an active region of the seventh transistor T7. The sixth doping region 1211 (or the fifth doping portion) and the seventh doping region 1213 (or the sixth doping portion) may be arranged on both sides (e.g., opposite sides) of the seventh active region AR7. The seventh doping region 1213 may be an end portion of the second semiconductor pattern Act2 and may be connected (e.g., electrically connected) to the second initialization voltage line VIL2 (see Figure 7G ).

[0163] refer to Figure 6 , Figure 7B , Figure 7C and Figure 8 , a first gate insulating layer 203 may be disposed on the first semiconductor layer 1200, and a first conductive layer 1300 may be disposed on the first gate insulating layer 203. The first conductive layer 1300 may include a first conductive pattern 1310, an emission control line EML, and a first scan line GWL (or a fourth scan line GBL).

[0164] The first conductive layer 1300 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and include a single layer or a multilayer containing the above materials.

[0165] The first conductive pattern 1310 may have an isolated shape when viewed in a direction perpendicular to the substrate 100. The first conductive pattern 1310 may be used as a gate electrode of the first transistor T1. The first conductive pattern 1310 may include a first capacitor electrode CE1. For example, the first conductive pattern 1310 and the first capacitor electrode CE1 may be integral with each other.

[0166] The first conductive pattern 1310 may be formed to completely cover the first active region AR1 of the first semiconductor pattern Act1. Fig. 7A ) may have a larger area than the first conductive pattern 1310.

[0167] The emission control line EML and the first scan line GWL may each extend in a first direction (e.g., an x-axis direction). When viewed in a direction perpendicular to the substrate 100, the emission control line EML and the first scan line GWL may be spaced apart from each other, and the first conductive pattern 1310 is between the emission control line EML and the first scan line GWL.

[0168] The emission control line EML may overlap the fifth active area AR5 and the sixth active area AR6 of the first semiconductor pattern Act1. A portion of the emission control line EML overlapping the fifth active area AR5 may be used as a gate electrode of the fifth transistor T5, and a portion of the emission control line EML overlapping the sixth active area AR6 may be used as a gate electrode of the sixth transistor T6. For example, the emission control line EML may include a gate electrode of the fifth transistor T5 and a gate electrode of the sixth transistor T6.

[0169] The first scan line GWL may overlap the second active area AR2 of the first semiconductor pattern Act1 and the seventh active area AR7 of the second semiconductor pattern Act2. The portion of the first scan line GWL overlapping the second active area AR2 may be used as the gate electrode of the second transistor T2, and the portion of the first scan line GWL overlapping the seventh active area AR7 may be used as the gate electrode of the seventh transistor T7. For example, the first scan line GWL may include the gate electrode of the second transistor T2 and the pixel circuit PC in the (n+1)th row (see Figure 2 ) in the gate electrode of the seventh transistor T7.

[0170] refer to Figure 6 , Figure 7B , Figure 7C , Fig.7D and Figure 8 The second gate insulating layer 205 may be disposed on the first conductive layer 1300, and the second conductive layer 1400 may be disposed on the second gate insulating layer 205. The second conductive layer 1400 may include a second conductive pattern 1410, a third conductive pattern 1420, a second first scan line GCL1, a third first scan line GIL1, and a first initialization voltage line VIL1.

[0171] The second conductive layer 1400 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and include a single layer or a plurality of layers containing the above materials.

[0172] When viewed in a direction perpendicular to the substrate 100, the second conductive pattern 1410 may have an isolated shape. The second conductive pattern 1410 may overlap the first conductive pattern 1310 and include a hole 1410h exposing a portion of the first conductive pattern 1310. The second conductive pattern 1410 may include a second capacitor electrode CE2. For example, the second conductive pattern 1410 and the second capacitor electrode CE2 may be integral with each other. The first capacitor electrode CE1 and the second capacitor electrode CE2 may form a storage capacitor Cst.

[0173] The third conductive pattern 1420 may have an isolated shape when viewed in a direction perpendicular to the substrate 100. The third conductive pattern 1420 may be in contact with (e.g., directly in contact with) the first doping region 1201 through a first contact hole CT1 that passes through the first gate insulating layer 203 and the second gate insulating layer 205 and exposes a portion of the first doping region 1201 of the first semiconductor pattern Act1. The third conductive pattern 1420 may be connected (e.g., electrically connected) to the fourth conductive pattern 1720 through a second contact hole CT2 that passes through the first interlayer insulating layer 207, the third gate insulating layer 209, and the second interlayer insulating layer 211 and exposes a portion of the third conductive pattern 1420.

[0174] After forming the first contact hole CT1 and before forming the second conductive layer 1400, the first semiconductor layer 1200 may be heat-treated. The driving range of the gate voltage of the first transistor T1 may be improved by removing hydrogen atoms of dangling bonds coupled to a region adjacent to the first contact hole CT1 through the heat treatment. After the heat treatment, impurities may be prevented from penetrating the first semiconductor layer 1200 through the first contact hole CT1 during subsequent processes by covering the first contact hole CT1 with the third conductive pattern 1420.

[0175] The first contact hole CT1 may be spaced apart from the second contact hole CT2 by a first distance d1. The first distance d1 may be about 1.0 μm to about 2.0 μm. In the case where the first distance d1 is less than about 1.0 μm, defects due to alignment errors may occur during the manufacturing process of the contact hole. In the case where the first distance d1 is greater than about 2.0 μm, the area of ​​the pixel circuit may increase, and the resolution of the display device may decrease.

[0176] The second first scan line GCL1, the third first scan line GIL1, and the first initialization voltage line VIL1 may each extend in a first direction (eg, an x-axis direction).

[0177] refer to Figure 6 , Figure 7C , Fig.7D , Fig. 7E , Figure 7G and Figure 8 , a first interlayer insulating layer 207 may be disposed on the second conductive layer 1400, and a second semiconductor layer 1500 may be disposed on the first interlayer insulating layer 207. The second semiconductor layer 1500 may be an oxide-based semiconductor layer. The second semiconductor layer 1500 may include a third semiconductor pattern Act3. The third semiconductor pattern Act3 may include a third active region AR3 (or an upper first active portion), a fourth active region AR4 (or an upper second active portion), and doped regions arranged on both sides (e.g., opposite sides) of each of the plurality of active regions.

[0178] The third active region AR3 may be an active region of the third transistor T3. The eighth doping region 1501 (or the second doping portion) and the ninth doping region 1503 (or the seventh doping portion) may be arranged on both sides (e.g., opposite sides) of the third active region AR3. The eighth doping region 1501 may be a drain region of the third transistor T3 and may be connected (e.g., electrically connected) to the first doping region 1201 as the drain region of the first transistor T1 through the third conductive pattern 1420 and the fourth conductive pattern 1720.

[0179] The fourth active region AR4 may be an active region of the fourth transistor T4. The ninth doping region 1503 and the tenth doping region 1505 may be arranged on both sides (e.g., opposite sides) of the fourth active region AR4. For example, the ninth doping region 1503 may be arranged between the third active region AR3 and the fourth active region AR4. The ninth doping region 1503 may be a source region of the third transistor T3 and a drain region of the fourth transistor T4. In an embodiment, a portion of the ninth doping region 1503 overlapping with the first scan line GWL may have a larger area than other regions. For example, a portion of the first scan line GWL and a portion of the ninth doping region 1503 overlapping each other may form a boost capacitor Cbt (see Figure 2 The tenth doping region 1505 may be a source region of the fourth transistor T4 and may be connected (eg, electrically connected) to the first initialization voltage line VIL1 through the seventh conductive pattern 1740 .

[0180] refer to Figure 6 , Fig.7D , Fig. 7E , Figure 7F and Figure 8 , a third gate insulating layer 209 may be disposed on the second semiconductor layer 1500, and a third conductive layer 1600 may be disposed on the third gate insulating layer 209. The third conductive layer 1600 may include a second second scan line GCL2 and a third second scan line GIL2. The second second scan line GCL2 and the third second scan line GIL2 may extend in a first direction (eg, an x-axis direction).

[0181] The third conductive layer 1600 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and include a single layer or a plurality of layers containing the above materials.

[0182] The second second scan line GCL2 may overlap with the third active area AR3 of the third semiconductor pattern Act3. The portion of the second second scan line GCL2 overlapping with the third active area AR3 may be the upper gate electrode of the third transistor T3. The second second scan line GCL2 may overlap with the second first scan line GCL1. The portion of the second first scan line GCL1 overlapping with the third active area AR3 may be the lower gate electrode of the third transistor T3. For example, the third active area AR3 may be disposed between the second first scan line GCL1 and the second second scan line GCL2. The third transistor T3 may have a dual gate electrode structure in which gate electrodes are disposed in an upper portion and a lower portion of the third transistor T3, respectively. In the region overlapping with the third active area AR3, the width of the second first scan line GCL1 in the second direction (e.g., the y-axis direction) may be greater than the width of the second second scan line GCL2 in the second direction (e.g., the y-axis direction).

[0183] The third second scan line GIL2 may overlap with the fourth active area AR4 of the third semiconductor pattern Act3. The portion of the third second scan line GIL2 overlapping with the fourth active area AR4 may be the upper gate electrode of the fourth transistor T4. The third second scan line GIL2 may overlap with the third first scan line GIL1. The portion of the third first scan line GIL1 overlapping with the fourth active area AR4 may be the lower gate electrode of the fourth transistor T4. For example, the fourth active area AR4 may be disposed between the third first scan line GIL1 and the third second scan line GIL2. The fourth transistor T4 may have a dual gate electrode structure in which the gate electrodes are disposed in the upper portion and the lower portion of the fourth transistor T4, respectively. In the region overlapping with the fourth active area AR4, the width of the third first scan line GIL1 in the second direction (e.g., the y-axis direction) may be greater than the width of the third second scan line GIL2 in the second direction (e.g., the y-axis direction).

[0184] refer to Figure 6 , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 7F , Figure 7G and Figure 8, the second interlayer insulating layer 211 may be disposed on the third conductive layer 1600, and the fourth conductive layer 1700 may be disposed on the second interlayer insulating layer 211. The fourth conductive layer 1700 may include a fourth conductive pattern 1720, a fifth conductive pattern 1710, a sixth conductive pattern 1730, a seventh conductive pattern 1740, an eighth conductive pattern 1750, a ninth conductive pattern 1760, and a second initialization voltage line VIL2.

[0185] The fourth conductive layer 1700 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and include a single layer or a plurality of layers containing the above materials.

[0186] The fourth conductive pattern 1720 may be connected (e.g., electrically connected) to the third conductive pattern 1420 through the second contact hole CT2, and connected (e.g., electrically connected) to the eighth doping region 1501 of the third semiconductor pattern Act3 through the third contact hole CT3. For example, the drain region of the first transistor T1 may be connected (e.g., electrically connected) to the drain region of the third transistor T3 through the fourth conductive pattern 1720 and the third conductive pattern 1420.

[0187] The fifth conductive pattern 1710 may be connected (eg, electrically connected) to the third doping region 1205 of the first semiconductor pattern Act1 through the fourth contact hole CT4. The drain region of the sixth transistor T6 may be connected (eg, electrically connected) to the pixel electrode 310 of the organic light emitting diode OLED through the fifth conductive pattern 1710.

[0188] The sixth conductive pattern 1730 may be connected (e.g., electrically connected) to the ninth doping region 1503 of the third semiconductor pattern Act3 through the fifth contact hole CT5, and connected (e.g., electrically connected) to the first conductive pattern 1310 through the twelfth contact hole CT12. When viewed in a direction perpendicular to the substrate 100, the twelfth contact hole CT12 may be positioned inside the hole 1410h of the second conductive pattern 1410, and the sixth conductive pattern 1730 may be connected (e.g., electrically connected) to the first conductive pattern 1310 exposed through the hole 1410h of the second conductive pattern 1410. The source region of the third transistor T3 may be connected (e.g., electrically connected) to the gate electrode of the first transistor T1 through the sixth conductive pattern 1730.

[0189] The seventh conductive pattern 1740 may be connected (e.g., electrically connected) to the first initialization voltage line VIL1 through the sixth contact hole CT6, and connected (e.g., electrically connected) to the tenth doping region 1505 of the third semiconductor pattern Act3 through the seventh contact hole CT7. The source region of the fourth transistor T4 may be connected (e.g., electrically connected) to the first initialization voltage line VIL1 through the seventh conductive pattern 1740.

[0190] The eighth conductive pattern 1750 may be connected (eg, electrically connected) to the fifth doping region 1209 of the first semiconductor pattern Act1 through the eighth contact hole CT8. The source region of the second transistor T2 may be connected (eg, electrically connected) to the data line DL through the eighth conductive pattern 1750.

[0191] The ninth conductive pattern 1760 may be connected (e.g., electrically connected) to the second conductive pattern 1410 of the second conductive layer 1400 through the tenth contact hole CT10, and may be connected (e.g., electrically connected) to the fourth doping region 1207 of the first semiconductor pattern Act1 through the eleventh contact hole CT11. The source region of the fifth transistor T5 and the second capacitor electrode CE2 of the storage capacitor Cst may be connected (e.g., electrically connected) to the driving voltage line PL through the ninth conductive pattern 1760.

[0192] The second initialization voltage line VIL2 may have a bent shape not overlapping the eighth conductive pattern 1750 and may extend in approximately the first direction (eg, the x-axis direction). The second initialization voltage line VIL2 may be connected (eg, electrically connected) to the seventh doping region 1213 of the second semiconductor pattern Act2 through a ninth contact hole CT9.

[0193] refer to Figure 7G and Figure 8 , a first planarization layer 213 may be disposed on the fourth conductive layer 1700. A fifth conductive layer including a data line DL and a driving voltage line PL may be disposed on the first planarization layer 213. The fifth conductive layer may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and includes a single layer or a plurality of layers including the above materials.

[0194] The second planarization layer 215 may be disposed on the fifth conductive layer. The organic light emitting diode OLED may be disposed on the second planarization layer 215. The organic light emitting diode OLED may include a pixel electrode 310 on the second planarization layer 215, an opposing electrode 330, and an intermediate layer 320 between the pixel electrode 310 and the opposing electrode 330.

[0195] For example, the pixel electrode 310 may be connected (eg, electrically connected) to the fifth conductive pattern 1710 of the fourth conductive layer 1700 through a connection electrode disposed between the first planarization layer 213 and the second planarization layer 215 .

[0196] Despite FIG. 7A to FIG. 7G and Figure 8 4 shows that the first contact hole CT1 exposes a portion of the first doping region 1201 , and the third conductive pattern 1420 of the second conductive layer 1400 overlaps the first doping region 1201 , but the embodiment is not limited thereto.

[0197] In an embodiment, the first contact hole CT1 may expose a portion of the second doping region 1203 of the first semiconductor pattern Act1, and the third conductive pattern 1420 of the second conductive layer 1400 may be formed to overlap the first contact hole CT1. The fourth conductive pattern 1720 of the fourth conductive layer 1700 may contact (eg, directly contact) the first doping region 1201 of the first semiconductor pattern Act1.

[0198] In another embodiment, the first contact hole CT1 and the thirteenth contact hole may be formed to expose a portion of the first doping region 1201 and a portion of the second doping region 1203 , respectively, and the second conductive layer 1400 may further include a conductive pattern overlapping the third conductive pattern 1420 and the thirteenth contact hole.

[0199] In the embodiment, since at least one contact hole exposing the source region and / or the drain region of the first transistor T1 is formed before forming the second semiconductor layer 1500, and the first semiconductor layer 1200 is heat-treated, damage to the second semiconductor layer 1500 due to the heat treatment can be prevented. Therefore, the display device 10 having the second semiconductor layer 1500 with a long channel length in a narrow space is provided, and the display device 10 has high electron mobility and can be driven with low power consumption.

[0200] The display device having the above-described configuration can be highly integrated and can provide high-quality images even when driven at high speeds. However, the scope of the present disclosure is not limited by this effect.

[0201] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the appended claims.

Claims

1. A display device, wherein: The display device comprises: substrate; a first semiconductor layer disposed on the substrate and comprising a first active portion, a second active portion, and a first doped portion between the first active portion and the second active portion; a first conductive layer disposed on the first semiconductor layer and including a first conductive pattern overlapping the first active portion; a second conductive layer disposed on the first conductive layer and comprising a second conductive pattern and a third conductive pattern, the second conductive pattern overlapping the first conductive pattern, the third conductive pattern being connected to the first doped portion through a first contact hole exposing a portion of the first doped portion; a second semiconductor layer disposed on the second conductive layer and comprising an upper first active portion and a second doped portion extending from the upper first active portion; a third conductive layer disposed on the second semiconductor layer and including a first conductive line overlapping the upper first active portion; and A fourth conductive layer is disposed on the third conductive layer and includes a fourth conductive pattern electrically connecting the third conductive pattern to the second doped portion.

2. The display device according to claim 1, wherein: The first semiconductor layer further includes a fourth active portion and a third doped portion between the first active portion and the fourth active portion, and The first conductive layer further includes a second conductive line extending in a first direction and overlapping the second active portion and the fourth active portion.

3. The display device according to claim 2, wherein: The first semiconductor layer further includes a fifth active portion extending from the third doped portion to be further away from the fourth active portion, and The first conductive layer further includes a third conductive line extending in the first direction and overlapping the fifth active portion.

4. The display device according to claim 3, wherein: The first semiconductor layer further includes a fourth doped portion extending from the fifth active portion to be further away from the third doped portion, and The fourth doped portion is electrically connected to the data line.

5. The display device according to claim 1, wherein: The second conductive layer also includes a fourth conductive line extending in the first direction and overlapping the upper first active portion.

6. The display device according to claim 5, wherein: The first conductive line and the fourth conductive line overlap each other.

7. The display device according to claim 1, wherein: The first semiconductor layer further includes a sixth active portion and a fifth doped portion and a sixth doped portion respectively arranged on both sides of the sixth active portion, and The first conductive layer further includes a fifth conductive line extending in the first direction and overlapping the sixth active portion.

8. The display device according to claim 1, wherein: The second semiconductor layer further includes an upper second active portion and a seventh doped portion between the upper first active portion and the upper second active portion, and The third conductive layer also includes a sixth conductive line extending in the first direction and overlapping the upper second active portion.

9. The display device according to claim 1, wherein: The first semiconductor layer includes a silicon semiconductor material, and The second semiconductor layer includes an oxide-based semiconductor material.

10. The display device according to claim 1, wherein: The fourth conductive pattern is connected to the third conductive pattern through a second contact hole exposing a portion of the third conductive pattern, The first contact hole is spaced apart from the second contact hole by a first distance, and The first distance is in the range of 1 μm to 2 μm.

11. A method for manufacturing a display device, wherein: The method comprises: forming a first semiconductor layer on the substrate; forming a first insulating layer on the first semiconductor layer; forming a first conductive layer including a first gate electrode overlapping the first semiconductor layer on the first insulating layer and doping the first semiconductor layer; forming a second insulating layer on the first conductive layer; forming a first contact hole exposing a portion of the first semiconductor layer, and heat-treating the first semiconductor layer; forming a second conductive layer including a capacitor electrode overlapping the first gate electrode and a first connection electrode overlapping the first contact hole on the second insulating layer; forming a third insulating layer on the second conductive layer; and A second semiconductor layer is formed on the third insulating layer.

12. The method according to claim 11, wherein: The first semiconductor layer includes a first active region and a first doped region and a second doped region respectively arranged on both sides of the first active region, and The first active region overlaps with the first gate electrode, and In the forming of the first contact hole and the heat treatment of the first semiconductor layer, the first contact hole is formed to overlap with the first doping region.

13. The method according to claim 12, wherein: The method further comprises: forming a fourth insulating layer on the second semiconductor layer; forming a third conductive layer including a second gate electrode overlapping the second semiconductor layer on the fourth insulating layer; forming a fifth insulating layer on the third conductive layer; forming a second contact hole, a third contact hole, and a fourth contact hole, the second contact hole exposing a portion of the first connection electrode, the third contact hole exposing a portion of the second doping region of the first semiconductor layer, and the fourth contact hole exposing a portion of the second semiconductor layer; and A fourth conductive layer including a first source / drain electrode overlapping the second contact hole, a second source / drain electrode overlapping the third contact hole, and a third source / drain electrode overlapping the fourth contact hole is formed on the fifth insulating layer.

14. The method according to claim 13, wherein: The forming of the second contact hole, the third contact hole and the fourth contact hole comprises: forming the second contact hole and the third contact hole simultaneously; and After the forming of the second contact hole and the third contact hole, the fourth contact hole is formed.

15. The method according to claim 13, wherein: The second contact hole, the third contact hole, and the fourth contact hole are formed simultaneously.

16. The method according to claim 13, wherein: The first contact hole is spaced apart from the second contact hole by a first distance, and The first distance is 1 μm to 2 μm.

17. The method according to claim 12, wherein: During the formation of the first contact hole and the heat treatment of the first semiconductor layer, a fifth contact hole overlapping the second doped region is formed simultaneously with the first contact hole, and during the formation of the second conductive layer, the second conductive layer also includes a second connecting electrode overlapping the fifth contact hole.

18. The method according to claim 17, wherein: The method further comprises: forming a fourth insulating layer covering the second semiconductor layer; forming a third conductive layer including a second gate electrode overlapping the second semiconductor layer on the fourth insulating layer; forming a fifth insulating layer on the third conductive layer; forming a second contact hole exposing a portion of the first connection electrode, a third contact hole exposing a portion of the second connection electrode, and a fourth contact hole exposing a portion of the second semiconductor layer; and A fourth conductive layer including a first source / drain electrode overlapping the second contact hole, a second source / drain electrode overlapping the third contact hole, and a third source / drain electrode overlapping the fourth contact hole is formed on the fifth insulating layer.

19. The method according to claim 18, wherein: The second contact hole, the third contact hole, and the fourth contact hole are formed simultaneously.

20. The method according to claim 11, wherein: The first semiconductor layer includes a silicon semiconductor material, and the second semiconductor layer includes an oxide-based semiconductor material.

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