Display device

Abstract

The invention relates to a display device. In the transparent display panel, a VSS voltage line does not surround an outer periphery of a display area, but an upper VSS voltage line and a lower VSS voltage line disposed on upper and lower sides of the display area, respectively, are electrically connected to each other via at least one VSS voltage connection line extending across the display area. Accordingly, left and right opaque and thick VSS voltage lines disposed on the left and right sides of the display area may be omitted. Accordingly, the transparent area of the transparent display panel and the bezel of the transparent display device may be maximized, or the bezel may be thinned.

Description

[0001] This application is a divisional application of the original invention patent application with application number 202011203615.6 (application date: November 2, 2020, invention name: transparent display panel and transparent display device including the transparent display panel). Technical Field

[0002] The present disclosure relates to a transparent display panel having a frame having a maximum transparent area or having a minimum frame area, that is, a thin frame, and a transparent display device including the panel. Background Art

[0003] Display devices that display various information using images include plasma display panel-based devices, liquid crystal display devices (LCDs), and organic light emitting diode (OLED)-based display devices.

[0004] With the advancement of image realization technology, in recent years, there has been an increasing demand for a transparent display device having a transparent region in which at least a partial region of the display device is transparent.

[0005] A transparent display device refers to a display device in which at least a portion of the area on which information is displayed is transparent to transmit light, so that an object or background behind the display device is visible to a user in front of the device.

[0006] The transparent display device transmits light in the front and rear directions. Therefore, the device can display information in the front and rear directions of the display device, so that the front user and the rear user in front and back of the display device can see the object or background opposite thereto, respectively.

[0007] For example, a transparent display device implemented as an organic light emitting display device may include a transparent region that transmits incident light as it is and a light emitting region that emits light. Summary of the invention

[0008] The transparent display device requires various lines for supplying a data voltage or a power supply voltage, etc. Generally, these lines are opaque and thick in consideration of resistance.

[0009] In particular, when an opaque and thick line as described above is provided in the frame of the transparent display device, the size of the transparent area is correspondingly reduced due to the presence of the opaque line therein.

[0010] Furthermore, when an opaque and thick line is provided in the bezel of a transparent display device, a space for accommodating the thick line must be ensured, thereby causing a limitation in making the bezel thinner.

[0011] Therefore, the inventors of the present disclosure have invented a transparent display panel having a bezel with a maximized transparent area or a minimized bezel area, that is, a narrow bezel, and a transparent display device including the panel.

[0012] An object of the present disclosure is to provide a transparent display panel and a transparent display device including the same, in which the size of a transparent area of ​​a frame is maximized by minimizing the size of a portion of the transparent area of ​​the frame shielded by an opaque line.

[0013] Furthermore, an object of the present disclosure is to provide a transparent display panel having a thin bezel by minimizing the area of ​​a portion of the bezel occupied by an opaque line, and a transparent display device including the same.

[0014] In addition, an object of the present disclosure is to provide a transparent display panel and a transparent display device including the panel, in which the size of the transparent area in the GIP (gate in panel) circuit area set in the frame is increased to maximize the size of the transparent area of ​​the frame.

[0015] The purpose of the present disclosure is not limited to the above-mentioned purpose. As mentioned above, other purposes and advantages of the present disclosure can be understood from the following description, and other purposes and advantages of the present disclosure can be more clearly understood from the embodiments of the present disclosure. In addition, it will be easily understood that the purposes and advantages of the present disclosure can be achieved by the features disclosed in the claims and their combinations.

[0016] In one embodiment of the present disclosure, a transparent display panel and a transparent display device including the panel are provided. The transparent display panel includes a frame with a maximized transparent area or a minimized frame area, that is, a thin frame.

[0017] A transparent display panel according to one embodiment of the present disclosure includes a display area and a non-display area, the display panel including: a first VSS voltage line and a second VSS voltage line arranged in the non-display area, with the display area inserted between the first VSS voltage line and the second VSS voltage line; at least one VSS voltage connecting line, which electrically connects the first VSS voltage line and the second VSS voltage line to each other, wherein the VSS voltage connecting line is arranged in the display area.

[0018] A transparent display panel according to another embodiment of the present disclosure includes: a display area, which includes a light-emitting area and a transmission area; a first VSS voltage line and a second VSS voltage line, and the display area is inserted therebetween; a GIP (gate in panel) circuit area, which is arranged in at least one side area outside the display area, wherein the first VSS voltage line and the second VSS voltage line are electrically connected to each other to at least one VSS voltage connection line, wherein the VSS voltage connection line extends across the display area.

[0019] Thus, in the transparent display panel according to the present disclosure, the upper VSS voltage line and the lower VSS voltage line disposed above and below the display area are electrically connected to each other via at least one VSS voltage connection line extending across the display area. Therefore, the opaque VSS voltage lines disposed on the left and right areas of the display area, respectively, can be omitted.

[0020] Therefore, the transparent display panel and the transparent display device according to the present disclosure can maximize the transparent area of ​​the bezel, or allow the bezel to be narrowed to the same size as the area where the opaque VSS voltage line is omitted.

[0021] According to the present disclosure, the VSS voltage line does not surround the periphery of the display area. Instead, the VSS voltage lines disposed above and below the display area are electrically connected to each other via at least one VSS voltage connection line extending across the display area. Therefore, the left and right opaque VSS voltage lines disposed on the left and right sides of the display area can be omitted. The transparent area of ​​the transparent display panel and the frame of the transparent display device can be maximized.

[0022] In addition, according to the present disclosure, the VSS voltage line does not surround the periphery of the display area. Instead, the VSS voltage lines disposed above and below the display area are electrically connected to each other via at least one VSS voltage connection line extending across the display area. Therefore, the left and right thick VSS voltage lines disposed on the left and right sides of the display area can be omitted. Therefore, the frame of the transparent display panel and the transparent display device can be narrowed.

[0023] In addition, according to the present disclosure, when the left and right thick and opaque VSS voltage lines disposed on the left and right sides of the display area are omitted, it is further ensured that the frame area can be used as a transparent area in the GIP circuit area. Therefore, the transparency of the frame of the transparent display panel and the transparent display device can be maximized.

[0024] Further specific effects of the present disclosure as well as the effects described above will be described in conjunction with descriptions of specific details for carrying out the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a block diagram schematically illustrating a system of a transparent display device.

[0026] Figure 2 It is a plan view for schematically illustrating the connection and arrangement relationship of components constituting the transparent display device.

[0027] Figure 3 is a schematic cross-sectional view of a light emitting region and a transmissive region of a pixel in an organic light emitting display panel.

[0028] Figure 4is a more detailed cross-sectional view of a light emitting region of a pixel in an organic light emitting display panel.

[0029] Figure 5 The connection relationship of the wire connection pads disposed on the first substrate in the transparent display panel according to the embodiment of the present disclosure is shown.

[0030] Figures 6 to 10 Based on the interlayer stacking structure, the transparent display panel according to the embodiment of the present disclosure is shown. Figure 5 A plane diagram of the connection relationship between the lines.

[0031] Fig.11 yes Figure 8 An enlarged plan view of the A-A' region in FIG.

[0032] Fig.12 yes Fig.11 Enlarged plan view of the B-B' region.

[0033] Fig.13 yes Fig.11 Enlarged plan view of the C-C' region.

[0034] Fig.14 yes Fig. 9 Enlarged plan view of the D-D' region.

[0035] Fig.15 yes Fig.10 Enlarged plan view of the E-E' region.

[0036] Fig.16 yes Fig.10 Enlarged cross-sectional view of the F-F' region.

[0037] Fig.17 yes Fig.10 Enlarged plan view of the G-G' region.

[0038] Fig.18 yes Fig.17 Enlarged cross-sectional view of the H-H' region. DETAILED DESCRIPTION

[0039] For the sake of simplicity and clarity of explanation, the elements in the figures are not drawn to scale. The same reference numerals in different figures represent the same or similar elements, and therefore perform similar functions. In addition, in order to simplify the description, the description and details of the known steps and elements are omitted. In addition, in the following detailed description of the present disclosure, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be understood that the present disclosure can be practiced without these specific details. In other examples, the known methods, steps, components and circuits are not described in detail to avoid unnecessary ambiguity of various aspects of the present disclosure.

[0040] Examples of various embodiments are illustrated and described below. It will be understood that the description herein is not intended to limit the claims to the specific embodiments described. On the contrary, it is intended to cover substitutions, modifications and equivalents that may be included in the spirit and scope of the present disclosure defined by the appended claims.

[0041] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "one" and "a kind of" are also intended to include plural forms. It will be further understood that when the terms "include", "comprise", "include" and "include" are used in this specification, the features, integers, operations, elements and / or parts are specified to exist, but the presence or increase of one or more other features, integers, operations, elements, parts and / or parts thereof are not excluded. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. When before a list of elements, expressions such as "at least one" can modify the entire list of elements, and the individual elements of the list may not be modified.

[0042] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part described below may be referred to as a second element, component, region, layer or part.

[0043] In addition, it will also be understood that when a first element or layer is referred to as being “on” or “under” a second element or layer, the first element can be directly disposed on or under the second element, or can be indirectly disposed on or under the second element with a third element or layer disposed between the first element or layer and the second element or layer.

[0044] It will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly connected or coupled to the other element or layer, or one or more intervening elements or layers may be present. Additionally, it will be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0045] In addition, as used herein, when a layer, film, region, or plate, etc. is disposed "on" or "on top" of another layer, film, region, or plate, etc., the former may directly contact the latter, or another layer, film, region, or plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, or plate, etc. is disposed directly "on" or "on top" of another layer, film, region, or plate, etc., the former directly contacts the latter, and another layer, film, region, or plate, etc. is not disposed between the former and the latter. In addition, as used herein, when a layer, film, region, or plate, etc. is disposed "under" or "below" another layer, film, region, or plate, etc., the former may directly contact the latter, or another layer, film, region, or plate, etc. may also be disposed between the former and the latter. As used herein, when a layer, film, region, or plate, etc. is disposed directly "under" or "below" another layer, film, region, or plate, etc., the former directly contacts the latter, and another layer, film, region, or plate, etc. is not disposed between the former and the latter.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the inventive concept belongs. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art, and unless explicitly defined herein, should not be interpreted in an idealized or overly formal sense.

[0047] Hereinafter, a transparent display panel and a transparent display device including the same according to some embodiments of the present disclosure will be exemplified.

[0048] Figure 1 is a block diagram for schematically illustrating a transparent display device according to an embodiment of the present disclosure. Figure 2 : is a plan view for schematically illustrating the connection and arrangement relationship of components constituting the transparent display device according to an embodiment of the present disclosure.

[0049] However, Figure 1 and Figure 2 Each of them is only one embodiment according to the present disclosure. Therefore, the connection and arrangement relationship of the components of the transparent display device 100 according to the present disclosure is not limited thereto.

[0050] The transparent display device 100 may include a transparent display panel 110 , a timing controller 140 , a data driver 120 , and a gate driver 130 .

[0051] The transparent display panel 110 may include a display area DA including at least one pixel P to display an image, and a non-display area NDA in which no image is displayed.

[0052] The non-display area NDA may be provided to surround the display area DA.

[0053] In the non-display area NDA, a gate driver 130, a data driving IC pad DPA, and various lines may be disposed. The non-display area NDA may correspond to a bezel.

[0054] The transparent area of ​​the transparent display panel 110 may be included in both the display area DA and the non-display area NDA.

[0055] The transparent display panel 110 may include a plurality of pixel regions defined by a plurality of gate lines GL extending in a first direction and a plurality of data lines DL extending in a second direction orthogonal to the gate lines GL.

[0056] The pixel regions may be arranged in a matrix form. Each pixel region may include a pixel P composed of at least one sub-pixel SP.

[0057] The gate driver 130 controls on / off of the driving thin film transistor 210 of the pixel.

[0058] To this end, the gate driver 130 sequentially outputs gate signals such as a scan signal or a light emitting signal, and sequentially supplies the gate signals to the gate lines GL.

[0059] Therefore, the data voltage may be applied to the sub-pixel corresponding to the pixel circuit connected to the specific gate line GL.

[0060] The gate driver 130 may include at least one gate driver integrated circuit (gate driver IC). Depending on a driving scheme or design scheme of the transparent display panel 110, the gate driver may be located on one side or both sides of the transparent display panel 110.

[0061] Each gate driver integrated circuit (IC) may be implemented in a chip on glass (COG) manner or a chip on film (COF) manner.

[0062] In addition, if Figure 2 As shown, in the gate driver 130, various elements such as transistors are directly stacked on the transparent display panel 110 in the form of GIP (Gate In Panel) through a photolithography process.

[0063] In this case, a plurality of GIP circuit areas may be arranged in a GIP form and may be disposed in the left and right portions of the non-display area NDA adjacent to the left and right peripheral portions of the display area DA, respectively, while inserting the display area DA between the left and right portions of the non-display area NDA.

[0064] When a specific gate line GL is turned on, the data driver 120 converts image data received from the timing controller 140 into a data voltage in an analog form, then synchronizes the data voltage with a gate control signal, and then supplies the data voltage to the data line DL.

[0065] Furthermore, the data driver 120 may serve as a channel through which various power lines pass.

[0066] The data driver 120 may include at least one source driver integrated circuit 121 (source driver IC) to drive the plurality of data lines DL.

[0067] Each source driver integrated circuit 121 may be implemented in a chip on glass (COG) manner or a chip on film (COF) manner.

[0068] For example, Figure 2 As shown, a source driver chip corresponding to each source driver integrated circuit 121 may be mounted on the flexible film 123. One end of the flexible film 123 may be bonded to at least one control printed circuit board 150, and the other end thereof may be bonded to a data driver IC pad (DPA) of the transparent display panel 110.

[0069] A plurality of circuits implemented as a driving chip may be mounted on the control printed circuit board 150. For example, Figure 2 As shown, the timing controller 140 may be disposed on a control printed circuit board 150 .

[0070] In addition, a power controller that supplies various voltages or currents to the transparent display panel 110 , the data driver 120 , and the gate driver 130 or controls various voltages or currents to be supplied thereto may also be provided on the control printed circuit board 150 .

[0071] In addition, a source printed circuit board may be additionally disposed between the flexible film 123 and the control printed circuit board 150. In this case, the source printed circuit board may be connected to the control printed circuit board 150 via a connection medium such as a flexible flat cable (FFC) or a flexible printed circuit (FPC).

[0072] The timing controller 140 supplies a gate control signal to the gate driver 130 , and supplies a data control signal to the data driver 120 to control the data driver 120 and the gate driver 130 .

[0073] In one example, the transparent display device 100 may be implemented as a liquid crystal display device, an organic light emitting display device, etc. However, the present disclosure is not limited thereto. Figure 3 and Figure 4An example in which the transparent display device 100 may be implemented as an organic light emitting display device is described.

[0074] Figure 3 is a schematic cross-sectional view of a pixel emission area EA and a transmission area TA of a pixel in an organic light emitting display panel. Figure 4 is a more detailed cross-sectional view of the light emitting area EA of a pixel in the organic light emitting display panel.

[0075] The transparent display panel may include a first substrate 200 and a second substrate 270 .

[0076] The first substrate 200 may serve as a base substrate including a display area DA in which pixels are disposed and a non-display area NDA in which a gate driver 130 , a data drive IC pad 310 , and various lines are disposed.

[0077] The second substrate 270 may be opposite to the first substrate 200 and may be used as a package substrate.

[0078] Each of the first substrate 200 and the second substrate 270 may be implemented as a plastic substrate or a glass substrate.

[0079] The display area DA of the first substrate 200 includes a light emitting area EA and a transmission area TA. Figure 3 shown.

[0080] Each sub-pixel may be disposed in the emission area EA.

[0081] Each subpixel may be a red subpixel emitting red light, or may be a green subpixel emitting green light, or may be a blue subpixel emitting blue light, or may be a subpixel emitting light (eg, white light other than red, green, or blue light).

[0082] Each sub-pixel may include a light emitting area EA for emitting light of a corresponding color, and a circuit area electrically connected to the light emitting area EA to control light emission from the light emitting area EA.

[0083] For example, when in a transparent display panel according to an embodiment of the present disclosure, a pixel is composed of three color sub-pixels, the first color sub-pixel includes a first color light-emitting area EA and a first color circuit area electrically connected to the first color light-emitting area EA, the second color sub-pixel includes a second color light-emitting area EA and a second color circuit area electrically connected to the second color light-emitting area EA, and the third color sub-pixel includes a third color light-emitting area EA and a third color circuit area electrically connected to the third color light-emitting area EA.

[0084] The emission area EA of the subpixel may refer to a region in which light of a color corresponding to each subpixel is emitted, or may refer to a pixel electrode such as an anode existing in each subpixel, or may refer to a region where a pixel electrode is disposed.

[0085] The emission area EA includes an organic light emitting element 220 including an anode as a first electrode 221, an organic light emitting layer 223, and a cathode as a second electrode 225. The organic light emitting element 220 emits light at a predetermined brightness using a voltage supplied to the first electrode 221 and a voltage supplied to the second electrode 225.

[0086] In this case, the second electrode 225 as a transparent electrode may extend across both the emission area EA and the transmission area TA.

[0087] The circuit region of the sub-pixel refers to a circuit region including the driving thin film transistor 210 that supplies voltage or current to a pixel electrode of each sub-pixel to control light emission from the light emitting area EA, or refers to a region where the circuit region is provided.

[0088] The driving thin film transistor 210 includes a gate electrode 214 , a source electrode 217 a , a drain electrode 217 b , and an active layer 212 .

[0089] When the circuit area receives a gate signal from the gate line GL using the thin film transistor, the circuit area may provide a predetermined voltage to the first electrode 221 of the organic light emitting element 220 of the emission area EA based on the data voltage of the data line DL.

[0090] The circuit area may at least partially vertically overlap the light emitting area EA, but may also be disposed on a side opposite to a side where light is emitted so as not to interfere with the light emission.

[0091] The encapsulation layer 250 is formed on the organic light emitting element 220, specifically, on the second electrode 225 thereof. A color filter 260 corresponding to the organic light emitting element 220 may be formed on the encapsulation layer 250.

[0092] The color filter 260 may have the same or different color as its corresponding sub-pixel.

[0093] The transmission area TA refers to an area through which incident light is transmitted, and may be an area other than a circuit area. The transmittance of the transparent display device depends on the area of ​​the transmission area TA.

[0094] Figure 3 An embodiment of the present disclosure is shown in which the emission area EA and the transmission area TA correspond to one sub-pixel. However, the present disclosure is not limited thereto. The arrangement form of the emission area EA and the transmission area TA of the transparent display device according to the present disclosure is not limited thereto.

[0095] For example, in one embodiment of the present disclosure, in which a plurality of light emitting areas EA correspond to a single transmission area TA, for example, an arrangement in which a plurality of light emitting areas EA surround a single transmission area TA may be implemented. In addition, various arrangements of the light emitting areas EA and the transmission areas TA may be implemented.

[0096] Figure 4 is a more detailed cross-sectional view of a light emitting area EA corresponding to one sub-pixel in an organic light emitting display device according to an embodiment of the present disclosure.

[0097] A driving thin film transistor 210 as a driving element and an organic light emitting element 220 connected to the driving thin film transistor 210 are provided over the first substrate 200. A buffer layer 201 may be formed over the first substrate 200, a gate insulating layer 213 may be formed over the active layer 212, and an interlayer insulating layer 216 may be formed over the gate 214.

[0098] A passivation layer 218 may be formed on the driving thin film transistor 210 to cover the driving thin film transistor 210. A contact hole exposing the drain electrode 217b may be formed in the passivation layer 218.

[0099] The passivation layer 218 may serve as a planarization layer made of an organic insulating material.

[0100] The first electrode 221 constituting the organic light emitting element 220 is formed on the passivation layer 218. The first electrode 221 is electrically connected to the drain electrode 217b via a contact hole defined in the passivation layer 218. Therefore, the driving thin film transistor 210 and the first electrode 221 on the passivation layer 218 may be electrically connected to each other.

[0101] The first electrode 221 may serve as an anode for injecting holes and may be made of a material with a high work function.

[0102] In this case, the first electrode may be implemented as a transparent electrode made of at least one transparent conductive material such as indium tin oxide (ITO), antimony tin oxide (ATO), and indium zinc oxide (IZO).

[0103] The bank layer 231 is formed on and above the passivation layer 218. The sub-pixels may be separated from each other via the bank layer 231 to form a boundary between adjacent emission areas EA to render corresponding colors, respectively. The bank layer 231 may define a bank hole corresponding to the sub-pixel area therein to partially expose the first electrode 221.

[0104] The organic light emitting layer 223 may be formed on the top surface of the bank layer 231 and a portion of the first electrode 221 exposed through the bank hole. The region where the organic light emitting layer 223 contacts the first electrode 221 may correspond to a sub-pixel region (more specifically, the emission area EA).

[0105] The organic light emitting layer 223 may include a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL).

[0106] The light emitting layer (EML) may emit red R light, green G light, or blue B light, and may be made of a phosphorescent material or a fluorescent material emitting the corresponding color.

[0107] In this case, each of the hole injection layer (HIL), the hole transport layer (HTL), the electron transport layer (ETL), and the electron injection layer (EIL) may occupy the entire display area. The light emitting layer EML may be patterned to correspond to each color region, specifically, to the first electrode 221.

[0108] However, the present disclosure is not limited thereto. Each of the hole injection layer (HIL), the hole transport layer (HTL), the electron transport layer (ETL), and the electron injection layer (EIL) may be patterned to correspond to each color region, specifically, to the first electrode 221 .

[0109] The second electrode 225 is formed on the organic light emitting layer 223 and over the entire first substrate 200. The second electrode 225 is disposed over the entire display area DA of the first substrate 200. In this case, the second electrode 225 may be disposed over the entire display area DA except the transmission area TA.

[0110] The second electrode 225 may serve as a cathode for injecting electrons and may be made of a metal with a low work function to well inject electrons.

[0111] In this case, the second electrode 225 may include at least one of materials such as Ca, Al:Li, Mg:Ag, and Ag.

[0112] In addition, the second electrode 225 may be implemented as a transparent electrode made of at least one of a transparent conductive material such as indium tin oxide (ITO), antimony tin oxide (ATO), and indium zinc oxide (IZO).

[0113] On the organic light emitting element 220 , an encapsulation layer 250 is formed to prevent external moisture from penetrating into the organic light emitting element 220 .

[0114] The encapsulation layer 250 may be formed of a plurality of layers in which inorganic layers and organic layers are alternately stacked on each other. However, the present disclosure is not limited thereto.

[0115] On the encapsulation layer 250 , a second substrate 270 as an encapsulation substrate opposite to the first substrate 200 may be formed.

[0116] In this case, a barrier layer may be formed between the encapsulation layer 250 and the second substrate 270 to more effectively prevent external moisture or oxygen from penetrating into the organic light emitting element 220 .

[0117] The barrier layer may be manufactured in the form of a film and adhered to the encapsulation layer 250 by an adhesive.

[0118] Figure 5 1 and 2. The connection relationship of the wire connection pads provided on the first substrate 301 in the transparent display panel 300 according to the embodiment of the present disclosure is shown.

[0119] The first substrate 301 includes a display area DA and a non-display area NDA disposed to surround the display area DA.

[0120] That is, the non-display area NDA may surround the top, bottom, left, and right sides of the display area DA.

[0121] like Figure 5 As shown, according to the embodiment of the present disclosure, the vertical direction or up-down direction of the display area DA refers to the Y-axis direction, and the horizontal direction or left-right direction of the display area DA refers to the X-axis direction. Figure 5 shown.

[0122] The display area DA may have a rectangular shape including long sides and short sides.

[0123] In this case, the long side is longer than the short side.

[0124] In addition, the long side refers to a side parallel to the X-axis direction which is the left-right direction of the display area DA.

[0125] The short side refers to a side parallel to the Y-axis direction which is the vertical direction or the up-down direction of the display area DA.

[0126] The gate driver 130 may be provided on at least one side of the display area DA in the form of a GIP (Gate In Panel).

[0127] That is, a pair of GIP circuit areas 360 are respectively disposed in portions of the non-display area NDA located on the left and right sides of the display area DA.

[0128] For example, the GIP circuit area 360 is disposed along a short side of the display area DA. The first VSS voltage line 321 and the second VSS voltage line 322 may be disposed along a long side of the display area DA.

[0129] Therefore, the GIP circuit area 360 may be disposed on a side of the display area DA different from a side thereof on which the first and second VSS voltage lines 321 and 322 are disposed.

[0130] On a portion of the non-display area NDA where the GIP circuit area 360 is disposed, a GIP ESD (electrostatic discharge) protection circuit area 365 operating to minimize the inflow of static electricity when static electricity is introduced into the GIP circuit area 360 may be disposed.

[0131] exist Figure 5 , the GIP ESD protection circuit region 365 is disposed above the GIP circuit region 360 in the Y direction. However, the present disclosure is not limited thereto.

[0132] At least one data drive IC pad 310 may be disposed at one side of the display area DA where the GIP circuit area 360 is not disposed, for example, at a portion of the non-display area NDA on a top long side of the display area DA.

[0133] The data driving IC pads 310 are connected to various lines required to drive the transparent display panel 300 , for example, power lines and data lines.

[0134] Between the data driving IC pad 310 and the display area DA, a data line connection pad 311 , a reference voltage line connection pad 340 , a VSS voltage line connection pad 320 , and a VDD voltage line connection pad 330 are provided to be connected to each other via the data driving IC pad 310 and various lines.

[0135] Specifically, each of the left and right reference voltage line connection pads 340, each of the left and right VDD voltage line connection pads 330, and each of the left and right VSS voltage line connection pads 320 may be disposed adjacent to each of the left and right portions of the data driver IC pad 310. The interval between each of the left and right reference voltage line connection pads 340 and the center in the length direction of the data driver IC pad 310 is smaller than the interval between each of the left and right VDD voltage line connection pads 330 and the center in the length direction of the data driver IC pad 310. The interval between each of the left and right VDD voltage line connection pads 330 and the center in the length direction of the data driver IC pad 310 is smaller than the interval between each of the left and right VSS voltage line connection pads 320 and the center in the length direction of the data driver IC pad 310.

[0136] That is, two reference voltage line connection pads 340 , two VDD voltage line connection pads 330 , and two VSS voltage line connection pads 320 may be arranged symmetrically to each other around the center of the data line connection pad 311 .

[0137] The reference voltage line connection pad 340 , the VDD voltage line connection pad 330 , and the VSS voltage line connection pad 320 are arranged to be spaced apart from each other.

[0138] The VDD voltage line connection pad 330 can be used as a high level voltage power line connection pad for providing high level voltage power to the pixel to drive the pixel, and the VSS voltage line connection pad 320 can be used as a low level voltage power line connection pad for applying low level voltage power to the pixel to drive the pixel.

[0139] The reference voltage line connection pad 340 may provide a reference voltage Vref to the pixel.

[0140] A reference voltage line 341 electrically connected to the reference voltage line connecting pad 340, a first VDD voltage line 331 electrically connected to the VDD voltage line connecting pad 330, and a first VSS voltage line 321 electrically connected to the VSS voltage line connecting pad 320 may be respectively arranged between the reference voltage line connecting pad 340 and the display area DA, between the VDD voltage line connecting pad 330 and the display area DA, and between the VSS voltage line connecting pad 320 and the display area DA.

[0141] For example, the reference voltage line connection pad 340 and the reference voltage line 341 may be integrally formed with each other and electrically connected to each other, or may be formed to be spaced apart from each other and may be electrically connected to each other via a separate connection electrode.

[0142] In addition, the VDD voltage line connection pad 330 and the first VDD voltage line 331 may be integrally formed with each other and electrically connected to each other, or may be formed to be spaced apart from each other and may be electrically connected to each other via separate connection electrodes.

[0143] In addition, the VSS voltage line connection pad 320 and the first VSS voltage line 321 may be integrally formed with each other and electrically connected to each other, or may be formed to be spaced apart from each other and may be electrically connected to each other via separate connection electrodes.

[0144] However, hereinafter, in one embodiment of the present disclosure, the following will be described. Figure 5An exemplary arrangement is shown in which a VDD voltage line connecting pad 330 and a first VDD voltage line 331 are formed integrally with each other, a reference voltage line connecting pad 340 and a reference voltage line 341 are formed to be spaced apart from each other and electrically connected to each other via separate connecting electrodes, and a VSS voltage line connecting pad 320 and a first VSS voltage line 321 are formed to be spaced apart from each other and electrically connected to each other via separate connecting electrodes.

[0145] The first VDD voltage line 331 may be formed to have a bar shape and may extend parallel to one side of the display area DA, specifically, along a long side of the display area DA, and may be integrally formed with the VDD voltage line connection pad 330 .

[0146] In addition, the first VDD voltage line 331 may be integrally formed with the plurality of VDD voltage line connection pads 330 corresponding to each data drive IC pad 310 to electrically connect the plurality of VDD voltage line connection pads 330 to one another.

[0147] The reference voltage line 341 may be disposed between the first VDD voltage line 331 and the display area DA.

[0148] The reference voltage line 341 may be used as an initial voltage line. However, the present disclosure is not limited thereto. Depending on the compensation circuit area, the reference voltage line 341 may be used as a line separated from the initial voltage line.

[0149] However, in one embodiment of the present disclosure, an example in which a reference voltage line may be used as an initial voltage line will be described.

[0150] Therefore, the reference voltage line connection pad 340 may be disposed to be spaced apart from the reference voltage line 341 in the Y direction, while an interval between the former and the display area DA is greater than an interval between the latter and the display area DA.

[0151] The reference voltage line 341 may be formed to have a bar shape, and may extend parallel to the first VDD voltage line 331 .

[0152] The reference voltage line 341 is disposed to be spaced apart from the reference voltage line connection pad 340, while the first VDD voltage line 331 is disposed between the reference voltage line 341 and the reference voltage line connection pad 340. Therefore, in order to apply a reference voltage to the reference voltage line 341, the reference voltage line connection pad 340 and the reference voltage line 341 may be electrically connected to each other via the second connection electrode 352 as a separate connection electrode.

[0153] The first VSS voltage line 321 may be disposed between the reference voltage line 341 and the display area DA.

[0154] Therefore, the VSS voltage line connection pad 320 may be disposed to be spaced apart from the first VSS voltage line 321 in the Y direction, while an interval between the former and the display area DA is greater than an interval between the latter and the display area DA.

[0155] The first VSS voltage line 321 may be formed to have a bar shape, and may extend in parallel with the first VDD voltage line 331 and the reference voltage line 341 .

[0156] The first VSS voltage line 321 is spaced apart from the VSS voltage line connection pad 320, while the first VDD voltage line 331 and the reference voltage line 341 are interposed between the first VSS voltage line 321 and the VSS voltage line connection pad 320. Therefore, in order to apply a VSS voltage to the first VSS voltage line 321, the VSS voltage line connection pad 320 and the first VSS voltage line 321 may be electrically connected to each other via the first connection electrode 351 as a separate connection electrode.

[0157] Furthermore, a VSS voltage auxiliary line connection pad 326 which is a separated portion from the VSS voltage line connection pad 320 may be disposed between the left and right reference voltage line connection pads 340 .

[0158] Specifically, the VSS voltage auxiliary line connection pad 326 can have the form of an island set between the left and right reference voltage line connection pads 340 and spaced apart from the left and right reference voltage line connection pads 340 and set between the data line connection pad 311 and the VDD voltage line and spaced apart from the data line connection pad 311 and the VDD voltage line.

[0159] The VSS voltage auxiliary line connection pad 326 may be electrically connected to the first VSS voltage line 321 via the first connection electrode 351 .

[0160] In this way, when the VSS voltage auxiliary line connection pad 326 is electrically connected to the first VSS voltage line 321 via the first connection electrode 351, the entire contact area of ​​the first VSS voltage line 321 increases, thereby reducing its total resistance while keeping the resistance distribution of the first VSS voltage line 321 uniform.

[0161] The ESD protection circuit area 371 may be disposed between the reference voltage line 341 and the display area DA. The multiplexer (MUX) circuit area 373 may be disposed between the first VSS voltage line 321 and the display area DA. However, the present disclosure is not limited thereto. The positions of the ESD protection circuit area 371 and the MUX circuit area 373 may vary based on the design scheme of the transparent display panel 300.

[0162] The ESD protection circuit region 371 may include a plurality of thin film transistors constituting an ESD protection circuit. When static electricity is generated from the transparent display panel 300, the ESD protection circuit region operates to take the static electricity to the outside.

[0163] The MUX circuit region 373 may be configured to include a plurality of thin film transistors constituting a MUX circuit.

[0164] When the MUX circuit area 373 is used, one channel of the driver IC output can provide signals to two or more data lines 313. This has the advantage of reducing the number of driver ICs used.

[0165] Each of the ESD protection circuit region 371 and the MUX circuit region 373 may be formed in a stripe shape extending parallel to the reference voltage line 341 , etc. However, the present disclosure is not limited thereto.

[0166] The first VDD voltage line 331 and the first VSS voltage line 321 may be disposed in an upper portion of the non-display area NDA adjacent to an upper side of the display area DA, and the second VDD voltage line 332 and the second VSS voltage line 322 may be disposed in a lower portion of the non-display area NDA adjacent to a lower side of the display area DA.

[0167] The second VDD voltage line 332 and the second VSS voltage line 322 may be spaced apart from each other, with an interval between the former and the display area DA being smaller than an interval between the latter and the display area DA.

[0168] The second VDD voltage line 332 may be formed to have a bar shape, and may extend in parallel along one side of the display area DA, specifically, along a long side of the display area DA.

[0169] The second VDD voltage line 332 is disposed to be spaced apart from the first VDD voltage line 331 while interposing the reference voltage line 341, the first VSS voltage line 321, and the display area DA between the second VDD voltage line 332 and the first VDD voltage line 331. Therefore, in order to apply a VDD voltage to the second VDD voltage line 332, the first VDD voltage line 331 and the second VDD voltage line 332 may be electrically connected to each other via a separate connection electrode as a VDD voltage connection line 333.

[0170] Therefore, using the connection structure as described above, the VDD voltage provided via the VDD voltage line connection pad 330 may be applied to the second VDD voltage line 332 via the first VDD voltage line 331 and the VDD voltage connection line 333 .

[0171] In this case, at least one VDD voltage connection line 333 is disposed in the display area DA to extend across the display area DA, thereby electrically connecting the first VDD voltage line 331 and the second VDD voltage line 332 to each other.

[0172] In one example, the second VSS voltage line 322 may be formed to have a bar shape, and may extend in parallel along one side of the display area DA, specifically, along a long side of the display area DA.

[0173] The width of the second VSS voltage line 322 may be smaller than the width of the first VSS voltage line 321 , such that the second VSS voltage line 322 is thinner than the first VSS voltage line 321 .

[0174] The second VSS voltage line 322 is disposed to be spaced apart from the first VSS voltage line 321 while interposing the display area DA and the second VDD voltage line 332 between the second VSS voltage line 322 and the first VSS voltage line 321. Therefore, in order to apply a VSS voltage to the second VSS voltage line 322, the first VSS voltage line 321 and the second VSS voltage line 322 may be electrically connected to each other via a separate connection electrode as a VSS voltage connection line 323.

[0175] Therefore, using the connection structure as described above, the VSS voltage supplied through the VSS voltage line connection pad 320 may be applied to the second VSS voltage line 322 through the first VSS voltage line 321 and the VSS voltage connection line 323 .

[0176] In this case, at least one VSS voltage connection line 323 may be arranged in the display area DA to extend across the display area DA, thus electrically connecting the first VSS voltage line 321 and the second VSS voltage line 322 to each other.

[0177] As in one embodiment of the present disclosure, the VSS voltage line does not surround the periphery of the display area DA. Instead, the first VSS voltage line 321 and the second VSS voltage line 322 disposed above and below the display area DA may be electrically connected to each other via at least one VSS voltage connection line 323 extending across the display area DA. Therefore, the following effects may be achieved.

[0178] First, the opaque VSS voltage lines at the left and right portions of the non-display area located at the left and right sides of the display area DA may be omitted. Therefore, the transparent area of ​​the frame may be enlarged so that the transparent area in the frame may be maximized.

[0179] In addition, the opaque VSS voltage lines at the left and right portions of the non-display area on the left and right sides of the display area DA can be omitted. Therefore, there is no need to place the VSS voltage lines at the VSS voltage line connection areas required on the frame portions on the left and right sides of the display area DA. Therefore, the frame can be very thin.

[0180] For example, as in one embodiment of the present disclosure, the VSS voltage connection line 323 is disposed in the display area DA and extends across the display area DA. In contrast, when the VSS voltage connection line 323 is disposed at the left and right portions of the non-display area NDA to the left and right of the display area DA, the VSS voltage line is disposed to surround the display area DA and extend along the periphery of the display area DA.

[0181] When the VSS voltage line extends around the periphery of the display area DA, since the opaque VSS voltage line is formed in the non-display area NDA outside the periphery of the display area DA, the size of the transparent area of ​​the bezel is reduced, thereby not allowing the bezel area to be reduced.

[0182] However, in the VSS voltage line arrangement structure according to the embodiment of the present disclosure, the VSS voltage line is not provided on the top, bottom, left and right sides of the display area DA, that is, not provided on the four sides of the frame. Instead, it is sufficient to provide the VSS voltage line only in the frame on the top and bottom sides of the display area DA.

[0183] Therefore, in the transparent display panel 300 and the transparent display device 100 according to the embodiment of the present disclosure, the maximum value of the transparent area of ​​the frame where the opaque VSS voltage line is not set can be ensured. If necessary, the size of the frame can be reduced so that the frame can be thinner.

[0184] In addition, when the VSS voltage line surrounds the periphery of the display area DA, the VSS voltage flows around the periphery of the display area DA and flows into the display area DA, and is then provided to the pixels in the display area DA. Therefore, the VSS voltage line used as a current path must be thick in order to be used as a current path in a reliable manner in terms of resistance.

[0185] However, as in one embodiment of the present disclosure, the first VSS voltage line 321 and the second VSS voltage line 322 are connected to each other via a VSS voltage connection line 323 extending across the display area DA. Therefore, when the VSS voltage connection line 323 passes through the display area DA, the VSS voltage connection line can directly provide the VSS voltage to the pixel. Therefore, the second VSS voltage line 322 may not be used as a current path.

[0186] As such, when the second VSS voltage line 322 does not function as a current path, the second VSS voltage line 322 does not need to be formed thick in consideration of resistance and is thus as thin as possible.

[0187] Therefore, according to an embodiment of the present disclosure, the second VSS voltage line 322 may have a width smaller than that of the first VSS voltage line 321. Therefore, as the width of the second VSS voltage line 322 decreases, the size of the second VSS voltage line 322 decreases. The size of the transparent area in the lower frame portion under the display area DA may be increased. If necessary, the size of the lower frame portion under the display area DA may be reduced, so the frame may be made narrower.

[0188] In one example, the light emitting tester 375 may be disposed in the non-display area NDA and spaced apart from the second VSS voltage line 322 , while an interval between the former and the display area DA is greater than an interval between the latter and the display area DA.

[0189] The light emitting tester 375 may be formed in a bar shape extending in parallel to the second VSS voltage line 322 , and may also extend along both left and right sides of the display area DA, thereby surrounding three sides of the display area DA.

[0190] The light emitting tester 375 may provide a light emitting test signal to the plurality of data lines 313 before a module process after manufacturing the transparent display panel 300 , and may inspect defects of the transparent display panel 300 .

[0191] The light emission tester 375 includes a plurality of inspection switching elements respectively connected to the plurality of data lines 313 .

[0192] For example, the luminous tester 375 includes a plurality of red test switching elements respectively connected to the data lines 313 for applying data voltages to red sub-pixels, a plurality of green test switching elements respectively connected to the data lines 313 for applying data voltages to green sub-pixels, and a plurality of blue test switching elements respectively connected to the data lines 313 for applying data voltages to blue sub-pixels.

[0193] Therefore, a plurality of data lines 313 branched from the data line connection pads 311 extend across the display area DA and are then electrically connected to the light emitting tester 375 .

[0194] The light emitting test signal applier 376 may be formed on a partial area of ​​each of the reference voltage line connection pad 340 , the VDD voltage line connection pad 330 , and the VSS voltage line connection pad 320 to provide a light emitting test signal to the light emitting tester 375 .

[0195] Figures 6 to 10 FIG. 2 is a diagram showing a transparent display panel 300 based on an interlayer stacking structure according to an embodiment of the present disclosure. Figure 5 A plane diagram of the connection relationship between the lines.

[0196] like Figure 6 As shown, the reference voltage line connecting pad 340, the VDD voltage line connecting pad 330, the VSS voltage line connecting pad 320, the VSS voltage auxiliary line connecting pad 326, the reference voltage line 341, the first VDD voltage line 331, the second VDD voltage line 332, the first VSS voltage line 321 and the second VSS voltage line 322 of the transparent display panel 300 according to an embodiment of the present disclosure may constitute the same layer and may be spaced apart from each other.

[0197] Specifically, the reference voltage line connecting pad 340, the VDD voltage line connecting pad 330, the VSS voltage line connecting pad 320, the VSS voltage auxiliary line connecting pad 326, the reference voltage line 341, the first VDD voltage line 331, the second VDD voltage line 332, the first VSS voltage line 321, the second VSS voltage line 322, the source 217a and the drain 217b of the pixel's driving thin film transistor 210 can be made of the same material and can constitute the same layer.

[0198] However, as described above, the VDD voltage line connection pad 330 and the first VDD voltage line 331 may be integrally formed with each other without being separated from each other.

[0199] Therefore, the wire connection pad and the wire constitute the same layer. Therefore, the connection electrode that electrically connects the wire connection pad and the wire to each other should not form a short circuit with other wires between the wire connection pad and the wire to be connected to each other or between the wires.

[0200] For example, in order to connect the data line 313 branched from the data line connection pad 311 to the light emitting tester 375 , the data line 313 may be composed of a first data line 314 and a second data line 315 constituting different layers and electrically connected to each other.

[0201] In this case, the first data line 314, the source electrode 217a and the drain electrode 217b of the pixel driving thin film transistor 210 may constitute the same layer and may be made of the same material. The second data line 315 and the gate electrode 214 of the pixel driving thin film transistor 210 may constitute the same layer and may be made of the same material.

[0202] The data line 313 applies a data signal to the pixels in the display area DA. Therefore, the first data line 314 and the second data line 315 of the data line 313 branched from the data line connection pad 311 may constitute different layers so as not to form a short circuit with various wire connection pads and wires disposed in the area between the display area DA and the data line connection pad 311.

[0203] Therefore, the second data line 315 may function as the data line 313 in the area between the display area DA and the data line connection pad 311. The first data line 314 constituting a layer different from that of the second data line 315 may function as the data line 313 in the display area.

[0204] Then, the second data line 315 may be used as the data line 313 in the area between the display area DA and the light emitting tester 375. Then, the first data line 314 as the data line 313 may be connected to the light emitting tester 375.

[0205] However, the first data line 314 and the second data line 315 can be used as the data line 313 in a repeated alternating manner so that the data line 313 does not form a short circuit with the second VDD voltage line 332 and the second VSS voltage line 322 in the area where the data line 313 overlaps with the second VDD voltage line 332 and the second VSS voltage line 322 in the area between the display area DA and the light tester 375.

[0206] In other words, Figures 11 to 13 As shown, the data line 313 can be changed from the first data line 314 to the second data line 315 in an area where the data line 313 does not overlap with the second VDD voltage line 332, so that the data line 313 does not form a short circuit with the second VDD voltage line 332 when extending across the second VDD voltage line 332. In this way, the second data line 315 and the second VDD voltage line 332 do not constitute the same layer, thereby preventing a short circuit between them.

[0207] In connection, the data line 313 changes from the first data line 314 to the second data line 315 may refer to, for example Fig.12 As shown, the first data line 314 is connected to the second data line 315 via at least one contact hole so that the electrical connection between them is maintained, but the first data line 314 and the second data line 315 constitute different layers and are made of different materials. This principle can be equally applied to other lines in the following examples.

[0208] After the second data line 315 extends across the second VDD voltage line 332 , the second data line 315 may be changed back to the first data line 314 in a region where the data line 313 does not overlap the second VDD voltage line 332 .

[0209] That is, the first data line 314 and the second data line 315 may constitute different layers and be electrically connected to each other via at least one second data line contact hole 315h.

[0210] In the same manner, the reference voltage connection line 343 may be composed of a first reference voltage connection line 344 and a second reference voltage connection line 345 which constitute different layers and are electrically connected to each other.

[0211] In this case, the first reference voltage connection line 344, the source 217a and the drain 217b of the driving thin film transistor 210 of the pixel may constitute the same layer and may be made of the same material. The second reference voltage connection line 345 and the gate 214 of the driving thin film transistor 210 of the pixel may constitute the same layer and may be made of the same material.

[0212] For example, the reference voltage connection line 343 extends to the lower end of the display area DA. The reference voltage connection line 343 may be composed of a first reference voltage connection line 344 and a second reference voltage connection line 345 constituting different layers and electrically connected to each other.

[0213] The reference voltage connection line 343 extends across the display area DA. The distal end of the reference voltage connection line 343 does not need to contact a separate line.

[0214] Because the reference voltage connection line 343 applies the reference voltage to the pixels in the display area DA, the reference voltage connection line 343 is composed of different reference voltage connection lines constituting different layers, so that the reference voltage connection line 343 will not form a short circuit with various wire connection pads and wires in the area between the display area DA and the reference voltage line 341.

[0215] Therefore, the reference voltage connection line 343 is implemented as the second reference voltage connection line 345 in the area between the display area DA and the reference voltage line 341. The reference voltage connection line 343 is implemented as the first reference voltage connection line 344 constituting a different layer from the second reference voltage connection line 345 in the display area DA.

[0216] The first reference voltage connection line 344 and the second reference voltage connection line 345 may constitute different layers and may be electrically connected to each other via at least one contact hole.

[0217] In addition, the VSS voltage connection line 323 may be composed of a first VSS voltage connection line 324 and a second VSS voltage connection line 325 constituting different layers and electrically connected to each other.

[0218] In this case, the first VSS voltage connection line 324, the source 217a and the drain 217b of the driving thin film transistor 210 of the pixel may constitute the same layer and may be made of the same material. The second VSS voltage connection line 325 and the gate 214 of the driving thin film transistor 210 of the pixel may constitute the same layer and may be made of the same material.

[0219] For example, in order to connect the VSS voltage link line 323 to the second VSS voltage link line 322 , the first VSS voltage link line 324 and the second VSS voltage link line 325 constituting different layers are electrically connected to each other.

[0220] Since the VSS voltage connection line 323 electrically connects the first VSS voltage line 321 and the second VSS voltage line 322 sandwiching the display area DA between each other, the first VSS voltage connection line 324 and the second VSS voltage connection line 325 of the VSS voltage connection line can constitute different layers so that the VSS voltage connection line does not form a short circuit with various line connection pads and lines in the area between the first VSS voltage line 321 and the second VSS voltage line 322.

[0221] In one embodiment of the present disclosure, no other lines are provided between the display area DA and the first VSS voltage line 321. Therefore, the VSS voltage connection line 323 extending from the first VSS voltage line 321 may be implemented as a first VSS voltage connection line 324 integrally formed with the first VSS voltage line 321 and made of the same material and constituting the same layer as the first VSS voltage line 321.

[0222] The first VSS voltage connection line 324 branched from the first VSS voltage line 321 may extend across the display area DA. Then, when the VSS voltage connection line 323 extends across the second VDD voltage line 332, the first VSS voltage connection line 324 and the second VSS voltage connection line 325 may be used as the VSS voltage connection line 323 in a repeated alternating manner so that the VSS voltage connection line 323 does not form a short circuit with the second VDD voltage line 332 in an area where the VSS voltage connection line 323 overlaps the second VDD voltage line 332.

[0223] In other words, Figures 11 to 13 As shown, when the VSS voltage connection line 323 extends across the second VDD voltage line 332, the VSS voltage connection line 323 may be changed from the first VSS voltage connection line 324 to the second VSS voltage connection line 325 in a region where the VSS voltage connection line 323 does not overlap with the second VDD voltage line 332. Therefore, when the VSS voltage connection line 323 extends across the second VDD voltage line 332, the VSS voltage connection line 323 does not form a short circuit with the second VDD voltage line 332.

[0224] That is, the first VSS voltage link line 324 and the second VSS voltage link line 325 constitute different layers and are electrically connected to each other via at least one second VSS voltage link line contact hole 325h.

[0225] After the VSS voltage connection line 323 extends across the second VDD voltage line 332, the first VSS voltage connection line 324 may be connected to the second VSS voltage line 322, such as Fig.13 shown.

[0226] In this case, the first VSS voltage link line 324 and the second VSS voltage link line 322 may be electrically connected to each other via at least one second VSS voltage link line 325 connected to the first VSS voltage link line 324 via at least one second VSS voltage link line contact hole 325h.

[0227] In addition, in a region where the second VSS voltage line 322 does not overlap the data line 313 , an auxiliary line 327 connected to the second VSS voltage line 322 via at least one auxiliary line contact hole 327 h is disposed under the second VSS voltage line 322 .

[0228] The auxiliary line 327 and the gate electrode 214 may be made of the same material and may constitute the same layer.

[0229] The auxiliary line 327 may be connected to the back side of the second VSS voltage line 322 , thereby reducing the total resistance of the second VSS voltage line 322 .

[0230] In addition, the VDD voltage connection line 333 may be composed of a first VDD voltage connection line 334 and a second VDD voltage connection line 335 constituting different layers and being electrically connected to each other.

[0231] In this case, the first VDD voltage connection line 334, the source 217a and the drain 217b of the driving thin film transistor 210 of the pixel can be made of the same material and can constitute the same layer. The second VDD voltage connection line 335 and the gate 214 of the driving thin film transistor 210 of the pixel can be made of the same material and can constitute the same layer.

[0232] For example, in order to connect the VDD voltage link line 333 to the second VDD voltage link line 332 , the first VDD voltage link line 334 and the second VDD voltage link line 335 constitute different layers and are electrically connected to each other.

[0233] The VDD voltage connection line 333 electrically connects the first VDD voltage line 331 and the second VDD voltage line 332 sandwiching the display area DA therebetween. Therefore, the first VDD voltage connection line 334 and the second VDD voltage connection line 335 constitute different layers, so that the VDD voltage connection line 333 does not form a short circuit with various wire connection pads and wires in the area between the first VDD voltage line 331 and the second VDD voltage line 332.

[0234] Therefore, in the area between the first VDD voltage line 331 and the display area DA, the VDD voltage connection line 333 may be implemented as the first VDD voltage connection line 334. When the VDD voltage connection line 333 extends across the display area DA, the VDD voltage connection line 333 may be implemented as the second VDD voltage connection line 335. That is, the VDD voltage connection line 333 is changed from the first VDD voltage connection line 334 to the second VDD voltage connection line 335.

[0235] That is, the first VDD voltage connection line 334 and the second VDD voltage connection line 335 constitute different layers and are electrically connected to each other via at least one contact hole.

[0236] Then, if Fig.12 As shown, in the area between the display area DA and the second VDD voltage line 332 , the VDD voltage connection line 333 may be implemented as a first VDD voltage connection line 334 that may be connected to the second VDD voltage line 332 .

[0237] In this case, the first VDD voltage link line 334 and the second VDD voltage link line 332 may be electrically connected to each other via a second VDD voltage link line 335 connected to the first VDD voltage link line 334 via at least one second VDD voltage link line contact hole 335h.

[0238] In addition, the auxiliary line 327 connected to the second VDD voltage line 332 via at least one contact hole may be disposed in a region where the second VDD voltage line 332 does not overlap the data line 313 and does not overlap the VSS voltage connection line 323 .

[0239] The auxiliary line 327 and the gate electrode 214 may be made of the same material and may constitute the same layer.

[0240] The VDD voltage auxiliary line 327 may be connected to the back side of the second VDD voltage line 332 to reduce the total resistance of the second VDD voltage line 332 .

[0241] Figure 7 Also shown are passivation holes formed in the passivation layer 218 . Figure 8 Also shown are a first connection electrode 351 connecting the VSS voltage line connection pad 320 and the first VSS voltage line 321 to each other, and a second connection electrode 352 connecting the reference voltage line connection pad 340 and the reference voltage line 341 to each other.

[0242] A passivation layer 218 may be formed on the reference voltage line connection pad 340 , the VDD voltage line connection pad 330 , the VSS voltage line connection pad 320 , the reference voltage line 341 , the first VSS voltage line 321 , the second VSS voltage line 322 , the first VDD voltage line 331 , and the second VDD voltage line 332 .

[0243] The passivation layer 218 may serve as a planarization layer made of an organic material layer such as PAC, and may be formed on various wire connection pads and lines to form a planar top surface.

[0244] In addition, the passivation layer 218 serves as an insulating layer. Therefore, in order to make electrical connections between the wire connection pads and the wires, a passivation hole, that is, a planarization hole may be formed in each wire connection pad and a portion of each wire.

[0245] In this case, the passivation hole refers not only to a contact hole for contact but also to an open hole formed by partially removing the passivation layer 218 to ensure a contact area as much as possible.

[0246] Each wire connection pad and each wire may be electrically connected to each other via connection electrodes connected to each other through the planarization hole.

[0247] exist Figure 7 In order to make the distinction between the layers clear, the passivation layer 218 is not shown separately, and only the region where the passivation hole is formed is shown in an emphasized manner.

[0248] A first passivation hole 218a is formed on the VSS voltage line connection pad 320 and the first VSS voltage line 321. The first connection electrode 351 formed on the passivation layer 218 electrically connects the VSS voltage line connection pad 320 and the first VSS voltage line 321 to each other via the first passivation hole 218a. Figure 8 and Fig.14 shown.

[0249] In other words, in order to prevent a short circuit from occurring between the VSS voltage line connecting pad 320 and the first VSS voltage line 321 and between the first VDD voltage line 331 and the reference voltage line 341 arranged between the VSS voltage line connecting pad 320 and the first VSS voltage line 321, a jumper connection structure of electrodes for connecting the VSS voltage line connecting pad 320 and the first VSS voltage line 321 to each other may be required.

[0250] Therefore, according to an embodiment of the present disclosure, the passivation layer 218 is formed on the first VDD voltage line 331 and the reference voltage line 341. The first passivation hole 218a is formed on the VSS voltage line connection pad 320 and the first VSS voltage line 321.

[0251] Therefore, a jumper connection structure of an electrode formed on the passivation layer 218 and having a portion connected to the VSS voltage line connection pad 320 through a first passivation hole 218a and having an opposite portion connected to the first VSS voltage line 321 via the opposite first passivation hole 218a can be used.

[0252] The first connection electrode 351 of the organic light emitting element 220 constituting the pixel and the anode as the first electrode 221 may be made of the same material and may constitute the same layer.

[0253] The first connection electrode 351 electrically connects the VSS voltage line connection pad 320 and the first VSS voltage line 321 to each other, and to this end, is preferably formed to have as large an area as possible to minimize resistance and maximize uniformity of resistance distribution.

[0254] Therefore, the first connection electrode 351 may be formed to extend over the first VDD voltage line 331 , the reference voltage line 341 , and the first VSS voltage line 321 , and thus may be formed to have a maximum area.

[0255] However, the first connection electrode 351 does not extend over all regions of the first VDD voltage line 331 and the reference voltage line 341 and the first VSS voltage line 321. The first connection electrode 351 does not extend over a partial region such as a region of a second connection electrode 352 described later or a spacing region between the first connection electrode 351 and the second connection electrode 352.

[0256] In addition, when the first connection electrode 351 has as large an area as possible, the first passivation hole 218 a may preferably have as large an area as possible to maximize its contact area with the VSS voltage line connection pad 320 and the VSS voltage line 321 .

[0257] Therefore, the first passivation hole 218 a formed on the first VSS voltage line 321 may have a shape corresponding to the first VSS voltage line 321 , that is, a long strip shape.

[0258] Due to the connection scheme using the first connection electrode 351, a jumper connection structure of the VSS voltage line having a minimum resistance can be implemented.

[0259] In addition, if Fig.14 As shown, at least one exhaust hole 355 may be formed in at least a portion of the first connection electrode 351 .

[0260] The exhaust hole 355 serves to exhaust unnecessary gas that may be generated during a process of forming the transparent display panel 300. Therefore, when the exhaust hole 355 is formed in the first connection electrode 351 having a large area, the reliability of the transparent display panel 300 may be further enhanced.

[0261] The bank layer 231 formed on the first connection electrode 351 has an opening area defined therein corresponding to the exhaust hole 355 to ensure a passage of the exhaust hole 355. Each of the bank layers 231 may define a boundary between adjacent exhaust holes 355.

[0262] In addition, if Figure 8 As shown, a VSS voltage auxiliary line connection pad 326 may be additionally provided and may be electrically connected to the first VSS voltage line 321 via a first connection electrode 351 .

[0263] The VSS voltage auxiliary line connection pad 326 and the VSS voltage line connection pad 320 may be made of the same material and constitute the same layer. However, the VSS voltage auxiliary line connection pad 326 has an island shape that is separated from the VSS voltage line connection pad 320 and is not connected to a separate line.

[0264] The first passivation hole 218a is formed on the VSS voltage auxiliary line connection pad 326, so that the VSS voltage auxiliary line connection pad 326 is connected to the first connection electrode 351 via the first passivation hole 218a, thereby increasing the total area of ​​the first connection electrode 351, thereby reducing the total resistance and making the resistance distribution more uniform.

[0265] In one example, the passivation layer 218 is formed on the reference voltage line connection pad 340 and the reference voltage line 341. The second connection electrode 352 formed on the passivation layer 218 electrically connects the reference voltage line connection pad 340 and the reference voltage line 341 to each other via the second passivation hole 218b. Figure 8 and Fig.14 shown.

[0266] In order to prevent short circuit between the reference voltage line connection pad 340 and the reference voltage line 341 and the first VDD voltage line 331 therebetween, a jumper structure of electrodes for connecting the reference voltage line connection pad 340 and the reference voltage line 341 to each other is required.

[0267] Therefore, according to an embodiment of the present disclosure, the passivation layer 218 is formed on the first VDD voltage line 331 , and the second passivation hole 218 b is formed on each of the reference voltage line connection pad 340 and the reference voltage line 341 .

[0268] Therefore, a jumper connection structure of the electrode can be formed using a second connection electrode 352 formed on the passivation layer 218 and having a portion connected to the reference voltage line connection pad 340 through a second passivation hole 218b and a relative portion connected to the reference voltage line 341 through a relative second passivation hole 218b.

[0269] The second connection electrode 352 and the first connection electrode 351 may be made of the same material and may constitute the same layer, but may be spaced apart from each other. Therefore, the second connection electrode 352 may have an island shape.

[0270] Therefore, the second connection electrode 352 of the organic light emitting element 220 constituting the pixel and the anode as the first electrode 221 may be made of the same material and may constitute the same layer.

[0271] The second connection electrode 352 electrically connects the reference voltage line connection pad 340 and the reference voltage line 341 to each other, and for this purpose, preferably, the second connection electrode 352 is formed to have as large an area as possible to minimize its resistance and maximize its resistance distribution uniformity.

[0272] In addition, when the second connection electrode 352 has as large an area as possible, the second passivation hole 218 b is formed to have as large an area as possible to maximize its contact area with the reference voltage line connection pad 340 and the reference voltage line 341 .

[0273] Due to the connection mode using the second connection electrode 352 , a jumper connection structure of the reference voltage line 341 with minimum resistance can be realized.

[0274] In addition, as in the first connection electrode 351 , at least one exhaust hole 355 may be formed in a partial region of the second connection electrode 352 .

[0275] In one example, the third passivation hole 218c may be formed on the second VSS voltage line 322. Figure 7 As shown. Figure 8 As shown, the third connection electrode 353 may be formed on the third passivation hole 218 c.

[0276] The third passivation hole 218c formed on the second VSS voltage line 322 is used to connect the second VSS voltage line 322 and the third connection electrode 353 to each other. The third connection electrode 353 is electrically connected to the second VSS voltage line 322 via the third passivation hole 218c.

[0277] In order to reduce resistance by maximizing the contact area between the second VSS voltage line 322 and the third connection electrode 353 , the third passivation hole 218 c formed on the second VSS voltage line 322 may have a bar shape corresponding to the second VSS voltage line 322 .

[0278] In addition, when the third connection electrode 353 is formed at the lower end of the transparent display panel 300, the following effect occurs: the difference in vertical height between the lower end of the transparent display panel 300 and the upper end of the transparent display panel 300 of the first and second connection electrodes 351 and 352 can be removed.

[0279] The third connection electrode 353 , the first connection electrode 351 , and the second connection electrode may be made of the same material and may constitute the same layer, but may be spaced apart from each other. Therefore, the third connection electrode 353 is formed to have an island shape.

[0280] Therefore, the third connection electrode 353 of the organic light emitting element 220 constituting the pixel and the anode as the first electrode 221 may be made of the same material and may constitute the same layer.

[0281] A bank layer 231 may be formed on the first connection electrode 351 , the second connection electrode 352 , and the third connection electrode 353 .

[0282] like Fig. 9 As shown, the bank layer 231 may form a barrier 380 disposed in the non-display area NDA to surround the display area DA. In this case, the barrier 380 may include at least one patterned barrier 380 .

[0283] When the encapsulation layer 250 is formed on the first substrate 200 , the barrier 380 may serve to prevent an encapsulation material used to form the encapsulation layer 250 from flowing to the outside.

[0284] Specifically, Fig. 9 As shown, the barrier 380 may be disposed in the non-display area NDA, and may be disposed to surround the light emitting tester 375 and the first VDD voltage line 331 disposed in the non-display area NDA.

[0285] In one example, the fourth connection electrode 354 is formed on the bank layer 231 and is connected to the cathode of the second electrode 225 which is the pixel.

[0286] The fourth connection electrode 354 is electrically connected to a VSS voltage line to apply a VSS voltage to the cathode of the pixel.

[0287] In this case, the cathode and the fourth connection electrode 354 may be formed integrally with each other.

[0288] Therefore, in one embodiment of the present disclosure, one end of the fourth connection electrode 354 is electrically connected to the first connection electrode 351 to which the VSS voltage is applied, and the other end of the fourth connection electrode 354 is electrically connected to the third connection electrode 353, thereby applying the VSS voltage to the cathode.

[0289] Specifically, Fig. 9 , Fig.10 and Fig.16 As shown, the bank layer 231 is formed on the first connection electrode 351. The first bank hole 231a is formed on the first connection electrode 351 and is formed by removing a portion of the bank layer 231, thereby exposing the first connection electrode 351 to the outside. Therefore, the first connection electrode 351 can be electrically connected to one end of the fourth connection electrode 354 via the first bank hole 231a.

[0290] When a VSS voltage is applied to the fourth connection electrode 354 , the fourth connection electrode 354 is not directly connected to the first VSS voltage line 321 , but is connected thereto via the first connection electrode 351 made of the same material as an anode, thereby reducing resistance.

[0291] In order to maximize the contact area between the first connection electrode 351 and the fourth connection electrode 354 , the first bank hole 231 a of the bank layer 231 on the first connection electrode 351 may be formed in the same stripe shape as the reference voltage line 341 .

[0292] In addition, the first bank hole 231 a may be formed in such a manner as to correspond to the reference voltage line 341 or the first VSS voltage line 321 .

[0293] For example, when the first bank hole 231a is formed on a separate circuit region such as the ESD protection circuit region 371 rather than on a line such as the reference voltage line 341 or the first VSS voltage line 321, there may be a problem of forming the bank hole in a region with poor flatness.

[0294] Furthermore, when the first bank hole 231a is formed on a line such as the first VDD voltage line 331 that is away from the first VSS voltage line 321, the fourth connection electrode 354 that is electrically connected to the first VSS voltage line 321 via the first bank hole 231a is away from the first VSS voltage line 321. Therefore, as the current path becomes longer, the resistance increases accordingly.

[0295] For example, when the fourth connection electrode 354 is used as a transparent cathode as a high resistance line, its resistance may be high. Therefore, when the connection length to the fourth connection electrode 354 as a high resistance cathode rather than a low resistance anode is larger, the total resistance may be larger.

[0296] Therefore, according to an embodiment of the present disclosure, it is preferable to form the first bank hole 231 a on the reference voltage line 341 or the first VSS voltage line 321 .

[0297] When the first bank hole 231 a is formed on the reference voltage line 341 , the inclined surface of the hole can be removed to obtain high flatness, thereby reducing resistance variation compared to when the bank hole is formed in a portion of the bank layer 231 where no line is formed.

[0298] Furthermore, when the first bank hole 231 a is formed on the first VSS voltage line 321 , the connection length between the fourth connection electrode 354 and the first VSS voltage line 321 becomes smaller, thereby reducing resistance.

[0299] like Fig. 9 and Fig.10 As shown, a second bank hole 231b formed by removing a partial area of ​​the bank layer 231 is formed in a portion of the bank layer 231 on the third connection electrode 353 electrically connected to the second VSS voltage line 322, thereby electrically connecting the opposite portion of the fourth connection electrode 354 to the third connection electrode 353.

[0300] In this case, the second bank hole 231b is formed to correspond to the third passivation hole 218c on the second VSS voltage line 322. Therefore, when the second VSS voltage line 322, the third connection electrode 353 and the fourth connection electrode 354 are in a stacked state, they electrically contact each other at the same position.

[0301] In addition, the second VSS voltage line 322 is not directly connected to the cathode but is connected thereto via the third connection electrode 353 which is a low-resistance anode, thereby reducing resistance.

[0302] Due to the connection structure of the fourth connection electrode 354, the VSS voltage may be applied to the fourth connection electrode 354. Therefore, the VSS voltage may be applied to the cathode of the organic light emitting element 220.

[0303] That is, the VSS voltage applied from the VSS voltage line connection pad 320 may be applied to the fourth connection electrode 354 via the first VSS voltage line 321 and the first connection electrode 351 .

[0304] The fourth connection electrode 354 may extend across the entire display area DA including the first VDD voltage line 331 , the reference voltage line 341 , the first VSS voltage line 321 , the second VDD voltage line 332 , and the second VSS voltage line 322 .

[0305] For example, Fig.15As shown, the cathode electrode may extend across the entire display area DA including the second VDD voltage line 332 and the second VSS voltage line 322 , and may be surrounded by the barrier 380 .

[0306] In one example, if Fig.17 As shown, the GIP circuit area 360 includes a GIP partition block 361 and a clock signal line area 363 .

[0307] The GIP partition block 361 includes at least one GIP partition block that divides the gate line GL into a plurality of blocks and drives each of the plurality of blocks in each of a plurality of display driving periods. The clock signal line region 363 may include at least one clock signal line to control the nodes of the GIP circuit region 360 .

[0308] According to an embodiment of the present disclosure, the GIP partition blocks 361 and the clock signal line regions 363 may be alternately arranged in a direction away from the display area DA.

[0309] Specifically, in one embodiment of the present disclosure, the opaque and thick VSS voltage line may be omitted in the left and right portions of the non-display area NDA to the left and right of the display area DA. Therefore, the GIP circuit area 360 may occupy an area increased by the omitted area.

[0310] Therefore, components such as the GIP partition block 361 and the clock signal line region 363 constituting the GIP circuit region 360 can be arranged in a non-compact manner. Therefore, a transparent region can be ensured even in the GIP circuit region 360.

[0311] For example, when the space occupied by the GIP circuit area 360 is narrow, the GIP partition block 361 and the clock signal line area 363 must be arranged in a very dense manner to maximize space utilization. Therefore, it is difficult to ensure a separate transparent area in the GIP circuit area 360.

[0312] On the contrary, as in one embodiment of the present disclosure, when the space occupied by the GIP circuit area 360 increases, the GIP partition blocks 361 having a larger amount of opaque areas and the clock signal line areas 363 having a larger amount of transparent areas may be alternately arranged in a differentiated manner in the GIP circuit area 360. Therefore, even in the GIP circuit area 360, it is possible to ensure that the transparent area is maximized.

[0313] In other words, according to one embodiment of the present disclosure, the VSS voltage line is omitted in a side area of ​​the non-display area NDA outside the display area DA where the GIP circuit area 360 is disposed. Fig.17 and Fig.18Therefore, the reduction of the transparent area due to the opaque VSS voltage line can be minimized.

[0314] Therefore, the light emitting tester 375 may be disposed between the barrier 380 and the GIP circuit region 360 , but the VSS voltage line may not be disposed between the barrier 380 and the GIP circuit region 360 .

[0315] As described above, the transparent display panel 300 according to the embodiment of the present disclosure includes a display area DA and a non-display area NDA, wherein the panel includes a first VSS voltage line 321 and a second VSS voltage line 322 disposed in the non-display area NDA while interposing the display area DA therebetween, and at least one VSS voltage connection line 323 electrically connects the first VSS voltage line 321 and the second VSS voltage line 322 to each other. The VSS voltage connection line 323 is disposed in the display area DA.

[0316] In this case, the second VSS voltage line 322 may be thinner than the first VSS voltage line 321 .

[0317] In addition, the display area DA includes long sides and short sides. Each of the first VSS voltage line 321 and the second VSS voltage line 322 may have a bar shape and extend along the long sides of the display area DA.

[0318] In addition, the transparent display panel 300 according to the embodiment of the present disclosure further includes a VSS voltage line connection pad 320 disposed to be spaced apart from the first VSS voltage line 321, wherein the latter is closer to the display area DA than the former. The first VSS voltage line 321 and the VSS voltage line connection pad 320 may be electrically connected to each other via the first connection electrode 351.

[0319] In this case, the display area DA includes at least one emission area EA and at least one transmission area TA. The emission area EA includes an organic light emitting element 220 having a first electrode 221, an organic light emitting layer 223, and a second electrode 225. The first connection electrode 351 is made of the same material as the first electrode 221 and can constitute the same layer therewith.

[0320] In addition, the transparent display panel 300 according to the embodiment of the present disclosure further includes a first VDD voltage line 331 and a second VDD voltage line 332 disposed in the non-display area NDA while interposing the display area DA therebetween, and at least one VDD voltage connection line 333 electrically connects the first VDD voltage line 331 and the second VDD voltage line 332 to each other. The VDD voltage connection line 333 may be disposed in the display area DA.

[0321] In addition, the first VSS voltage line 321 may be disposed between the first VDD voltage line 331 and the display area DA. The second VDD voltage line 332 may be disposed between the second VSS voltage line 322 and the display area DA.

[0322] In addition, the transparent display panel 300 according to the embodiment of the present disclosure further includes a reference voltage line 341 disposed between the first VDD voltage line 331 and the first VSS voltage line 321, and a reference voltage line connection pad 340 spaced apart from the reference voltage line 341 so that the latter is closer to the display area DA than the former. The reference voltage line 341 and the reference voltage line connection pad 340 may be electrically connected to each other via the second connection electrode 352.

[0323] In this case, the first connection electrode 351 and the second connection electrode 352 may be made of the same material and may constitute the same layer.

[0324] In addition, the light emitting area EA includes a driving thin film transistor 210 connected to the organic light emitting element 220. The driving thin film transistor 210 may include a gate electrode 214, a source electrode 217a, a drain electrode 217b, and an active layer 212. A first VSS voltage line 321, a second VSS voltage line 322, a first VDD voltage line 331, a second VDD voltage line 332, and a reference voltage line 341 are made of the same material as the source electrode 217a and the drain electrode 217b, and may constitute the same layer therewith.

[0325] The VSS voltage connection line 323 may include a first VSS voltage connection line 324 and a second VSS voltage connection line 325. The first VSS voltage connection line 324 may be made of the same material as the source 217a and the drain 217b and may constitute the same layer therewith. The second VSS voltage connection line 325 may be made of the same material as the gate 214 and may constitute the same layer therewith.

[0326] The VDD voltage connection line 333 may include a first VDD voltage connection line 334 and a second VDD voltage connection line 335. The first VDD voltage connection line 334 may be made of the same material as the source 217a and the drain 217b and may constitute the same layer therewith. The second VDD voltage connection line 335 may be made of the same material as the gate 214 and may constitute the same layer therewith.

[0327] The reference voltage connection line 343 may include a first reference voltage connection line 344 and a second reference voltage connection line 345. The first reference voltage connection line 344 may be made of the same material as the source 217a and the drain 217b and may constitute the same layer therewith. The second reference voltage connection line 345 may be made of the same material as the gate 214 and may constitute the same layer therewith.

[0328] A passivation layer 218 may be formed on the first VDD voltage line 331, the reference voltage line 341, and the first VSS voltage line 321, and a first connection electrode 351 may be formed on the passivation layer 218. On the first connection electrode 351, a bank layer 231 and a first bank hole 231a formed by removing a partial region of the bank layer 231 may be formed. A second electrode 225 may be formed on the bank layer 231. A portion of the second electrode 225 may be connected to the first connection electrode 351 via the first bank hole 231a.

[0329] At least one auxiliary line 327 may contact a bottom surface of at least one of the second VDD voltage line 332 and the second VSS voltage line 322. The auxiliary line 327 may be made of the same material as the gate electrode 214 and may constitute the same layer therewith.

[0330] In this case, the first bank hole 231 a may correspond to the reference voltage line 341 or the first VSS voltage line 321 .

[0331] On the second VSS voltage line 322, a passivation layer 218 and a passivation hole formed by removing a partial region of the passivation layer 218 may be formed. On the passivation layer 218, a third connection electrode 353 connected to the second VSS voltage line 322 via the passivation hole may be formed. On the third connection electrode 353, a bank layer 231 and a second bank hole 231b formed by removing a partial region of the bank layer 231 may be formed. The second electrode 225 may be formed on the bank layer 231. An opposing portion of the second electrode 225 may be connected to the third connection electrode 353 via the second bank hole 231b.

[0332] In this case, at least one of the first connection electrode 351 and the second connection electrode 352 may have at least one exhaust hole 355 defined therein.

[0333] In addition, the transparent display panel 300 according to another embodiment of the present disclosure may include: a display area DA including a light emitting area EA and a transmission area; a first VSS voltage line 321 and a second VSS voltage line 322, while interposing the display area DA therebetween; and a GIP circuit area 360, which is disposed in at least one side area outside the display area DA. The first VSS voltage line 321 and the second VSS voltage line 322 are electrically connected to each other via at least one VSS voltage connection line 323. The VSS voltage connection line 323 may extend across the display area DA.

[0334] In this case, the transparent display panel 300 according to another embodiment of the present disclosure may include a reference voltage line 341, a first VDD voltage line 331, and a data driver IC pad 310 that are spaced apart from the first VSS voltage line and spaced apart from each other, wherein the interval between the reference voltage line and the display area is smaller than the interval between the first VDD voltage line and the display area, and the interval between the first VDD voltage line and the display area is smaller than the interval between the data driver IC pad and the display area. Between the display area DA and the second VSS voltage line 322, a second VDD voltage line 332 may be provided. Between the first VDD voltage line 331 and the data driver IC pad 310, a first VSS voltage line connection pad, a first VDD voltage line connection pad, a reference voltage line connection pad 340, and a data line connection pad 311 may be provided.

[0335] In addition, an ESD protection circuit region 371 may be provided between the reference voltage line 341 and the first VSS voltage line 321. A MUX circuit region 373 may be provided between the display area DA and the first VSS voltage line 321. The light emission tester 375 may be spaced apart from the second VSS voltage line 322 such that the latter is closer to the display area DA than the former.

[0336] In this case, the light emitting tester 375 may be connected to the data line 313 branched from the data line connection pad 311 .

[0337] The GIP circuit region 360 may be disposed in a side region outside the display region DA different from the display region DA in which the first and second VSS voltage lines 321 and 322 are disposed.

[0338] The GIP circuit region 360 includes a GIP partition block 361 and a clock signal line region 363. The GIP partition block 361 and the clock signal line region 363 may be alternately arranged in a direction away from the display area DA.

[0339] At least one barrier 380 may extend around the periphery of the display area DA to surround the GIP circuit area 360, the light emission tester 375, and the first VDD voltage line 331. The barrier 380 may be made of the same material as the planarization layer, the bank layer, and the spacer layer and constitute the same layer as them.

[0340] An additional light emitting tester 375 may be disposed between the barrier 380 and the GIP circuit region 360. A VSS voltage line may not exist between the barrier 380 and the GIP circuit region 360.

[0341] The transparent display device 100 according to an embodiment of the present disclosure may include the transparent display panel 300 as described above, a data driver 120 for providing a data voltage to the transparent display panel 300, a gate driver 130 for providing a scan signal to the transparent display panel 300, and a timing controller 140 for controlling the gate driver 130 and the data driver 120.

[0342] As described above, the present disclosure is described with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments and drawings disclosed in this specification. It is obvious that those skilled in the art may make various modifications thereto within the scope of the present disclosure. In addition, although the effects caused by the features of the present disclosure are not explicitly described in the description of the embodiments of the present disclosure, it is obvious that the predictable effects caused by the features of the present disclosure should be recognized.

Claims

1. A display device, comprising: A display panel, the display panel comprising a display area and a non-display area adjacent to the display area; a first VSS voltage line, wherein the first VSS voltage line is in the non-display area; a second VSS voltage line, wherein the second VSS voltage line is in the non-display area; a first VDD voltage line, wherein the first VDD voltage line is in the non-display area; a second VDD voltage line, wherein the second VDD voltage line is in the non-display area; a plurality of VSS voltage connection lines, the plurality of VSS voltage connection lines electrically connecting the first VSS voltage line and the second VSS voltage line to each other; a plurality of VDD voltage connection lines, the plurality of VDD voltage connection lines electrically connecting the first VDD voltage line and the second VDD voltage line to each other; A data line connection pad, wherein a plurality of data lines are branched in the data line connection pad; A VSS voltage line connection pad, wherein the VSS voltage line connection pad is electrically connected to the first VSS voltage line; A VDD voltage line connection pad, wherein the VDD voltage line connection pad is electrically connected to the first VDD voltage line; as well as a plurality of driver ICs, wherein the data line connection pad, the VSS voltage line connection pad, and the VDD voltage line connection pad are electrically connected to one driver IC respectively, wherein the plurality of VSS voltage connection lines and the plurality of VDD voltage connection lines arranged in the display area extend across the display area, and Among them, each VSS voltage connection line and each VDD voltage connection line are arranged alternately with each other.

2. The display device according to claim 1, in, The display panel further includes a VSS voltage auxiliary line connection pad disposed between the driver IC and the first VSS voltage line.

3. The display device according to claim 1, in, The display area includes a transmissive area.

4. The display device according to claim 1, in, The display panel further includes a plurality of barriers surrounding the first VDD voltage line and the second VDD voltage line.

5. The display device according to claim 4, in, The plurality of barriers also surround the first VSS voltage line and the second VSS voltage line.

6. The display device according to claim 1, in, The display panel further includes an encapsulation layer formed of a plurality of layers in which an inorganic layer and an organic layer are stacked.

7. The display device according to claim 1, in, The display panel further includes an intra-panel gate GIP circuit region disposed in the non-display region, and a plurality of barriers surrounding the intra-panel gate GIP circuit region.

8. The display device according to claim 1, wherein: The display panel further includes a reference voltage line and a data driver IC pad, the reference voltage line and the data driver IC pad are spaced apart from each other and from the first VSS voltage line, wherein a spacing between the reference voltage line and the display area is smaller than a spacing between the first VDD voltage line and the display area, and a spacing between the first VDD voltage line and the display area is smaller than a spacing between the data driver IC pad and the display area, Wherein, the second VDD voltage line is arranged between the display area and the second VSS voltage line, and The display panel further includes a first VSS voltage line connection pad, a first VDD voltage line connection pad, a reference voltage line connection pad and a data line connection pad disposed between the first VDD voltage line and the data driver IC pad.

9. The display device according to claim 8, wherein: The display panel further includes: an electrostatic discharge protection circuit area, wherein the electrostatic discharge protection circuit area is arranged between the reference voltage line and the first VSS voltage line; a multiplexer circuit region, the multiplexer circuit region being disposed between the display region and the first VSS voltage line; and a light emitting tester spaced apart from the second VSS voltage line, wherein the second VSS voltage line is closer to the display area than the light emitting tester, and The light emitting tester is electrically connected to the data line branched from the data line connection pad.

10. The display device according to claim 1, further comprising an in-panel gate in-panel (GIP) circuit region, wherein the GIP circuit region is disposed in at least one side region outside the display region. in, The GIP circuit area is disposed in another side area outside the display area which is different from a side area outside the display area where the first VSS voltage line and the second VSS voltage line are disposed, The GIP circuit area includes a GIP partition block and a clock signal line area, and The GIP partition blocks and the clock signal line regions are arranged alternately in a direction away from the display region.

11. The display device according to claim 10, in, The display panel further includes at least one barrier extending along the periphery of the display area to surround the GIP circuit area, the light emitting tester, and the first VDD voltage line, wherein the bank layer forms the barrier, The display panel further comprises an additional light emitting tester disposed between the barrier and the GIP circuit area, and Wherein, there is no VSS voltage line between the barrier and the GIP circuit area.

12. The display device according to claim 1, wherein: The display panel further includes: A VSS voltage line connection pad, the VSS voltage line connection pad being disposed to be spaced apart from the first VSS voltage line; and a first connection electrode electrically connecting the VSS voltage line connection pad and the first VSS voltage line to each other, The light-emitting region includes an organic light-emitting element, and the organic light-emitting element includes a first electrode, an organic light-emitting layer and a second electrode, and The first connecting electrode is made of the same material as that of the first electrode, and the first connecting electrode and the first electrode form a same layer.

13. The display device according to claim 12, wherein: The first connection electrode is located between the display area and the VSS voltage line connection pad.

14. The display device according to claim 1, wherein: The light emitting region includes a driving thin film transistor, The driving thin film transistor includes a gate electrode, a source electrode, a drain electrode and an active layer, and The first VSS voltage line, the second VSS voltage line, the source electrode, and the drain electrode are made of the same material and constitute the same layer.

15. The display device according to claim 14, wherein: The at least one VSS voltage connection line includes a plurality of VSS voltage connection lines.

16. The display device according to claim 15, wherein: The at least one VSS voltage connection line includes a first VSS voltage connection line and a second VSS voltage connection line to provide a plurality of VSS voltage connection lines extending across the display area, Wherein, the first VSS voltage connection line, the source electrode and the drain electrode are made of the same material and constitute the same layer, and The second VSS voltage connection line and the gate are made of the same material and constitute the same layer.

17. The display device according to claim 7, wherein: The gate IP circuit area in the panel includes a transparent area.

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