Chip electronic component

Abstract

Provided is a chip electronic component in which a spacer and a mounting substrate are not easily separated. A chip electronic component (1) according to the present invention is provided with: a laminated ceramic capacitor (1A) provided with a laminated body (2) including internal electrode layers (5) and dielectric layers (4) arranged alternately, and external electrodes (3); when two surfaces of the laminated body (2), which face each other in the lamination direction, are defined as capacitor main surfaces (A), two surfaces of the laminated body (2), which face each other in the width direction, are defined as capacitor side surfaces (B), and two surfaces of the laminated body (2), which face each other in the length direction, are defined as capacitor end surfaces (C), the external electrodes (3) are respectively provided on the capacitor end surfaces (C). And spacers (10) that are disposed on both sides in the longitudinal direction of the capacitor main surface (A) on the mounting substrate side of the laminated ceramic capacitor (1A), and that, when two surfaces of the spacers (10) that face each other in the lamination direction are defined as spacer main surfaces (AS), have recesses (11) formed in the surface of the spacer main surfaces (AS) on the mounting substrate side.

Description

Technical Field

[0001] The present invention relates to a chip-type electronic component. Background Art

[0002] A laminated ceramic capacitor has a laminate and external electrodes disposed on both end surfaces of the laminate in the long side direction, and the laminate has an inner layer portion in which dielectric layers and internal electrodes are alternately stacked. Here, if a voltage is applied to the laminated ceramic capacitor, the dielectric layer is sometimes polarized, and the laminated ceramic capacitor vibrates in the polarization direction. Then, the vibration is transmitted to the mounting substrate, and cracks may be generated in the mounting substrate. Therefore, there is a technology in the past that a spacer is arranged on the mounting surface side of the laminated ceramic capacitor to make a chip-type electronic component, and the spacer cushions the vibration to suppress the vibration transmitted to the mounting substrate (see Patent Document 1).

[0003] Prior Art Literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2015 / 098990 Summary of the invention

[0006] Problems to be solved by the invention

[0007] However, for example, if a material with a high dielectric constant is used as a component of the dielectric layer, the vibration becomes large. Therefore, if the bonding force between the mounting substrate and the spacer is weak, the spacer may be peeled off from the mounting substrate.

[0008] An object of the present invention is to provide a chip-type electronic component in which a spacer and a mounting substrate are not easily separated.

[0009] Technical solutions to solve problems

[0010] In order to solve the above-mentioned problems, the present invention provides a chip-type electronic component, comprising: a stacked ceramic capacitor, comprising a stacked body and external electrodes, the stacked body including a plurality of internal electrode layers and a plurality of internal dielectric layers arranged alternately with each other, when two surfaces of the stacked body facing each other in a stacking direction are set as capacitor main surfaces, two surfaces of the stacked body facing each other in a width direction intersecting the stacking direction are set as capacitor side surfaces, and two surfaces of the stacked body facing each other in a length direction intersecting the stacking direction and the width direction are set as capacitor end surfaces, the external electrodes are respectively arranged on the capacitor end surfaces; and a spacer, arranged on both sides of the length direction of the capacitor main surface on the mounting substrate side of the stacked ceramic capacitor, when two surfaces of the spacer facing each other in the stacking direction are set as spacer main surfaces, a recess is formed on the surface of the spacer main surface on the mounting substrate side.

[0011] Effects of the Invention

[0012] According to the present invention, it is possible to provide a chip-type electronic component in which a spacer and a mounting substrate are unlikely to be separated. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic perspective view of a chip-type electronic component 1 according to the embodiment.

[0014] Figure 2 It is a chip electronic component 1 along Figure 1 A partial cross-sectional view of line II-II in FIG.

[0015] Figure 3 It is a chip electronic component 1 along Figure 1 Cross-sectional view along line III-III.

[0016] Figure 4 This is a diagram in which the second spacer main surface AS2 of the spacer 10 faces upward.

[0017] Figure 5 1 is a flowchart for explaining a method for manufacturing the chip-type electronic component 1 .

[0018] Figure 6 This is a partial cross-sectional view of a modified form of the chip-type electronic component 1 . DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present invention will be described. Figure 1 It is a schematic perspective view of a chip-type electronic component 1 according to the embodiment. Figure 2 It is a chip electronic component 1 along Figure 1 A partial cross-sectional view of line II-II in FIG. Figure 3 It is a chip electronic component 1 along Figure 1 Cross-sectional view along line III-III. Figure 1 , Figure 2 as well as Figure 3 The state joined to the mounting substrate 210 is shown.

[0020] The chip-type electronic component 1 includes a laminated ceramic capacitor 1A and a spacer 10 mounted on the laminated ceramic capacitor 1A. The laminated ceramic capacitor 1A includes a laminated body 2 having a substantially rectangular parallelepiped shape and a pair of external electrodes 3 provided at both ends of the laminated body 2. In addition, the laminated body 2 includes an inner layer portion 6, and the inner layer portion 6 includes a plurality of sets of dielectric layers 4 and internal electrode layers 5.

[0021] In the following description, as a term indicating the orientation of the chip electronic component 1, the direction in which the pair of external electrodes 3 are provided is referred to as the length direction L. The direction in which the dielectric layer 4 and the internal electrode layer 5 are stacked is referred to as the stacking direction T. The direction intersecting both the length direction L and the stacking direction T is referred to as the width direction W. In the embodiment, the width direction W is orthogonal to both the length direction L and the stacking direction T.

[0022] In addition, among the six outer surfaces of the stacked body 2, a pair of outer surfaces opposite to each other in the stacking direction T are set as the first capacitor main surface A1 and the second capacitor main surface A2, a pair of outer surfaces opposite to each other in the width direction W are set as the first capacitor side surface B1 and the second capacitor side surface B2, and a pair of outer surfaces opposite to each other in the length direction L are set as the first capacitor end surface C1 and the second capacitor end surface C2.

[0023] In addition, when there is no need to distinguish between the first capacitor main surface A1 and the second capacitor main surface A2, they are uniformly described as the capacitor main surface A; when there is no need to distinguish between the first capacitor side surface B1 and the second capacitor side surface B2, they are uniformly described as the capacitor side surface B; when there is no need to distinguish between the first capacitor end surface C1 and the second capacitor end surface C2, they are uniformly described as the capacitor end surface C.

[0024] (Laminate 2)

[0025] The laminate 2 includes an inner layer portion 6, an outer layer portion 7 disposed on the capacitor main surface A side of the inner layer portion 6, and a side gap portion 8. The laminate 2 preferably has rounded corners at the ridgeline portion R. The ridgeline portion R is a portion where two surfaces of the laminate 2, i.e., the capacitor main surface A and the capacitor side surface B, the capacitor main surface A and the capacitor end surface C, or the capacitor side surface B and the capacitor end surface C intersect, and also includes a corner where the capacitor main surface A, the capacitor side surface B, and the capacitor end surface C intersect.

[0026] (Inner layer 6)

[0027] The inner layer portion 6 includes a plurality of sets of dielectric layers 4 and internal electrode layers 5 alternately stacked in the stacking direction T.

[0028] (Dielectric layer 4)

[0029] The dielectric layer 4 is made of a ceramic material. As the ceramic material, for example, a dielectric ceramic having BaTiO3 as a main component can be used. In addition, as the ceramic material, a material having at least one of the auxiliary components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and nickel compounds added to these main components can also be used.

[0030] (Internal electrode layer 5)

[0031] The internal electrode layer 5 is preferably formed of a metal material represented by nickel, Cu, Ag, Pd, Ag—Pd alloy, Au, or the like.

[0032] The internal electrode layer 5 includes a plurality of first internal electrode layers 5A and a plurality of second internal electrode layers 5B. The first internal electrode layers 5A and the second internal electrode layers 5B are arranged alternately. In addition, when there is no need to distinguish the first internal electrode layers 5A and the second internal electrode layers 5B in particular, they are collectively described as the internal electrode layers 5.

[0033] The internal electrode layer 5 includes an opposing portion 52 that is opposed to each other between the first internal electrode layer 5A and the second internal electrode layer 5B, and a lead portion 51 that is not opposed to each other between the first internal electrode layer 5A and the second internal electrode layer 5B and is led out from the opposing portion 52 to one capacitor end surface C. The end of the lead portion 51 is exposed at the capacitor end surface C and is electrically connected to the external electrode 3. The direction in which the lead portion 51 extends is different between the first internal electrode layer 5A and the second internal electrode layer 5B, and is alternately led out to the first capacitor end surface C1 side and the second capacitor end surface C2 side. Then, electric charges are accumulated between the opposing portions 52 of the first internal electrode layer 5A and the second internal electrode layer 5B that are adjacent in the stacking direction T, and function as a capacitor.

[0034] (Outer layer 7)

[0035] The outer layer portion 7 is disposed on both capacitor main surface A sides of the inner layer portion 6 , and is made of the same material as the dielectric layer 4 of the inner layer portion 6 .

[0036] (Side gap 8)

[0037] The side gaps 8 are provided on both capacitor side faces B of the inner layer portion 6 in the laminate 2. The side gaps 8 are made of the same material as the dielectric layer 4 and are integrally formed therewith.

[0038] (External electrode 3)

[0039] The external electrodes 3 are provided on both capacitor end faces C of the laminate 2. That is, the first external electrode 3A is formed on the first capacitor end face C1, and the second external electrode 3B is formed on the second capacitor end face C2. The external electrodes 3 cover not only the capacitor end faces C but also a portion of the capacitor main face A and the capacitor side face B on the capacitor end face C side. The external electrodes 3 include a base electrode layer 30 and a plating layer 31 formed on the periphery of the base electrode layer 30.

[0040] (Base electrode layer 30)

[0041] The base electrode layer 30 is electrically connected to the end of the lead portion 51 of the internal electrode layer 5 exposed at the capacitor end surface C. In the embodiment, the base electrode layer 30 is a so-called sintered electrode formed by sintering a conductive paste containing a conductive metal such as copper, nickel, silver, palladium, silver-palladium alloy, gold, etc., and the sintered electrode contains a glass component and a metal. The glass component contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The sintered electrode is formed by applying a conductive paste containing glass and metal to the stacked body 2 and sintering it, and can be sintered simultaneously with the internal electrode layer 5 and the dielectric layer 4, or can be sintered after the internal electrode layer 5 is sintered. In addition, when sintering simultaneously with the internal electrode layer 5 and the dielectric layer 4, it is preferable to add a dielectric material instead of the glass component to form the sintered electrode.

[0042] (Plating layer 31)

[0043] The plating layer 31 includes a Ni plating layer 31a arranged on the periphery of the base electrode layer 30 to cover the base electrode layer 30, and a Sn plating layer 31b arranged on the periphery of the Ni plating layer 31a to cover the Ni plating layer 31a. The Ni plating layer 31a can prevent the base electrode layer 30 from being corroded by the solder when the ceramic electronic component is mounted, and the Sn plating layer 31b can improve the wettability of the solder when the multilayer ceramic capacitor 1A is mounted, making it easy to mount. The Ni plating layer 31a includes plating of nickel or an alloy containing nickel. The Sn plating layer 31b includes plating of Sn or an alloy containing Sn. In addition to the above-mentioned metals, the plating layer 31 may also include at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0044] (Spacer 10)

[0045] The spacer 10 includes a first spacer 10A and a second spacer 10B as a pair of two spacers. In the following, when it is not necessary to distinguish between the first spacer 10A and the second spacer 10B for description, the spacer 10 will be described. The first spacer 10A is arranged on one side of the second capacitor main surface A2 side of the multilayer ceramic capacitor 1A in the longitudinal direction L, and the second spacer 10B is arranged on the other side. The first spacer 10A and the second spacer 10B have the same substantially rectangular shape and are opposed to each other and are arranged at a certain distance apart.

[0046] The spacer 10 is a roughly rectangular parallelepiped, and a pair of outer surfaces opposite to each other in the stacking direction T among the six outer surfaces are set as the first spacer main surface AS1 and the second spacer main surface AS2, a pair of outer surfaces opposite to each other in the width direction W are set as the first spacer side surface BS1 and the second spacer side surface BS2, and a pair of outer surfaces opposite to each other in the length direction L are set as the first spacer end surface CS1 and the second spacer end surface CS2.

[0047] The first spacer main surface AS1 is a surface on the laminated body 2 side, and the second spacer main surface AS2 is a mounting surface to be mounted on the mounting substrate 210 .

[0048] The first spacer main surface AS1 of the first spacer 10A contacts the second capacitor main surface A2 side of the first external electrode formed on the first capacitor end surface C1 , and the first spacer main surface AS1 of the second spacer 10B contacts the second capacitor main surface A2 side of the first external electrode formed on the second capacitor end surface C2 .

[0049] The cross-sectional shape of the spacer 10 perpendicular to the stacking direction T is a rectangle whose sides extending in the length direction L are short sides and whose sides extending in the width direction W are long sides. The first spacer side surface BS1 and the second spacer side surface BS2 are surfaces along the short sides of the spacer 10, and the first spacer end surface CS1 and the second spacer end surface CS2 are surfaces along the short sides of the spacer 10.

[0050] The first spacer end surface CS1 of the first spacer 10A is formed on the first capacitor end surface C1 side of the first external electrode 3A, and the second spacer end surface CS2 of the second spacer 10B is formed on the second capacitor end surface C2 side of the second external electrode 3B.

[0051] In addition, when there is no need to specifically distinguish between the first spacer main surface AS1 and the second spacer main surface AS2 for description, they are uniformly described as the spacer main surface AS; when there is no need to specifically distinguish between the first spacer side surface BS1 and the second spacer side surface BS2 for description, they are uniformly described as the spacer side surface BS; when there is no need to specifically distinguish between the first spacer end surface CS1 and the second spacer end surface CS2 for description, they are uniformly described as the spacer end surface CS.

[0052] The spacer 10 is not limited to a rectangular parallelepiped shape, and may be another hexahedral shape in which the area of ​​the first spacer main surface AS1 is larger than the area of ​​the second spacer main surface AS2. In addition, the spacer side surface BS and the spacer end surface CS may not be arranged perpendicularly to the second spacer main surface AS2 as the mounting surface. Furthermore, for example, the first spacer side surface BS1, the second spacer side surface BS2, the first spacer end surface CS1, and the second spacer end surface CS2 may also be curved surfaces.

[0053] The spacer 10 is made of a so-called high temperature solder having an intermetallic compound containing a high melting point metal and a low melting point metal as a main component. In this specification, the so-called main component means that the content is 50% or more. If the intermetallic compound is used as the main component, the reaction speed is fast and the shape change is small.

[0054] The high melting point metal includes at least one of Cu and Ni, and the low melting point metal includes Sn. In this way, when the intermetallic compound including the high melting point metal including at least one of Cu and Ni and the low melting point metal including Sn is used as the main component, it has a melting point that does not melt even at the welding temperature, and can be arranged while maintaining the desired form during welding. In addition, as the intermetallic compound, the intermetallic compound generated by the reaction of Sn and Cu-Ni alloy is particularly preferred. In addition, as the high melting point metal constituting the intermetallic compound, Ag may also be included.

[0055] (Conductive resin)

[0056] In addition, the spacer 10 may be made of a conductive resin. The conductive resin includes metal and thermosetting resin. When the spacer 10 is made of a conductive resin, since it includes resin, it is more flexible than, for example, a conductive layer including a plated film or a sintered product of a conductive paste.

[0057] (Metal in conductive resin)

[0058] As the metal contained in the conductive resin, Ag, Cu, or their alloys can be used. In addition, a material coated with Ag on the surface of the metal powder can be used. When using a material coated with Ag on the surface of the metal powder, Cu and Ni are preferably used as metal powders. In addition, a material to which Cu has been subjected to an oxidation resistance treatment can also be used. The metal contained in the conductive resin preferably contains more than 35 vol% and less than 75 vol% relative to the volume of the entire conductive resin. The metal contained in the conductive resin can use spherical, flat, and other materials, but it is preferred to use a mixture of spherical metal powder and flat metal powder. The average particle size of the metal contained in the conductive resin is not particularly limited. For example, the average particle size of the conductive filler can also be more than 0.3 μm and less than 10 μm. The metal contained in the conductive resin mainly bears the electrical conductivity of the conductive resin. Specifically, the conductive fillers are in contact with each other, thereby forming an electrical path inside the conductive resin.

[0059] (Conductive resin)

[0060] As the resin contained in the conductive resin, for example, various known thermosetting resins such as epoxy resin, phenolic resin, polyurethane resin, silicone resin, polyimide resin, etc. can be used. Among them, epoxy resin with excellent heat resistance, moisture resistance, adhesion, etc. is one of the most suitable resins. The resin contained in the conductive resin preferably contains more than 25vol% and less than 65vol% relative to the volume of the conductive resin as a whole. In addition, in the conductive resin, it is preferred to contain a curing agent together with the thermosetting resin. As a curing agent, when using epoxy resin as a base resin, various known compounds such as phenolic, amine, anhydride, and imidazole can be used as a curing agent for the epoxy resin.

[0061] (Surface shape)

[0062] The spacer 10 has a recessed portion 11 formed on the surface of the second spacer main surface AS2 serving as a mounting surface. A plurality of recessed portions 11 are formed. Figure 4 The figure shows the second spacer main surface AS2 of the spacer 10 facing upward. According to the present embodiment, a recess 11 is formed on the surface on the second spacer main surface AS2 side, so that when the chip electronic component 1 is mounted on the mounting substrate 210, the solder 240 enters the recess 11, and the fixing force between the solder 240 and the spacer 10 can be improved through the anchoring effect.

[0063] (Total opening area of ​​the recess 11)

[0064] The total opening area of ​​the recessed portions 11 is preferably not less than 25% and not more than 75% of the surface area of ​​the second spacer main surface AS2 .

[0065] The reason is that if the total opening area of ​​the recessed portion 11 is greater than 75% of the area of ​​the second spacer main surface AS2, the solder 240 is mostly captured by the recessed portion 11, and it becomes difficult for the solder 240 to go around the spacer end surface CS and the spacer side surface BS of the spacer 10, so the bonding strength between the spacer 10 and the mounting substrate 210 is weakened. If the total opening area of ​​the recessed portion 11 is less than 25% of the area of ​​the entire second spacer main surface AS2, the bonding area between the solder 240 and the spacer 10 is reduced, so the anchoring effect with the solder 240 cannot be fully obtained.

[0066] The total opening area of ​​the recessed portion 11 of the spacer 10 is the total area of ​​the opening of the recessed portion 11 when viewed from the second spacer main surface AS2 side.

[0067] (Definition of Recessed Portion 11)

[0068] The second spacer main surface AS2 of the spacer 10 is not flat, but is provided with projections and depressions. Here, the distance in the stacking direction T between the most protruding position on the second spacer main surface AS2 of the spacer 10, that is, the top of the projection, and the first spacer main surface AS1 is set as the thickness of the spacer 10. Moreover, if it is assumed that the second spacer main surface AS2 is in contact with the flat surface, the flat surface is in contact with the top of the projection of the second spacer main surface AS2. The portion within 1% of the thickness of the spacer 10 from the position of the flat surface, that is, the top of the projection toward the first spacer main surface AS1 is considered to be included in the flat surface of the second spacer main surface AS2, and the portion that is more recessed than 1% of the thickness of the spacer 10 is defined as the recess 11.

[0069] (Opening area of ​​one recess 11)

[0070] The opening area of ​​one recess 11 is preferably not less than 0.1% and not more than 70% of the surface area of ​​the second spacer main surface AS2.

[0071] The reason is that if the opening area of ​​one recess 11 is larger than 70% of the area of ​​the second spacer main surface AS2, the solder 240 is excessively captured by the recess 11, and it becomes difficult for the solder 240 to go around the spacer end surface CS and the spacer side surface BS of the spacer 10, so the bonding strength between the spacer 10 and the mounting substrate 210 may be reduced. If the opening area of ​​one recess 11 is less than 0.1% of the area of ​​the second spacer main surface AS2, the solder 240 does not sufficiently enter the recess 11 of the spacer 10, and therefore cannot be sufficiently affected by the anchoring effect.

[0072] The opening area of ​​one recess 11 is more preferably 0.5% to 65% of the area of ​​the second spacer main surface AS2 , further preferably 1% to 60%, and particularly preferably 5% to 50%.

[0073] (Number of recesses 11)

[0074] The number of recesses 11 is appropriately selected so as to meet the above-mentioned conditions of the total opening area of ​​the recesses 11 and the opening area of ​​one recess 11 .

[0075] (Internal shape of recess 11)

[0076] The shape of the interior of the recess 11 is not particularly limited, and may be, for example, a tapered shape that becomes thinner as it approaches the first spacer main surface AS1 from the second spacer main surface AS2 or an octopus pot shape whose interior is larger than the opening.

[0077] (Depth of recess 11)

[0078] The depth of the recess 11 is preferably not less than 1% and not more than 50% of the thickness of the spacer 10 in the stacking direction T. The stacking direction T is the direction in which the dielectric layer 4 and the internal electrode layer 5 in the above-mentioned multilayer ceramic capacitor 1A are stacked, and in the case of the spacer 10, it is the direction connecting the first spacer main surface AS1 and the second spacer main surface AS2.

[0079] The “depth” refers to the length of the recess 11 in the stacking direction T from the opening to the bottom.

[0080] The reason why the depth of the recess 11 is preferably 1% or more of the thickness of the spacer 10 in the stacking direction T is that if the depth of the recess 11 is less than 1%, the surface becomes smooth and it is difficult to obtain the anchor effect described later.

[0081] The reason why the depth of the recess 11 is preferably less than 50% of the thickness of the spacer 10 in the stacking direction T is that if the depth of the recess 11 is greater than 50%, the length of the stacking direction T of the portion of the spacer 10 where the recess 11 is provided becomes shorter, and thus the mechanical strength of the spacer 10 may become lower.

[0082] In the embodiment, the recesses 11 are a mixture of the recesses 11 of 1% or more and less than 5% and the recesses 11 of 5% or more. In addition, the average depth of the recesses 11 of 5% or more is more preferably 5% or more and 35% or less of the thickness of the spacer 10 in the stacking direction T, and further preferably 10% or more and 20% or less. The recesses 11 are preferably a mixture of the recesses 11 of 1% or more and less than 5% and the recesses 11 of 5% or more. The recesses 11 may be only the recesses 11 of 1% or more and less than 5%, or only the recesses 11 of 5% or more.

[0083] (Side and end)

[0084] The recessed portion 11 is preferably formed also on the surfaces of two spacer end faces CS facing each other in the longitudinal direction L of the spacer 10. Furthermore, the recessed portion 11 is preferably formed also on the surfaces of two spacer side faces BS facing each other in the width direction W of the spacer 10.

[0085] In this way, if the recess 11 is also arranged on the surface of the spacer end surface CS and the surface of the spacer side surface BS, the solder 240 wets and climbs onto the surface of the spacer end surface CS and the spacer side surface BS, thereby improving the fixing force between the solder 240 and the external electrode 3.

[0086] However, the recessed portion 11 of the spacer 10 may not be provided on other surfaces as long as it is provided on the second spacer main surface AS2. Furthermore, when provided on other surfaces, it may not be arranged on all surfaces but on a part of the surfaces. The part of the surface may be any surface.

[0087] For example, as long as the recessed portion 11 is provided on the second spacer main surface AS2 , it may be disposed on both or only one of the spacer side surfaces BS, and may be disposed on both or only one of the spacer end surfaces CS.

[0088] In the case of configuring one, the recess 11 is preferably formed on the end surface CS1 of the first spacer 10A and the end surface CS2 of the second spacer 10B. Since the solder 240 that is to be wetted and climbed on the first spacer end surface CS1 and the second spacer end surface CS2 is absorbed by the recess 11 of the end surface CS1 of the first spacer 10A and the recess 11 of the end surface CS2 of the second spacer 10B, it is possible to suppress the formation of excessive fillets. In addition, as long as the recess 11 of the spacer 10 is provided on the second spacer main surface AS2, it can be configured on different surfaces in the first spacer 10A and the second spacer 10B.

[0089] (Mounting substrate 210)

[0090] The mounting substrate 210 on which the chip electronic component 1 is mounted has lands 230 . The lands 230 include first lands 230A and second lands 230B. The first spacer 10A is connected to the first land 230A by solder 240 , and the second spacer 10B is connected to the second land 230B by solder 240 .

[0091] Here, the recessed portion 11 is formed on the surface on the second spacer main surface AS2 side, and the solder 240 enters the recessed portion 11. Therefore, the chip-type electronic component 1 and the mounting substrate 210 are bonded with a high fixing force due to the anchor effect.

[0092] (Method for Manufacturing Chip-Type Electronic Component 1)

[0093] Next, a method for manufacturing the chip type electronic component 1 according to the embodiment will be described. Figure 5 1 is a flowchart for explaining a method for manufacturing the chip-type electronic component 1 .

[0094] The manufacturing process of the chip-type electronic component 1 includes a laminate manufacturing process S1 , an external electrode forming process S2 , a spacer arranging process S3 , and a recess forming process S4 .

[0095] (Laminate Manufacturing Step S1)

[0096] First, in the laminate manufacturing process S1, a raw material sheet having a pattern of an internal electrode layer 5 printed on a conductive paste for a laminated ceramic green sheet formed into a sheet shape by a ceramic slurry is prepared. Then, a plurality of raw material sheets are stacked so that the internal electrode pattern is staggered by half a pitch in the length direction between adjacent raw material sheets. In addition, ceramic green sheets for the outer layer portion that will become the outer layer portion are stacked on both sides of the laminated raw material sheets, and a mother block component is formed by thermal compression. A plurality of laminates 2 are manufactured by dividing the mother block component along a cutting line corresponding to the size of the laminate.

[0097] (External Electrode Forming Step S2)

[0098] Next, in the external electrode forming step S2, external electrodes 3 are formed at both ends of the laminate 2. First, for example, a conductive paste containing a conductive metal and glass is applied to both ends of the laminate 2 and baked to form the base electrode layer 30. Figure 2 As shown, the base electrode layer 30 is formed to not only cover the capacitor end faces C on both sides of the laminate 2 but also extend to the capacitor main face A side to also cover a portion of the capacitor main face A on the capacitor end face C side.

[0099] Next, first, a Ni plating layer 31a is formed on the periphery of the base electrode layer 30 so as to cover the base electrode layer 30. Next, a Sn plating layer 31b is formed on the periphery of the Ni plating layer 31a so as to cover the Ni plating layer 31a. Through the above steps, a laminated ceramic capacitor 1A having external electrodes 3 formed on the laminated body 2 is manufactured.

[0100] (Spacer Arrangement Step S3)

[0101] In the spacer disposing step S3 , an intermetallic compound paste serving as a material of the spacer 10 is disposed on the outer periphery of the external electrode 3 on the second capacitor main surface A2 side in the multilayer ceramic capacitor 1A.

[0102] The intermetallic compound paste is a so-called high-temperature solder having an intermetallic compound as a main component that contains at least one of Cu and Ni as a high-melting-point metal and Sn as a low-melting-point metal.

[0103] Such an intermetallic compound paste is disposed on the surface of the Sn plating layer 31 b in a liquid state that is temporarily melted at 200° C. or higher.

[0104] The high temperature solder has a melting point that does not melt even at a normal soldering temperature, and can be arranged while maintaining a desired shape even during soldering.

[0105] (Recessed portion forming step S4)

[0106] Before the high temperature solder solidifies, the intermetallic compound paste is bonded from the second main surface side to a plate having desired concavities and convexities that is not bonded to the high temperature solder, such as an alumina plate. After the intermetallic compound paste solidifies, the alumina plate is removed. Thus, the recess 11 can be formed on the second spacer main surface AS2 of the spacer 10.

[0107] The recessed portion 11 on the spacer end surface CS and the spacer side surface BS can be formed by arranging the alumina plate so as to wrap around the end surface and the side surface.

[0108] The area and depth of the recessed portion 11 can be adjusted by adjusting the area, height, and depth of the recesses and projections formed on the alumina plate.

[0109] In addition, when forming the recessed portion 11 with a depth of 5% or more of the thickness in the stacking direction T of the spacer 10, such a method of making the alumina plate abut is suitable. In addition, when the depth of the recessed portion 11 is 1% or more and less than 5% of the thickness in the stacking direction T of the spacer 10, a method of forming the recessed portion 11 by sandblasting or the like is suitable. However, regardless of the depth of the recessed portion 11, the recessed portion 11 can be formed by any method.

[0110] The method for forming the recess 11 is not limited thereto, and other methods may be used. For example, the recess may be formed by roughening the solidified surface of the intermetallic compound paste with a file or the like after the solidification, or by chemical methods such as etching.

[0111] Through the above steps, the chip-type electronic component 1 can be manufactured.

[0112] As described above, according to the chip electronic component 1 of this embodiment, since a recess 11 is formed on the surface on the second spacer main surface AS2 side, when the chip electronic component 1 is mounted on the mounting substrate 210, the solder 240 enters the recess 11, and the fixing force between the solder 240 and the spacer 10 can be improved through the anchoring effect.

[0113] In addition, there is not only solder 240 such as Figure 2 In the case where the spacer 10 and the connection plate 230 are arranged as shown, there is also a case where Figure 6 As shown in FIG. 1 , the solder 240 covers the spacer 10 and covers the side surfaces of the external electrodes 3. The spacer 10 of the embodiment also has recesses 11 formed on the surface of the spacer end surface CS and the surface of the spacer side surface BS. Figure 6 When the solder 240 covers the spacer 10 and covers the side of the external electrode 3 as shown, the solder 240 enters the surface of the spacer end face CS and the recess 11 on the surface of the spacer side face BS, thereby further improving the fixing force between the solder 240 and the spacer 10 through a stronger anchoring effect.

[0114] As mentioned above, although the preferred embodiment of the present invention was described, the present invention includes the following combinations.

[0115] <1> A chip-type electronic component comprises: a stacked ceramic capacitor having a stacked body and external electrodes, the stacked body including a plurality of internal electrode layers and a plurality of internal dielectric layers arranged alternately, wherein when two surfaces of the stacked body facing each other in a stacking direction are set as capacitor main surfaces, two surfaces of the stacked body facing each other in a width direction intersecting the stacking direction are set as capacitor side surfaces, and two surfaces of the stacked body facing each other in a length direction intersecting the stacking direction and the width direction are set as capacitor end surfaces, the external electrodes are respectively arranged on the capacitor end surfaces; and a spacer arranged on both sides of the length direction of the capacitor main surface on the mounting substrate side of the stacked ceramic capacitor, when two surfaces of the spacer facing each other in the stacking direction are set as spacer main surfaces, a recess is formed on the surface of the spacer main surface on the mounting substrate side.

[0116] <2> exist <1> In the described chip-type electronic component, the spacer contains an intermetallic compound containing a high melting point metal and a low melting point metal as a main component.

[0117] <3> exist <2> In the described chip-type electronic component, the high melting point metal includes at least one of Cu and Ni, and the low melting point metal includes Sn.

[0118] <4> exist <1> In the described chip-type electronic component, the spacer is made of a conductive resin.

[0119] <5> exist <1> to <4> In the chip-type electronic component described in any one of the above, a total opening area of ​​the recessed portions of the spacer is 25% or more and 75% or less of a surface area of ​​a main surface of the spacer on the mounting substrate side.

[0120] <6> exist <1> to <5> In the chip-type electronic component described in any one of the above, an opening area of ​​one of the recessed portions of the spacer is not less than 0.1% and not more than 70% of a surface area of ​​a main surface of the spacer on the mounting substrate side.

[0121] <7> exist <1> to <6> In the chip-type electronic component described in any one of the above, a depth of the recessed portion in the stacking direction is not less than 1% and not more than 50% of a thickness of the spacer in the stacking direction.

[0122] <8> exist <1> to <7> In the chip-type electronic component described in any one of the above, recessed portions are formed on surfaces of two spacer end faces CS of the spacer that face each other in the longitudinal direction.

[0123] <9> exist <1> to <8> In the chip-type electronic component described in any one of the above, recessed portions are formed on surfaces of two side surfaces of the spacer that are opposed to each other in the width direction.

[0124] exist <1> to <9> In the chip electronic component described in any one of the items, when one of the two capacitor end faces in the stack is set as the first capacitor end face, the other is set as the second capacitor end face, the surface of the two capacitor main faces on the spacer side is set as the second capacitor main face, and when the two spacer end faces of each of the spacers that are opposite to each other in the longitudinal direction are set as the first spacer end face and the other is set as the second spacer end face, the spacer comprises: a first spacer that is in contact with a portion of a first external electrode that is arranged on the first capacitor end face side and extends on the second capacitor main face; and a second spacer that is in contact with a portion of a second external electrode that is arranged on the second capacitor end face side and extends on the second capacitor main face, a recess is formed on the first spacer end face of the first spacer that is a surface on the first capacitor end face side, and a recess is formed on the second spacer end face of the second spacer that is a surface on the second capacitor end face side.

[0125] Description of Reference Numerals

[0126] A Main surface of capacitor

[0127] B Capacitor side

[0128] C Capacitor end face

[0129] AS Spacer Main Surface

[0130] AS1 Main surface of the first spacer

[0131] AS2 Second spacer main surface

[0132] BS Spacer Side

[0133] CS Spacer End Face

[0134] 1 Chip electronic components

[0135] 1A Multilayer Ceramic Capacitors

[0136] 2 Laminated body

[0137] 3 External electrodes

[0138] 4 Dielectric layer

[0139] 5 Internal electrode layer

[0140] 10 Spacer

[0141] 10A 1st spacer

[0142] 10B Second spacer

[0143] 11 recess

[0144] 210 Mounting base plate

[0145] 230 Connection plate

[0146] 230A 1st connection plate

[0147] 230B 2nd connection plate

[0148] 240 Solder.

Claims

1. A chip-type electronic component, comprising: A laminated ceramic capacitor, comprising a laminate and external electrodes, the laminate comprising a plurality of internal electrode layers and a plurality of internal dielectric layers alternately arranged, wherein when two surfaces of the laminate facing each other in a lamination direction are set as capacitor main surfaces, two surfaces of the laminate facing each other in a width direction intersecting the lamination direction are set as capacitor side surfaces, and two surfaces of the laminate facing each other in a length direction intersecting the lamination direction and the width direction are set as capacitor end surfaces, the external electrodes are respectively provided on the capacitor end surfaces; and spacers are arranged on both sides of the main surface of the capacitor on the mounting substrate side of the multilayer ceramic capacitor in the longitudinal direction, When two surfaces of the spacer that are opposed to each other in the stacking direction are defined as spacer main surfaces, a recessed portion is formed on a surface of the spacer main surface on the mounting substrate side.

2. The chip-type electronic component according to claim 1, wherein: The spacer includes an intermetallic compound containing a high melting point metal and a low melting point metal as a main component.

3. The chip-type electronic component according to claim 2, wherein: The high melting point metal comprises at least one of Cu and Ni, The low melting point metal includes Sn.

4. The chip-type electronic component according to claim 1, wherein: The spacer is made of conductive resin.

5. The chip-type electronic component according to claim 1, wherein: A total opening area of ​​the recessed portions of the spacer is not less than 25% and not more than 75% of a surface area of ​​a main surface of the spacer on the mounting substrate side.

6. The chip-type electronic component according to claim 1, wherein: An opening area of ​​one of the recessed portions of the spacer is not less than 0.1% and not more than 70% of a surface area of ​​a main surface of the spacer on the mounting substrate side.

7. The chip-type electronic component according to claim 1, wherein: A depth of the recessed portion in the stacking direction is not less than 1% and not more than 50% of a thickness of the spacer in the stacking direction.

8. The chip-type electronic component according to claim 1, wherein: The spacer has recessed portions formed on surfaces of two spacer end surfaces that face each other in the longitudinal direction.

9. The chip-type electronic component according to claim 1, wherein: The spacer has recessed portions formed on surfaces of two side surfaces of the spacer that are opposed to each other in the width direction.

10. The chip-type electronic component according to claim 1, wherein One of the two capacitor end surfaces in the stack is set as a first capacitor end surface, the other is set as a second capacitor end surface, and the surface on the spacer side of the two capacitor main surfaces is set as a second capacitor main surface, and When one of the two spacer end faces facing each other in the longitudinal direction in each of the spacers is set as a first spacer end face and the other is set as a second spacer end face, The spacer has: a first spacer in contact with a portion of the first external electrode disposed on the first capacitor end surface side, which extends on the second capacitor main surface side, among the external electrodes; and a second spacer in contact with a portion of the second external electrode disposed on the second capacitor end surface side extending on the second capacitor main surface side among the external electrodes; A recess is formed on a first spacer end surface, which is a surface of the first spacer on the first capacitor end surface side. A recessed portion is formed on a second spacer end surface, which is a surface of the second spacer on the second capacitor end surface side.

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