Scaling for post-die advanced IC package

Abstract

Embodiments of the present disclosure relate to systems, software applications, and methods for digital lithography for semiconductor packages. The method includes comparing a location of the via and a via location, generating location data based on comparing the location of the via and the via location, providing the location data of the via to a digital lithography device, updating a redistribution metal layer (RDL) mask pattern according to the location data such that the RDL location corresponds to the location of the via, and providing the RDL mask pattern to the digital lithography device. And projecting the RDL mask pattern with a digital lithography device.

Description

[0001] Related Applications

[0002] This application claims the benefit of and priority to U.S. Application No. 63 / 379,936, filed on October 18, 2022, and U.S. Application No. 63 / 380,223, filed on October 19, 2022, which are incorporated herein by reference in their entirety for all purposes. Technical Field

[0003] Embodiments of the present disclosure relate generally to lithography systems. More particularly, embodiments of the present disclosure relate to systems, software applications, and methods for digital lithography of semiconductor packaging. Background Art

[0004] Electronic packaging and assembly are commonly used to connect small-sized integrated circuits (ICs) to an interconnect substrate, such as a printed circuit board (PCB) or an interposer. The PCB typically includes multiple passive devices and ICs to build a microelectronic device, and the interposer is a connecting board embedded in the packaged chip with multiple small chip ICs on the interposer. The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic devices (such as transistors, diodes, resistors, and capacitors). In large part, the increase in integration density is due to the iterative reduction of the minimum feature size, which allows more components to be integrated into a given area. As the demand for ever-shrinking electronic devices grows, the need for smaller and more innovative packaging technologies for semiconductor die has emerged.

[0005] For the reasons stated above, there is a need for a lithography system, software application, and method for semiconductor packaging. Summary of the invention

[0006] In one embodiment, a method is provided. The method includes comparing positions of vias with via locations, generating positioning data based on comparing the positions of the vias with the via locations, providing the positioning data of the vias to a digital lithography device, updating a redistributed metal layer (RDL) mask pattern according to the positioning data so that the RDL positions correspond to the positions of the vias, and projecting the RDL mask pattern with the digital lithography device.

[0007] In another embodiment, a method is provided. The method includes comparing the positioning of a via and a via location; generating positioning data based on comparing the positioning of the via and the via location; providing the positioning data of the via to a digital lithography device; generating a connecting via mask pattern according to the positioning data, the connecting via mask pattern including a connecting via having a first end point contacting the via and a second end point contacting a redistribution metal layer (RDL) to be patterned at the via location according to an RDL mask pattern; projecting the connecting via mask pattern with the digital lithography device, the connecting via having a first end point contacting the via; and projecting the RDL mask pattern with the digital lithography device, the RDL contacting the second end point of the connecting via.

[0008] In another embodiment, a non-transitory computer-readable medium is provided. The non-transitory computer-readable medium stores instructions that, when executed by a processor, cause a computer system to perform the following steps: compare the positioning of a via and a via location; generate positioning data based on the comparison of the positioning of the via and the via location; provide the positioning data of the via to a digital lithography device; generate a connecting via mask pattern based on the positioning data, the connecting via mask pattern including a connecting via having a first end contacting the via and a second end contacting a redistribution metal layer (RDL) to be patterned at the via location according to an RDL mask pattern; project the connecting via mask pattern with the digital lithography device, the connecting via having a first end contacting the via; and project the RDL mask pattern with the digital lithography device, the RDL contacting the second end of the connecting via.

[0009] In yet another embodiment, a packaged circuit system is provided. The packaged circuit system includes: a via located at a via position of a via mask pattern according to mask pattern data; a connecting via having a first end point contacting the via and a second end point contacting a redistributed metal layer (RDL) to be patterned at the via position according to an RDL mask pattern of the mask pattern data; and the RDL contacting the second end point of the connecting via. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are achieved, a more specific description of the present disclosure briefly summarized above may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only exemplary embodiments and are therefore not to be considered as limiting the scope thereof, and other equally effective embodiments may be allowed.

[0011] Figure 1 is a schematic diagram of a lithography system according to an embodiment.

[0012] Figure 2is a perspective view of a digital lithography apparatus according to an embodiment.

[0013] Figure 3 is a schematic diagram of a portion of a mask pattern according to an embodiment.

[0014] Figure 4 is a schematic diagram of an interface according to an embodiment.

[0015] Figure 5 is a schematic top view of a package substrate after an embedding process according to an embodiment.

[0016] Figure 6 is a schematic top view of a portion of a package substrate before a first operation of a digital connection method according to an embodiment.

[0017] Figure 7 is a flow chart of a digital connection method according to an embodiment.

[0018] Figure 8 is a flow chart of a digital connection method according to an embodiment.

[0019] Fig. 9 is a schematic top view of a portion of a package substrate after a fourth operation of a digital connection method according to an embodiment.

[0020] Fig. 10A is a schematic top view of a portion of a package substrate after a fourth operation of a digital connection method according to an embodiment.

[0021] Fig. 10B is a schematic top view of a portion of a packaging substrate after a fifth operation of digital connection according to an embodiment.

[0022] To facilitate understanding, like reference numerals have been used, where possible, to designate like devices in the drawings. It is contemplated that devices and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0023] Embodiments of the present disclosure relate generally to lithography systems. More particularly, embodiments of the present disclosure relate to systems, software applications, and methods for digital lithography of semiconductor packaging.

[0024] Figure 11 is a schematic diagram of a lithography system 100. As shown, the lithography system 100 includes, but is not limited to, a virtual mask device 102, a metrology device 104, a digital lithography device 108, a controller 110, and a plurality of communication links 101. The lithography system 100 may also include a transport system 103. The digital lithography device 108 and the metrology device 104 may be connected via the transport system 103. The transport system is operable to transport a substrate between the digital lithography device 108 and the metrology device 104.

[0025] Each of the lithography system devices (virtual mask device 102, metrology device 104, digital lithography device 108, and controller 110) is operable to be connected to each other via a communication link 101. Alternatively or in addition, each lithography system device may communicate indirectly by first communicating with the controller 110, which then communicates with the lithography system device in question. The lithography system 100 may be located in the same area or production facility, or each lithography system device may be located in a different area.

[0026] Each of the plurality of lithography system devices is additionally indexed with a digital connection method 700, 800. Each of the virtual mask device 102, the metrology device 104, the digital lithography device 108, and the controller 110 includes an onboard processor and a memory, wherein the memory is configured to store instructions corresponding to any portion of the method 500 described below. The communication link 101 may include at least one of a wired connection, a wireless connection, a satellite connection, etc. According to embodiments further described herein, the communication link 101 facilitates sending and receiving files to store data. Data transmission along the communication link 101 may include temporarily or permanently storing files or data in the cloud before transmitting or copying the files or data to the lithography environment device.

[0027] Controller 110 includes a central processing unit (CPU) 112, support circuits 114, and memory 116. CPU 112 may be one of any form of computer processor that may be used in an industrial environment to control a lithography system device. Memory 116 is coupled to CPU 112. Memory 116 may be one or more readily available memories, such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of local or remote digital memory. Support circuits 114 are coupled to CPU 112 for supporting the processor in a conventional manner. These circuits include caches, power supplies, clock circuits, input / output circuit systems, subsystems, etc. Controller 110 may include CPU 112 coupled to input / output (I / O) devices in support circuits 114 and memory 116. Controller 110 is operable to facilitate and transmit design files to digital lithography device 108 via communication link 101.

[0028] The memory 116 may include one or more software applications, such as a control software program. The memory 116 may also include stored media data used by the CPU 112 to execute the method 500 described herein. The CPU 112 may be a hardware unit or a combination of hardware units capable of executing software applications and processing data. In some configurations, the CPU 112 includes a central processing unit (CPU), a digital signal processor (digital signal processor; DSP), an application-specific integrated circuit (application-specific integrated circuit; ASIC) and / or a combination of such units. The CPU 112 is generally configured to execute one or more software applications and process stored media data, each of which may be included in the memory 116. The controller 110 controls the transmission of data and files in and out of various lithography system devices. The memory 116 is configured to store instructions corresponding to any operation of the digital connection method 700, 800 according to the embodiments described herein.

[0029] Figure 22 is a perspective view of a digital lithography apparatus 108 (e.g., a digital lithography system) that may benefit from the embodiments described herein. The digital lithography apparatus 108 includes a stage 214 and a processing unit 204. The stage 214 is supported by a pair of rails 216. A package substrate 220 is supported by the stage 214. The stage 214 is operable to move along the pair of rails 216. An encoder 218 is coupled to the stage 214 to provide position information of the stage 214 to a lithography controller 222.

[0030] The lithography controller 222 is generally designed to facilitate control and automation of the processing techniques described herein. The lithography controller 222 can be coupled to or in communication with the processing unit 204, the stage 214, and the encoder 218. The processing unit 204 and the encoder 218 can provide information to the lithography controller 222 regarding substrate processing and substrate alignment. For example, the processing unit 204 can provide information to the lithography controller 222 to alert the lithography controller 222 that substrate processing has been completed. The lithography controller 222 facilitates control and automation of the digital lithography process based on the design files provided by the interface 230. A design file (or computer instructions), which can be referred to as an imaging design file, that can be read by the lithography controller 222 determines the tasks to be performed on the substrate. The design file (e.g., Figure 4 The design file 420 includes mask pattern data. The mask pattern data includes a mask pattern 300 and a code for monitoring and controlling processing time and substrate positioning. The mask pattern 300 corresponds to a pattern written using electromagnetic radiation.

[0031] The packaging substrate 220 includes any suitable material, such as glass. In other embodiments that may be combined with other embodiments described herein, the packaging substrate 220 is made of other materials that can be used as part of a flat panel display. The packaging substrate 220 has a thin film layer to be patterned formed thereon, such as formed by etching its pattern, and a photoresist layer formed on the thin film layer to be patterned, which is sensitive to electromagnetic radiation, such as UV or deep UV "light". The positive photoresist includes portions of the photoresist that, when exposed to radiation, are respectively soluble in a photoresist developer applied to the photoresist after the pattern is written to the photoresist using electromagnetic radiation. After the photoresist is exposed to electromagnetic radiation, the resist is developed to leave a patterned photoresist on the underlying thin film layer. Then, using the patterned photoresist, the underlying thin film is etched through the opening pattern in the photoresist to form a portion of the packaged circuit system.

[0032] The processing unit 204 is supported by a support 208 so that the processing unit 204 straddles a pair of rails 216. The support 208 provides an opening 212 for the pair of rails 216 and the stage 214 to pass under the processing unit 204. The processing unit 204 is a pattern generator configured to receive mask pattern data from an interface 230 and to expose a photoresist in a maskless lithography process using one or more image projection systems 206, which are operable to project a write beam of electromagnetic radiation to a packaging substrate 220. The pattern generated by the processing unit 204 is projected by the image projection system 206 to expose the photoresist of the packaging substrate 220 to the mask pattern written in the photoresist. In one embodiment that can be combined with other embodiments described herein, each image projection system 206 includes a spatial light modulator to modulate incident light to generate a desired image. Each spatial light modulator includes a plurality of electrically addressable devices that can be individually controlled. Based on the mask pattern data and the correction provided by the positioning correction model generated by the method 500 described herein, each electrically addressable device can be in an "on" position or an "off" position. When the light reaches the spatial light modulator, the electrically addressable device in the "on" position projects multiple writing beams to the projection lens (not shown). The projection lens then projects the writing beams to the packaging substrate 220. The electrically addressable devices include, but are not limited to, digital micromirrors, liquid crystal displays (LCDs), liquid crystal over silicon (LCoS) devices, ferroelectric liquid crystal on silicon (FLCoS) devices, micro LEDs, VCSELs, liquid crystal displays (LCDs), or any solid-state emitter of electromagnetic radiation.

[0033] Figure 3 is a schematic diagram of a portion of a mask pattern 300. The mask pattern 300 is written into a photoresist using a processing unit 204. The mask pattern data includes a via mask pattern 301 and a redistributed metal layer (RDL) mask pattern 303. The via mask pattern 301 includes one or more via locations 302. The RDL mask pattern 303 includes one or more RDL locations 304. The via locations 302 and the RDL locations 304 correspond to interposers 306 (e.g., a first interposer 306A, a second interposer 306B, and a third interposer 306C) for attaching a die in a further packaging process. Each of the via locations 302 and the RDL locations 304 includes an x-coordinate and a y-coordinate, so that the metrology device 104 can perform recipe-based measurements at defined locations after the packaging substrate 220 is processed via the digital lithography device 108.

[0034] Figure 4 is a schematic diagram of the interface 230. The interface 230 includes a computing device 410 and an input / output (I / O) device 430. The interface 230 may be used to optimize, verify, or update at least one of the design files (e.g., the design file 420). The interface 230 may be used to optimize, verify, or update at least one of the design files 420 according to instructions and readable data of a Universal Metrology File (UMF) provided from one of the virtual mask device 102, the metrology device 104, the evaluation device 106, and the controller 110. The optimization, verification, and update of the design file 420 are further described in the operation of the digital connection method 700, 800.

[0035] Computing device 410 may include controller 412, network interface 414, and memory 416. Controller 412 accesses and executes programming data stored in memory 416 and coordinates the operation of other system devices. Similarly, controller 412 stores and accesses application data residing in memory 416. Controller 412 may be one or more central processing units (CPUs).

[0036] The memory 416 may store instructions and logic executed by the controller 412. In addition, the memory 416 may be one or more of a random access memory (RAM) and a non-volatile memory (NVM). The NVM may be a hard disk, a network attached storage (NAS), a removable storage device, etc. In addition, the memory 416 may include a design application 418 and a design file 420.

[0037] The design application 418 at least one of optimizes, verifies, and updates the design data of the design file 420. The design application 418 may be controlled by the controller 412 to optimize and / or update the design data of the design file 420.

[0038] The design file 420 may be stored in the memory 416 and may be accessed by the controller 412 and the design application 418. The design file 420 includes mask pattern data of the photoresist that is interpreted by the lithography controller 222 to pattern the photoresist disposed on the package substrate 220. The design file 420 may be provided in different formats. For example, the format of the design file 420 may be one of the GDS format and the OASIS format and other formats. The mask pattern data of the design file 420 includes a via mask pattern 301 and an RDL mask pattern 303. Other data included in the design file include exposure dose data, exposure focus data, and image projection system (image projection system;) to IPS calibration data. The exposure dose data corresponds to the dose of the writing beam to be projected onto the photoresist. The exposure focus data corresponds to the focus of each image projection system 206. The IPS to IPS calibration data corresponds to the splicing of the image projection system 206 so that the entirety of the mask pattern 300 is projected. The design file 420 may be in the form of a bitmap or similar file.

[0039] The I / O device 430 may include one or more of a keyboard, a display device, a mouse, an audio device, a touch screen, etc. The I / O device 430 may be used to input information to the virtual mask device 102 and / or output data from the virtual mask device 102. For example, a user may use a keyboard and a pointing device to generate and / or adjust elements of the design file 420. In another embodiment that may be combined with other embodiments described herein, the I / O device 430 is coupled to the controller 110 via a network interface 414 that communicates with the communication link 101. The virtual mask device 102 coupled to the controller provides a computer-integrated manufacturing (CIM) program that utilizes a computer to control the overall operation of the digital connection methods 700, 800 described herein.

[0040] Figure 5 is a schematic top view of the package substrate 220 after the embedding process. Figure 6 6 is a schematic top view of a portion 600 of a package substrate 220 prior to the first operation of the digital connection methods 700, 800 described herein. The embedding process may be a process step of a die-to-die final packaging process. After the embedding process, the device 504 is disposed on the interposer 306. In the die-to-die final packaging process, the die will be attached to the corresponding interposer 306. The die must be aligned with the device 504 and the RDL circuit including the via 602 and the RDL 904. Figure 5As shown, as a result of the embedding process, the device 504 may be offset or rotated from the desired device location 502. As a result, the via 602 may not be patterned at the via location 302 of the via mask pattern 301 of the mask pattern date. For example, the via 602 may have an x-coordinate and a y-coordinate relative to the via location 302. In order for the die to operate at its maximum capacity, the via 602 must be connected to the RDL 904.

[0041] Figure 7 is a flow chart of a digital connection method 700 . Fig. 9 is a schematic top view of a portion 900 of a package substrate 220 after a fourth operation of a digital connection method. At operation 701, a location of a via 602 is determined. The metrology device 104 determines the location and generates location data. The location data is generated by comparing the location of the via 602 with the via location 302. For example, an x-coordinate and a y-coordinate target x offset and a y-offset of the via 602 relative to the via location 302 are determined. An x-offset and a y-offset or a new x-coordinate and a y-coordinate target location data corresponding to the via 602 is generated. At operation 702, the location data of the via 602 is provided to the digital lithography device 108. The interface 230 of the digital lithography device 108 receives the location data from the metrology device 104 via the communication link 101, or receives the location data from the controller 110 in communication with the metrology device 104.

[0042] In operation 703, the RDL mask pattern 303 of the mask pattern data is updated according to the positioning data. The interface 230 of the digital lithography apparatus 108 may be used to optimize, verify or update at least one of the design files 420 according to the positioning data. The mask pattern data is updated so that the RDL position 304 of the RDL mask pattern 303 corresponds to the positioning change of the via 602 so that the RDL 904 is aligned with the via 602. In operation 704, the digital lithography apparatus 108 projects the RDL mask pattern 303 updated according to the positioning data. The processing unit 204 of the digital lithography apparatus 108 is a pattern generator configured to receive the mask pattern data with the updated RDL mask pattern 303 from the interface 230. The processing unit exposes the photoresist in a maskless lithography process using one or more image projection systems 206, which are operable to project a write beam of electromagnetic radiation onto the package substrate 220 according to the RDL mask pattern 303 updated according to the positioning data. After operation 704 , the RDL 904 is aligned with the vias 602 of each interposer 306 (eg, the first interposer 306A, the second interposer 306B, and the third interposer 306C).

[0043] Figure 8 is a flow chart of a digital connection method 800 . Fig. 10Ais a schematic top view of a portion 1000 of a package substrate 220 after a fourth operation of the digital connection method 800 . Fig. 10B 8 is a schematic top view of a portion 1000 of a package substrate 220 after a fifth operation of the digital connection method 800. At operation 801, a location of a via 602 is determined. The metrology device 104 determines the location and generates location data. For example, an x-coordinate and a y-coordinate target x-offset and y-offset of the via 602 relative to the via position 302 are determined. An x-offset and a y-offset or a new x-coordinate and a y-coordinate target location data corresponding to the via 602 is generated. At operation 802, the location data of the via 602 is provided to the digital lithography device 108. The interface 230 of the digital lithography device 108 receives the location data from the metrology device 104 via the communication link 101, or receives the location data from the controller 110 in communication with the metrology device 104.

[0044] In operation 803, a connecting via mask pattern 1001 is generated according to the positioning data, and the mask pattern data is updated. The connecting via mask pattern 1001 includes a connecting via 1002 to connect the via 602 to the RDL 1004 to be patterned to align with the via position 302. The connecting via 1002 has a first terminal 1003 that contacts the via 602 and a second terminal 1005 that contacts the RDL 1004 at the via position 302. The interface 230 of the digital lithography device 108 can be used to optimize, verify or update at least one of the design files 420 having the connecting via mask pattern according to the positioning data. The mask pattern data is updated so that the connecting via 1002 of the connecting via mask pattern 1001 corresponds to the positioning change of the via 602, so that the RDL 1004 patterned at the RDL position 304 of the RDL mask pattern 303 is aligned with the second terminal 1005 of the connecting via 1002 at the via position 302.

[0045] At operation 804, the digital lithography apparatus 108 projects the connected via mask pattern 1001. The processing unit 204 of the digital lithography apparatus 108 is a pattern generator configured to receive mask pattern data having the connected via mask pattern 1001 from the interface 230. The processing unit exposes the photoresist in a maskless lithography process using one or more image projection systems 206 operable to project a writing beam of electromagnetic radiation onto the package substrate 220 in accordance with the connected via mask pattern 1001 generated according to the positioning data.

[0046] In operation 805, the digital lithography device 108 projects the RDL mask pattern 303. The processing unit exposes the photoresist in a maskless lithography process using one or more image projection systems 206, which are operable to project a writing beam of electromagnetic radiation to the package substrate 220 according to the RDL mask pattern 303. The RDL 1004 at the RDL position 304 of the RDL mask pattern 303 contacts the second terminal 1005 of the connection via 1002 at the via position 302. The first terminal 1003 of the connection via 1002 contacts the via 602.

[0047] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope of the same is to be determined by the claims hereinafter.

Claims

1. A method, comprising: Compare via positioning and via location; generating positioning data based on the positioning of the comparison via and the via position; providing said positioning data of said via to a digital lithography device; updating a redistribution metal layer (RDL) mask pattern according to the positioning data so that the RDL position corresponds to the positioning of the via; as well as The RDL mask pattern is projected using the digital lithography device.

2. The method of claim 1, wherein a metrology device determines the positioning of the via.

3. The method of claim 2, wherein an interface of the digital lithography device receives the positioning data. The method of claim 1 , wherein the positioning data comprises an x-offset and a y-offset of the via.

5. The method of claim 1, wherein the interface of the digital lithography device at least one of optimizes, verifies, or updates the design file.

6. The method of claim 1, wherein the processing unit of the digital lithography device is a pattern generator.

7. A method comprising: Compare via positioning and via location; generating positioning data based on the positioning of the comparison via and the via position; providing said positioning data of said via to a digital lithography device; generating a connection via mask pattern according to the positioning data, the connection via mask pattern comprising a connection via having a first end point for contacting the via and a second end point contacting a redistribution metal layer (RDL) to be patterned at the via location according to the RDL mask pattern; projecting the connection via mask pattern with the digital lithography device, the connection via having the first end contacting the via; as well as The RDL mask pattern is projected using the digital lithography device, and the RDL contacts the second end of the connecting via.

8. The method of claim 7, wherein a metrology device determines the location and generates the location data.

9. The method of claim 8, wherein an interface of the digital lithography device receives the positioning data from the metrology device.

10. The method of claim 7, wherein the positioning data comprises an x-offset and a y-offset of the via.

11. The method of claim 7, wherein the interface of the digital lithography device at least one of optimizes, verifies, or updates the design file.

12. The method of claim 7, wherein the processing unit of the digital lithography device is a pattern generator.

13. The method of claim 7, wherein the via is disposed on an interposer.

14. The method of claim 13, wherein a die is to be attached to the interposer.

15. A non-transitory computer readable medium storing instructions which, when executed by a processor, cause a computer system to perform the following steps: Compare via positioning and via location; generating positioning data based on the positioning of the comparison via and the via position; providing said positioning data of said via to a digital lithography device; generating a connection via mask pattern according to the positioning data, the connection via mask pattern comprising a connection via having a first end contacting the via and a second end contacting a redistribution metal layer (RDL) to be patterned at the via location according to the RDL mask pattern; projecting the connection via mask pattern with the digital lithography device, the connection via having the first end contacting the via; as well as The RDL mask pattern is projected using the digital lithography device, and the RDL contacts the second end of the connecting via.

16. The non-transitory computer readable medium of claim 15, wherein a metrology device determines the location and generates the location data.

17. The non-transitory computer readable medium of claim 16, wherein an interface of the digital lithography device receives the positioning data from the metrology device.

18. The non-transitory computer readable medium of claim 15, wherein the positioning data comprises an x-offset and a y-offset of the via.

19. The non-transitory computer readable medium of claim 15, wherein the interface of the digital lithography device at least one of optimizes, verifies, or updates a design file.

20. The non-transitory computer readable medium of claim 15, wherein the processing unit of the digital lithography device is a pattern generator.

21. A packaged circuit system, the packaged circuit system comprising: a via hole located at a via hole position of a via mask pattern according to the mask pattern data; a connecting via having a first terminal contacting the via and a second terminal contacting a redistribution metal layer (RDL) to be patterned at the via location according to an RDL mask pattern of the mask pattern data; as well as RDL contacts the second end point of the connecting via.

22. The packaged circuit system of claim 21, wherein the packaged circuit comprises an interposer corresponding to the via location.

23. The packaged circuitry of claim 21, wherein each of the via locations and RDL locations of the RDL comprises an x-coordinate and a y-coordinate.

24. The packaged circuit system of claim 21, wherein a connection via mask pattern includes the connection via.

25. The packaged circuit system of claim 24, wherein the connecting via mask pattern is generated based on positioning data of the via.

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