Power gate dummy power transistor for backside power delivery network

Abstract

A semiconductor chip device includes a substrate having a back-end line layer and a backside power delivery network. The input power line is electrically coupled to the backside power delivery network. The dummy transistor is located in a circuit having analog or digital circuit elements. The power gating transistor is located in a circuit between the dummy transistor and the analog or digital circuit element. Power from the power input lines is provided from the backside power delivery network through dummy transistors and controlled by power gating transistors for delivery to analog or digital circuit elements. The device uses backside power delivery to regions of dummy transistors to transfer power into analog or digital circuit elements, which leaves more front side footprint for the functional device.

Description

Technical Field

[0001] The present disclosure relates generally to electrical devices, and more particularly, to a power gate dummy power transistor for a backside power delivery network. Background Art

[0002] Power gate transistors are often used to disconnect logic cells from power and / or ground to reduce leakage in standby mode. When logic areas are disconnected, power consumption is reduced. In one example, multi-threshold CMOS (MTCMOS) uses low leakage N-type metal oxide semiconductor (NMOS) (or PMOS) transistors as foot-end (or head-end) switches to disconnect ground (or power) from portions of the design in circuit standby mode.

[0003] Recently, it has been discussed to have power gate transistors on the back side of semiconductor wafers to couple or decouple integrated circuit blocks to a power source. However, the fabrication of transistors on the back side of the wafer involves additional back side process steps compared to fabricating gate transistors on the front side of the wafer. When the gate transistors are not used, the gate transistors can be used to turn off power to certain functional circuits to minimize leakage current in standby mode. When the functional circuit is in active mode, the power gate transistor will turn on the power.

[0004] A current method for wafer manufacturing provides a direct backside contact scheme. However, the backside contact scheme of the present invention allows power to flow sometimes. In another wafer manufacturing scheme, dummy devices are used for power connection between the back end of line (BEOL) layer and the back side power delivery network (BSPDN) layer. The dummy devices are usually non-functional. In the method of using dummy devices for power connection, there is usually a lack of power control between the BEOL and the BSPDN, which leads to unnecessary power consumption if there is power leakage in the device area. Summary of the invention

[0005] According to an embodiment of the present disclosure, a semiconductor chip device is provided. The semiconductor device includes a substrate having a back-end line layer and a back-side power delivery network below the substrate. The input power line is electrically coupled to the back-side power delivery network. The substrate also includes an analog or digital circuit element. A dummy transistor is located in a circuit having the analog or digital circuit element. A power gating transistor is located in a circuit between the dummy transistor and the analog or digital circuit element. Power from the power input line is provided from the back-side power delivery network through the dummy transistor and is controlled by the power gating transistor for delivery to the analog or digital circuit element. The structure of the semiconductor device uses back-side power delivery to the region of the dummy transistor to deliver power to the analog or digital circuit element. Back-side power delivery has the benefit of leaving more front-side occupied area for functional devices. Using dummy transistors to transmit power from the back side avoids the need for complex back-side formation processes and the use of other interconnect mechanisms that only serve to provide power connections. Therefore, the entire formation process is made easier and the space on the semiconductor wafer is used more efficiently. In addition, the gating transistor can turn off the gate of the analog or digital circuit element to control power consumption.

[0006] In an embodiment that may be combined with the preceding embodiments, the device includes a connection between a back-end line layer and a power gate transistor. Elements in the back-end line layer control the on-state or off-state of the gate transistor. In conventional schemes, power is typically passed unchecked through the back end of the line to the back-side power delivery network regardless of the dummy transistor used. In the present device, the back end of the line controls the power flow through the power gate transistor, so that the device saves power consumption when the dummy transistor is not used to connect the back end of the line to the back-side power delivery network.

[0007] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes forming an analog or digital circuit feature layer on a substrate. A power gate transistor is formed on the substrate. A dummy transistor is formed on the substrate. A back-end line layer is formed on top of the analog or digital circuit feature layer, the power gate transistor, and the dummy transistor. A back-end power delivery network layer is formed below the analog or digital circuit feature layer, the power gate transistor, and the dummy transistor. A circuit path is formed from a power input source in the back-end power delivery network layer, through a dummy transistor, and through a back-end line interconnection electrically coupled to the power gate transistor. Power is transmitted from the power gate transistor to the analog or digital circuit feature through an interconnect at the back-end power delivery network, which is located between the power gate transistor and the analog or digital circuit feature. As can be understood, the method provides controlled power delivery from the back side of the device to the analog or digital circuit feature through a dummy transistor. By using the back side for power delivery, more wafer substrate surfaces on the front side can be used for functional components. The dummy transistor (which may exist and play other roles) provides a convenient connection element from the back side to the gate transistor. Furthermore, gate power can be turned on when needed and power dissipation in the device can be saved.

[0008] In an embodiment that may be combined with the preceding embodiments, the method includes forming a connection path from a power terminal at a backside power delivery network through a dummy transistor to a backend line layer and from the backend line layer to a power gate transistor and to the backside power delivery network. This feature provides benefits by routing power from the backside power delivery network through a dummy transistor to the backend of the line, where an interconnect is coupled to a line mid-contact of a gate transistor, and the gated power is again routed back to the backside power delivery network through a source / drain backside contact, where an interconnect at the backside power delivery network is coupled to an analog or digital element through a source / drain backside contact. This feature provides benefits by closing the gate of a power gate transistor to cut off power to a block of unused analog or digital elements.

[0009] According to an embodiment of the present disclosure, a method for manufacturing a controlled power path from the back side to the front side of a wafer with a substrate in a semiconductor device is provided. The method includes forming a plurality of dummy transistors in the front side to back side connection area of ​​the wafer. A power gate transistor is formed at the gate transistor area of ​​the wafer. A first dummy placeholder element is formed from a placeholder material below the source / drain epitaxial region of the wafer. A second dummy placeholder element is formed below the dummy gate transistor. A back end line layer and a carrier wafer layer are added to the wafer. The wafer is flipped over and the substrate material is removed. Some of the placeholder material is removed from below the first dummy placeholder element to form a back side to front side connection contact to the power input and ground line through the dummy transistor and through the power gate transistor. This embodiment utilizes a process of combining placeholder elements in an area that is usually filled with a substrate. By using placeholders that are removed when the wafer is flipped over, contacts from the back side to the front side can be formed so that the back side power input can be used. The resulting structure provides power from the back side to the front side, where the power is gated by the gate transistor. Thus, power is gated to the backside and from the backside to the analog or digital components.

[0010] In an embodiment which may be combined with the before-mentioned embodiment, the method comprises forming a self-aligned backside contact during the step of removing some placeholder material under the first dummy placeholder element.The resulting self-aligned backside contact makes manufacturing easier and the final product more reliable.

[0011] The technology described herein can be implemented in a variety of ways. Example implementations are provided below with reference to the following figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are illustrative embodiments. They do not show all embodiments. Other embodiments may be used in addition or alternatively. Details that may be obvious or unnecessary may be omitted to save space or for more effective description. Some embodiments may be practiced with additional components or steps and / or without all components or steps shown. When the same reference numeral appears in different drawings, it refers to the same or similar components or steps.

[0013] Figures 1A-1C is a cross-sectional view of a source, a gate, and a drain of a semiconductor device according to an embodiment.

[0014] Figures 2A-2C Yes Figures 1A-1C The cross-sectional view of the semiconductor device is mapped to Figure 3A-17E An illustration of a perspective view of a semiconductor device shown in FIG.

[0015] Figure 3A is a side view of a wafer block according to an embodiment, which depicts the initial basis in a method of manufacturing a semiconductor device.

[0016] Figure 3B and 3C It shows that according to the embodiment Figure 3A Two views of nanosheet patterning in a wafer block.

[0017] Figure 4A and 4B Two views of shallow trench isolation according to an embodiment are shown.

[0018] FIG. 5A to FIG. 5G Different regions of a wafer during an inline front-end formation process according to an embodiment are shown.

[0019] 6A to 6H FIG. 1 shows a method for forming a middle of line (MOL) contact according to an embodiment. FIG. 5A to FIG. 5G A view that is consistent with the view of the

[0020] 7A to 7H A view showing forming a back end line layer and a carrier wafer according to an embodiment is shown.

[0021] FIG. 8A to FIG. 8H The embodiment shows the 7A to 7H A view that is consistent with the view of the

[0022] 9A to 9H The present invention shows the process of removing the silicon substrate layer according to the embodiment. FIG. 8A to FIG. 8H A view that is consistent with the view of the

[0023] Figures 10A-10H The embodiment according to the present invention is shown Figures 9A-9H The views are consistent with those in removing the etch stop layer, removing the remaining substrate layer, interlayer dielectric deposition and chemical mechanical planarization.

[0024] Figures 11A-11H FIG. 1 shows a method for patterning backside contacts according to an embodiment of the present invention. Figures 10A-10H A view that is consistent with the view of the

[0025] FIG. 12A to FIG. 12H The embodiment according to the present invention is shown FIG. 11A to FIG. 11H A view that is consistent with the view when placeholder material is selectively removed.

[0026] FIG. 13A to FIG. 13H FIG. 1 shows a method for metallizing the back side of a wafer according to an embodiment. FIG. 12A to FIG. 12H A view that is consistent with the view of the

[0027] FIG. 14A to FIG. 14H FIG. 1 shows a method for forming a backside power delivery network according to an embodiment. FIG. 13A to FIG. 13H A view that is consistent with the view of the

[0028] Figures 15A-15EA detailed view of the connection architecture from the backside power delivery network area to the back end through dummy resistors, from the back end to the backside power delivery network through power gate transistors, and from the backside power delivery network to analog or digital elements from source / drain cross sections of dummy transistors, power gate transistors, and analog or digital elements according to an embodiment is shown.

[0029] Figures 16A-16E A detailed view of the connection architecture from the backside power delivery network area through the dummy transistor to the back end of the line, from the back end of the line through the power gate transistor to the backside power delivery network, and from the backside power delivery network to the analog or digital element along the gate cross section of the dummy transistor, the power gate transistor, and the analog or digital element according to an embodiment is shown.

[0030] FIG. 17A to FIG. 17E A detailed view of the connection architecture from the backside power delivery network area through the dummy transistor to the back end of the line, from the back end of the line through the power gate transistor to the backside power delivery network, and from the backside power delivery network from the dummy transistor, the power gate transistor, and the source / drain cross section of the analog or digital element to the analog or digital element according to one embodiment is shown. DETAILED DESCRIPTION

[0031] Overview

[0032] In the following detailed description, many specific details are set forth by way of example in order to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings can be practiced without these details. In other cases, well-known methods, processes, components and / or circuits have been described at a relatively high level without detailed description to avoid unnecessarily obscuring aspects of the present teachings.

[0033] In one aspect, spatially relative terms such as "front", "rear", "top", "bottom", "below", "below", "lower", "above", "upper", "side", "left", "right", etc. are used with reference to the direction of the drawings being described. Since the components of the embodiments of the present disclosure can be positioned in a plurality of different directions, the directional terms are used for illustrative purposes and are by no means restrictive. Therefore, it will be understood that, in addition to the directions depicted in the figures, the spatially relative terms are intended to cover different directions of the device in use or operation. For example, if the device in the figure is flipped, the elements described as being "below" or "below" other elements or features will be oriented "above" the other elements or features. Therefore, for example, the term "below" can cover the orientation of above as well as below. The device can be oriented in other ways (rotated 90 degrees or viewed or referenced in other directions), and the spatially relative descriptors used herein should be interpreted accordingly.

[0034] As used herein, the terms "lateral", "planar", and "horizontal" describe an orientation parallel to a first surface of a chip or substrate. In the disclosure herein, a "first surface" may be a top layer of a semiconductor device where various circuit devices are patterned in the semiconductor material. The "first surface" in the context of discussion may also be referred to as the "front side" or "front end of line" (FEOL) of the device. The "header" of a device may be based on which side of the device contains the high side voltage line (Vdd). The "foot end" includes the low side voltage (VSS).

[0035] As used herein, the term “vertical” describes an orientation that is arranged perpendicular to a first surface of a chip, a chip carrier, a chip substrate or a semiconductor body.

[0036] As used herein, the terms "coupled" and / or "electrically coupled" do not mean that elements must be directly coupled together - intermediate elements may be provided between the "coupled" or "electrically coupled" elements. In contrast, if an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements. The term "electrically connected" refers to a low-ohmic electrical connection between elements that are electrically connected together.

[0037] Although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the exemplary embodiment, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. Describing an element as "first" or "second" etc. does not necessarily mean that there is an order or priority of any element. As used herein, the term "and / or" includes any and all combinations of one or more related listed items.

[0038] Example embodiments are described herein with reference to cross-sectional illustrations, which are schematic diagrams of idealized or simplified embodiments (and intermediate structures). Therefore, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the regions shown in the figures are schematic in nature, and their shapes do not necessarily illustrate the actual shapes of the regions of the device, and do not limit the scope. It should be understood that the figures and / or drawings attached to the present disclosure are exemplary, non-limiting, and are not necessarily drawn to scale.

[0039] It should be understood that other embodiments may be used and structural or logical changes may be made without departing from the spirit and scope defined by the claims. The description of the embodiments is not restrictive. In particular, the elements of the embodiments described below may be combined with elements of different embodiments.

[0040] Device structure

[0041] Reference now Figures 1A to 1C , wherein a semiconductor device 100 (sometimes referred to as "device 100") according to an embodiment is shown. Device 100 provides power gating of dummy transistors for the back side of a wafer power delivery network. For illustration purposes, Figures 1A to 1C Only three cross-sectional areas of the device 100 are shown where features providing gate functionality are located. Figure 1A A cross section of the source side is shown. Figure 1B A cross section of the gate side is shown. Figure 1C The cross section of the drain side is shown. The labels Y3, Y4 and Y5 refer to the cross-sectional axes referenced throughout the drawings to provide an indication of which view of the device (source, gate or drain) is being shown. Figure 2A-2C The details of the cross-sectional axes are discussed in.

[0042] Typically, embodiments of the device 100 include a power gate transistor 315 located between the back end line layer 130 and the back side power delivery network 150. The carrier wafer layer 135 is shown as a reference point, for example, it can be located on the side of the device 100 opposite the back side power delivery network 150. As will be understood, the device 100 includes a structure that defines a controlled power path. The structure uses the power gate transistor 315 to control the power through the dummy transistor (shown in further detail below), which can be processed using the built-in power conduction function from the back side power input of the wafer to the front side back end of the wafer. Embodiments typically include positioning the gate transistor 315 on the same layer as the dummy transistor and the logic circuit element / device. By using dummy transistors that occupy a large percentage of the actual area of ​​the wafer to conduct power through the wafer, the area required to conduct power (e.g., by using micro silicon through vias (uTSVs)) is greatly reduced. As a benefit of the proposed structure, the logic device density can be increased, resulting in a more powerful chip device. Furthermore, using power gate transistors in combination with dummy transistors can reduce power consumption by cutting off current to unused circuit blocks.

[0043] Figures 2A-2C 1 shows an example of a cross-sectional view of an area of ​​device 100. The following figures will show device 100 from different angles and will include standard logic device areas ( Figure 2A ), power gate transistor area ( Figure 2B ) and the dummy transistor area ( Figure 2C ) section. The power gate transistor region includes a head (PMOS) and a tail (NMOS) section that includes structures that provide a controlled power path from the backside power delivery network to the logic device or circuit element. Because device 100 (and its formation steps) includes many elements that may appear different depending on the viewing angle, it should be constantly referenced. Figure 2A-2C to track the viewing angle shown.

[0044] Figure 2A 1. The cross-sectional area of ​​a standard digital or analog device element in device 100 is represented. Figure 2B denoting the cross-sectional area of ​​a power gate transistor. The power gate transistor width of the subject device is longer (e.g., approximately equal to 80 nm or greater) than that of a standard logic device, resulting in a higher threshold voltage (VT) than that of a standard logic device. Figure 2B The width of the power gate transistor in Figure 2A The width of the device in the area is compared, Figure 2B The width of the power gate transistors in is much larger. Figure 2C Represents a cross section of a dummy device used to connect the backside end of the line to the backside power delivery network.

[0045] In the following description, sometimes Figures 2A-2C Reference is made back to the drawings so as to understand where fabrication in the device is performed relative to standard logic device elements, power gate transistor elements, dummy transistor elements, and those elements that are the subject of the present disclosure. Figure 2B The device features in the relevant section are the features of interest to the subject disclosure. For example, axis "Y3" represents a cross section along the source side of the device. Axis "Y4" represents a cross section along the gate side of the device. Axis "Y5" represents a cross section along the drain side of the device.

[0046] Example Manufacturing Method

[0047] Now refer to Figure 3 and FIG. 4A to FIG. 17E, to describe by way of illustration a method for fabricating a semiconductor device including power gating of dummy transistors for the backside of a wafer power delivery network. The accompanying drawings illustrate a wafer fabrication process including additive and subtractive processes to form some circuit elements in a terminal device. The additive and subtractive processes involved (e.g., masking, deposition, etching, lithography, etc.) may be known to those skilled in the art and are not necessarily identified in each action shown. The fabrication of the devices described herein may include, for example, a multi-step sequence of lithographic and / or chemical processing steps that facilitates the gradual creation of electronic-based systems, devices, components, and / or circuits in semiconductor and / or superconducting devices (e.g., integrated circuits). For example, devices may be fabricated on one or more substrates (e.g., silicon (Si) substrates and / or other substrates) by employing techniques including, but not limited to, photolithography, microlithography, nanolithography, nanoimprint lithography, photomask technology, patterning technology, photoresist technology (e.g., positive photoresist, negative photoresist, mixed tone photoresist, and / or another photoresist technology), etching technology (e.g., reactive ion etching (RIE), dry etching, wet etching, ion beam etching, plasma etching, laser ablation, and / or another etching technology), evaporation technology, sputtering technology, plasma ashing technology, thermal treatment (e.g., rapid thermal annealing, furnace annealing, thermal oxidation, and / or another thermal treatment), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical mechanical planarization (CMP), backside grinding technology, and / or another technology for fabricating integrated circuits. In some figures, some reference numerals of elements not affected by the steps may not be repeated.

[0048] Figure 3A-17E The drawings are shown along different perspective axes and in different cross-sectional views. Figure 2A-2C Come and view Figure 3A-17E .

[0049] Reference now Figure 3A , a device 100 including a semiconductor material 105 (e.g., silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), or a III-V compound semiconductor material (e.g., gallium arsenide (GaAs)) is first formed, which may include a buried oxide or silicon germanium layer 110 epitaxially grown onto the semiconductor material 105. The layer 110 will be used as an etch stop layer for further processing. A bottom sacrificial layer 107, alternating active semiconductor layers 103, and a sacrificial layer 109 may be added to the semiconductor material 105. Figure 3AThe structure shown in can represent a starting block for fabrication. In various embodiments, the active semiconductor layer 103 can be the same semiconductor material as the semiconductor material 105 or a different semiconductor material formed on the buried layer 110, for example, a semiconductor material epitaxially grown on a buried silicon germanium segmentation layer. In various embodiments, the sacrificial layer 109 can be a silicon germanium (SiGe) layer having a germanium concentration sufficient to allow selective etching and removal relative to the bottom sacrificial layer 107 and the active semiconductor layer 103. In various embodiments, the bottom sacrificial layer 107 can be a silicon germanium (SiGe) layer having a germanium concentration sufficient to allow selective etching and removal relative to the semiconductor material 105, the sacrificial layer 109, and the active semiconductor layer 103. In various embodiments, the bottom sacrificial layer 107 can be a silicon germanium (SiGe) layer having a germanium concentration greater than 50 atomic percent (at.%), and the sacrificial layer 109 can be a silicon germanium (SiGe) layer having a germanium concentration less than 40 atomic percent (at.%).

[0050] Figure 3B and 3C Nanosheet patterning of a wafer is shown. A hard mask layer 112 may be placed over regions of the wafer to prevent removal of material. This action creates a power gate transistor region with a longer gate length than a standard logic device region gate length. Figure 3B Represents nanosheet patterning in the standard logic device area and standard channel length in the dummy transistor fabrication area. Figure 3C represents the patterning in the power gate transistor region, which shows greater than Figure 3B ” represents the width (gate length). Figure 4A and 4B The step of shallow trench isolation (STI) 114 is shown, which fills the openings created in the previous nanosheet patterning.

[0051] Figure 5A 5H to 5C show different areas of the wafer in the front end of the inline process steps. Figure 5A Indicates along Figure 2A The “Y1” cross-sectional axis of a standard device logic (having a logic circuit device 330 ). Figure 5B Indicates along Figure 2A The “Y2” cross-sectional axis is the standard device logic. Figure 5C Indicates along Figure 2B The power gate transistor portion of the “Y3” cross-sectional axis. Figure 5D Indicates along Figure 2B Figure 1 shows the power gate transistor portion of the wafer along the “Y4” cross-sectional axis of FIG. 1. The focus is on fabrication in the Y3, Y4, and Y5 regions where gating structures are being developed to provide power to the back side of the wafer through the dummy transistor portion. Figure 5E Indicates along Figure 2CThe “X1” cross-sectional axis is the dummy transistor portion. Fig. 5F Indicates along Figure 2C The dummy transistor portion of the “Y6” cross-section axis. Figure 5G Indicates along Figure 2C In this step, an interlayer dielectric layer 115 is deposited in the region shown (in Figure 5A , 5C , 5E and 5F). Some areas may receive high-K metal gate 117 material (in Figure 5B , 5D , 5E and 5G).

[0052] Figures 6A-6H The fabrication including the middle of line contact (MOL) formation is shown. It should be noted that as the process opens up the middle of the line source / drain contact area along Y3, the views along Y3 and Y5 begin to look different. Therefore, another view Y5 is added to the figure so that the view from both sides of Y3 and Y5 is shown. Figures 6A-6H In the contact formation step of , source / drain contacts 120A are formed to connect with interconnects in the back-end process. Gate contacts 120B are formed to connect with interconnects in the back-end of the line. Placeholder 125 is a feature not germane to the present invention. Gate cutout opening 122 is formed at Figure 6B is shown as a reference point. In the region of the dummy transistor, Figure 6F-6H , all contacts 120A and 120B may be patterned / opened during the MOL process, including, for example, all gates and S / Ds of the MOL metal contact dummy transistors.

[0053] Figures 7A-7H The manufacturing steps for forming the back-end line layer and the carrier wafer are shown. The back-end line layer 130 is formed over the MOL source / drain contacts 120A and the MOL gate contacts 120B and the interlayer dielectric 115. The carrier wafer layer 135 may be formed over the back-end line layer 130. Fig. 7A , 7C , 7E, 7F, 7G, 7H, some embodiments may include placeholder 125 material below the source / drain (S / D) epitaxial regions 355 and the gate region 325.

[0054] Figures 8A-8H The wafer is shown flipped. It can be seen that the semiconductor 105 layer (which may be, for example, a silicon layer) and the buried oxide or silicon germanium layer 110 are now on top. The carrier wafer layer 135 is now on the bottom.

[0055] Figures 9A-9H The semiconductor 105 is shown removed until the etch stop layer. The buried oxide or silicon germanium layer 110 acts as an etch stop layer.

[0056] Figures 10A-10H Shown is the removal of the etch stop layer 110 and the semiconductor layer 105 below the etch stop layer 110. After removing the underlying semiconductor 105, the open areas may be backfilled with a backside interlayer dielectric 115 followed by chemical mechanical planarization.

[0057] Figures 11A-11H Backside contact patterning is shown. In standard logic devices ( Figures 11A-11B ), region 140 may be patterned (dielectric removed) to expose placeholders 125 for source / drain regions. In the region of the power gate transistor ( Figures 11C-11E ), the source side of the placeholder 125 can remain covered. Fig.11E In the process, the dielectric 115 can be removed to expose the drain side of the placeholder 125 on the back side of the wafer. Figures 11F-11H ), in order to conduct power through this area, the dielectric 115 can be removed, thereby exposing all the placeholders 125 for conductive elements. Figures 11A-11H The exposed elements also include shallow trench isolation 114 .

[0058] Figures 12A-12H The selective removal of the placeholder 125 material is shown. The placeholder 125 material may be removed where exposed using, for example, a wet process. The selective removal of the placeholder material may temporarily expose components including, for example, shallow trench isolation 114.

[0059] Figures 13A-13H The metallization of the back side of the wafer is shown. The space exposed by removing the placeholder 125 and the region 140 can be backfilled with the contact metal 180. For example, in the dummy transistor region ( Figures 13F-13H ), backfill all openings so that the future BSPDN and back-end line layer 130 will have a direct contact path. Figures 13C-13E ), one side of the source of the gate transistor region is connected to the back end of the line ( Fig. 13C ), while the drain is connected to BSPDN ( Fig.13E In the standard logic device area ( Figures 13A-13B ), the source / drain of the standard logic device is connected to the BSPDN through the backside contact metal 180. As can be understood, this structure now provides control of the power between the backside power delivery network of the standard logic area and the back end line of the dummy transistor. Power consumption can be stopped by gating the transistor area so that power is not provided to the standard logic device area when it is not necessary.

[0060] Figures 14A-14HThe formation of the backside power delivery network is shown. The backside power delivery network delivers power from the power terminals (Vdd, Vss) to the back end of the line through a direct contact path included in the dummy transistor area, and the power from the back end of the line is gated by the power gate transistor area. The gate power is delivered to the standard logic area through the backside contact metal 180 and the backside power delivery network between the power gate transistor and the standard logic device area.

[0061] FIG. 15A to FIG. 15E , FIG. 16A to FIG. 16E and FIG. 17A to FIG. 17E The cross-source / drain, gate and source / drain cross-sections of the front-end process, back-end process and back-side power delivery network of the semiconductor device 100 are shown respectively, with more focus on the interconnection details of the back-end process and back-side power delivery network and how the gate power is passed through the power gate transistor and how the gate power is delivered to the standard logic device area. FIG. 15A to FIG. 15E , FIG. 16A to FIG. 16E and FIG. 17A to FIG. 17E Therefore use Figure 2B The power gate transistor axis in the figure is used to show different perspectives of the structure of the dummy transistor area and the logic device area, such as a cross-source, drain or gate perspective. The "A" and "E" figures of each series of figures show the dummy transistor area for connecting the back end of the line to the backside power delivery network. The figure "B" of each series shows the power gate transistor foot end area (NMOS) perspective. The figure "C" of each series shows the standard logic device area. The figure "D" of each series shows the power gate transistor head area (PMOS) perspective.

[0062] Reference now Figures 15A-15E , Fig. 15B , Fig.15D Shown from the perspective of the Y3 axis of the source / drain of the tail and head of the power gate transistor respectively. Fig.15A and Fig.15E It is shown from the source / drain perspective of the dummy transistor area. Fig. 15C is shown from a source / drain perspective of a standard logic device region. In the series of figures shown here, the focus is on the components of the power gate transistor 315 located in the header and footer portions ( Fig. 15B and 15D ). In order for the header or footer to gate power, power is transferred between the back end of the line and the backside power delivery network of the header or footer. In an embodiment of the subject device, the power gate transistor 315 is located in the path between the dummy transistor 310 and the logic circuit device 330. The logic circuit device 330 can be analog or digital. The high side of the voltage input (VDD) 301 is located on the header side ( Fig.15EThe low-side voltage input (VSS) 302 is located at the pin-end side of the area for connecting to the back-side power delivery network ( Fig.15A ). Fig. 15C The input of a virtual high side voltage (VDD') 301' and a virtual low side voltage (VSS') 302' for PMOS and NMOS, respectively, is shown after power gating by the power gate transistor header and foot. In operation, power from the voltage sources 301, 302 is conducted through the backside power delivery network layer 303, through the backside contact metal 180, into the dummy transistor 310. The power continues through another metal contact 120A into the level 1 metal layer 305 at the back end of the line. The level 1 metal layer 305 may be in direct contact with the header element, such as Fig.15D , or can be in direct contact with the footer element, such as Fig. 15B as shown in . Fig.15E , Fig.15D An example of power flow is shown indicated by arrows. Power may continue through another contact metal 120A into a source side power gate transistor 315. The power gate transistor 315 controls whether power is allowed to pass into the standard logic circuit device 330.

[0063] Reference now FIG. 16A to FIG. 16E , respectively, from the perspective of the Y4 axis of the gate of the power gate transistor foot and head Fig. 16B , Fig.16D . Fig.16A and Fig.16E Shown from the gate perspective of the dummy transistor region. Fig. 16C It is shown from the source / drain perspective of the logic device area. From the gate side of the device, it can be seen that Fig.16A and Fig.16E The power flow is similar to Fig.15A and Fig.15E The power flow in the power gate transistor is shown in Figure 1, except that the power passes through the high-k metal gate 117. In addition, when the power reaches the level 1 metal layer 305, the power is physically disconnected from the level 1 metal layer 305 at the foot and head of the power gate transistor, such as Fig. 16B and Fig.16D See Fig. 16B and Fig.16D , where the level 1 metal layer 305 provides a signal (on or off) to the gate of the tail and head of the power gate transistor 315. This arrangement provides control of the power at the gate side of the power gate transistor 315. The gate side of the power gate transistor can be controlled separately by the back end of the line. The gate side of the power gate transistor 315 controls whether power flows into the logic circuit device 330 by turning it on or off.

[0064] Reference now Figures 17A-17E, showing the Y5-axis perspective of the source / drain at the tail and head of the power gate transistor, respectively. Fig. 17B , Fig.17D . Fig.17A and Fig.17E It is shown from the source / drain perspective of the dummy transistor area. Fig. 15C is shown from the source / drain perspective of the logic device region. When the gate of the power gate transistor is turned on, the power gate transistor 315 ( Fig. 17B , Fig.17D ) is transferred to the backside power delivery layer 303, thereby passing through the virtual power lines (Vss') 302' and (VDD') 301' ( Fig. 17B , Fig. 17C and Fig.17D ) converts the input power into virtual power and transfers it to the logic circuit device 330 ( Fig. 17C )middle. Fig.17E , Fig.17D An example of power flow is shown indicated by arrows.

[0065] in conclusion

[0066] The description of various embodiments of the present teachings has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

[0067] Although the foregoing has described what is considered to be the best state and / or other examples, it should be understood that various modifications may be made therein, and the subject matter disclosed herein may be implemented in various forms and examples, and the teachings may be applied to many applications, only some of which are described herein. The appended claims are intended to claim any and all applications, modifications, and variations that fall within the true scope of the present teachings.

[0068] The components, steps, features, objects, benefits and advantages discussed herein are merely illustrative. None of them and the discussion related to them are intended to limit the scope of protection. Although various advantages have been discussed herein, it should be understood that not all embodiments must include all advantages. Unless otherwise stated, all measurements, values, rated values, positions, sizes, dimensions and other specifications set forth in this specification (including in the appended claims) are approximate and not precise. They are intended to have a reasonable range consistent with the functions to which they are related and the conventions in the field to which they belong.

[0069] Many other embodiments are also contemplated. These include embodiments with fewer, additional and / or different components, steps, features, objects, benefits and advantages. These also include embodiments in which components and / or steps are arranged and / or ordered differently.

[0070] Although the foregoing has been described in conjunction with exemplary embodiments, it should be understood that the term "exemplary" is meant only as an example, rather than the best or optimal. Except as stated immediately above, nothing stated or shown is intended or should be construed as causing any component, step, feature, object, benefit, advantage, or equivalent to be dedicated to the public, whether or not recited in the claims.

[0071] It should be understood that the terms and expressions used herein have the common meaning consistent with these terms and expressions of the corresponding investigation and research fields corresponding thereto, unless a specific meaning is otherwise set forth herein. Relational terms such as first and second etc. can be used only to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual such relationship or order between these entities or actions. The term "comprises", "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including the list of elements not only includes those elements, but may also include other elements that are not explicitly listed or inherent to such process, method, article or device. In the absence of further constraints, an element beginning with "one" or "an" does not exclude the presence of additional identical elements in the process, method, article or device including the element.

[0072] An abstract of the present disclosure is provided to allow the reader to quickly determine the nature of the present technical disclosure. It should be understood that the abstract will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing detailed description, it can be seen that various features are grouped together in various embodiments for the purpose of simplifying the present disclosure. The method of the present disclosure should not be interpreted as reflecting the intention that the claimed embodiments have more features than the features explicitly recited in each claim. On the contrary, as reflected in the following claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the attached claims are hereby incorporated into the detailed description, with each claim independently serving as a separately claimed subject matter.

Claims

1. A semiconductor chip device, comprising: substrate; a back-end line layer on the substrate; a backside power delivery network beneath the substrate; an input power line electrically coupled to the backside power delivery network; a plurality of analog or digital circuit elements on said substrate; one or more dummy transistors located in a circuit having the plurality of analog or digital circuit elements; and a power gate transistor positioned in the circuit between the one or more dummy transistors and the plurality of analog or digital circuit elements, wherein power from the power input line is provided from the backside power delivery network through the one or more dummy transistors and controlled by the power gate transistor for transmission to the plurality of analog or digital circuit elements. 2 . The semiconductor chip device according to claim 1 , further comprising a connection between the back-end wiring layer and the power gate transistor, wherein an on state or an off state of the power gate transistor is controlled by an element in the back-end wiring layer. 3 . The semiconductor chip device according to claim 1 , wherein the power gate transistor is located on the same layer as the one or more dummy transistors. The semiconductor chip device according to claim 3 , wherein the one or more dummy transistors are located on the substrate. 5 . The semiconductor chip device according to claim 1 , wherein the back-end line layer is located on the front side of the substrate, on a side of the substrate opposite to the backside power delivery network.

6. The semiconductor chip device according to claim 1, further comprising a metal gate and a direct source / drain contact, wherein power from the power input line passes through the direct source / drain contact and is connected to the back-end line layer through the metal gate. 7 . The semiconductor chip device of claim 6 , wherein the power gate transistor is configured to convert power from the back end line layer into virtual power provided to the back side power delivery network through the direct source / drain contacts.

8. A method for manufacturing a semiconductor device, comprising: forming an analog or digital circuit feature layer on the substrate; forming a back-end line layer on the substrate adjacent to the analog or digital circuit feature layer; forming a power gate transistor on the substrate, wherein the power gate transistor is electrically coupled to the analog or digital circuit feature layer; forming a backside power delivery network layer below the substrate; forming one or more dummy transistors on the substrate; A circuit path is formed from a power input source in the backside power delivery network layer through the one or more dummy transistors and through metal contacts electrically coupled to the power gate transistor, wherein power is transferred from the power gate transistor to the analog or digital circuit feature through an interconnect at the backside power delivery network located between the dummy transistor and the analog or digital circuit feature.

9. The method of claim 8 further comprising forming a connection path from a power terminal at the backside power delivery network through the one or more dummy transistors to the backend wiring layer, and from the backend wiring layer to the power gate transistor and to the backside power delivery network.

10. The method according to claim 9, further comprising: The power gate transistor is configured to convert power received by the back end line layer into a virtual power input that is transmitted to the back side power delivery network layer.

11. The method of claim 10, further comprising transmitting the virtual power input to the backside power delivery network layer through a second direct source / drain contact.

12. The method according to claim 8, further comprising: A connection is formed between the back-end wiring layer and the power gate transistor, wherein an on state or an off state of the power gate transistor is controlled by an element in the back-end wiring layer.

13. The method of claim 8, wherein the one or more dummy transistors are formed on the substrate.

14. The method of claim 8, wherein the back-end line layer is formed on a front side of the substrate, on a side of the substrate opposite the backside power delivery network.

15. The method of claim 8, further comprising forming dummy placeholder elements adjacent to the source / drain epitaxial regions. 16 . The method of claim 15 , further comprising forming a dummy placeholder element adjacent to the one or more dummy transistors.

17. A method of fabricating a controlled power path from a backside to a frontside of a wafer having a substrate in a semiconductor device, comprising: forming a plurality of dummy transistors in a front-side to backside connection region of the wafer; forming a gate transistor at a power gate transistor region of the wafer; forming a first dummy placeholder element using a placeholder material below a source / drain epitaxial region of the power gate transistor; forming a second dummy placeholder element below the dummy transistor using a placeholder material; adding a back end line layer and a carrier wafer layer to the wafer; flipping the wafer and removing the substrate; and Some of the placeholder material below the first dummy placeholder element is removed to form backside to frontside connection contacts to power input and ground lines through the dummy transistor and through the power gate transistor.

18. The method of claim 17, further comprising forming a self-aligned backside contact during removal of some placeholder material beneath the source / drain epitaxial regions of the wafer.

19. The manufacturing method according to claim 17, wherein a width of the power gate transistor is greater than or equal to 80 nm.

20. The manufacturing method of claim 17, wherein the power gate transistor is formed on the substrate. 21 . The manufacturing method according to claim 20 , wherein the dummy transistor is formed on the substrate.

22. The manufacturing method according to claim 20, further comprising: forming a connection between the back end wiring layer and the power gate transistor; and The on state or the off state of the gate transistor is controlled by the elements in the back-end wiring layer.

23. The manufacturing method of claim 17, further comprising configuring the gate transistor to convert power received by the front side of the wafer into a virtual power input delivered to a back side of the wafer.

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