A high-current, wide-capacitance-range LDO based on frequency compensation circuit

Abstract

This invention discloses a high-current, wide-capacitance-range LDO based on a frequency compensation circuit, comprising: a first-stage operational amplifier for amplifying an error signal; a second-stage operational amplifier for further amplifying the amplified error signal; a driving circuit for enhancing the driving capability of the secondary amplified error signal; a current output circuit for adjusting the required output current based on the enhanced driving capability of the secondary amplified error signal and the input voltage; a feedback circuit for generating a new feedback voltage based on the output current; the first-stage operational amplifier also amplifies the new error signal; and a frequency compensation circuit that utilizes a multi-zero-pole dynamic compensation branch and a current buffer supplementary branch to adjust the positions of multiple zeros and poles in the new error signal based on the output current to cancel out secondary poles while widening the entire unity-gain bandwidth, thereby obtaining the adjusted error signal. This invention can still achieve a large bandwidth under a large current output range and a large load capacitance range.

Description

Technical Field

[0001] This invention belongs to the field of low-dropout linear regulator chip technology, specifically relating to a high-current, wide-capacitance-range LDO (Low-Dropout Regulator) based on a frequency compensation circuit. Background Technology

[0002] With the increasing popularity of modern new energy vehicles, the performance requirements for automotive power management chips are rising significantly. New energy vehicles contain far more electronic devices than traditional vehicles, such as advanced driver assistance systems, battery management systems, and infotainment systems. These modules may require higher power supplies, necessitating LDOs with a wider output current range and stronger load capacity to meet these requirements. Conversely, certain modules (such as microcontrollers and sensors) may require lower-power LDOs, but need to meet a broader range of current output capabilities (e.g., from a few milliamps to hundreds of milliamps). This requires LDOs with a sufficiently large output range to satisfy these demands.

[0003] New energy vehicles contain a variety of load types, including sensors, MCUs (Microcontroller Units), communication modules, audio modules, and high-power modules. These loads have different power requirements. Low-current loads, such as sensors or MCUs, require smaller load capacitance to maintain response speed. High-current loads, such as infotainment systems and drive motor controllers, require LDOs with larger capacitance connected to the output to stabilize the output power and improve transient current performance. Therefore, LDO design must support a wide range of load capacitances to address these issues.

[0004] In designing automotive LDOs, key characteristics to meet automotive requirements include high load current and a wide range of external capacitance to accommodate diverse load needs. The output current range and the size of the external capacitor both affect the LDO's system stability. To design an LDO with high load capacity and the ability to accommodate a wide range of external capacitors, appropriate compensation schemes are needed to ensure the LDO loop remains stable under all conditions. Since automotive low-dropout linear regulators must accommodate high load current and a wide range of external capacitors, effective compensation methods are essential for system stability. Current technologies include ESR (Equivalent Series Resistance) compensation and dynamic zero-point compensation.

[0005] In LDOs using a traditional two-stage operational amplifier structure, most currently employ external ESR capacitors for compensation. For example... Figure 1As shown, an ESR capacitor is connected to the output of the LDO to stabilize the system. The principle of ESR compensation is that two main low-frequency poles in a two-stage LDO affect system stability, located at the output of the error amplifier EA and the LDO output respectively (the output of the follower buffer, with its lower impedance, generates a higher frequency pole, which is not considered). When two poles appear within the unity-gain bandwidth, the phase margin of the LDO circuit is at least less than 45°, indicating a possibility of instability. To ensure a phase margin greater than 45° within the unity-gain bandwidth, there must be only one pole or a left-half-plane zero that cancels out the second pole. ESR compensation achieves this by adding an ESR capacitor at the output to generate a left-half-plane zero between the first and second poles. The phase increase of this zero reduces the impact of the phase decrease of the second pole on the LDO's phase margin.

[0006] When designing a low-dropout linear regulator (LDO) with a large load current, the wide range of output current variations will cause pole position shifts at the LDO output. When the output current is small, meaning the LDO load is large (i.e., the load resistance RL is small), the pole positions shift towards higher frequencies according to the pole formula, due to the smaller RL. To achieve a larger unity-gain bandwidth and system stability, dynamic zero-point compensation can be used. For example... Figure 2 As shown, a capacitor and resistor are added in series between EA and BUFFER. The total resistance of the compensation circuit is determined by both R1 and transistor MN1, which is located in the linear region. MN1 is connected such that the transistor is in the linear region. The resistance of the MOS transistor increases or decreases with the increase or decrease of the output current. The change in resistance value changes the zero-point position, causing this zero-point to change with the position of the dominant pole.

[0007] However, ESR compensation and dynamic zero-point compensation each have the following drawbacks:

[0008] 1) Disadvantages of ESR compensation: This method uses the +45° phase introduced by the zero point of ESR compensation and the -45° phase introduced by the secondary pole to neutralize each other, so that the secondary pole will not affect the stability of the LDO system. After compensation, the design requirement of a phase margin greater than 45° can be achieved. However, when applied to LDOs with a large range of output current variation, there are two obvious disadvantages: The first disadvantage is that the resistance R at the LDO output terminal is increased when the current changes. OUTThis change further alters the bandwidth of the LDO. When the output current is low, the leftward shift of the dominant pole reduces the unity-gain bandwidth, which decreases the dynamic response performance of the LDO under low load current conditions and also reduces the LDO's power supply rejection ratio. The second drawback is that LDOs with high output current often use larger power transistors. Larger transistors result in larger parasitic capacitances, which cause the third pole to be located at a lower frequency. The presence of the third pole further affects the stability of the LDO.

[0009] 2) Disadvantages of dynamic zero-point compensation: Traditional dynamic zero-point compensation performs well when the output current range is not very large, but when the output current range is large, dynamic zero-point compensation may not be able to fully cover all operating conditions, resulting in a non-optimal compensation effect. Summary of the Invention

[0010] To address the aforementioned problems in the prior art, this invention provides a high-current, wide-capacitance-range LDO based on a frequency compensation circuit. The technical problem to be solved by this invention is achieved through the following technical solution:

[0011] In a first aspect, embodiments of the present invention provide a high-current, wide-capacitance-range LDO based on a frequency compensation circuit, comprising:

[0012] A single-stage operational amplifier is used to amplify the error signal; the error signal is the difference between the reference voltage and the feedback voltage.

[0013] A second-stage operational amplifier, connected to the first-stage operational amplifier, is used to amplify the amplified error signal a second time.

[0014] A driving circuit, connected to the second-stage operational amplifier, is used to enhance the driving capability of the error signal in the second amplification.

[0015] A current output circuit, connected to the drive circuit, is used to adjust the output current required by the output based on the error signal of the secondary amplification that enhances the drive capability and the input voltage, so as to output the required output voltage through the load circuit.

[0016] A feedback circuit, connected to the current output circuit, is used to generate a new feedback voltage based on the output current.

[0017] The first-stage operational amplifier, connected to the feedback circuit, is also used to amplify the new error signal; the new error signal is the difference between the reference voltage and the new feedback voltage.

[0018] A frequency compensation circuit, connected to the current output circuit and the first-stage operational amplifier, is used to adjust the positions of multiple zeros and poles in the new error signal according to the output current using a multi-zero-pole dynamic compensation branch and a current buffer supplement branch to cancel the secondary poles while widening the entire unity-gain bandwidth, thereby obtaining the adjusted error signal.

[0019] The second-stage operational amplifier, connected to the frequency compensation circuit, is also used to amplify the adjusted error signal a second time.

[0020] In one embodiment of the present invention, the first-stage operational amplifier includes transistors MN1 to MN6, transistors MP1 to MP4, and current source I. bias ;in,

[0021] The gate of transistor MN1 is used as the reference voltage V ref The input terminal, the source of transistor MN1 and the source of transistor MN2, and the current source I bias The input terminals are connected, the drain of transistor MN1 is connected to the source of transistor MP1 and the drain of transistor MP3, the gate of transistor MN2 is connected to the feedback circuit, the drain of transistor MN2 is connected to the source of transistor MP2 and the drain of transistor MP4, the gates of transistors MN3 and MN4 are both connected to the third bias voltage, the source of transistor MN3 is connected to the drain of transistor MN5, the drain of transistor MN3 is connected to the drain of transistor MP1, the gate of transistor MN5, the gate of transistor MN6, and the current buffer supplement branch, the source of transistor MN4 is connected to the drain of transistor MN6, the drain of transistor MN4 is connected to the drain of transistor MP2 and the multi-zero pole dynamic compensation branch, the source of transistor MN5, the source of transistor MN6, and the current source I bias The output terminals of all transistors are grounded. The gates of transistors MP1 and MP2 are connected to the second bias voltage, the gates of transistors MP3 and MP4 are connected to the first bias voltage, and the source of transistor MP3 and the source of transistor MP4 are connected to the power supply VDD.

[0022] In one embodiment of the present invention, the secondary operational amplifier includes a high-voltage power transistor HVMN1 and a resistor R. P Transistor MN7; among which,

[0023] The gate of the high-voltage power transistor HVMN1 is connected to the power supply VDD, and the drain of the high-voltage power transistor HVMN1 is connected to the resistor R. P One end of the drive circuit is connected, the source of the high-voltage power transistor HVMN1 is connected to the drain of transistor MN7, the gate of transistor MN7 is connected to the first-stage operational amplifier, the source of transistor MN7 is grounded, and resistor R... PThe other end is connected to the input voltage V IN .

[0024] In one embodiment of the present invention, the driving circuit includes a follower buffer; the input terminal of the follower buffer is connected to the second-stage operational amplifier, and the output terminal of the follower buffer is connected to the current output circuit.

[0025] In one embodiment of the present invention, the current output circuit includes a high-voltage power transistor HVMP1; the source of the high-voltage power transistor HVMP1 is connected to the input voltage V. IN The drain of the high-voltage power transistor HVMP1 is connected to the feedback circuit, the load circuit, and the current buffer supplement branch, and the gate of the high-voltage power transistor HVMP1 is connected to the multi-zero pole dynamic compensation branch.

[0026] In one embodiment of the present invention, the feedback circuit includes resistor R1 and resistor R2; wherein,

[0027] One end of resistor R1 is connected to the current output circuit, the other end of resistor R1 is connected to one end of resistor R2 and the first-stage operational amplifier, and the other end of resistor R2 is grounded.

[0028] In one embodiment of the present invention, the frequency compensation circuit includes N parallel zero-pole dynamic compensation branches, where N is an integer greater than 1; each zero-pole compensation sub-branch consists of a fixed capacitor and a variable resistor connected in series, with the other end of each fixed capacitor connected to the first-stage operational amplifier and the other end of each variable resistor grounded; wherein, the variable resistor of each zero-pole compensation sub-branch is generated by a variable resistor generation module according to the output current adjusted by the current output circuit; the ratio of the fixed capacitors in all zero-pole compensation sub-branches is 1:2:…:2 N-1 The proportional relationship of the resistance values ​​of the variable resistors is 2. N-1 :…:2:1.

[0029] In one embodiment of the present invention, the variable resistor generating module includes N variable resistor generating branches, transistor MN8, high-voltage power transistor HVMP2, and resistor R. s ;in,

[0030] N variable resistor generation branches are connected in parallel, and each variable resistor generation branch includes a fixed resistor and several transistors connected in series with the fixed resistor. The other end of the fixed resistor is connected to a corresponding fixed capacitor, and the source of the last transistor is connected to the source of transistor MN8. The ratio of the resistance values ​​of the fixed resistors in all variable resistor generation branches is 2:1. N-1 The ratio of transistors is 2:…:2:1. N-1 :…:2:1;

[0031] The gate of transistor MN8 is connected to the drain of transistor MN8, the drain of high-voltage power transistor HVMP2, and the gates of all transistors in each variable resistor generation branch. The gate of high-voltage power transistor HVMP2 is connected to the current output circuit, and the source of high-voltage power transistor HVMP2 is connected to resistor R. s One end is connected to resistor R s The other end is connected to the input voltage V IN .

[0032] In one embodiment of the present invention, the current buffer supplement branch in the frequency compensation circuit includes a capacitor C1; one end of the capacitor C1 is connected to the current output circuit, and the other end of the capacitor C1 is connected to the first-stage operational amplifier.

[0033] In one embodiment of the present invention, the load circuit includes a resistor R. L and capacitor C L ;in,

[0034] resistor R L One end is connected to capacitor C L One end of the current output circuit is connected and serves as the output voltage V. OUT The output terminal has a resistor R. L The other end, capacitor C L The other end of each is grounded.

[0035] The beneficial effects of this invention are:

[0036] This invention proposes a high-current, wide-capacitance-range LDO based on a frequency compensation circuit. Addressing the instability of LDO circuits caused by large load current variations and large allowable load capacitance ranges, it offers a novel frequency compensation scheme. Compared to traditional compensation circuits, it innovatively combines multi-zero-pole dynamic compensation and current buffer compensation to achieve frequency compensation for high-current, wide-capacitance-range LDO circuits. This reduces the power consumption of the dynamic compensation circuit while expanding the frequency compensation range. It enables the LDO circuit to achieve good phase margin under a wide output current range and wide capacitive load conditions, while minimizing bandwidth loss. This ensures a large bandwidth even with a large current output range and a large load capacitance range, and also guarantees the stability of the LDO circuit, thus solving the stability problem of high-current, wide-capacitance-range LDOs.

[0037] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of a traditional LDO structure based on ESR compensation;

[0039] Figure 2 This is a schematic diagram of a traditional LDO structure based on dynamic zero-point compensation;

[0040] Figure 3 This is a schematic diagram of a high-current, wide-capacitance-range LDO based on a frequency compensation circuit provided in an embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram of a high-current, wide-capacitance-range LDO based on a frequency compensation circuit provided in an embodiment of the present invention.

[0042] Figure 5 This is a schematic diagram of a variable resistor generating circuit provided in an embodiment of the present invention;

[0043] Figure 6 This is provided by the embodiments of the present invention. Figure 4 A schematic diagram of the corresponding small-signal model of LDO;

[0044] Figure 7 This is provided by the embodiments of the present invention. Figure 4 A schematic diagram comparing the frequency response before and after adding a multi-zero-pole dynamic compensation branch. Detailed Implementation

[0045] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0046] Please see Figure 3 This invention provides a high-current, wide-capacitance-range LDO based on a frequency compensation circuit, comprising:

[0047] A single operational amplifier is used to amplify the error signal; the error signal is the difference between the reference voltage and the feedback voltage.

[0048] The second-stage operational amplifier connects to the first-stage operational amplifier and is used to amplify the amplified error signal a second time.

[0049] The driving circuit, connected to the two-stage operational amplifier, is used to enhance the driving capability of the error signal in the secondary amplification.

[0050] The current output circuit, connected to the drive circuit, is used to adjust the output current required by the secondary amplified error signal with enhanced drive capability and the input voltage, so as to output the required output voltage through the load circuit.

[0051] The feedback circuit is connected to the current output circuit and is used to generate a new feedback voltage based on the output current.

[0052] The first-stage operational amplifier, connected to the feedback circuit, is also used to amplify the new error signal; the new error signal is the difference between the reference voltage and the new feedback voltage.

[0053] The frequency compensation circuit connects the current output circuit and the first-stage operational amplifier. It is used to adjust the positions of multiple zeros and poles in the new error signal according to the output current to cancel the secondary poles and widen the entire unity-gain bandwidth, thereby obtaining the adjusted error signal.

[0054] The second-stage operational amplifier, connected to the frequency compensation circuit, is also used to amplify the adjusted error signal a second time.

[0055] Next, each part will be introduced in detail.

[0056] In this embodiment of the invention, the first-stage operational amplifier is as follows: Figure 4 As shown, it includes transistors MN1 to MN6, transistors MP1 to MP4, and current source I. bias ;in,

[0057] The gate of transistor MN1 is used as the reference voltage V ref The input terminal, the source of transistor MN1 and the source of transistor MN2, and the current source I bias The input terminals are connected, the drain of transistor MN1 is connected to the source of transistor MP1 and the drain of transistor MP3, the gate of transistor MN2 is connected to the feedback circuit, the drain of transistor MN2 is connected to the source of transistor MP2 and the drain of transistor MP4, and the gates of transistors MN3 and MN4 are both connected to the third bias voltage V. b3 The source of transistor MN3 is connected to the drain of transistor MN5. The drain of transistor MN3 is connected to the drain of transistor MP1, the gate of transistor MN5, the gate of transistor MN6, and the current buffer compensation branch. The source of transistor MN4 is connected to the drain of transistor MN6. The drain of transistor MN4 is connected to the drain of transistor MP2 and the multi-zero pole dynamic compensation branch. The source of transistor MN5, the source of transistor MN6, and current source I... bias The output terminals of both transistors are grounded, and the gates of transistors MP1 and MP2 are connected to the second bias voltage V. b2 The gates of transistors MP3 and MP4 are both connected to the first bias voltage V. b1 The source of transistor MP3 and transistor MP4 are both connected to the power supply VDD. The reference voltage V... ref First bias voltage V b1 Second bias voltage V b2 Third bias voltage V b3 It is set according to actual needs.

[0058] In this embodiment of the invention, transistors MN1 to MN6 are NMOS transistors; transistors MP1 to MP4 are PMOS transistors.

[0059] Furthermore, in this embodiment of the invention, the secondary operational amplifier is as follows: Figure 4 As shown, it includes a high-voltage power transistor HVMN1 and a resistor R. P Transistor MN7; among which,

[0060] The gate of the high-voltage power transistor HVMN1 is connected to the power supply VDD, and the drain of the high-voltage power transistor HVMN1 is connected to the resistor R. P One end is connected to the drive circuit. The source of the high-voltage power transistor HVMN1 is connected to the drain of transistor MN7. The gate of transistor MN7 is connected to the first-stage operational amplifier. The source of transistor MN7 is grounded. Resistor R P The other end is connected to the input voltage V IN Among them, the input voltage V IN It is set according to actual needs.

[0061] In this embodiment of the invention, transistor MN7 is an NMOS transistor; high-voltage power transistor HVMN1 is an NMOS power transistor.

[0062] Furthermore, the driving circuit in the embodiments of the present invention is as follows: Figure 4 As shown, it includes a follower buffer; the input of the follower buffer is connected to the second-stage operational amplifier, and the output of the follower buffer is connected to the current output circuit.

[0063] Furthermore, in this embodiment of the invention, the current output circuit is as follows: Figure 4 As shown, it includes a high-voltage power transistor HVMP1; the source of the high-voltage power transistor HVMP1 is connected to the input voltage V. IN The drain of the high-voltage power transistor HVMP1 is connected to the feedback circuit, the load circuit, and the current buffer supplement branch, and the gate of the high-voltage power transistor HVMP1 is connected to the multi-zero pole dynamic compensation branch.

[0064] In this embodiment of the invention, the high-voltage power transistor HVMP1 is a PMOS power transistor.

[0065] Furthermore, in this embodiment of the invention, the feedback circuit is as follows: Figure 4 As shown, it includes resistors R1 and R2; one end of resistor R1 is connected to the current output circuit, the other end of resistor R1 is connected to one end of resistor R2 and a first-stage operational amplifier, and the other end of resistor R2 is grounded.

[0066] Furthermore, in this embodiment of the invention, the frequency compensation circuit includes N parallel zero-pole dynamic compensation branches, where N is an integer greater than 1. Each zero-pole compensation sub-branch consists of a fixed capacitor and a variable resistor connected in series. The other end of each fixed capacitor is connected to a first-stage operational amplifier, and the other end of each variable resistor is grounded. The variable resistor of each zero-pole compensation sub-branch is generated by a variable resistor generation module that adjusts the output current according to the current output circuit. The ratio of the fixed capacitors in all zero-pole compensation sub-branches is 1:2:…:2. N-1 The proportional relationship of the resistance values ​​of the variable resistors is 2. N-1 :…:2:1. Figure 4 The structure of a multi-zero-pole dynamic compensation branch with N=3 is illustrated.

[0067] In this embodiment of the invention, the variable resistor generation module includes N variable resistor generation branches, transistor MN8, high-voltage power transistor HVMP2, and resistor R. s ;in,

[0068] N variable resistor generation branches are connected in parallel, and each variable resistor generation branch includes a fixed resistor and several transistors connected in series with the fixed resistor. The other end of the fixed resistor is connected to a corresponding fixed capacitor, and the source of the last transistor is connected to the source of transistor MN8. The ratio of the resistance values ​​of the fixed resistors in all variable resistor generation branches is 2:1. N-1 The ratio of transistors is 2:...:2:1. N-1 :...:2:1; The gate of transistor MN8 is connected to the drain of transistor MN8, the drain of high-voltage power transistor HVMP2, and the gates of all transistors in each variable resistor generation branch. The gate of high-voltage power transistor HVMP2 is connected to the current output circuit. The source of high-voltage power transistor HVMP2 is connected to resistor R. s One end is connected to resistor R s The other end is connected to the input voltage V IN .like Figure 5 The structure of a variable resistor generation module with N=3 is illustrated.

[0069] In this embodiment of the invention, transistor MN8 is an NMOS transistor; high-voltage power transistor HVMP2 is a PMOS power transistor.

[0070] Furthermore, in the frequency compensation circuit of this embodiment, the current buffer supplement branch is as follows: Figure 4 As shown, it includes capacitor C1; one end of capacitor C1 is connected to the current output circuit, and the other end of capacitor C1 is connected to the first-stage operational amplifier.

[0071] Furthermore, in this embodiment of the invention, the load circuit is as follows: Figure 4 As shown, it includes resistor R Land capacitor C L Among them, the resistance R L One end is connected to capacitor C L One end is connected to the current output circuit and serves as the output voltage V. OUT The output terminal has a resistor R. L The other end, capacitor C L The other end of each is grounded.

[0072] Next, the working principle of the LDO proposed in this invention will be introduced.

[0073] Before analyzing the LDO circuit, we first derive its small-signal model. From this model, we can see that without frequency compensation, the LDO circuit has three poles: Figure 4 The magnitudes of the three poles at three points—A (output node of the first-stage operational amplifier), B (gate of the high-voltage power transistor HVMP1), and C (output terminal of the LDO)—are as follows:

[0074]

[0075] In formula (1), ω A R represents the frequency of the pole at the output node of a first-stage operational amplifier. EA This represents the equivalent resistance of the output node of the first-stage operational amplifier, C. EA ω represents the parasitic capacitance at the output node of the first-stage operational amplifier; in formula (2) ω B R represents the frequency of the pole at the gate of the high-voltage power transistor HVMP1. g C represents the equivalent resistance at the gate of the high-voltage power transistor HVMP1. g This represents the equivalent capacitance at the gate of the high-voltage power transistor HVMP1; in formula (3), ω C R represents the frequency of the LDO output poles. L C represents the load resistance at the LDO output. L This represents the load capacitance at the LDO output. In the design, it is located at pole A, due to R... EA and C EA The value of ω is fixed and will not change with the output current and load capacitance, therefore ω A The frequency positions are fixed; the pole at B varies with the load, potentially below or above unity-gain frequency; the pole at C moves across a wide frequency range with the load current. In this case, the dominant pole is C under light load and gradually transitions to A as the load increases. Considering that all three poles may appear below unity-gain frequency, it is difficult to achieve stability even by introducing zeros within the bandwidth.

[0076] Based on the above analysis, it was found that the LDO has stability issues. Therefore, the frequency compensation circuit designed in this invention was added to compensate for the instability. The following analysis explains how the LDO achieves stability after adding the frequency compensation circuit.

[0077] Figure 6 This is a small-signal model of an LDO circuit including a frequency compensation circuit, where gm1 is the transconductance of transistor MN1, gm2 is the transconductance of transistor MN6, gm3 is the transconductance of high-voltage power transistor HVMP1, gm4 is the transconductance of transistor MN5, and F = R2 / (R1 + R2) is the feedback factor. Figure 4 and Figure 5 Taking N=3 as an example, if we directly consider the effects of three multi-zero pole dynamic compensation branches and one current buffer compensation branch on the circuit, there will be too many poles, making it impossible to calculate the transfer function. To reduce the difficulty of analysis, we will discuss the effects of the two types of compensation on the circuit below.

[0078] For the current buffer compensation branch section, see [link / reference]. Figure 4 The red lines mark the branches and Figure 6 The branch is marked with a red line. The current buffer compensation branch includes capacitor C1, which acts on the following components in the LDO circuit: high-voltage power transistors HVMP1 and HVMN1, transistors MN2, MN4, and MN5, the (source) follower buffer, and resistor R. P Transistor MP2 and transistor MP4. When considering current buffer compensation, the multi-zero-pole dynamic compensation branch is equivalent to C. Z and R Z Series (e.g.) Figure 6 (As shown in the blue dashed box), r is substituted into the calculation for convenience. o = 1 / gm4. The transfer function of the current buffer compensation branch is calculated as follows:

[0079]

[0080] Observing the denominator of the transfer function in formula (4), the highest-order term is fifth, which means there are five poles. Ignoring the higher-order terms and considering only the first two poles, we can obtain the frequencies of the two poles and two zeros:

[0081]

[0082] Because r o The value of C1 is relatively small, so the frequency ω Z2 The frequency is relatively high and has no impact on the circuit, so this high-frequency zero is not considered here. Firstly, through the relationship between frequency ω1 and frequency ω... A The comparison shows that the dominant pole frequency ω1 after frequency compensation is significantly lower than the dominant pole frequency ω before compensation. AThis means that the loop gain decreases from a lower frequency, and by adjusting the parameters, it can be reduced to 0 before the pole at point B takes effect. Secondly, the frequency at the dominant pole A is less sensitive to changes in load current and capacitance than before compensation, especially under heavy load conditions, making the dominant pole more stable. Secondly, the frequency change at the second pole (sub-pole) C is divided into light load and heavy load conditions; under light load conditions, g... m2 R g g m3 R L C1 is much larger than C Z Formula (6) can be simplified to:

[0083]

[0084] As can be seen from formula (9), under light load conditions, frequency ω'2 is always less than frequency ω. Z1 By designing R Z The resistance is used to control ω Z1 The distance between ω'2 and the zero point can compensate for the second pole C, ensuring that the phase margin is still greater than 60 degrees when the gain drops to 0, thus maintaining a stable state. Under heavy load conditions, R L Much smaller than R EA Formula (6) can be simplified to:

[0085]

[0086] As can be seen from formula (10), if the frequency of the second pole under heavy load is greater than that under light load, and the pole is stable under light load, then it is guaranteed to be stable under heavy load as well.

[0087] As can be seen from the above analysis, the stability of the LDO circuit is improved after compensation by the current buffer compensation branch. However, under light load conditions, if the load capacitance is large, the main pole and the second pole will be close together, and the unity gain bandwidth will be very small. Therefore, a multi-zero pole dynamic compensation branch is added to increase the unity gain bandwidth of the circuit.

[0088] For the multi-zero-pole dynamic compensation branch section, see [link / reference]. Figure 4 The circuit within the blue dashed box and Figure 6 The circuit within the blue dashed box contains a zero-pole branch compensation branch connected to a variable resistor R. Z1 Variable resistor R Z2 Variable resistor R Z3 Fixed capacitor C Z1 Fixed capacitor C Z2 Fixed capacitor C Z3 Composition, in which the variable resistor R Z1 R Z2 R Z3 The circuit generated by the variable resistor is as follows Figure 5As shown, the variable resistor R is generated. Z3 By fixed resistor R C and several transistors MN connected in series 11 Composition, variable resistor R Z2 By fixed resistor R B and several transistors MN connected in series 10 Composition, variable resistor R Z1 By fixed resistor R A It consists of several transistors MN9 connected in series. In addition to the above components, the variable resistor generating circuit also includes a resistor R. S The system consists of a high-voltage power transistor HVMP2 and a transistor MN8. In the variable resistor generation module, the gate of HVMP2 is connected to the gate of HVMP1 to form a current mirror. The width-to-length ratio of HVMP2 and HVMP1 is set in a certain proportion so that the current flowing through HVMP2 and the load current I... OUT Proportional, for example, load current I OUT When the current is 100mA, the aspect ratio of HVMP2 to HVMP1 is set so that the current flowing through HVMP2 is 1mA. This is how the load current I is controlled. OUT Sampling. Here, a resistor R is added. S This improves the linearity of dynamic resistance and load current changes in the variable resistor generation branch. The width-to-length ratio of MN8 is similar to that of MN9 and MN... 10 MN 11 All transistors in the transistor have the same width-to-length ratio. The sampled current flows through MN8 to control MN9 and MN2. 10 MN 11 The gate voltages of each transistor in the circuit, under heavy load conditions, are MN9 and MN2. 10 MN 11 The resistance of each lattice transistor is too small, therefore a fixed resistor R is increased. A R B R C This increases the total resistance and helps stabilize the circuit.

[0089] A dynamic network with multiple zero-pole dynamic compensation branches is used to solve the problem of large pole variation range. Multiple zeros and poles move together to cancel out secondary poles while widening the unity-gain bandwidth. Figure 4 The blue dashed box illustrates the structure with N=3. A compensation network is designed with three zero-pole compensating sub-branches. The resistance and capacitance values ​​of the three sub-branches are proportional, generating three zeros and three poles that are alternately distributed. For example... Figure 4 Fixed capacitor C Z1 :C Z2 :C Z3 =1:2:4, Figure 5 Fixed resistor RA :R B :R C =1:2:4, Figure 5 Number of transistors in MN9:MN 10 :MN 11 =1:2:4, Figure 6 C EA Much smaller than the compensation capacitor C Z1 C Z2 C Z3 Therefore, it can be ignored.

[0090] The transfer function of the multi-zero pole dynamic compensation branch is as follows:

[0091]

[0092] Because of R A :R B :R C =1R:2R:4R, C Z1 :C Z2 :C Z3 =1C:2C:4C, R EA If the value is much greater than R, then the transfer function of the multi-zero-pole dynamic compensation branch is simplified:

[0093]

[0094] From formula (11), we can see that Figure 4 The frequencies at which the multi-zero-pole dynamic compensation branch generates three poles are denoted as P1, P2, and P3, and the frequencies at which it generates three zeros are denoted as Z1, Z2, and Z3. Analyzing the magnitudes of the generated zeros and poles, the frequency relationship between the zeros and poles is P1 < Z1 < P2 < Z2 < P3 < Z3. Therefore, the generated zeros and poles will interact and influence the phase. To verify the effect of adding the multi-zero-pole dynamic compensation branch, Figure 7 The results show a comparison of the frequency response before and after adding a multi-zero-pole dynamic compensation branch. Figure 7 It can be seen that adding a multi-zero-pole dynamic compensation branch can improve the phase margin and the dominant pole P EA The pole frequency P1 of the multi-zero-pole dynamic compensation branch and the main pole ω1 of the current buffer compensation branch jointly determine that no matter how the frequency POUT of the LDO output pole changes, the phase margin is always greater than 90° within the unity-gain bandwidth, and the unity-gain bandwidth of the LDO circuit is improved on this basis.

[0095] This invention provides a frequency compensation circuit for a high-current, wide-capacitance LDO. Compared to traditional compensation circuits, it utilizes a combination of multi-pole-zero dynamic compensation and current buffer compensation. In the multi-pole-zero dynamic compensation branch, the variable resistor is generated by a variable resistor generation module. The current buffer compensation branch of the LDO is implemented using Miller capacitors, which are connected from the LDO's output node to the gates of the operational amplifier's active current mirror loads MN5 and MN6. The multi-pole-zero dynamic compensation branch of the LDO is implemented by connecting multiple fixed capacitors and variable resistors in series to the output node of the first-stage operational amplifier. The resistance value of the variable resistor changes with the increase or decrease of the load current, thereby generating multiple zeros with varying frequencies. The current buffer compensation branch separates the poles at the output of the first-stage operational amplifier from those at the LDO's output, pushing them away from their respective positions. The multi-pole-zero dynamic compensation branch then addresses the issue of a potential second pole entering the unity-gain bandwidth. The design of the multi-pole-zero dynamic compensation branch incorporates multiple pole-zero generation branches, ensuring the LDO remains stable under both minimum and maximum load current conditions. As can be seen, the frequency compensation scheme proposed in this embodiment of the invention can maintain the stability of the LDO circuit under a large output current range and a wide load capacitance range, and improve the bandwidth of the LDO circuit, so that the LDO circuit can both ensure stability and have a larger bandwidth. It innovatively combines two compensation methods to compensate the LDO, which, unlike traditional dynamic compensation, generates multiple zeros and poles through parallel connection of multiple branches, enabling the LDO circuit to obtain a larger bandwidth. At the same time, by using this compensation method to place the dominant pole on-chip, the requirement for external capacitors to ensure system stability of the LDO chip can be reduced.

[0096] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0097] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0098] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high-current, wide-capacitance-range LDO based on a frequency compensation circuit, characterized in that, include: A single-stage operational amplifier is used to amplify the error signal; the error signal is the difference between the reference voltage and the feedback voltage. A second-stage operational amplifier, connected to the first-stage operational amplifier, is used to amplify the amplified error signal a second time. A driving circuit, connected to the second-stage operational amplifier, is used to enhance the driving capability of the error signal in the second amplification. A current output circuit, connected to the drive circuit, is used to adjust the output current required by the output based on the error signal of the secondary amplification that enhances the drive capability and the input voltage, so as to output the required output voltage through the load circuit. A feedback circuit, connected to the current output circuit, is used to generate a new feedback voltage based on the output current. The first-stage operational amplifier, connected to the feedback circuit, is also used to amplify the new error signal; the new error signal is the difference between the reference voltage and the new feedback voltage. A frequency compensation circuit, connected to the current output circuit and the first-stage operational amplifier, is used to adjust the positions of multiple zeros and poles in the new error signal based on the output current using a multi-zero-pole dynamic compensation branch and a current buffer supplementary branch. This adjusts the position of secondary poles while widening the entire unity-gain bandwidth, resulting in an adjusted error signal. The multi-zero-pole dynamic compensation branch in the frequency compensation circuit includes N parallel zero-pole compensation sub-branches, where N is an integer greater than 1. Each zero-pole compensation sub-branch consists of a fixed capacitor and a variable resistor connected in series. The other end of each fixed capacitor is connected to the first-stage operational amplifier, and the other end of each variable resistor is grounded. The variable resistor in each zero-pole compensation sub-branch is generated by a variable resistor generation module based on the output current adjusted by the current output circuit. The proportional relationship of the fixed capacitors in all zero-pole compensation sub-branches is as follows: The proportional relationship of the resistance values ​​of the variable resistors is as follows: The frequency compensation circuit includes a current buffer supplement branch with capacitor C1; one end of capacitor C1 is connected to the current output circuit, and the other end of capacitor C1 is connected to the first-stage operational amplifier. The second-stage operational amplifier, connected to the frequency compensation circuit, is also used to amplify the adjusted error signal a second time.

2. The high-current, wide-capacitance-range LDO based on a frequency compensation circuit according to claim 1, characterized in that, The first-stage operational amplifier includes transistors MN1 to MN6, transistors MP1 to MP4, and a current source I. bias ;in, The gate of transistor MN1 is used as the reference voltage V ref The input terminal, the source of transistor MN1 and the source of transistor MN2, and the current source I bias The input terminals are connected, the drain of transistor MN1 is connected to the source of transistor MP1 and the drain of transistor MP3, the gate of transistor MN2 is connected to the feedback circuit, the drain of transistor MN2 is connected to the source of transistor MP2 and the drain of transistor MP4, the gates of transistors MN3 and MN4 are both connected to the third bias voltage, the source of transistor MN3 is connected to the drain of transistor MN5, the drain of transistor MN3 is connected to the drain of transistor MP1, the gate of transistor MN5, the gate of transistor MN6, and the current buffer supplement branch, the source of transistor MN4 is connected to the drain of transistor MN6, the drain of transistor MN4 is connected to the drain of transistor MP2 and the multi-zero pole dynamic compensation branch, the source of transistor MN5, the source of transistor MN6, and the current source I bias The output terminals of all transistors are grounded. The gates of transistors MP1 and MP2 are connected to the second bias voltage, the gates of transistors MP3 and MP4 are connected to the first bias voltage, and the source of transistor MP3 and the source of transistor MP4 are connected to the power supply VDD.

3. The high-current, wide-capacitance-range LDO based on a frequency compensation circuit according to claim 1, characterized in that, The secondary operational amplifier includes a high-voltage power transistor HVMN1 and a resistor R. P Transistor MN7; among which, The gate of the high-voltage power transistor HVMN1 is connected to the power supply VDD, and the drain of the high-voltage power transistor HVMN1 is connected to the resistor R. P One end of the drive circuit is connected, the source of the high-voltage power transistor HVMN1 is connected to the drain of transistor MN7, the gate of transistor MN7 is connected to the first-stage operational amplifier, the source of transistor MN7 is grounded, and resistor R... P The other end is connected to the input voltage V IN .

4. The high-current, wide-capacitance-range LDO based on a frequency compensation circuit according to claim 1, characterized in that, The driving circuit includes a follower buffer; the input terminal of the follower buffer is connected to the second-stage operational amplifier, and the output terminal of the follower buffer is connected to the current output circuit.

5. The high-current, wide-capacitance-range LDO based on a frequency compensation circuit according to claim 1, characterized in that, The current output circuit includes a high-voltage power transistor HVMP1; the source of the high-voltage power transistor HVMP1 is connected to the input voltage V. IN The drain of the high-voltage power transistor HVMP1 is connected to the feedback circuit, the load circuit, and the current buffer supplement branch, and the gate of the high-voltage power transistor HVMP1 is connected to the multi-zero pole dynamic compensation branch.

6. The high-current, wide-capacitance-range LDO based on a frequency compensation circuit according to claim 1, characterized in that, The feedback circuit includes resistors R1 and R2; wherein... One end of resistor R1 is connected to the current output circuit, the other end of resistor R1 is connected to one end of resistor R2 and the first-stage operational amplifier, and the other end of resistor R2 is grounded.

7. The high-current, wide-capacitance-range LDO based on a frequency compensation circuit according to claim 1, characterized in that, The variable resistor generation module includes N variable resistor generation branches, transistor MN8, high-voltage power transistor HVMP2, and resistor R. s ;in, N variable resistor generation branches are connected in parallel, and each variable resistor generation branch includes a fixed resistor and several transistors connected in series with the fixed resistor. The other end of the fixed resistor is connected to a corresponding fixed capacitor, and the source of the last transistor is connected to the source of transistor MN8. The proportional relationship of the resistance values ​​of the fixed resistors in all variable resistor generation branches is as follows: The ratio of the number of transistors is as follows: ; The gate of transistor MN8 is connected to the drain of transistor MN8, the drain of high-voltage power transistor HVMP2, and the gates of all transistors in each variable resistor generation branch. The gate of high-voltage power transistor HVMP2 is connected to the current output circuit, and the source of high-voltage power transistor HVMP2 is connected to resistor R. s One end is connected to resistor R s The other end is connected to the input voltage V IN .

8. The high-current, wide-capacitance-range LDO based on a frequency compensation circuit according to claim 1, characterized in that, The load circuit includes a resistor R. L and capacitor C L ;in, resistor R L One end is connected to capacitor C L One end of the current output circuit is connected and serves as the output voltage V. OUT The output terminal has a resistor R. L The other end, capacitor C L The other end of each is grounded.

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