Current reference source circuit, chip and electronic equipment
By using multiple current mirrors and NPN transistors in the reference current source circuit, setting the current ratio and saturation current ratio, the existing circuit complex, large area and high cost are solved, and the reference current output with high precision and low temperature drift is achieved and the circuit simplification is achieved.
Patent Information
- Application Number
- CN202311518468.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-14
- Publication Date
- 2025-05-16
Smart Images
Figure CN120010616A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a current reference source circuit, a chip and an electronic device. Background Art
[0002] The reference current source circuit is a key basic module widely used in analog circuit design and is widely used in various analog integrated circuits with high performance requirements, such as operational amplifiers, A / D converters, D / A converters, etc. The temperature stability of the reference current source circuit is particularly important. The reference current source it outputs must have a low temperature coefficient, that is, low temperature drift, otherwise the performance of the integrated circuit will change with temperature changes.
[0003] The traditional reference current source circuit is as follows Figure 1 As shown, the bandgap reference generates a low-temperature drift reference voltage Vref and connects it to the positive input of the op amp. Since the input of the op amp has a virtual short characteristic, the voltage at its negative input (i.e., the voltage on the resistor) is also equal to Vref. Figure 1 R in the figure is a zero temperature coefficient resistor, whose resistance does not change with temperature, so the current flowing through R (also the current flowing through N1 and P1) is: I = Vref / R. Since Vref is a low temperature drift reference voltage and R is a zero temperature coefficient resistor, I is also a low temperature drift current. The two PMOS tubes P1 and P2 form a current mirror, and the current flowing through P2 is equal to the current flowing through P1, so the reference current output from the IBIAS port will also be a low temperature drift current.
[0004] Figure 1 The conventional solution of the reference current source circuit shown in the figure can generate a high-precision and low-temperature drift reference current, but the circuit is relatively complex, occupies a large area, and is relatively costly.
[0005] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention
[0006] The purpose of the present invention is to provide a current reference source circuit, chip and electronic equipment to solve the problems of complex circuits, large occupied area and high cost in existing solutions.
[0007] In order to solve the above technical problems, the present invention provides a current reference source circuit, comprising a first current mirror, a second current mirror, a third current mirror and a fourth current mirror, wherein current input terminals of the first current mirror and the second current mirror are both connected to a power supply voltage, and mirror current output terminals of the first current mirror and the second current mirror are connected in common and connected to a reference current input terminal of the third current mirror, currents output by the mirror current output terminals of the first current mirror and the second current mirror have a first preset ratio, and the mirror current output terminal of the third current mirror is used to output a reference current; the fourth current mirror comprises:
[0008] a first NPN transistor, wherein the base and the collector of the first NPN transistor are interconnected, the base of the first NPN transistor serves as a reference current input terminal, and the base of the first NPN transistor is also connected to the power supply voltage;
[0009] a third NPN transistor, wherein the third NPN transistor is interconnected with the base of the first NPN transistor, the collector of the third NPN transistor is connected to the reference current output terminal of the first current mirror, and the emitter of the first NPN transistor is connected to the collector of the second NPN transistor; in addition:
[0010] The emitter of the third NPN transistor is connected to the collector of the fourth NPN transistor, the base of the second NPN transistor is connected to the collector of the fourth NPN transistor, the fourth NPN transistor is connected to the collector of the second NPN transistor, the emitters of the second NPN transistor and the fourth NPN transistor are both grounded, the reference current output end of the second current mirror is connected to the collector of the fifth NPN transistor, the base of the fifth NPN transistor is connected to the third NPN transistor, and the emitter of the fifth NPN transistor is grounded;
[0011] There is a second preset ratio between the saturation currents of the first NPN transistor, the second NPN transistor, the third NPN transistor, the fourth NPN transistor and the fifth NPN transistor.
[0012] Preferably, a second preset ratio between the saturation currents of the first NPN transistor, the second NPN transistor, the third NPN transistor, the fourth NPN transistor and the fifth NPN transistor is m:1:1:n:1.
[0013] Preferably, the first current mirror includes a first PMOS tube and a second PMOS tube, the gates of the first PMOS tube and the second PMOS tube are interconnected, the sources of the first PMOS tube and the second PMOS tube serve as a reference current input terminal and a mirror current input terminal respectively, and are connected to the power supply voltage, the drain and the gate of the first PMOS tube are commonly connected to the collector of the third NPN transistor, and the drain of the second PMOS tube serves as a mirror current output terminal.
[0014] Preferably, the second current mirror includes a third PMOS tube and a fourth PMOS tube, the gates of the third PMOS tube and the fourth PMOS tube are interconnected, the sources of the third PMOS tube and the fourth PMOS tube serve as a reference current input terminal and a mirror current input terminal respectively, and are connected to the power supply voltage, the drain and the gate of the third PMOS tube are commonly connected to the collector of the fifth NPN transistor, and the drain of the fourth PMOS tube serves as a mirror current output terminal.
[0015] Preferably, the third current mirror includes a first NMOS tube and a second NMOS tube, the gates of the first NMOS tube and the second NMOS tube are interconnected, the drain and the gate of the first NMOS tube are interconnected, and the gate serves as a reference current input terminal, the sources of the first NMOS tube and the second NMOS tube are connected in common and grounded, and the drain of the second NMOS tube serves as a mirror current output terminal.
[0016] Preferably, one end of the first NPN transistor where the base and the collector are connected is also connected to the power supply voltage via a first resistor.
[0017] Preferably, the emitter of the fourth NPN transistor is connected to the first end of the second resistor, and the second end of the second resistor is grounded.
[0018] Preferably, the emitter of the fifth NPN transistor is grounded through a third resistor.
[0019] A chip comprises the above-mentioned current reference source circuit.
[0020] An electronic device comprises the above-mentioned current reference source circuit.
[0021] In the current reference source circuit provided by the present invention, by setting the proportional relationship between the output currents of the first current mirror and the second current mirror, and based on the second preset ratio between the saturation currents of the first NPN transistor npn1, the second NPN transistor npn2, the third NPN transistor npn3, the fourth NPN transistor npn4 and the fifth NPN transistor npn5, the characteristics of the NPN transistor itself and the relationship between the input and output currents of the current mirror are utilized, so that a current with a zero temperature coefficient is output at the mirror current output terminal IBIAS of the third current mirror, and the provided current reference source circuit has a simple structure, small occupied area and low cost.
[0022] The chip and electronic device provided by the present invention and the current reference source circuit provided by the present invention belong to the same inventive concept, therefore, the chip and electronic device provided by the present invention at least have all the advantages of the current reference source circuit provided by the present invention, which will not be described in detail here. Further, by utilizing the characteristics of the NPN transistor itself and the relationship between the input and output currents of the current mirror, the proportional relationship between the output currents of the first current mirror and the second current mirror and the proportional relationship between the saturation currents of the NPN transistors are set, forming a current reference source circuit with a simple structure, capable of outputting a current with a zero temperature coefficient, and having the advantages of small area and low cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 It is a traditional reference current source circuit diagram;
[0024] Figure 2 This is a current reference source circuit diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0025] The current reference source circuit, chip and electronic device proposed in the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to illustrate certain principles of the present invention in the drawings in the specification will also be slightly simplified. The specific design features of the present invention disclosed herein include, for example, specific dimensions, directions, positions and shapes, which will be determined in part by the specific application and use environment. And, in the embodiments described below, sometimes the same figure mark is used in common between different drawings to represent the same part or the part with the same function, and its repeated description is omitted. In this specification, similar numbers and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.
[0026] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0027] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.
[0028] The inventors have found that the conventional current reference current source circuit is complex, occupies a large area and has high cost.
[0029] Based on this, the core idea of the present invention is to form a current reference source circuit with a simple structure by setting multiple current mirrors and multiple NPN transistors, so as to output a high-precision and low-temperature drift reference current, and has the advantages of small footprint and low cost.
[0030] Please refer to Figure 2 , which is a schematic diagram of an embodiment of the present invention. A current reference source circuit includes a first current mirror, a second current mirror, a third current mirror and a fourth current mirror, the current input terminals of the first current mirror and the second current mirror are both connected to a power supply voltage VDD, and the mirror current output terminals of the first current mirror and the second current mirror are connected in common and connected to a reference current input terminal of the third current mirror, the currents output by the mirror current output terminals of the first current mirror and the second current mirror have a first preset ratio, and the mirror current output terminal IBIAS of the third current mirror is used to output a reference current; the fourth current mirror includes:
[0031] a first NPN transistor npn1, wherein the base and the collector of the first NPN transistor npn1 are interconnected, the base of the first NPN transistor npn1 serves as a reference current input terminal, and the base of the first NPN transistor npn1 is also connected to the power supply voltage VDD;
[0032] a third NPN transistor npn3, wherein the third NPN transistor npn3 is interconnected with the base of the first NPN transistor npn1, the collector of the third NPN transistor npn3 is connected to the reference current output end of the first current mirror, and the emitter of the first NPN transistor npn1 is connected to the collector of the second NPN transistor npn2;
[0033] In addition, the emitter of the third NPN transistor npn3 is connected to the collector of the fourth NPN transistor npn4, the base of the second NPN transistor npn2 is connected to the collector of the fourth NPN transistor npn4, the fourth NPN transistor npn4 is connected to the collector of the second NPN transistor npn2, the emitters of the second NPN transistor npn2 and the fourth NPN transistor npn4 are both grounded, the reference current output end of the second current mirror is connected to the collector of the fifth NPN transistor npn5, the base of the fifth NPN transistor npn5 is connected to the third NPN transistor npn3, and the emitter of the fifth NPN transistor npn5 is grounded;
[0034] There is a second preset ratio between the saturation currents of the first NPN transistor npn1, the second NPN transistor npn2, the third NPN transistor npn3, the fourth NPN transistor npn4 and the fifth NPN transistor npn5.
[0035] By setting a proportional relationship between the output currents of the first current mirror and the second current mirror, and based on a second preset ratio between the saturation currents of the first NPN transistor npn1, the second NPN transistor npn2, the third NPN transistor npn3, the fourth NPN transistor npn4 and the fifth NPN transistor npn5, utilizing the characteristics of the NPN transistor itself and the relationship between the input and output currents of the current mirror, a current with a zero temperature coefficient is output at the mirror current output terminal IBIAS of the third current mirror, and the provided current reference source circuit has a simple structure, a small occupied area and a low cost.
[0036] Specifically, a second preset ratio between the saturation currents of the first NPN transistor npn1, the second NPN transistor npn2, the third NPN transistor npn3, the fourth NPN transistor npn4 and the fifth NPN transistor npn5 is m:1:1:n:1.
[0037] In one embodiment, the area ratio of the five npn tubes npn1 to npn5 is:
[0038] S npn1 :S npn2 :S npn3 :S npn4 :Snpn5 =m:1:1:n:1
[0039] Furthermore, assuming that the saturation current of the second NPN transistor npn2 is Is, the saturation current of npn3 is also I S , the area of the first NPN transistor npn1 is m times that of the second NPN transistor npn2, so the saturation current of the first NPN transistor npn1 is mI S , the area of the fourth NPN transistor npn4 is n times that of npn1, so the saturation current of the fourth NPN transistor npn4 is nI S , the saturation current of the fifth NPN transistor npn5 is I S . According to the characteristics of the transistor:
[0040] I C =I S exp(V BE / V T )
[0041] Where V T =kT / q,I C is the current flowing through the transistor collector, we can get:
[0042] V BE =V T ln(I C / I S )
[0043] Further information is available Figure 2 The V of the five npn transistors npn1 to npn5 BE The voltages are as follows:
[0044]
[0045]
[0046]
[0047]
[0048]
[0049] Therefore, the current I in the figure 2 It can be expressed as:
[0050]
[0051] From the above formula, we can see that I 2 is a current with a positive temperature coefficient. Figure 2 The voltage of the net5 node can be expressed as: V net5=V be2 +V be3 -V be5
[0052] Generally speaking, the V BE The relationship between and temperature is:
[0053]
[0054] Where m, E g and q are constants, which will not be described here. For details, please refer to the reference document (Analog CMOS Integrated Circuits, author Behzad Razavi, page 513, formula 12.13). Based on the above relationship, the relationship between Vbe2, Vbe3, Vbe5 and temperature can be obtained:
[0055]
[0056]
[0057]
[0058] It is understandable that the relationship between the voltage and temperature of the net5 node is:
[0059]
[0060]
[0061] As shown in the above relationship, Vnet5 is a negative temperature coefficient voltage, and its voltage value decreases as the temperature increases. 3 is a negative temperature coefficient current:
[0062]
[0063] Its current value decreases with increasing temperature. 2 is a current with a positive temperature coefficient, I 3 It is a negative temperature coefficient current, and the current is accurately mirrored according to the set first current mirror, second current mirror and third current mirror, and the first preset ratio between the first current mirror and the second current mirror can make the current finally output to the third current mirror a current with a zero temperature coefficient.
[0064] Specifically, the first current mirror includes a first PMOS tube P1 and a second PMOS tube P2, the gates of the first PMOS tube P1 and the second PMOS tube P2 are interconnected, the sources of the first PMOS tube P1 and the second PMOS tube P2 are respectively used as a reference current input terminal and a mirror current input terminal, and are connected to the power supply voltage VDD, the drain and the gate of the first PMOS tube P1 are commonly connected to the collector of the third NPN transistor npn3, and the drain of the second PMOS tube P2 is used as a mirror current output terminal.
[0065] like Figure 2 As shown, the first PMOS tube P1 and the second PMOS tube P2 form a current mirror, and the width-to-length ratio of the second PMOS tube P2 is α times that of the first PMOS tube P1, so the current flowing through the second PMOS tube P2 is α times that of the first PMOS tube P1.
[0066] Specifically, the second current mirror includes a third PMOS tube P3 and a fourth PMOS tube P4, the gates of the third PMOS tube P3 and the fourth PMOS tube P4 are interconnected, the sources of the third PMOS tube P3 and the fourth PMOS tube P4 are respectively used as a reference current input terminal and a mirror current input terminal, and are connected to the power supply voltage VDD, the drain and the gate of the third PMOS tube P3 are commonly connected to the collector of the fifth NPN transistor npn5, and the drain of the fourth PMOS tube P4 is used as a mirror current output terminal.
[0067] P4 and P3 form a current mirror. The width-to-length ratio of P4 is β times that of P3, so the current flowing through P4 is β times that of P3. Therefore, the current flowing into N1 can be expressed as
[0068] I N1 =αI 2 +βI 3
[0069] Among them, because I 2 is a current with a positive temperature coefficient, I 3 is a negative temperature coefficient current, so by setting the appropriate values of α and β, αI 2 and βI 3 As the temperature changes, they cancel each other out, and eventually the temperature coefficient of the sum of these two items is zero, that is, I N1 Forming a current with zero temperature coefficient.
[0070] Specifically, the third current mirror includes a first NMOS tube N1 and a second NMOS tube N2, the gates of the first NMOS tube N1 and the second NMOS tube N2 are interconnected, the drain and the gate of the first NMOS tube N1 are interconnected, and the gate serves as a reference current input terminal, the sources of the first NMOS tube N1 and the second NMOS tube N2 are connected in common and grounded, and the drain of the second NMOS tube N2 serves as a mirror current output terminal IBIAS.
[0071] It can be understood that the first NMOS tube N1 and the second NMOS tube N2 form a current mirror. Assuming that the width-to-length ratio of the second NMOS tube N2 is γ times that of N1, the reference current output through the IBIAS port is equal to γI N1 , which is also a current with zero temperature coefficient.
[0072] Specifically, the end of the base and collector of the first NPN transistor npn1 is also connected to the power supply voltage VDD through the first resistor R1. The emitter of the fourth NPN transistor npn4 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded.
[0073] Specifically, the emitter of the fifth NPN transistor npn5 is grounded through the third resistor R3.
[0074] The present invention also provides a chip, comprising the above-mentioned current reference source circuit.
[0075] The present invention also provides an electronic device, comprising the above-mentioned current reference source circuit.
[0076] In summary, it can be seen that in the current reference source circuit, chip and electronic device provided in the embodiments of the present invention, by setting the proportional relationship between the output currents of the first current mirror and the second current mirror, and according to the second preset ratio between the saturation currents of the first NPN transistor npn1, the second NPN transistor npn2, the third NPN transistor npn3, the fourth NPN transistor npn4 and the fifth NPN transistor npn5, the characteristics of the NPN transistor itself and the relationship between the input and output currents of the current mirror are utilized, so that a current with a zero temperature coefficient is output at the mirror current output terminal IBIAS of the third current mirror, and the circuit device area is small and the cost is low.
[0077] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A current reference source circuit, characterized in that: The device comprises a first current mirror, a second current mirror, a third current mirror and a fourth current mirror, wherein current input terminals of the first current mirror and the second current mirror are both connected to a power supply voltage, and mirror current output terminals of the first current mirror and the second current mirror are connected in common and connected to a reference current input terminal of the third current mirror, currents output by the mirror current output terminals of the first current mirror and the second current mirror have a first preset ratio, and the mirror current output terminal of the third current mirror is used to output a reference current; The fourth current mirror comprises: a first NPN transistor, wherein the base and the collector of the first NPN transistor are interconnected, the base of the first NPN transistor serves as a reference current input terminal, and the base of the first NPN transistor is also connected to the power supply voltage; a third NPN transistor, wherein the third NPN transistor is interconnected with the base of the first NPN transistor, the collector of the third NPN transistor is connected to the reference current output end of the first current mirror, and the emitter of the first NPN transistor is connected to the collector of the second NPN transistor; In addition, the emitter of the third NPN transistor is connected to the collector of the fourth NPN transistor, the base of the second NPN transistor is connected to the collector of the fourth NPN transistor, the fourth NPN transistor is connected to the collector of the second NPN transistor, the emitters of the second NPN transistor and the fourth NPN transistor are both grounded, the reference current output end of the second current mirror is connected to the collector of the fifth NPN transistor, the base of the fifth NPN transistor is connected to the third NPN transistor, and the emitter of the fifth NPN transistor is grounded; There is a second preset ratio between the saturation currents of the first NPN transistor, the second NPN transistor, the third NPN transistor, the fourth NPN transistor and the fifth NPN transistor.
2. The current reference source circuit according to claim 1, characterized in that: A second preset ratio between the saturation currents of the first NPN transistor, the second NPN transistor, the third NPN transistor, the fourth NPN transistor and the fifth NPN transistor is m:1:1:n:
1.
3. The current reference source circuit according to claim 1, characterized in that: The first current mirror includes a first PMOS tube and a second PMOS tube, the gates of the first PMOS tube and the second PMOS tube are interconnected, the sources of the first PMOS tube and the second PMOS tube are respectively used as a reference current input terminal and a mirror current input terminal, and are connected to the power supply voltage, the drain and the gate of the first PMOS tube are commonly connected to the collector of the third NPN transistor, and the drain of the second PMOS tube is used as a mirror current output terminal.
4. The current reference source circuit according to claim 1, characterized in that: The second current mirror includes a third PMOS tube and a fourth PMOS tube, the gates of the third PMOS tube and the fourth PMOS tube are interconnected, the sources of the third PMOS tube and the fourth PMOS tube are respectively used as a reference current input terminal and a mirror current input terminal, and are connected to the power supply voltage, the drain and the gate of the third PMOS tube are commonly connected to the collector of the fifth NPN transistor, and the drain of the fourth PMOS tube is used as a mirror current output terminal.
5. The current reference source circuit according to claim 1, characterized in that: The third current mirror includes a first NMOS tube and a second NMOS tube, the gates of the first NMOS tube and the second NMOS tube are interconnected, the drain and the gate of the first NMOS tube are interconnected, and the gate serves as a reference current input terminal, the sources of the first NMOS tube and the second NMOS tube are connected in common and grounded, and the drain of the second NMOS tube serves as a mirror current output terminal.
6. The current reference source circuit according to claim 1, characterized in that: One end of the first NPN transistor where the base and collector are connected is also connected to the power supply voltage through a first resistor.
7. The current reference source circuit according to claim 1, characterized in that: The emitter of the fourth NPN transistor is connected to the first end of the second resistor, and the second end of the second resistor is grounded.
8. The current reference source circuit according to claim 1, characterized in that: The emitter of the fifth NPN transistor is grounded through a third resistor.
9. A chip, characterized in that: The invention comprises a current reference source circuit as described in any one of claims 1 to 8.
10. An electronic device, characterized in that: The invention comprises a current reference source circuit as described in any one of claims 1 to 8.