An EMarker chip wake-up circuit, method, apparatus, medium, product, and chip.

Abstract

This application discloses an EMarker chip wake-up circuit, method, device, medium, product, and chip, relating to the field of integrated circuit technology. The circuit includes a BMC receiving circuit, a BMC edge detection circuit, an EMarker sleep control circuit, and an EMarker chip. The input terminal of the BMC receiving circuit is connected to the CC channel, the output terminal of the BMC receiving circuit is connected to the input terminal of the BMC edge detection circuit, and the output terminal of the BMC edge detection circuit is connected to the input terminal of the EMarker sleep control circuit. Specifically: the BMC receiving circuit converts the analog BMC signal input from the CC channel into a digital signal; the BMC edge detection circuit analyzes the digital signal to determine whether PD communication exists in the CC channel, obtaining a judgment result; and the EMarker sleep control circuit activates the clock signal of the EMarker chip when the judgment result indicates the presence of PD communication in the CC channel, enabling the EMarker chip to respond to PD messages transmitted through the CC channel. This application can reduce the additional power consumption of the EMarker chip, thereby improving the user experience.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an EMarker chip wake-up circuit, method, apparatus, medium, product and chip. Background Technology

[0002] With the rapid development of modern electronic technology, the USB Type-C interface, with its advantages of reversible plugging, support for high-power charging, and high-speed data transmission, has become the mainstream interface standard for many electronic devices. Within this technological framework, the Emarker chip, as a core component of Type-C cables, plays a crucial role. The Emarker chip not only stores key cable information, such as the manufacturer ID, maximum supported current, and communication rate, but also interacts with connected devices via the USB PD (Power Delivery) protocol, enabling intelligent identification and configuration optimization.

[0003] Especially in high-end or specialized applications, Type-C cables are more complex in design, potentially incorporating multiple Emarker chips to meet diverse functional requirements. For instance, placing Emarker chips at both ends of the cable allows for real-time temperature monitoring of the devices, proactively disconnecting in case of abnormal temperatures to ensure safe operation. While this design enhances the cable's intelligence, it also places higher demands on the power management of the Emarker chips.

[0004] However, it's worth noting that Type-C cables themselves do not provide power; the power for their internal Emarker chip comes from the Type-C devices connected to either end of the cable. When connecting power-sensitive devices such as power banks and mobile phones, the additional power consumption of the Emarker chip directly reduces the device's battery life, thus impacting the user experience. Summary of the Invention

[0005] The purpose of this application is to provide an EMarker chip wake-up circuit, method, device, medium, product, and chip that can reduce the additional power consumption of the EMarker chip, thereby improving the user experience.

[0006] To achieve the above objectives, this application provides the following solution:

[0007] In a first aspect, this application provides an EMarker chip wake-up circuit, which includes a BMC receiving circuit, a BMC edge detection circuit, an EMarker sleep control circuit, and an EMarker chip. The input terminal of the BMC receiving circuit is connected to the CC channel of a Type-C cable; the output terminal of the BMC receiving circuit is connected to the input terminal of the BMC edge detection circuit; the output terminal of the BMC edge detection circuit is connected to the input terminal of the EMarker sleep control circuit; and the output terminal of the EMarker sleep control circuit is connected to the EMarker chip. Wherein:

[0008] The BMC receiving circuit is used to convert the analog BMC signal input from the CC channel into a digital signal.

[0009] The BMC edge detection circuit is used to determine whether PD communication exists in the CC channel by parsing the digital signal, and to obtain the determination result;

[0010] The Emarker sleep control circuit is used to turn on the clock signal of the EMarker chip when the judgment result indicates that the PD communication exists in the CC channel, so that the EMarker chip responds to the PD message transmitted through the CC channel.

[0011] Optionally, the BMC receiving circuit includes a comparator, a Schmitt trigger, and a first inverter, wherein:

[0012] The comparator is used to compare the voltage of the analog BMC signal input to the CC channel with a reference voltage, obtain a comparison result, and output a first level that matches the comparison result;

[0013] The Schmitt trigger is used to input the first level to the first inverter;

[0014] The first inverter is used to invert the first level to obtain a second level, and output the second level as a digital signal.

[0015] Optionally, the BMC receiving circuit includes a second inverter, a third inverter, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, wherein:

[0016] The input terminal of the second inverter is connected to the CC channel of the Type-C cable, and the output terminal of the second inverter is connected to the input terminal of the third inverter and the gate of the second NMOS transistor.

[0017] The output terminal of the third inverter is connected to the gate of the first NMOS transistor;

[0018] The source of the first NMOS transistor is connected to the source power supply voltage, and the drain of the first NMOS transistor is connected to the source of the first PMOS transistor and the gate of the second PMOS transistor.

[0019] The source of the second NMOS transistor is connected to the source power supply voltage, and the drain of the second NMOS transistor is connected to the source of the second PMOS transistor and the gate of the first PMOS transistor.

[0020] The drains of the first PMOS transistor and the second PMOS transistor are connected to the power supply.

[0021] Optionally, the digital signal is an asynchronous digital signal. The BMC edge detection circuit determines whether PD communication exists in the CC channel by parsing the digital signal. The specific method for obtaining the determination result is as follows:

[0022] The asynchronous digital signal is synchronized to obtain a synchronized digital signal;

[0023] The synchronous digital signal is delayed to obtain a delayed digital signal;

[0024] Edge identification is performed on the synchronous digital signal and the delayed digital signal to obtain an edge identification result; wherein, the edge identification result indicates that an edge event has occurred on the synchronous digital signal;

[0025] Obtain the total number of times the edge event occurs within a preset time period;

[0026] If the total number of times reaches the preset number, then it is determined that PD communication exists in the CC channel.

[0027] Optionally, the Emarker sleep control circuit includes a second 4-bit counter, a third 4-bit counter, a fourth 4-bit counter, a fifth 4-bit counter, a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a seventh AND gate, an eighth AND gate, a ninth AND gate, a tenth AND gate, a fourth inverter, a fourth flip-flop, a first crystal oscillator, and a first clock gating unit, wherein:

[0028] The second 4-bit counter, the third 4-bit counter, the fourth 4-bit counter, the fifth 4-bit counter, the sixth AND gate, the seventh AND gate, the eighth AND gate, the ninth AND gate, the tenth AND gate, and the fourth flip-flop are used to send an enable signal to the first clock gating unit when the judgment result indicates that the PD communication exists in the CC channel;

[0029] The first crystal oscillator is used to send a crystal oscillator signal to the first clock gating unit;

[0030] The first clock gating unit is used to connect the crystal oscillator signal to the clock signal output by the first clock gating unit when an enable signal is received; wherein the clock signal is used to provide a clock for the operation of the EMarker chip;

[0031] The fourth inverter, the second 4-bit counter, the third 4-bit counter, the fourth 4-bit counter, the fifth 4-bit counter, the third AND gate, the fourth AND gate, and the fifth AND gate are used to control the connection duration between the crystal oscillator signal and the clock signal; the connection duration is a preset connection duration.

[0032] Optionally, the Emarker sleep control circuit includes a fifth flip-flop, a sixth flip-flop, a multiplexer, a second crystal oscillator, a second clock gating unit, a fifth inverter, and a NAND gate, wherein:

[0033] The output of the multiplexer is connected to the input D of the fifth flip-flop, the input O of the multiplexer is connected to the BMC edge detection circuit, the input I of the multiplexer is connected to the output of the NAND gate, and the selection S0 of the multiplexer is connected to the output Q of the fifth flip-flop.

[0034] The output terminal Q of the fifth flip-flop is also connected to the enable terminal of the second clock gating unit;

[0035] The input terminal of the second clock gating unit is connected to the output terminal of the second crystal oscillator, and the output terminal of the second clock gating unit is connected to the input terminal of the Emarker chip.

[0036] The input terminal D of the sixth flip-flop is connected to the output terminal of the Emarker chip, and the output terminal Q of the sixth flip-flop is connected to one input terminal of the NAND gate.

[0037] The input terminal of the fifth inverter is connected to the output terminal of the Emarker chip, and the output terminal of the fifth inverter is connected to the other input terminal of the NAND gate.

[0038] Secondly, this application provides an EMarker chip wake-up method, which is applied to the EMarker chip wake-up circuit in the first aspect, and the EMarker chip wake-up method includes:

[0039] Convert the analog BMC signal input to the CC channel into a digital signal;

[0040] The digital signals are synchronized to obtain synchronized digital signals;

[0041] The synchronous digital signal is delayed to obtain a delayed digital signal;

[0042] Based on the synchronous digital signal and the delayed digital signal, obtain the total number of edge events occurring within a preset time period;

[0043] If the total number of times reaches the preset number, it is determined that there is PD communication in the CC channel, and the clock signal of the EMarker chip is turned on so that the EMarker chip responds to the PD message transmitted through the CC channel.

[0044] Thirdly, this application provides a computer device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the EMarker chip wake-up method described above.

[0045] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the EMarker chip wake-up method described above.

[0046] Fifthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the EMarker chip wake-up method described above.

[0047] Sixthly, this application provides a chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run a program or instructions, and the processor implementing the steps of the EMarker chip wake-up method described above when executing the program or instructions.

[0048] According to the specific embodiments provided in this application, the following technical effects are disclosed:

[0049] This application provides an EMarker chip wake-up circuit, method, device, medium, product, and chip. The BMC receiving circuit converts analog BMC signals into digital signals, and the BMC edge detection circuit analyzes these digital signals to determine if PD communication exists in the CC channel. If PD communication is detected, the EMarker sleep control circuit wakes up the dormant EMarker chip, enabling it to respond to PD messages transmitted through the CC channel. This allows the EMarker chip to remain in sleep mode when no PD communication is detected, waking it up only when PD communication is detected. This method reduces the EMarker chip's power consumption, thus improving the user experience. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a schematic diagram of the structure of an EMarker chip wake-up circuit according to one embodiment of this application;

[0052] Figure 2 This is a schematic diagram of the structure of a BMC receiving circuit provided in one embodiment of this application;

[0053] Figure 3 This is a schematic diagram of another BMC receiving circuit provided in an embodiment of this application;

[0054] Figure 4 This is a schematic diagram of the structure of a BMC edge detection circuit provided in one embodiment of this application;

[0055] Figure 5 This is a schematic diagram of the structure of an Emarker sleep control circuit provided in an embodiment of this application;

[0056] Figure 6 This is a schematic diagram of another Emarker sleep control circuit provided in an embodiment of this application;

[0057] Figure 7 This is a flowchart illustrating an EMarker chip wake-up method according to an embodiment of this application.

[0058] Figure 8 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0059] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0060] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0061] In one exemplary embodiment, such as Figure 1 As shown, an EMarker chip wake-up circuit is provided. The EMarker chip wake-up circuit includes a BMC (Biphase Mark Coding) receiving circuit, a BMC edge detection circuit, an EMarker sleep control circuit, and an EMarker chip. The input terminal of the BMC receiving circuit is connected to the CC channel of the Type-C cable, the output terminal of the BMC receiving circuit is connected to the input terminal of the BMC edge detection circuit, the output terminal of the BMC edge detection circuit is connected to the input terminal of the EMarker sleep control circuit, and the output terminal of the EMarker sleep control circuit is connected to the EMarker chip.

[0062] In this embodiment of the application, the BMC receiving circuit can convert the analog BMC signal transmitted on the CC channel into a digital signal that can be processed by the digital circuit.

[0063] The BMC edge detection circuit can analyze the digital signal output by the BMC receiving circuit and then determine whether PD communication exists in the CC channel.

[0064] In this embodiment of the application, the method for determining whether PD communication exists in the CC channel can be:

[0065] The number of edges of the simulated BMC signal BMC waveform is counted over a period of time. If the number of edges of the BMC waveform exceeds a specified number over a period of time, it is considered that PD communication exists in the CC channel.

[0066] For the BMC edge detection circuit, after the number of edges within a certain period of time is found to be greater than a specified number, the confirmation signal (bmc_edge_max_flag) will be set to 1 to notify the Emarker sleep control circuit that there may be PD communication at present.

[0067] When the Emarker sleep control circuit detects an acknowledgment signal of 1, it will turn on the clock signal of the Emarker chip, enabling the Emarker chip to respond normally to any PD messages that may arrive.

[0068] If no PD message is detected for a period of time (the acknowledgment signal remains low), the Emarker sleep control circuit will shut down the clock signal of the Emarker chip, causing the Emarker chip to enter sleep mode. Because the clock source of the Emarker chip is turned off, the dynamic power consumption of the Emarker chip is significantly reduced compared to when the clock is on.

[0069] In this embodiment of the application, the PD communication protocol uses BMC encoding to encode the data to be transmitted.

[0070] Please refer to the following: Figure 2 , Figure 2 This is a schematic diagram of a BMC receiver circuit; the BMC receiver circuit includes a comparator CMP1, a Schmitt trigger U1, and a first inverter INV1, wherein:

[0071] The comparator CMP1 is used to compare the voltage of the analog BMC signal input to the CC channel with a reference voltage, obtain a comparison result, and output a first level that matches the comparison result;

[0072] The Schmitt trigger U1 is used to input the first level to the first inverter INV1;

[0073] The first inverter INV1 is used to invert the first level to obtain a second level, and output the second level as a digital signal.

[0074] The positive input terminal of the comparator CMP1 is connected to the reference voltage Vref, the negative input terminal of the comparator CMP1 is connected to the CC channel of the Type-C cable, and the output terminal of the comparator CMP1 is connected to the input terminal of the Schmitt trigger U1.

[0075] The input terminal of the first inverter INV1 is connected to the output terminal of the Schmitt trigger U1, and the output terminal of the first inverter INV1 is connected to the input terminal of the BMC edge detection circuit.

[0076] In this embodiment of the application, the data signal output from the output terminal of the first inverter INV1 can be a digital signal (rxdata).

[0077] In this embodiment of the application, it can be seen from the Type-C protocol and PD protocol specifications that the Emarker chip and other devices use the PD protocol for communication, and the encoding method used for the transmission of the PD protocol on the CC channel is BMC encoding.

[0078] When there is no PD communication, the voltage level on the CC channel is approximately 1.68V or 0.92V (determined by the Type-C devices at both ends of the cable).

[0079] When PD communication begins on the CC channel, the high level of the BMC waveform is approximately 1.125V, and the low level is approximately 0V.

[0080] In order to wake up the Emarker chip in a timely manner when an external device accesses the Emarker chip, it is necessary to identify and analyze the BMC waveform.

[0081] When the digital circuit operates at 5V, a high level on the BMC channel of the CC channel, if sent directly to the digital circuit without conversion, will be considered a low level by the digital circuit. Therefore, this embodiment uses... Figure 2 The circuit shown converts the analog BMC signal present on the CC channel into a digital signal so that subsequent digital circuits can perform further processing.

[0082] from Figure 2 As can be seen from the diagram, this embodiment uses a comparator CMP1 and a reference voltage Vref (the reference voltage can be 1.125V / 2 = 0.56V) to convert the CC level.

[0083] When the digital signal output by the first inverter INV1 (i.e., the second level) is high, the first level output by the Schmitt trigger U1 is low, and the first level output by the comparator CMP1 is also low. This means that the voltage at the negative input terminal of the comparator (the CC channel of the Type-C cable) is greater than the voltage at the positive input terminal (0.56V reference voltage). At this time, it is assumed that the CC channel has a BMC data high level (BMC high level 1.125V) or no data transmission (the CC channel level is 1.68V or 0.92V when there is no PD communication).

[0084] When the digital signal output by the first inverter INV1 is low, the first level output by the Schmitt trigger U1 is high, and the first level output by the comparator CMP1 is also high. This means that the voltage at the negative input terminal of the comparator (CC channel of the Type-C cable) is less than the voltage at the positive input terminal (0.56V reference voltage), and at this time, it is considered that there is a low level of BMC data in the CC channel.

[0085] As can be seen from the above analysis, the BMC receiving circuit in this embodiment converts voltages on the CC channel that are greater than the reference voltage Vref into a high level of the digital circuit, and converts voltages on the CC channel that are less than the reference voltage Vref into a low level of the digital circuit. Finally, the converted results are sent to the BMC edge detection circuit for further analysis.

[0086] Please refer to the following: Figure 3 , Figure 3 This is a schematic diagram of another BMC receiver circuit; the BMC receiver circuit includes a second inverter INV2, a third inverter INV3, a first PMOS transistor Q1, a second PMOS transistor Q2, a first NMOS transistor Q3, and a second NMOS transistor Q4, wherein:

[0087] The input terminal of the second inverter INV2 is connected to the CC channel of the Type-C cable, and the output terminal of the second inverter INV2 is connected to the input terminal of the third inverter INV3 and the gate of the second NMOS transistor Q4.

[0088] The output terminal of the third inverter INV3 is connected to the gate of the first NMOS transistor Q3;

[0089] The source of the first NMOS transistor Q3 is connected to the source power supply voltage Vss, and the drain of the first NMOS transistor Q3 is connected to the source of the first PMOS transistor Q1 and the gate of the second PMOS transistor Q2.

[0090] The source of the second NMOS transistor Q4 is connected to the source power supply voltage Vss, and the drain of the second NMOS transistor Q4 is connected to the source of the second PMOS transistor Q2 and the gate of the first PMOS transistor Q1.

[0091] The drains of the first PMOS transistor Q1 and the second PMOS transistor Q2 are connected to the power supply Vdd.

[0092] In this embodiment, the operating voltage of the second inverter INV2 and the third inverter INV3 can be 1.8V, and the voltage of the power supply Vdd can be 5V.

[0093] Figure 3 In the circuit, when the CC level is low, the second inverter INV2 outputs a high level, and the third inverter INV3 outputs a low level. Therefore, the second NMOS transistor Q4 is turned on, the first NMOS transistor Q3 is turned off, the first PMOS transistor Q1 is turned on, and the second PMOS transistor Q2 is turned off. Thus, the digital signal is connected to Vss, meaning the digital signal output from the digital circuit is at a low level at this time.

[0094] When CC is high, the second inverter INV2 outputs a low level, and the third inverter INV3 outputs a high level. Therefore, the second NMOS transistor Q4 is off, the first NMOS transistor Q3 is on, the second PMOS transistor Q2 is on, and the first PMOS transistor Q1 is off. At this time, the digital signal is connected to Vdd, meaning the digital signal output from the digital circuit is at a high level.

[0095] The above analysis shows that... Figure 3 and Figure 2 Although the BMC receiving circuits shown have different circuit structures, they achieve essentially the same result: converting the analog BMC waveform on the CC channel into a digital signal that can be processed by the digital circuit.

[0096] The BMC edge detection circuit is used to determine whether PD communication exists in the CC channel by parsing the digital signal, and obtain the determination result.

[0097] In this embodiment of the application, the digital signal is an asynchronous digital signal. The BMC edge detection circuit analyzes the digital signal to determine whether PD communication exists in the CC channel. The specific method for obtaining the determination result is as follows:

[0098] The asynchronous digital signal is synchronized to obtain a synchronized digital signal;

[0099] The synchronous digital signal is delayed to obtain a delayed digital signal;

[0100] Edge identification is performed on the synchronous digital signal and the delayed digital signal to obtain an edge identification result; wherein, the edge identification result indicates that an edge event has occurred on the synchronous digital signal;

[0101] Obtain the total number of times the edge event occurs within a preset time period;

[0102] If the total number of times reaches the preset number, then it is determined that PD communication exists in the CC channel.

[0103] Please refer to the following: Figure 4 , Figure 4 This is a schematic diagram of a BMC edge detection circuit. The BMC edge detection circuit includes a first flip-flop DFF1, a second flip-flop DFF2, a third flip-flop DFF3, an XOR gate XOR1, a first 4-bit counter U2, a 2-bit counter U3, a first AND gate AND1, and a second AND gate AND2, wherein:

[0104] The first flip-flop DFF1 and the second flip-flop DFF2 are used to synchronize the asynchronous digital signal to obtain a synchronized digital signal;

[0105] The third flip-flop DFF3 is used to delay the synchronous digital signal to obtain a delayed digital signal;

[0106] An XOR gate (XOR1) is used to perform edge identification on the synchronous digital signal and the delayed digital signal to obtain an edge identification result; wherein, the edge identification result indicates that an edge event has occurred on the synchronous digital signal;

[0107] The 2-bit counter U3 is used to count edge events that occur within a preset time period;

[0108] The second AND gate AND2 is used to determine the presence of PD communication in the CC channel as a judgment result when both bit[0] and bit[1] of the 2-bit counter U3 are 1, and then outputs a confirmation signal indicating the presence of PD communication in the CC channel.

[0109] The first 4-bit counter U2 and the first AND gate AND1 are used to set the preset time period.

[0110] The D input terminal of the first flip-flop DFF1 is connected to the BMC receiving circuit, and the Q output terminal of the first flip-flop DFF1 is connected to the D input terminal of the second flip-flop DFF2.

[0111] The Q output of the second flip-flop DFF2 is connected to the D input of the third flip-flop DFF3 and one input of the XOR gate XOR1.

[0112] The Q output of the third flip-flop DFF3 is connected to the other input of the XOR gate XOR1;

[0113] The enable terminal ena of the first 4-bit counter U2 is connected to the power supply, the reset terminal rst of the first 4-bit counter U2 is connected to the output terminal of the first AND gate AND1, and the bit[3] terminal and bit[2] terminal of the first 4-bit counter U2 are respectively connected to the two input terminals of the first AND gate AND1;

[0114] The enable terminal ena of the 2-bit counter U3 is connected to the output terminal of the XOR gate XOR1, the reset terminal rst of the 2-bit counter U3 is connected to the output terminal of the first AND gate AND1, and the bit[0] terminal and bit[1] terminal of the 2-bit counter U3 are respectively connected to the two input terminals of the second AND gate AND2.

[0115] In this embodiment, the output digital signal of the BMC receiving circuit is the comparison result of the CC channel voltage and a certain fixed reference voltage. From the output digital signal, it can be determined whether the CC channel is currently transmitting a high or low level of the BMC. However, due to the connection and disconnection of Type-C devices, or interference from the external environment, the level on the CC channel can change. Therefore, after converting the BMC data on the CC channel using the BMC receiving circuit, further analysis of the BMC data is required to confirm whether PD communication exists.

[0116] The function of the BMC edge detection circuit is to determine whether there is PD communication on the CC channel based on the received BMC data, and then send the determination result to the Emarker sleep control circuit.

[0117] The input to the BMC edge detection circuit is the BMC digital signal converted by the analog BMC signal receiving circuit, and the output is a flag confirmation signal indicating the presence of PD communication on the CC.

[0118] like Figure 4 As shown, the function of the first flip-flop DFF1 and the second flip-flop DFF2 is to synchronize the digital signal, changing it from an asynchronous signal to a synchronous signal.

[0119] The function of the third flip-flop DFF3 is to delay the digital signal by one clock cycle. By XORing the current value of the digital signal with the previous value, the output of the XOR gate XOR1 can be used to determine whether a rising edge or a falling edge has occurred on the digital signal.

[0120] Figure 4 The output of the XOR gate XOR1 is connected to the enable terminal ena of the 2-bit counter U3. Therefore, whenever an edge event occurs on the digital signal, the output of the XOR gate XOR1 will go high, causing the value of the counter U3 to increment.

[0121] When both bit[0] and bit[1] of counter U3 are 1, that is, when the counter counts 3 edges, the second AND gate AND2 will output a high level, indicating that the number of BMC edges has reached the maximum number that the counter can reach.

[0122] The enable pin ena of the first 4-bit counter U2 is connected to Vdd, so the counter value will increment by 1 every time the rising edge of the clock arrives. When the first 4-bit counter U2 counts to bit[3] and bit[2] being 1, the output of the first AND gate AND1 will become 1, and then the count values ​​of the first 4-bit counter U2 and the 2-bit counter U3 will be cleared.

[0123] Based on the above analysis, it can be seen that the function of the first 4-bit counter U2 and the first AND gate AND1 is to generate a periodic pulse, while the 2-bit counter U3 is used to record the number of pulses on the digital signal. Therefore, the first 4-bit counter U2 actually plays the role of periodically clearing the currently counted pulse value.

[0124] The working principle of this circuit can be summarized as determining whether PD communication exists on the CC channel by counting the number of BMC data edges over a period of time.

[0125] If the clock speed is 1MHz, the first 4-bit counter U2 counting to 12 means that every 13 microseconds, the number of pulses counted by the 2-bit counter U3 will be reset to zero. If the count value of the 2-bit counter U3 reaches its maximum value of 3 before being reset to zero, it means that PD communication exists on the CC channel.

[0126] The Emarker sleep control circuit is used to turn on the clock signal of the EMarker chip when the judgment result indicates that the PD communication exists in the CC channel, so that the EMarker chip responds to the PD message transmitted through the CC channel.

[0127] In this embodiment, the Emarker sleep control circuit is used to control the sleep and wake-up of the Emarker chip.

[0128] Please refer to the following: Figure 5 , Figure 5 This is a schematic diagram of an Emarker sleep control circuit. The Emarker sleep control circuit includes a second 4-bit counter U4, a third 4-bit counter U5, a fourth 4-bit counter U6, a fifth 4-bit counter U7, a third AND gate AND3, a fourth AND gate AND4, a fifth AND gate AND5, a sixth AND gate AND6, a seventh AND gate AND7, an eighth AND gate AND8, a ninth AND gate AND9, a tenth AND gate AND10, a fourth inverter INV4, a fourth flip-flop DFF4, a first crystal oscillator OSC1, and a first clock gate unit CLK_GATE1, wherein:

[0129] The second 4-bit counter U4, the third 4-bit counter U5, the fourth 4-bit counter U6, the fifth 4-bit counter U7, the sixth AND gate AND6, the seventh AND gate AND7, the eighth AND gate AND8, the ninth AND gate AND9, the tenth AND gate AND10, and the fourth flip-flop DFF4 are used to send an enable signal to the first clock gating unit CLK_GATE1 when the judgment result indicates that the PD communication exists in the CC channel.

[0130] The first crystal oscillator OSC1 is used to send crystal oscillator signals to the first clock gate unit CLK_GATE1;

[0131] The first clock gate unit CLK_GATE1 is used to connect the crystal oscillator signal to the clock signal output by the first clock gate unit CLK_GATE1 when an enable signal is received; wherein, the clock signal is used to provide a clock for the operation of the EMarker chip;

[0132] The fourth inverter INV4, the second 4-bit counter U4, the third 4-bit counter U5, the fourth 4-bit counter U6, the fifth 4-bit counter U7, the third AND gate AND3, the fourth AND gate AND4, and the fifth AND gate AND5 are used to control the connection duration between the crystal oscillator signal and the clock signal; the connection duration is a preset connection duration.

[0133] The enable terminal ena of the second 4-bit counter U4 is connected to the output terminal of the fourth inverter INV4, the reset terminal rst of the second 4-bit counter U4 is connected to the BMC edge detection circuit, and the output terminal of the second 4-bit counter U4 is connected to the input terminal of the sixth AND gate AND6.

[0134] The enable terminal ena of the third 4-bit counter U5 is connected to the output terminal of the third AND gate AND3, the reset terminal rst of the third 4-bit counter U5 is connected to the BMC edge detection circuit, and the output terminal of the third 4-bit counter U5 is connected to the input terminal of the seventh AND gate AND7.

[0135] The enable terminal ena of the fourth 4-bit counter U6 is connected to the output terminal of the fourth AND gate AND4, the reset terminal rst of the fourth 4-bit counter U6 is connected to the BMC edge detection circuit, and the output terminal of the fourth 4-bit counter U6 is connected to the input terminal of the eighth AND gate AND8.

[0136] The enable terminal ena of the fifth 4-bit counter U7 is connected to the output terminal of the fifth AND gate AND5, the reset terminal rst of the fifth 4-bit counter U7 is connected to the BMC edge detection circuit, and the output terminal of the fifth 4-bit counter U7 is connected to the input terminal of the ninth AND gate AND9.

[0137] One input terminal of the third AND gate AND3 is connected to the output terminal of the sixth AND gate AND6, and the other input terminal of the third AND gate AND3 is connected to the output terminal of the fourth inverter INV4;

[0138] One input terminal of the fourth AND gate AND4 is connected to the output terminal of the seventh AND gate AND7, and the other input terminal of the fourth AND gate AND4 is connected to the output terminal of the fourth inverter INV4;

[0139] One input terminal of the fifth AND gate AND5 is connected to the output terminal of the eighth AND gate AND8, and the other input terminal of the fifth AND gate AND5 is connected to the output terminal of the fourth inverter INV4.

[0140] The input terminal of the tenth AND gate AND10 is connected to the output terminal of the sixth AND gate AND6, the output terminal of the seventh AND gate AND7, the output terminal of the eighth AND gate AND8, and the output terminal of the ninth AND gate AND9. The output terminal of the tenth AND gate AND10 is connected to the input terminal of the fourth inverter INV4 and the input terminal D of the fourth flip-flop DFF4.

[0141] The inverting output terminal of the fourth flip-flop DFF4 Connect to the enable terminal ena of the first clock gate unit CLK_GATE1;

[0142] The input terminal of the first clock gate unit CLK_GATE1 is connected to the output terminal of the first crystal oscillator OSC1, and the output terminal of the first clock gate unit CLK_GATE1 is connected to the Emarker chip.

[0143] In this embodiment, when the BMC edge detection circuit detects enough edge events within a certain time, the confirmation signal goes high, indicating that PD communication exists on the CC channel. The values ​​of the second 4-bit counter U4, the third 4-bit counter U5, the fourth 4-bit counter U6, and the fifth 4-bit counter U7 are then cleared. Simultaneously, the outputs of the 4-input AND gates (sixth AND gate AND6, seventh AND gate AND7, eighth AND gate AND8, ninth AND gate AND9, and tenth AND gate AND10) also become 0. Consequently, the D terminal of the fourth flip-flop DFF4 also becomes 0, ultimately causing the inverted output of the fourth flip-flop DFF4 to... It becomes 1.

[0144] The first clock gate unit CLK_GATE1 is turned on by the fourth flip-flop DFF4, and the clock signal clk_emarker sent to the Emarker chip is connected to the crystal oscillator signal clk_osc.

[0145] When the clock signal of the Emarker chip is turned on, the Emarker chip exits the sleep state and begins to respond to PD communication on the CC channel.

[0146] Furthermore, when the output of the tenth AND gate AND10 is set to 0, the output of the fourth inverter INV4 will become 1, and the second 4-bit counter U4 will continue to accumulate until the output of the sixth AND gate AND6 is high. Then, both inputs of the third AND gate AND3 will become 1, and the value of the third 4-bit counter U5 will also be incremented by 1.

[0147] Similarly, the count values ​​of the fourth 4-bit counter U6 and the fifth 4-bit counter U7 will also continuously accumulate.

[0148] After counting to the maximum value, the sixth AND gate AND6, the seventh AND gate AND7, the eighth AND gate AND8, the ninth AND gate AND9, and the tenth AND gate AND10 output 1. At this time, the outputs of the third AND gate AND3, the fourth AND gate AND4, and the fifth AND gate AND5 are all 0, and the second 4-bit counter U4, the third 4-bit counter U5, the fourth 4-bit counter U6, and the fifth 4-bit counter U7 stop counting.

[0149] The D terminal of the fourth flip-flop DFF4 will remain at 1, therefore the inverting output of the fourth flip-flop DFF4 will be... When the value is 0, the first clock gate unit CLK_GATE1 is turned off, the clock signal is disconnected from the crystal oscillator signal, and the Emarker chip will stop working because there is no clock source. At this time, the Emarker chip is said to enter a sleep state.

[0150] As can be seen from the working principle of the above circuit, the Emarker sleep control circuit works as follows: when a certain number of edges are detected on the CC channel within a certain period of time, it is considered that PD communication exists on the CC channel, and the Emarker chip starts working. When a certain number of edges do not appear on the CC channel within a certain period of time, and after a certain amount of time has passed, the Emarker chip will enter sleep mode to save power. In the current embodiment, assuming that the counter operates at a clock frequency of 1MHz, the Emarker chip will enter sleep mode after 65ms when no BMC data is detected on the CC channel.

[0151] Please refer to the following: Figure 6 , Figure 6 This is a schematic diagram of another Emarker sleep control circuit; the Emarker sleep control circuit includes a fifth flip-flop DFF5, a sixth flip-flop DFF6, a multiplexer Mux, a second crystal oscillator OSC2, a second clock gate unit CLK_GATE2, a fifth inverter INV5, and a NAND gate NAND1, wherein:

[0152] The output of the multiplexer Mux is connected to the input D of the fifth flip-flop DFF5, the input O of the multiplexer Mux is connected to the BMC edge detection circuit, the input I of the multiplexer Mux is connected to the output of the NAND gate, and the selection S0 of the multiplexer Mux is connected to the output Q of the fifth flip-flop DFF5.

[0153] The output terminal Q of the fifth flip-flop DFF5 is also connected to the enable terminal ena of the second clock gate unit CLK_GATE2;

[0154] The input terminal of the second clock gate unit CLK_GATE2 is connected to the output terminal of the second crystal oscillator OSC2, and the output terminal of the second clock gate unit CLK_GATE2 is connected to the input terminal of the Emarker chip;

[0155] The input terminal D of the sixth flip-flop DFF6 is connected to the output terminal of the Emarker chip, and the output terminal Q of the sixth flip-flop DFF6 is connected to one input terminal of the NAND gate NAND1.

[0156] The input terminal of the fifth inverter INV5 is connected to the output terminal of the Emarker chip, and the output terminal of the fifth inverter INV5 is connected to the other input terminal of the NAND gate NAND1.

[0157] In this embodiment, the busy signal (busy_flag) output by the Emarker chip is a port controlled by the Emarker chip. When the Emarker chip is in a busy state (such as when receiving a PD message or needing to respond to a PD message), it will set this port to a high level. When the Emarker chip finishes processing its tasks, it will clear the busy signal to zero.

[0158] The following is about Figure 6 The working principle of the circuit shown is briefly described below. Assume the initial state is that the Emarker chip is in sleep mode (busy signal is 0, the D and Q terminals of the fifth flip-flop DFF5 are both 0, and the select terminal S0 of the multiplexer Mux is 0). When the BMC edge detection circuit does not indicate the presence of PD communication, i.e., when bmc_edge_max_flg is 0, the D and Q terminals of the fifth flip-flop DFF5 remain 0, and the enable signal of the second clock gate unit CLK_GATE2 also remains 0. The clock signal and crystal oscillator signal are disconnected, and the Emarker chip remains in sleep mode. At this time, the power consumption of the Emarker chip is low.

[0159] When the BMC edge detection circuit indicates that there is PD communication on the CC channel (the confirmation signal changes from low to high), the D terminal of the fifth flip-flop DFF5 changes from 0 to 1. Therefore, after the next clock cycle arrives, the output Q terminal of the fifth flip-flop DFF5 becomes 1, the enable signal of the second clock gate unit CLK_GATE2 is 1, the clock signal of the Emarker chip is connected to the second crystal oscillator signal, and the Emarker chip exits the sleep state and starts working.

[0160] At the same time that the Emarker chip starts working, the selection terminal S0 of the multiplexer Mux also changes from 0 to 1. Thus, the D terminal of the fifth flip-flop DFF5 is determined by the output of the NAND gate NAND1. At this time, even if the acknowledgment signal becomes 0 (there is no PD communication on the CC channel), the D terminal of the fifth flip-flop DFF5 remains 1, that is, the Emarker chip is still in working state.

[0161] When the Emarker chip starts working, it sets the busy signal of its output port to a high level. However, the output of the NAND gate NAND1 is actually the result of inverting the falling edge of the busy signal. Therefore, the output of the NAND gate NAND1 will still remain 1, and thus the D terminal of the fifth flip-flop DFF5 will also remain 1.

[0162] Once the Emarker chip has finished responding to the message, it will clear the busy signal. At the moment the busy signal is cleared, the output of the fifth inverter INV5 is 1, the input of the sixth flip-flop DFF6 is 0, but the output Q of the sixth flip-flop DFF6 remains 1. Therefore, the output of the NAND gate NAND1 is 0, and the D input of the fifth flip-flop DFF5 changes from 1 to 0.

[0163] Ultimately, this causes the enable pin ena of the second clock gating unit CLK_GATE2 to become 0, the clock of the Emarker chip to be disconnected, and the Emarker chip to re-enter sleep mode.

[0164] At the same time, the selector S0 of the multiplexer Mux also changes from 1 to 0, so the D terminal of the fifth flip-flop DFF5 is re-determined by the acknowledgment signal.

[0165] The above analysis shows that... Figure 6 and Figure 5 The difference between the Emarker sleep control circuit and the Emarker sleep control circuit is that... Figure 5 An open-loop control strategy is adopted for the sleep mode of the Emarker chip. That is, no matter what state the Emarker chip is in, as long as the BMC edge detection circuit does not detect PD communication within a certain period of time, the Emarker sleep control circuit will turn off the clock of the Emarker chip and put it into sleep mode.

[0166] Figure 6 The middleware employs a closed-loop strategy. When the Emarker chip is processing data (such as responding to a message), it sets a busy signal. Once the Emarker chip has finished responding to the message, it clears the busy signal, thus turning off the Emarker chip's clock and saving power.

[0167] The embodiments of this application can reduce the power consumption of the Emarker chip when it is not in operation. According to actual tests, the Emarker chip equipped with the Emarker chip wake-up circuit of this application can reduce power consumption by about 50%.

[0168] This application converts analog BMC signals into digital signals using a BMC receiving circuit, and then analyzes these digital signals using a BMC edge detection circuit to determine if PD communication exists in the CC channel. If PD communication is detected in the CC channel, the Emarker chip can be woken up by the Emarker sleep control circuit to respond to PD messages transmitted through the CC channel. This allows the Emarker chip to remain in sleep mode when no PD communication is detected, and only wake up when PD communication is detected. Therefore, this method reduces the additional power consumption of the Emarker chip, thereby improving the user experience.

[0169] In one exemplary embodiment, such as Figure 7 As shown, an EMarker chip wake-up method is provided. This method is executed by the EMarker chip wake-up circuit, and in this embodiment, it includes steps 701 to 705. Wherein:

[0170] Step 701: Convert the analog BMC signal input from the CC channel into a digital signal.

[0171] Step 702: Synchronize the digital signal to obtain a synchronized digital signal.

[0172] Step 703: Delay the synchronous digital signal to obtain a delayed digital signal.

[0173] Step 704: Based on the synchronous digital signal and the delayed digital signal, obtain the total number of edge events occurring within a preset time period.

[0174] Step 705: If the total number of times reaches the preset number of times, it is determined that there is PD communication in the CC channel, and the clock signal of the EMarker chip is turned on so that the EMarker chip responds to the PD message transmitted through the CC channel.

[0175] Implementing steps 701 to 705 above can reduce the additional power consumption of the Emarker chip, thereby improving the user experience.

[0176] In one exemplary embodiment, a computer device is provided, which may be a server or a terminal, and its internal structure diagram may be as follows. Figure 8 As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media. The database stores EMarker chip wake-up data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements an EMarker chip wake-up method.

[0177] Those skilled in the art will understand that Figure 8 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0178] In one exemplary embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0179] In one exemplary embodiment, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0180] In one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0181] In one exemplary embodiment, a chip is provided, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the steps in the above method embodiments and achieve the same technical effect, and will not be described again here to avoid repetition.

[0182] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0183] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0184] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).

[0185] The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0186] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0187] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An EMarker chip wake-up circuit, characterized in that, The EMarker chip wake-up circuit includes a BMC receiving circuit, a BMC edge detection circuit, an EMarker sleep control circuit, and an EMarker chip. The input of the BMC receiving circuit is connected to the CC channel of the Type-C cable. The output of the BMC receiving circuit is connected to the input of the BMC edge detection circuit. The output of the BMC edge detection circuit is connected to the input of the EMarker sleep control circuit. The output of the EMarker sleep control circuit is connected to the EMarker chip. Wherein: The BMC receiving circuit is used to convert the analog BMC signal input from the CC channel into a digital signal. The BMC edge detection circuit is used to determine whether PD communication exists in the CC channel by parsing the digital signal, and to obtain the determination result; The Emarker sleep control circuit is used to turn on the clock signal of the EMarker chip when the judgment result indicates that the PD communication exists in the CC channel, so that the EMarker chip responds to the PD message transmitted through the CC channel; The BMC receiving circuit includes a comparator, a Schmitt trigger, and a first inverter, wherein: The comparator is used to compare the voltage of the analog BMC signal input to the CC channel with a reference voltage, obtain a comparison result, and output a first level that matches the comparison result; The Schmitt trigger is used to input the first level to the first inverter; The first inverter is used to invert the first level to obtain a second level, and output the second level as a digital signal; The digital signal is an asynchronous digital signal. The BMC edge detection circuit analyzes the digital signal to determine whether PD communication exists in the CC channel. The specific method for obtaining the determination result is as follows: The asynchronous digital signal is synchronized to obtain a synchronized digital signal; The synchronous digital signal is delayed to obtain a delayed digital signal; Edge identification is performed on the synchronous digital signal and the delayed digital signal to obtain an edge identification result; wherein, the edge identification result indicates that an edge event has occurred on the synchronous digital signal; Obtain the total number of times the edge event occurs within a preset time period; If the total number of times reaches the preset number, then it is determined that PD communication exists in the CC channel.

2. The EMarker chip wake-up circuit according to claim 1, characterized in that, The BMC receiving circuit includes a second inverter, a third inverter, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, wherein: The input terminal of the second inverter is connected to the CC channel of the Type-C cable, and the output terminal of the second inverter is connected to the input terminal of the third inverter and the gate of the second NMOS transistor. The output terminal of the third inverter is connected to the gate of the first NMOS transistor; The source of the first NMOS transistor is connected to the source power supply voltage, and the drain of the first NMOS transistor is connected to the source of the first PMOS transistor and the gate of the second PMOS transistor. The source of the second NMOS transistor is connected to the source power supply voltage, and the drain of the second NMOS transistor is connected to the source of the second PMOS transistor and the gate of the first PMOS transistor. The drains of the first PMOS transistor and the second PMOS transistor are connected to the power supply.

3. The EMarker chip wake-up circuit according to claim 1, characterized in that, The Emarker sleep control circuit includes a second 4-bit counter, a third 4-bit counter, a fourth 4-bit counter, a fifth 4-bit counter, a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a seventh AND gate, an eighth AND gate, a ninth AND gate, a tenth AND gate, a fourth inverter, a fourth flip-flop, a first crystal oscillator, and a first clock gating unit, wherein: The second 4-bit counter, the third 4-bit counter, the fourth 4-bit counter, the fifth 4-bit counter, the sixth AND gate, the seventh AND gate, the eighth AND gate, the ninth AND gate, the tenth AND gate, and the fourth flip-flop are used to send an enable signal to the first clock gating unit when the judgment result indicates that the PD communication exists in the CC channel; The first crystal oscillator is used to send a crystal oscillator signal to the first clock gating unit; The first clock gating unit is used to connect the crystal oscillator signal to the clock signal output by the first clock gating unit when an enable signal is received; wherein the clock signal is used to provide a clock for the operation of the EMarker chip; The fourth inverter, the second 4-bit counter, the third 4-bit counter, the fourth 4-bit counter, the fifth 4-bit counter, the third AND gate, the fourth AND gate, and the fifth AND gate are used to control the connection duration between the crystal oscillator signal and the clock signal; the connection duration is a preset connection duration.

4. The EMarker chip wake-up circuit according to claim 1, characterized in that, The Emarker sleep control circuit includes a fifth flip-flop, a sixth flip-flop, a multiplexer, a second crystal oscillator, a second clock gating unit, a fifth inverter, and a NAND gate, wherein: The output of the multiplexer is connected to the input D of the fifth flip-flop, the input O of the multiplexer is connected to the BMC edge detection circuit, the input I of the multiplexer is connected to the output of the NAND gate, and the selection S0 of the multiplexer is connected to the output Q of the fifth flip-flop. The output terminal Q of the fifth flip-flop is also connected to the enable terminal of the second clock gating unit; The input terminal of the second clock gating unit is connected to the output terminal of the second crystal oscillator, and the output terminal of the second clock gating unit is connected to the input terminal of the Emarker chip. The input terminal D of the sixth flip-flop is connected to the output terminal of the Emarker chip, and the output terminal Q of the sixth flip-flop is connected to one input terminal of the NAND gate. The input terminal of the fifth inverter is connected to the output terminal of the Emarker chip, and the output terminal of the fifth inverter is connected to the other input terminal of the NAND gate.

5. A method for waking up an EMarker chip, characterized in that, The method is applied to the EMarker chip wake-up circuit in claim 1, wherein the EMarker chip wake-up method includes: Convert the analog BMC signal input to the CC channel into a digital signal; The digital signals are synchronized to obtain synchronized digital signals; The synchronous digital signal is delayed to obtain a delayed digital signal; Based on the synchronous digital signal and the delayed digital signal, obtain the total number of edge events occurring within a preset time period; If the total number of times reaches the preset number, it is determined that there is PD communication in the CC channel, and the clock signal of the EMarker chip is turned on so that the EMarker chip responds to the PD message transmitted through the CC channel.

6. A computer device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor executes the computer program to implement the steps of the EMarker chip wake-up method of claim 5.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the EMarker chip wake-up method as described in claim 5.

8. A chip, the chip comprising a processor and a communication interface, the communication interface being coupled to the processor, characterized in that, The processor is used to run programs or instructions, and when the processor executes the programs or instructions, it implements the steps of the EMarker chip wake-up method as described in claim 5.

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