Nonvolatile memory device, memory device including the nonvolatile memory device, and method of operating the memory device

Abstract

A nonvolatile memory device, a memory device including the same, and an operating method of the memory device are provided. The nonvolatile memory device includes: a data pin configured to output a data signal; and a command address pin separate from the data pin, the command address pin configured to receive a read command corresponding to the data signal and output noise state data during a data output operation in which the data signal is output through the data pin in response to the read command.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0159085 filed in the Korean Intellectual Property Office on November 16, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a nonvolatile memory device, a memory apparatus including such a nonvolatile memory device, and a method of operating such a memory apparatus. Background Art

[0004] As the data processing speed of electronic devices increases, storage devices capable of high-speed input / output and low power are required. In order to achieve the above-mentioned high-speed input / output and low power, various technologies are being studied.

[0005] However, due to higher speed and lower power, the signal integrity (SI) characteristics of data signals input / output to the storage device deteriorate, and the data input / output (I0) operation becomes more susceptible to noise. As a result, the data reliability of the storage device is impaired, and thus it is necessary to efficiently detect noise in the data input / output operation. Summary of the invention

[0006] The present disclosure attempts to provide a nonvolatile memory device, a storage apparatus including the nonvolatile memory device, and a method of operating the storage apparatus.

[0007] Example embodiments provide a nonvolatile memory device that efficiently performs noise detection in a situation susceptible to noise.

[0008] Example embodiments provide a nonvolatile memory device that improves overhead of overlapping a noise monitoring operation and a data input / output operation.

[0009] According to an example embodiment, a nonvolatile memory device includes: a data pin configured to output a data signal; and a command address pin separated from the data pin, the command address pin configured to receive a read command corresponding to the data signal and output noise status data during a data output operation in which the data signal is output through the data pin in response to the read command.

[0010] According to example embodiments, a memory device includes: a first nonvolatile memory device and a second nonvolatile memory device connected to a first channel, the first nonvolatile memory device and the second nonvolatile memory device being configured to perform a data input / output operation through the first channel, and a memory controller configured to provide a data input / output command for the data input / output operation to the first nonvolatile memory device through a command address pin connected to the first channel, perform the data input / output operation on the first nonvolatile memory device through a data pin connected to the first channel that is different from the command address pin, and receive noise status data on at least one of the first nonvolatile memory device and the second nonvolatile memory device through the command address pin in parallel with the data input / output operation.

[0011] According to an example embodiment, an operating method of a storage device includes: providing a data input / output command through a command address pin; performing a data input / output operation through a data pin different from the command address pin based on the data input / output command; providing a noise monitoring command through the command address pin according to a situation during the data input / output operation, and receiving noise status data through the command address pin in response to the noise monitoring command. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram illustrating a storage device according to example embodiments.

[0013] Figure 2 Yes Description Figure 1 Figure 1 shows a ready / busy map of the .

[0014] Figure 3 is a diagram illustrating a storage device according to example embodiments.

[0015] Figure 4 is a block diagram illustrating a nonvolatile memory device according to example embodiments.

[0016] Figure 5 is a diagram illustrating a three-dimensional structure of a memory cell array according to example embodiments.

[0017] Figure 6 is a diagram illustrating a nonvolatile memory device according to example embodiments.

[0018] Figure 7 is a data frame showing noise status data according to example embodiments.

[0019] Figure 8 is a data frame showing noise status data according to example embodiments.

[0020] Fig. 9 and Fig.10is a diagram illustrating a current noise detection unit according to example embodiments.

[0021] Fig.11 and Fig.12 is a diagram illustrating a voltage noise detection unit according to example embodiments.

[0022] Fig.13 is a flowchart illustrating the operation of a storage device according to an example embodiment.

[0023] Fig.14 and Fig.15 is a diagram illustrating an operation of a storage device according to example embodiments.

[0024] Fig.16 is a diagram illustrating an operation of a storage device according to example embodiments.

[0025] Fig.17 is a diagram illustrating a storage device according to an embodiment.

[0026] Fig.18 and Fig.19 is a diagram illustrating an operation of a storage device according to example embodiments.

[0027] Fig. 20 is a diagram illustrating an operation of a storage device according to example embodiments.

[0028] Fig.21 is a block diagram illustrating an SSD system to which a storage device is applied according to example embodiments.

[0029] Fig. 22 is a block diagram illustrating a data center to which a storage device is applied according to example embodiments. DETAILED DESCRIPTION

[0030] Hereinafter, several exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the inventive concept belongs can easily practice these embodiments. The inventive concept can be implemented in several different forms and is not limited to the exemplary embodiments described herein.

[0031] In order to clearly explain the present inventive concept, parts irrelevant to the explanation are omitted, and the same or similar components are given the same reference numerals throughout the specification.

[0032] In addition, for better understanding and ease of description, the size and thickness of each component shown in the drawings are arbitrarily shown, so the inventive concept is not necessarily limited to the contents shown. In the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. In addition, in the drawings, the thickness of some layers and regions are exaggerated for better understanding and ease of description.

[0033] In addition, throughout the specification, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0034] Although the terms "same", "equal" or "identical" are used in the description of the exemplary embodiments, it should be understood that some imprecision may exist. Therefore, when one element is referred to as being the same as another element, it should be understood that the element or value is the same as the other element within a desired manufacturing or operating tolerance range (e.g., ±10%).

[0035] When the terms "approximately," "substantially," or "approximately" are used in conjunction with a numerical value in this specification, the associated numerical value is intended to include a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "approximately," "substantially," or "approximately" are used in conjunction with a geometric shape, the intent is that the accuracy of the geometric shape is not required, but the tolerance of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified to "approximately" or "substantially," it should be understood that these values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value or shape.

[0036] Figure 1 is a block diagram illustrating a storage device according to example embodiments. Figure 2 Yes Description Figure 1 Figure 1 shows a ready / busy map of the .

[0037] Reference Figure 1 and Figure 2 , the storage device 10a may include a nonvolatile memory device 100 and a storage controller 200. The storage device 10a may support a plurality of channels CH1 to CHm, and the nonvolatile memory device 100 and the storage controller 200 may be connected through the plurality of channels CH1 to CHm. For example, the storage device 10a may be implemented as a storage device such as a solid state drive (SSD).

[0038] The nonvolatile memory device 100 may include a plurality of nonvolatile memory devices NVM11 to NVMmn. Each of the plurality of nonvolatile memory devices NVM11 to NVMmn may be connected to one of the plurality of channels CH1 to CHm through a corresponding path. For example, the nonvolatile memory devices NVM11 to NVM1n may be connected to the first channel CH1 through paths W11-W1n, and the nonvolatile memory devices NVM21 to NVM2n may be connected to the second channel CH2 through paths W21 to W2n. In example embodiments, each of the nonvolatile memory devices NVM11 to NVMmn may be implemented as an arbitrary memory cell capable of operating according to a separate control signal from the memory controller 200. For example, each of the nonvolatile memory devices NVM11 to NVMmn may be implemented as a chip or a die, but the inventive concept is not limited thereto.

[0039] The memory controller 200 may include a noise monitoring module 220. When an expected (or alternatively, predetermined) situation is satisfied based on the ready / busy map RB_M, the noise monitoring module 220 may perform a noise monitoring operation on the nonvolatile memory devices NVM11 to NVMmn. The ready / busy map RB_M according to an example embodiment may include ready / busy status data of each of the nonvolatile memory devices NVM11-NVMmn in a bitmap format. The memory controller 200 according to an example embodiment may check the operation status of the nonvolatile memory devices NVM11 to NVMmn through the ready / busy map RB_M.

[0040] According to an example embodiment, the desired (or alternatively, predetermined) situation may be a situation susceptible to noise, in which various configurations are interleaved with each other, but are not limited thereto. The storage controller 200 according to an example embodiment may provide a noise monitoring command when a situation susceptible to noise is satisfied, and may efficiently detect noise by receiving stored noise state data. A detailed description of the desired (or alternatively, predetermined) situation will be described later.

[0041] The noise monitoring module 220 may provide a refresh command to the plurality of nonvolatile memory devices NVM11 to NVMmn at a desired (or alternatively, predetermined) cycle, and may receive a refresh command from the plurality of nonvolatile memory devices NVM11 to NVMmn. Figure 3 The ready / busy status data RBSD is used to update the pre-stored ready / busy mapping RB_M.

[0042] The ready / busy state data RBSD according to an example embodiment may include a ready state, a busy state, and an input / output state. When the ready / busy state data RBSD is in the ready state, it may correspond to a situation where an internal operation of the nonvolatile memory devices NVM11 to NVMmn (e.g., programming, reading, erasing, etc. of a memory cell) is not performed or has been completed. When the ready / busy state data is in the busy state, it may correspond to a situation where an internal operation in the memory device 300 of the nonvolatile memory devices NVM11 to NVMmn is being performed. When the ready / busy state data is in the input / output state, it may correspond to a situation where the nonvolatile memory devices NVM11 to NVMmn perform an input / output operation, such as a situation where the nonvolatile memory devices NVM11 to NVMmn receive input data to be programmed, or a situation where the nonvolatile memory devices NVM11 to NVMmn output read data, etc.

[0043] Reference Figure 2 , through the ready / busy mapping RB_M, the memory controller 200 can see that the 1_1 nonvolatile memory device NVM11 corresponding to the 1_1 path W11 in the first channel CH1 is in the ready state, the 1_2 nonvolatile memory device NVM12 corresponding to the 1_2 path W12 and the 1_n nonvolatile memory device NVM1n corresponding to the 1_n path W1n are in the busy state, and the 1_3 nonvolatile memory device NVM13 corresponding to the 1_3 path W13 is in the input / output state. In addition, the memory controller 200 can confirm whether the m_nth nonvolatile memory device NVMmn corresponding to the m_nth path Wmn in the nth channel CHn is in the busy state through the ready / busy mapping RB_M.

[0044] The memory controller 200 may transmit and receive signals with the nonvolatile memory device 100 through a plurality of channels CH1 to CHm. For example, the memory controller 200 may transmit commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the nonvolatile memory device 100 through the channels CH1 to CHm, and may receive data DATAa to DATAm and status data from the nonvolatile memory device 100.

[0045] The memory controller 200 may select one of the nonvolatile memory devices connected to the corresponding channel through each channel, and may transmit and receive signals with the selected nonvolatile memory device. For example, the memory controller 200 may select the nonvolatile memory device NVM11 connected to the first channel CH1 among the nonvolatile memory devices NVM11 to NVM1n. The memory controller 200 may transmit the command CMDa, the address ADDRa, and the data DATAa to the selected nonvolatile memory device NVM11 through the first channel CH1 to receive the data DATAa from the selected nonvolatile memory device NVM11.

[0046] The memory controller 200 may transmit and receive signals in parallel with the nonvolatile memory device 100 through different channels. For example, the memory controller 200 may send a command CMDb to the nonvolatile memory device 100 through the second channel CH2, while sending a command CMDa to the nonvolatile memory device 100 through the first channel CH1. For example, the memory controller 200 may receive data DATAb from the nonvolatile memory device 100 through the second channel CH2, while receiving data DATAa from the nonvolatile memory device 100 through the first channel CH1.

[0047] The memory controller 200 may control the overall operation of the nonvolatile memory device 100. The memory controller 200 may send signals to the channels CH1 to CHm to control each of the nonvolatile memory devices NVM11 to NVMmn connected to the channels CH1 to CHm. For example, the memory controller 200 may send a command (CMDa) and an address ADDRa to the first channel CH1 to control a selected one of the nonvolatile memory devices NVM11 to NVM1n.

[0048] Each of the nonvolatile memory devices NVM11 to NVMmn may operate under the control of the memory controller 200. For example, the nonvolatile memory device NVM11 may program data DATAa according to a command CMDa, an address ADDRa, and data DATAa supplied to the first channel CH1. For example, the nonvolatile memory device NVM21 may read data DATAb according to a command CMDb and an address ADDRb supplied to the second channel CH2, and may transmit the read data DATAb to the memory controller 200.

[0049] exist Figure 1 , the nonvolatile memory device 100 may communicate with the memory controller 200 through m channels, and although the nonvolatile memory device 100 is illustrated as including n nonvolatile memory devices corresponding to respective channels, the number of channels and the number of nonvolatile memory devices connected to one channel may be changed in various ways.

[0050] Figure 3 is a diagram illustrating a storage device according to example embodiments. Figure 4 is a block diagram illustrating a nonvolatile memory device according to example embodiments. Figure 5 is a diagram illustrating a three-dimensional structure of a memory cell array according to example embodiments.

[0051] The storage device 10a may include a nonvolatile memory device 100 and a storage controller 200. The nonvolatile memory device 100 may be connected to a memory controller 200. Figure 1 The memory controller 200 may correspond to one of the plurality of nonvolatile memory devices NVM11 to NVMmn, which communicates with the memory controller 200 based on or through a corresponding one of the plurality of channels CH1 to CHm. Figure 1 Corresponding to the storage controller 200.

[0052] The nonvolatile memory device 100 may include first to seventh pins P11 to P17, a memory interface circuit 110, a control logic circuit 120, and a memory cell array 130. The memory interface circuit 110 may receive a command address signal CA, a data signal DQ, a command address clock signal CA_CLK, a read enable signal nRE, a data strobe signal DQS, and a chip enable signal CA_CE through first to seventh pins P11 to P17 that are separated from each other and different from each other. The memory interface circuit 110 may not only receive the data signal DQ, but may also transmit the data signal DQ to the memory controller 200 through a plurality of third pins P13.

[0053] The command address clock signal CA_CLK may maintain a static state (eg, a high level or a low level) and may switch between a high level and a low level in a specific section. For example, the command address clock signal CA_CLK may be switched in a section where the command address signal CA is transmitted.

[0054] The memory interface circuit 110 may obtain a command / address CMD / ADDR from the command address signal CA based on the switching timing of the command address clock signal CA_CLK. According to an example embodiment, the first to second pins P11 to P12 receiving the command address signal CA may be command address pins. According to an example embodiment, the command CMD may include a data read command, a data write command, a noise monitoring command, an operation status update command, etc.

[0055] According to an example embodiment, the memory interface circuit 110 may output the noise status data NSD and / or the ready / busy status data RBSD generated based on the command address clock signal CA_CLK. According to an example embodiment, the memory interface circuit 110 may output the command address signal CA to the controller interface circuit 210 based on the switching timing of the command address clock signal CA_CLK. The command address signal CA including the noise status data NSD and / or the ready / busy status data RBSD based on the switching timing of the command address clock signal CA_CLK may be output and then input to the controller interface circuit 210.

[0056] According to example embodiments, the output of the noise status data NSD may be performed through a universal internal bus (UIB) read, a status read, or the like.

[0057] In the data DATA output operation of the non-volatile memory device 100, the memory interface circuit 110 may receive a read enable signal nRE switched by the fifth pin P15 before outputting the data DATA. The memory interface circuit 110 may generate a data strobe signal DQS switched based on the switching of the read enable signal nRE. For example, the memory interface circuit 110 may generate a data strobe signal DQS that starts switching after a desired (or alternatively, predetermined) delay based on the switching start time of the read enable signal nRE. The memory interface circuit 110 may output a data signal DQ including data DATA based on the switching timing of the data strobe signal DQS. Accordingly, the data DATA may be aligned with the switching timing of the data strobe signal DQS to be sent to the memory controller 200.

[0058] In the data DATA input operation of the nonvolatile memory device 100, the controller interface circuit 210 may generate a switching data strobe signal DQS. For example, the data strobe signal DQS may maintain a fixed state (e.g., a high level or a low level) and start switching before the data DATA is sent. The controller interface circuit 210 may send a data signal DQ including data DATA to the nonvolatile memory device 100 based on the switching timing of the data strobe signal DQS. For example, the data DATA may be sent aligned with the edge timing of the data strobe signal DQS.

[0059] According to example embodiments, the plurality of third pins P13 through which the data signals DQ are input / output may be data pins.

[0060] The memory controller 200 may include first to seventh pins P21 to P27 and a controller interface circuit 210. The first to seventh pins P21 to P27 may correspond to the first to seventh pins P11 to P17 of the nonvolatile memory device 100, respectively. Therefore, the controller interface circuit 210 may transmit a command address signal CA, a data signal DQ, a command address clock signal CA_CLK, a read enable signal nRE, a data strobe signal DQS, and a chip enable signal CA_CE. The controller interface circuit 210 may not only transmit the data signal DQ, but also receive the data signal DQ from the nonvolatile memory device 100 through a plurality of third pins P23. Likewise, according to example embodiments, the first to second pins P21 to P22 through which the command address signal CA is input / output may be command address pins, and the plurality of third pins P23 through which the data signal DQ is input / output may be data pins.

[0061] Refer to Figure 4 , the nonvolatile memory device 100 may include a control logic 120, a memory cell array 130, a page buffer 140, a voltage generator 150, and a row decoder 160. Figure 4 Although not shown, according to example embodiments, the nonvolatile memory device 100 may further include a memory interface circuit 110, and may further include a column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, and the like.

[0062] The control logic 120 may control various operations in the nonvolatile memory device 100 as a whole. The control logic 120 may output various control signals in response to the command CMD and / or the address ADDR from the first to second pins P11 to P12 of the memory interface circuit 110. For example, the control logic 120 may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR. The control logic 120 may output a page buffer control signal PCNT to control the page buffer 140.

[0063] The control logic 120 may include a current noise detection unit 121, a current noise register unit 122, a voltage noise detection unit 123, and a voltage noise register unit 124. According to an example embodiment, the current noise detection unit 121 and the voltage noise detection unit 123 may generate an index value related to noise. The current noise register unit 122 and the voltage noise register unit 124 may temporarily store the index value, and the control logic 120 may generate noise state data NSD based on the temporarily stored index value in response to receipt of a noise monitoring command.

[0064] According to example embodiments, the noise status data NSD may be generated based on a core voltage Vcc applied to the page buffer 140 and / or a core current Icc input to the page buffer 140. The noise status data NSD may include information of a noise detection status of a portion of the nonvolatile memory device 100 and / or the memory cell array 130. For example, the noise status data NSD may include noise status information of one plane of the memory cell array 130.

[0065] Later on Figures 7 to 12 A detailed description of the noise state data NSD, the current noise detection unit 121, the current noise register unit 122, the voltage noise detection unit 123, and the voltage noise register unit 124 is provided in the description of FIG.

[0066] The control logic 120 may generate the ready / busy status data RBSD. The generated ready / busy status data RBSD may indicate information about the operation status of a portion of the nonvolatile memory device 100 and / or the memory cell array 130. For example, the ready / busy status data RBSD may include operation status information of one plane of the memory cell array 130. The operation status may include a ready state, a busy state, and an input / output state.

[0067] The control logic 120 may output the generated noise status data NSD and / or the ready / busy status data RBSD to the first to second pins P11 to P12 of the memory interface circuit 110. The noise status data NSD and / or the ready / busy status data RBSD output through the first to second pins P11 to P12 may be provided to the memory controller 200 in the form of a command address signal CA.

[0068] The memory cell array 130 may include a plurality of memory blocks BLK1 to BLKz (z is a positive integer), and each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells and may include a plurality of planes 1301 to 1304 ( Figure 6 ). The memory cell array 130 may be connected to the page buffer 140 through the bit lines BL, and may be connected to the row decoder 160 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL.

[0069] In an example embodiment, the memory cell array 130 may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells connected to word lines stacked vertically on a substrate, respectively. In another example embodiment, the memory cell array 130 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged in a row direction and a column direction.

[0070] Reference Figure 5 , each of the plurality of memory blocks BLK1 to BLKz may be represented as an equivalent circuit as shown in the figure. Figure 5 The illustrated memory block BLKi represents a three-dimensional memory block formed in a three-dimensional structure on a substrate. For example, a plurality of memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.

[0071] The memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between a plurality of bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST. Figure 5 In the figure, each of the plurality of storage NAND strings NS11 to NS33 is shown to include eight storage cells MC1 to MC8, but is not limited thereto.

[0072] The string selection transistor SST may be connected to a corresponding one of the string selection lines SSL1, SSL2, and SSL3. Each of the plurality of memory cells MC1 to MC8 may be connected to a corresponding one of the gate lines GTL1 to GTL8. The gate lines GTL1 to GTL8 may correspond to word lines, and some of the gate lines GTL1 to GTL8 may correspond to dummy word lines. The ground selection transistor GST may be connected to a corresponding one of the ground selection lines GSL1, GSL2, and GSL3. The string selection transistor SST may be connected to a corresponding one of the bit lines BL1, BL2, and BL3, and the ground selection transistor GST may be connected to the common source line CSL. Each of the bit lines BL1, BL2, and BL3 may be connected to a corresponding one of the page buffers PB1, PB2, and PB3. Each of the page buffers PB1, PB2, and PB3 may be included in Figure 4 The page buffer in the page buffer 140.

[0073] Word lines of the same height may be connected in common, and ground selection lines GSL1, GSL2, and GSL3 and string selection lines SSL1, SSL2, and SSL3 may be separated, respectively. Figure 5 , the memory block BLK is illustrated as being connected to eight gate lines GTL1 to GTL8 and three bit lines BL1 , BL2 , and BL3 , but the inventive concept is not limited thereto.

[0074] The page buffer 140 may include a plurality of page buffers PB1 to PBn (n is an integer greater than or equal to 3), and the plurality of page buffers PB1 to PBn may be respectively connected to the memory cells through a plurality of bit lines BL. The page buffer 140 may select at least one bit line of the plurality of bit lines BL in response to a column address Y-ADDR.

[0075] The page buffer 140 may operate as a write driver or a sense amplifier according to an operation mode. For example, during a programming operation, the page buffer 140 may apply a bit line voltage corresponding to the data DATA to be programmed to a selected bit line based on an applied core voltage Vcc. During a read operation, the page buffer 140 may detect the data DATA stored in the memory cell by detecting a current or voltage of the selected bit line. According to an example embodiment, the data DATA may be input / output through a plurality of third pins P13 of the page buffer 140 and the memory interface circuit 110.

[0076] The voltage generator 150 can generate various types of voltages based on the voltage control signal CTRL_vol to perform programming, reading and erasing operations. For example, the voltage generator 150 can generate a programming voltage, a reading voltage, a programming verification voltage, an erasing voltage, etc. as a word line voltage VWL, or can generate a bit line voltage as a core voltage Vcc.

[0077] The row decoder 160 may select one of a plurality of word lines WL and one of a plurality of string selection lines SSL in response to the row address X-ADDR. For example, during a program operation, the row decoder 160 may apply a program voltage and a program verification voltage to the selected word line, and may apply a read voltage to the selected word line during a read operation.

[0078] Figure 6 is a diagram illustrating a nonvolatile memory device according to example embodiments. Figure 6 It is shown Figure 4 1 to 130_4 and page buffers 140_1 to 140_4 included in a memory cell array 130 of FIG. 1 .

[0079] Reference Figure 4 and Figure 6 , the memory cell array 130 may include a plurality of planes 130_1 to 130_4. The plurality of planes 130_1 to 130_4 may include Figure 4 The plurality of memory blocks BLK1 to BLKz are shown. Figure 6 , although the plurality of planes 130_1 to 130_4 are illustrated as consisting of four, the inventive concept is not limited thereto.

[0080] The page buffer 140 may include a plurality of page buffers 140_1 to 140_4. The plurality of page buffers 140_1 to 140_4 may be arranged to correspond to the plurality of planes 130_1 to 130_4, respectively, and may be connected to the plurality of planes 130_1 to 130_4, respectively. The plurality of page buffers 140_1 to 140_4 may include Figure 4 The page buffer 140 includes a plurality of page buffers PB1 to PBn.

[0081] The control logic 120 may provide a page buffer control signal PCNT to each of the plurality of page buffers 140_1 to 140_4 to read data stored in each of the plurality of planes 130_1 to 130_4. In addition, in order to perform a data input / output operation of the plurality of planes 130_1 to 130_4, first to fourth core voltages Vcc1 to Vcc4 and / or first to fourth core currents Icc1 to Icc4 may be provided to each of the plurality of page buffers 140_1 to 140_4.

[0082] The control logic 120 may output only data stored in one plane among the plurality of planes, and may perform a data input operation on only one plane among the plurality of planes. In addition, the control logic 120 may operate in a plane independent read (PIR) method or a plane independent core (PIC) method, and may control the configuration of the nonvolatile memory device 100 to read data stored in two or more planes among the plurality of planes 1301 to 1304 in parallel. Therefore, when one of the plurality of planes occupies a data bus within a channel and performs a data input / output operation, one of the remaining plurality of planes may perform a read operation in parallel internally.

[0083] Figure 7 is a data frame of noise status data according to an example embodiment. Figure 8 is a data frame of noise status data according to an example embodiment. Fig. 9 and Fig.10 is a diagram illustrating a current noise detection unit according to example embodiments. Fig.11 and Fig.12 is a diagram illustrating a voltage noise detection unit according to example embodiments.

[0084] Reference Figure 4 , Figure 6 as well as Figures 7 to 11, the noise state data NSD may include first to fourth noise state data NSD1 to NSD4 and path noise state data NSDW. In addition, the current noise detection unit 121 may include first to fourth current noise detection units 121_1 to 121_4 and a path current noise detection unit 121_W. The voltage noise detection unit 123 may include first to fourth voltage noise detection units 123_1 to 123_4 and a path voltage noise detection unit 123_W.

[0085] For ease of explanation, hereinafter, the first noise state data NSD1, the first current noise detection unit 121_1 and the first voltage noise detection unit 123_1, and the first to fourth noise state data NSD1 to NSD4 will be mainly described to describe the first to fourth current noise detection units 121_1 to 121_4 and the first to fourth voltage noise detection units 123_1 to 123_4.

[0086] The first noise state data NSD1 may correspond to the second to fourth noise state data NSD2 to NSD4, the first current noise detection unit 121_1 may correspond to the second to fourth current noise detection units 121_2 to 121_4, and the first voltage noise detection unit 123_1 may correspond to the second to fourth voltage noise detection units 123_2 to 123_4. Obviously, the description of the first to fourth noise state data NSD1 to NSD4, the first to fourth current noise detection units 121_1 to 121_4, and the first to fourth voltage noise detection units 123_1 to 123_4 may be replaced by the description of the first noise state data NSD1, the first current noise detection unit 121_1, and the first voltage noise detection unit 123_1, respectively.

[0087] The first noise status data NSD1 may be noise status data occurring in the first plane 130_1. Figure 7 The first noise state data NSD1 may include first current noise state data CNSD1, first voltage noise state data VNSD1 and a first flag bit FB1. The first noise state data NSD1 may be, for example, 1 byte, but is not limited thereto.

[0088] The first current noise state data CNSD1 may be a noise index value caused by a peak current generated by the first core current Icc1 input to the first page buffer 1401. According to example embodiments, the first current noise state data CNSD1 may be an index value having a 4-bit number, but is not limited thereto.

[0089] The first current noise detection unit 121_1 may compare the first core current Icc1 with the first to fifteenth reference current values ​​Icc_ref1 to Icc_ref15 and may generate first current noise state data CNSD1 and a first current noise detection bit CFB1 to be temporarily stored in the first current noise register unit 122_1 .

[0090] The first current noise detection bit CFB1 may be a flag bit that determines whether noise sufficient to cause an error in a data input / output operation in the first core current Icc1 is detected by comparing the first core current Icc1 with an expected (or alternatively, predetermined) detection current value.

[0091] Reference Fig.10 , the first current noise detection unit 1211 may generate the first current noise state data CNSD1 corresponding to a value between the fourteenth reference current value Icc_ref14 and the fifteenth reference current value Icc_ref15 at the measurement time tm1. The first current noise detection unit 121_1 may generate the first current noise detection bit CFB1 corresponding to “noise detection” at the measurement time tm1 using the thirteenth reference current value Icc_ref13 as the reference detection current value (Ith) during the measurement.

[0092] The number of the first to fifteenth reference current values ​​Icc_ref1 - Icc_ref15 is 15, but this number is only an example, and the number of reference current values ​​may vary according to example embodiments.

[0093] The first voltage noise state data VNSD1 may be a noise index value caused by a ripple phenomenon occurring at the first core voltage Vcc1 applied to the first page buffer 140_1. According to example embodiments, the first voltage noise state data VNSD1 may be an index value having a 3-bit number, but is not limited thereto.

[0094] The first voltage noise detection unit 123_1 may compare the first core voltage Vcc1 with the first to seventh reference voltage values ​​Vcc_ref1 to Vcc_ref7 and may generate first voltage noise state data VNSD1 and a first voltage noise detection bit VFB1 to be temporarily stored in the first voltage noise register unit 124_1 .

[0095] The first voltage noise detection bit VFB1 may be a flag bit that compares the first core voltage Vcc1 with a detection voltage value to determine whether noise sufficient to cause an error in a data input / output operation in the first core voltage Vcc1 is detected.

[0096] Reference Fig.12, the first voltage noise detection unit 123_1 may generate the first voltage noise state data VNSD1 corresponding to a value between the fifth reference voltage value Vcc_ref5 and the sixth reference voltage value Vcc_ref6 at the measurement time tm2. The first voltage noise detection unit 1231 may generate the first voltage noise detection bit VFB1 corresponding to “noise detection” at the measurement time tm2 using the fifth reference voltage value Vcc_ref5 as the reference detection voltage value Vth during the measurement.

[0097] The number of the first to seventh reference voltage values ​​Vcc_ref1 to Vcc_ref7 is 7, but this number is only an example, and the number of reference voltage values ​​may vary according to example embodiments.

[0098] The first flag bit FB1 may be a flag bit for determining noise detection in the first plane 1301. The first flag bit FB1 may be generated, for example, by an OR operation of the first current noise detection bit CFB1 and the first voltage noise detection bit VFB1, but is not limited thereto. According to example embodiments, Figure 1 The storage controller 200 may determine the noise detection state of the first plane 1301 through the first flag bit FB1.

[0099] The path noise state data NSDW may be noise state data generated in the nonvolatile memory device 100 corresponding to one path. Figure 8 , the path noise state data NSDW may include path current noise state data CNSDW, first voltage noise state data VNSD1 and path flag bit FBW. The path noise state data NSDW may be, for example, 1 byte, but is not limited thereto.

[0100] According to example embodiments, the path current noise state data CNSDW may be generated based on the first to fourth current noise state data CNSD1 to CNSD4. As an example, the path current noise state data CNSDW may be an average value of the first to fourth current noise state data CNSD1 to CNSD4. According to example embodiments, the path current noise state data CNSDW may be an index value having a 4-bit number, but the number of bits is not limited thereto.

[0101] The path current noise detection unit 121_W may generate path current noise state data CNSDW and a path current noise detection bit CFBW based on the first to fourth current noise state data CNSD1 to CNSD4 to be temporarily stored in the path current noise register unit 122_W.

[0102] For example, the path current noise detection bit CFBW can be generated by comparing the path current noise state data CNSDW with an expected (or alternatively, predetermined) value, and can be a flag bit that determines whether noise sufficient to cause an error in the overall data input / output operation is detected. According to example embodiments, the path voltage noise state data VNSDW can be generated based on the first to fourth voltage noise state data VNSD1 to VNSD4. As an example, the path voltage noise state data VNSDW can be an average value of the first to fourth voltage noise state data VNSD1 to VNSD4. According to example embodiments, the path voltage noise state data VNSDW can be an index value having a 3-bit number, but the number of bits is not limited thereto.

[0103] The path voltage noise detection unit 123_W may generate path voltage noise state data VNSDW and a path voltage noise detection bit VFBW based on the first to fourth voltage noise state data VNSD1 to VNSD4 to be temporarily stored in the path voltage noise register unit 124_W.

[0104] For example, the path voltage noise detection bit VFBW may be generated by comparing the path voltage noise status data VNSDW with an expected (or alternatively, predetermined) value, and may be a flag bit that determines whether noise sufficient to cause an error in the overall data input / output operation is detected.

[0105] The path flag bit FBW may be a flag bit for determining noise detection in the nonvolatile memory device 100 corresponding to one path. The path flag bit FBW may be generated by an OR operation of the path current noise detection bit CFBW and the path voltage noise detection bit VFBW, but is not limited thereto. According to example embodiments, Figure 1 The memory controller 200 may determine the noise detection state of the nonvolatile memory device 100 through the path flag bit FBW.

[0106] exist Figures 9 to 12 In the embodiment, the noise state data NSD of the paths and / or planes may be generated based on the core voltages Vcc1 to Vcc4 applied to the page buffer 140 and the core currents Icc1 to Icc4 inputted, but example embodiments are not limited thereto. The control logic 120 may generate the noise state data NSD based on any one of the voltages and currents (e.g., a program voltage, a program verification voltage, an erase voltage, etc.) of the nonvolatile memory device 100 for data input / output operations.

[0107] Fig.13 is a flowchart illustrating the operation of a storage device according to an example embodiment. Fig.14 and Fig.15is a diagram illustrating an operation of a storage device according to example embodiments.

[0108] Reference Figures 1 to 6 , Fig.13 and Fig.14 , the memory controller 200 may provide a data input / output command through the command address pin (S110). The memory controller 200 may provide a read command as a command address signal CA to the 1_3 nonvolatile memory device NVM13 corresponding to the 1_3 path W13 through the first to second pins P21 to P22 corresponding to the command address pin at time t1.

[0109] The memory controller 200 may perform a data input / output operation based on the data input / output command ( S120 ).

[0110] The memory controller 200 may provide the data signal DQ to the 1_3 nonvolatile memory device NVM13 based on the read command through the plurality of third pins P23 from time t2 after time t1 to time t9. During a third period PERIOD3 between time t2 and time t9, the 1_3 nonvolatile memory device NVM13 may receive the data signal DQ from the memory controller 200 through the plurality of third pins P13.

[0111] In addition, during the third period PERIOD3 between time t2 and time t9, i.e., the execution period of the data input / output operation, the data bus connected to the first channel CH1 of the nonvolatile memory device NVM13 may be occupied, and therefore, the data input / output operation in the first channel CH1 may not be performed during the third period PERIOD3.

[0112] According to example embodiments, the time range of the third period PERIOD3 may be 1 μs to 900 μs, for example, about 10 μs to about 900 μs.

[0113] The memory controller 200 may provide a noise monitoring command through a command address pin according to a desired (or alternatively, predetermined) situation during a data input / output operation ( S130 ).

[0114] One of the desired (or alternatively, predetermined) situations may include a situation where a nonvolatile memory device corresponding to one of a plurality of paths connected to one channel is in an input / output state, and a plurality of nonvolatile memory devices corresponding to the remaining paths are in a busy state.

[0115] In addition, another desired (or alternatively, predetermined) situation may include a situation where one plane among a plurality of planes connected to one channel is in an input / output state and the remaining plurality of planes are in a busy state.

[0116] A desired (or alternatively, predetermined) situation may be a noise-susceptible situation where various configurations are interleaved with each other within one channel.

[0117] Before time t3 during the third period PERIOD3, the memory controller 200 may include Figure 2 Since the 1_1 path W11 of the first channel CH1 is in the ready state, the expected (or alternatively, predetermined) condition may not be satisfied, and thus the memory controller 200 may not provide the noise monitoring command before time t3 during the third period PERIOD3.

[0118] At time t3 , the memory controller 200 may provide an operation status update command to the 1_1 nonvolatile memory device NVM11 corresponding to the 1_1 path W11 through the first to second pins P21 to P22 .

[0119] After time t3 , during a first period PERIOD1 between time t4 and time t5 , the 1_1 nonvolatile memory device NVM11 may provide ready / busy state data RBSD to the memory controller 200 through the first to second pins P11 to P12 based on the operation state update command.

[0120] According to example embodiments, the first period PERIOD1 may be an execution period of an operation state update operation, and the time range of the first period PERIOD1 may be 1 ns to 900 ns, for example, about 10 ns to about 900 ns. According to example embodiments, by the difference between the execution period of the first period PERIOD1 and the execution period of the third period PERIOD3, the storage controller 200 may quickly determine the operation state of the connected non-volatile memory device and whether the desired (or alternatively, predetermined) condition is met, and noise detection may be efficiently performed in an interleaved condition susceptible to noise.

[0121] In addition, refer to Fig.15 , by updating the operation state for the 1_1 path W11 in the first period PERIOD1, the memory device 10a can satisfy the desired (or alternatively, predetermined) condition because the 13 nonvolatile memory device NVM13 of the 1_3 path W13 within the first channel CH1 of the memory device 10a is in the input / output state, and the nonvolatile memory devices NVM11 to NVM12 and NVM14 to NVM1n corresponding to the remaining 1_1 to 1_2 paths W11 to W12 and 1_4 to 1_n paths W14 to W1n are in the busy state. The memory controller 200 can confirm that the desired (or alternatively, predetermined) condition is satisfied based on the updated ready / busy map RB_M.

[0122] The memory controller 200 may provide a noise monitoring command to the 1_3 nonvolatile memory device NVM13 of the 1_3 path W13 through the first to second pins P21 to P22 at time t6 within the third period PERIOD3. According to example embodiments, the operation state of the 1_3 nonvolatile memory device NVM13 of the 1_3 path W13 may be an input / output state.

[0123] The memory controller 200 may receive noise state data NSD through a command address pin during a data input / output operation ( S140 ).

[0124] During the second period PERIOD2 between time t7 and time t8 within the third period PERIOD3, the 1_3 nonvolatile memory device NVM13 may provide the noise status data NSD to the memory controller 200 through the first to second pins P11 to P12.

[0125] The memory controller 200 may receive the noise status data NSD through the first to second pins P21 to P22 during the third period PERIOD3.

[0126] According to example embodiments, the second period PERIOD2 may be a period of execution of a reception operation of the noise status data NSD, and a time range of the second period PERIOD2 may be about 1 ns to about 900 ns, for example, 10 ns to 900 ns.

[0127] According to example embodiments, the memory controller 200 may improve operation performance by performing a noise monitoring operation during a data input / output operation through a difference between an execution period of the second period PERIOD2 and an execution period of the third period PERIOD3 .

[0128] After time t8, the memory controller 200 may confirm the noise detection through the noise status data NSD (S150).

[0129] When the path flag bit FBW of the noise status data NSD indicates “noise detected”, the memory controller 200 may end the data output operation by providing a return signal command to the nonvolatile memory device NVM13 at time t10 after the third period PERIOD3 ends.

[0130] When the noise detection is confirmed by the noise status data NSD, the data input / output operation may be verified ( S160 ).

[0131] When the path flag bit FBW of the noise status data NSD indicates “noise detection,” a verification operation may be performed. According to example embodiments, after time t9, the memory controller 200 may verify an ECC generated by a read operation of a third period PERIOD3.

[0132] When a data input operation is performed during the third period PERIOD3 and the path flag bit FBW of the noise status data NSD indicates “noise detection”, according to example embodiments, the memory controller 200 may perform a recovery operation on data input after time t9 .

[0133] Fig.16 is a diagram illustrating an operation of a storage device according to example embodiments. Fig.16 Can be used with Fig.14 Correspondingly, and for the sake of convenience, Fig.16 The description will focus on Fig.14 difference.

[0134] Reference Figures 1 to 6 , Fig.13 and Fig.16 At time t6 within the third period PERIOD3, the memory controller 200 may provide a noise monitoring command to the 1n nonvolatile memory device NVM1n of the 1n path W1n through the first to second pins P21 to P22. According to example embodiments, the operation state of the 1n nonvolatile memory device NVM1n of the 1n path W1n may be a busy state.

[0135] During the second period PERIOD2 between time t7 and time t8 within the third period PERIOD3 , the 1_n nonvolatile memory device NVM1n may provide the noise status data NSD to the memory controller 200 through the first to second pins P11 to P12 .

[0136] Likewise, the memory controller 200 may receive the noise status data NSD through the first to second pins P21 to P22 during the third period PERIOD3.

[0137] Fig.17 is a diagram illustrating a storage device according to example embodiments. Fig.17 Represents the ready / busy map RB_M' including the ready / busy status data of the plane. Fig.17 Can be used with Figure 2 Correspondingly, and for the sake of convenience, Fig.17 The description will focus on Figure 2 difference.

[0138] Reference Figure 1 , Figure 4 , Figure 6 and Fig.17 , the ready / busy map RB_M' according to an example embodiment may include ready / busy status data of a plane within each of the nonvolatile memory devices NVM11 to NVMmn in a bitmap format. The memory controller 200 according to an example embodiment may check the operation status of a plurality of planes connected to the memory controller 200 through the ready / busy map RB_M'.

[0139] Reference Fig.17 , in the first channel CH1, through the ready / busy mapping RB_M', the storage controller 200 can confirm that the 1_11 plane P111, the 1_12 plane P112, the 1_13 plane P113, the 1_21 plane P121, the 1_22 plane P122, the 1_23 plane P123 and the 1_n1 to 1_n4 planes Pln1 to P1n4 are in a busy state, the 1_14 plane P114 is in a ready state, and the 1_24 plane P124 is in an input / output state. In addition, in the nth channel CHn, through the ready / busy mapping RB_M', the storage controller 200 can confirm that the m_n1th plane Pmn1 is in a busy state, the m_n2th plane Pmn2 is in an input / output state, and the m_n3th to m_n4th planes Pmn3 to Pmn4 are in a ready state.

[0140] 1_11 to 1_14 planes P111 to P114 may correspond to Figure 1 The 1_1 path W11, and the 1_21 to 1_24 planes P121 to P124 may correspond to Figure 1 The 1_2 path W12, and the 1_n1 to 1_n4 planes P1n1 to P1n4 may correspond to Figure 1 The 1_n path W1n, and the m_n1 to m_n4 planes Pmn1 to Pmn4 can correspond to Figure 1 The m_nth path Wmn.

[0141] Fig.17 and Fig.18 is a diagram illustrating an operation of a storage device according to example embodiments. Fig.17 and Fig.18 Can be respectively Fig.15 and Fig.14 Correspondingly, and for the sake of convenience, Fig.17 and Fig.18 The description will focus on Fig.14 and Fig.15 difference.

[0142] Reference Figure 1 , Figures 3 to 6 , Fig.13 , Fig.17 and Fig.18, the memory controller 200 may provide data input / output commands through command address pins.

[0143] At time t11, the memory controller 200 may provide a read command as a command address signal CA to the 1_24 plane P124 through the first to second pins P21 to P22 corresponding to the command address pins.

[0144] The memory controller 200 may perform a data input / output operation based on the data input / output command (S120). The memory controller 200 may provide a data signal DQ to the 1_24 plane P124 based on the read command through the plurality of third pins P23 from time t12 to time t19 after time t11. During a sixth period PERIOD6 between time t12 and time t19, the 1_24 plane P124 may receive the data signal DQ from the memory controller 200 through the plurality of third pins P13.

[0145] right Fig.14 The description of the third period PERIOD3 in can be applied to the sixth period PERIOD6.

[0146] The memory controller 200 may provide a noise monitoring command through a command address pin according to desired (or alternatively, predetermined) circumstances during a data input / output operation.

[0147] In addition, another desired (or alternatively, predetermined) situation may include a situation where one plane among a plurality of planes connected to one channel is in an input / output state and the remaining plurality of planes are in a busy state.

[0148] Before time t13 during the sixth period PERIOD6, the memory controller 200 may include Fig.17 Because the 1_14 plane P114 of the first channel CH1 is in the ready state, it may not meet the expected (or alternatively, predetermined) situation, so the memory controller 200 may not provide the noise monitoring command before time t13 during the sixth period PERIOD6.

[0149] At time t13, the memory controller 200 may provide an operation status update command to the 1_14 plane P114 through the first to second pins P21 to P22.

[0150] After time t13, during a fourth period PERIOD4 between time t14 and time t15, the 1_14 plane P114 may provide the ready / busy state data RBSD to the memory controller 200 through the first to second pins P11 to P12 based on the operation state update command. Fig.14The description of the first time period PERIOD1 in FIG. 1 can be applied to the fourth time period PERIOD4 .

[0151] In addition, refer to Fig.19 , by updating the operation state for the 1_14 plane P114 in the fourth period PERIOD4, the memory device 10a can meet the desired (or alternatively, predetermined) situation because the 1_24 plane P124 in the first channel CH1 is in the input / output state, and the remaining 1_11 to 1_23 planes P111 to P123 and 131 to 1n4 planes P131 to P1n4 are in the busy state. The memory controller 200 can confirm that the desired (or alternatively, predetermined) situation is met based on the updated ready / busy map RB_M'.

[0152] The memory controller 200 may provide a noise monitoring command to the 1_24 plane P124 through the first to second pins P21 to P22 at time t16 within the sixth period PERIOD6. According to example embodiments, the operation state of the 1_24 plane P124 may be an input / output state.

[0153] The memory controller 200 may receive noise state data NSD through a command address pin during a data input / output operation ( S140 ).

[0154] During a fifth period PERIOD5 between time t17 and time t18 within the sixth period PERIOD6, the 1-24 plane P124 may provide the noise status data NSD to the memory controller 200 through the first to second pins P11 to P12. Fig.14 The description of the second time period PERIOD2 in can be applied to the fifth time period PERIOD5.

[0155] The memory controller 200 may receive the noise status data NSD through the first to second pins P21 to P22 during the sixth period PERIOD6.

[0156] After time T18, the memory controller 200 may confirm the noise detection through the noise status data NSD (S150).

[0157] When the flag bit of the noise status data NSD of the 1_24 plane P124 indicates “noise detected”, the memory controller 200 may end the data output operation by providing a return signal command to the 1_24 plane P124 at time t20 after the sixth period PERIOD6 ends.

[0158] When the noise detection is confirmed by the noise status data NSD, the data input / output operation may be verified ( S160 ).

[0159] When the flag bit of the 1_24 plane P124 of the noise status data NSD indicates “noise detection,” a verification operation may be performed. According to example embodiments, the memory controller 200 may perform verification through a read operation in a sixth period PERIOD6 after time t19.

[0160] According to example embodiments, when a data input operation is performed during the sixth period PERIOD6 and the flag bit of the noise status data NSD indicates 'noise detection', the memory controller 200 may perform a recovery operation on data input after time t19.

[0161] Fig. 20 is a diagram illustrating the operation of a storage device according to an example embodiment. For ease of explanation, Fig. 20 Can be used with Figure 8 corresponding to, and Fig. 20 The description will focus on Fig.18 difference.

[0162] Reference Figures 1 to 6 , Fig.13 and Fig. 20 , the memory controller 200 may provide a noise monitoring command to the 1_n4 plane P1n4 through the first to second pins P21 to P22 at time t16 within the sixth period PERIOD6. According to example embodiments, the operation state of the 1_n4 plane P1n4 may be a busy state.

[0163] During a fifth period PERIOD5 between time t17 and time t18 within the sixth period PERIOD6, the 1-n4 plane P1n4 may provide the noise status data NSD to the memory controller 200 through the first to second pins P11 to P12.

[0164] Likewise, the memory controller 200 may receive the noise status data NSD through the first to second pins P21 to P22 during the sixth period PERIOD6.

[0165] Fig.21 is a block diagram illustrating an SSD system to which a storage device is applied according to an example embodiment. Fig.21 , the SSD system 1000 may include a host 1100 and an SSD 1200 .

[0166] The SSD 1200 may exchange a signal SIG with the host 1100 through a signal connector 1201, and receive a power PWR input through a power connector 1202. The SSD 1200 may include an SSD controller 1210, a plurality of flash memories 1221 to 122m, an auxiliary power supply 1230, and a buffer memory 1240. The plurality of flash memories 1221 to 122m may be connected to the SSD controller 1210 through a plurality of channels, respectively.

[0167] The SSD controller 1210 may control the plurality of flash memories 1221 to 122m in response to a signal SIG received from the host 1100. The SSD controller 1210 may store a signal generated internally or transmitted externally (eg, a signal SIC received from the host 1100) in the buffer memory 1240. The SSD controller 1210 may be implemented as described above with reference to Figures 1 to 20 The storage controller 200 described above. For example, the SSD controller 1210 may transmit a command / address CMD / ADDR through a pin different from a pin that transmits data DATA in one channel. Using this, the SSD controller 1210 may efficiently perform noise detection by receiving an operation status signal and / or a noise status signal for a path or plane during an input / output operation of the data DATA, and may improve the overhead of overlapping a noise monitoring operation and a data input / output operation.

[0168] The plurality of flash memories 1221 to 122m may operate under the control of the SSD controller 1.210. The auxiliary power supply 1230 may be connected to the host 1100 through the power connector 1202. Each of the plurality of flash memories 1221 to 122m may utilize the above reference Figures 1 to 20 For example, each of the plurality of flash memories 1221 to 122m may receive a command / address CMD / ADDR through a pin different from a pin receiving data DATA.

[0169] The auxiliary power supply 1230 may be connected to the host 1100 through the power connector 1202. The auxiliary power supply 1230 may receive power PWR from the host 1100 and charge the power PWR. When the power supply from the host 1100 is not smooth, the auxiliary power supply 1230 may provide power to the SSD 1200.

[0170] Fig. 22 is a block diagram illustrating a data center to which a storage device is applied according to an example embodiment. Fig. 22 , the network system 2000 is a facility that collects various data and provides services, and may be referred to as a data center or a data storage center. The network system 2000 may include application servers 2100 to 2100n and storage servers 2200 to 2200m, and the application servers 2100 to 2100n and the storage servers 2200 to 2200m may be referred to as computing nodes. According to example embodiments, the number of application servers 2100 to 2100n and the number of storage servers 2200 to 2200m may be selected in various ways, and the number of application servers 2100 to 2100n and the number of storage servers 2200 to 2200m may be different.

[0171] Application servers 2100 to 2100n and storage servers 2200 to 2200m can communicate with each other through network 2300. Network 2300 can be implemented using Fibre Channel (FC) or Ethernet. At this time, FC is a medium for high-speed data transmission, and an optical switch providing high performance / high availability can be used. According to the access method of network 2300, storage servers 2200 to 2200m can be provided as file storage, block storage or object storage.

[0172] In an example embodiment, the network 2300 may be a storage-specific network, such as a storage area network SAN. For example, the SAN may be an FC-SAN using an FC network and may be implemented according to the FC protocol FCP. In an example embodiment, the SAN may be an IP-SAN using a TCP / IP network and may be implemented according to the SCSI or Internet SCSI (iSCSI) protocol over TCP / IP. In an example embodiment, the network 2300 may be a general network, such as a TCP / IP network. For example, the network 2300 may be implemented according to protocols such as FC over Ethernet (FCoE), network attached storage (NAS), and NVMe over Fabrics (NVMe-oF).

[0173] Hereinafter, the description will be mainly focused on the application server 2100 and the storage server 2200. The description of the application server 2100 may also be applied to other application servers 2100n, and the description of the storage server 2200 may also be applied to other storage servers 2200m.

[0174] The application server 2100 may include a processor 2110 and a memory 2120. The processor 2110 may control the overall operation of the application server 2100 and may access the memory 2120 to execute instructions and / or data loaded in the memory 2120. According to example embodiments, the number of processors 2110 and memory 2120 included in the application server 2100 may be selected in various ways. In an example embodiment, the processor 2110 and the memory 2120 may be configured as a processor-memory pair. In an example embodiment, the number of processors 2110 and the number of memories 2120 may be configured differently.

[0175] The application server 2100 may further include a storage device 2150. At this time, the number of storage devices 2150 included in the application server 2100 may be selected in various ways according to example embodiments. The processor 2110 may provide a command to the storage device 2150, and the storage device 2150 may operate in response to the command received from the processor 2110. However, the inventive concept is not limited thereto, and the application server 2100 may not include the storage device 2150.

[0176] The application server 2100 may further include a switch 2130 and a network interface card (NIC) 2140. The switch 2130 may selectively connect the processor 2110 and the storage device 2150 or may selectively connect the NIC 2140 and the storage device 2150 according to the control of the processor 2110. The NIC 2140 may include a wired interface, a wireless interface, a Bluetooth interface, an optical interface, etc. In an example embodiment, the processor 2110 and the NIC 2140 may be integrated into one. In an example embodiment, the storage device 2150 and the NIC 2140 may be integrated into one.

[0177] The application server 2100 may store the data requested by the user or client to one of the storage servers 2200 to 2200m through the network 2300. In addition, the application server 2100 may obtain the data requested by the user or client from one of the storage servers 2200 to 2200m through the network 2300. For example, the application server 2100 may be implemented as a network server, a database management system (DBMS), etc.

[0178] The application server 2100 may access the memory 2120n or the storage device 2150n included in other application servers 2100n through the network 2300, or may access the memory 2220 and 2220m or the storage devices 2250 and 2250m included in the storage servers 2200 and 2200m through the network 2300. Therefore, the application server 2100 may perform various operations on the data stored in the application servers 2100 and 2100n and / or the storage servers 2200 and 2200m. For example, the application server 2100 may execute instructions to move or copy data between the application servers 2100 and 2100n and / or the storage servers 2200 and 2200m. In this case, for security or privacy, the data may be moved through the network 2300 in an encrypted state.

[0179] The storage server 2200 may include a processor 2210 and a memory 2220. The processor 2210 may control the overall operation of the storage server 2200 and may access the memory 2220 to execute instructions and / or data loaded into the memory 2220. According to example embodiments, the number of processors 2210 and the number of memories 2220 included in the storage server 2200 may be selected in various ways. In an example embodiment, the processor 2210 and the memory 2220 may be configured as a processor-memory pair. In an example embodiment, the number of processors 2210 and the number of memories 2220 may be configured differently.

[0180] The processor 2210 may include a single-core processor or a multi-core processor. For example, the processor 2210 may include a general-purpose processor, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a microcontroller (MCU), a microprocessor, a network processor, an embedded processor, and a field programmable gate array (FPGA), an application-specific instruction set processor (ASIP), an application-specific integrated circuit processor (ASIC), etc.

[0181] The storage server 2200 may further include at least one storage device 2250. According to an embodiment, the number of storage devices 2250 included in the storage server 2200 may be selected in various ways. The storage device 2250 may include a controller (CTRL) 2251, a NAND flash memory (NAND) 2252, a DRAM 2253, and an interface (I / F) 2254. Hereinafter, the configuration and operation of the storage device 2250 will be described in detail. The following description of the storage device 2250 may also be applied to the other storage devices 2150, 2150n, and 2250m.

[0182] The interface 2254 may provide a physical connection between the processor 2210 and the controller 2251 and a physical connection between the NIC 2240 and the controller 2251. For example, the interface 2254 may be implemented in a direct-attached storage DAS method of directly connecting the storage device 2250 with a dedicated cable. In addition, for example, the interface 2254 supports various interface methods such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), and Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVM Express (NVMe), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) Card, Multimedia Card (MMC), Embedded Multimedia Card (eMMC), and Compact Flash (CF) Card interfaces.

[0183] The controller 2251 may control the overall operation of the storage device 2250. The controller 2251 may program data into the NAND flash memory 2252 in response to a program command, or may read data from the NAND flash memory 2252 in response to a read command. For example, the program command and / or the read command may be provided by the processor 2210 in the storage server 2200. The program command and / or the read command may be provided by the processor 2210 from the processor 2210m in other storage servers 2200m or from the processors 2110, 2110n in the application servers 2100, 2100n, or may be provided directly.

[0184] The NAND flash memory 2252 may include a plurality of NAND flash memory cells. However, the inventive concept is not limited thereto, and the storage device 2250 may include a nonvolatile memory other than the NAND flash memory 2252, such as a resistive RAM (ReRAM), a phase change RAM (PRAM), a magnetic RAM (MRAM), a magnetic storage medium, or an optical storage medium, etc.

[0185] Dynamic RAM (DRAM) 2253 may be used as a buffer memory. For example, DRAM 2253 may be a double data rate synchronous DRAM (DDR SDRAM), a low power DDR (LPDDR) SDRAM, a graphic DDR (GDDR) SDRAM, a Rambus DRAM (RDRAM), or a high bandwidth memory (HBM). However, the inventive concept is not limited thereto, and in addition to DRAM, the storage device 2250 may use a volatile memory or a non-volatile memory as a buffer memory. DRAM 2253 may temporarily store (buffer) data to be written to or read from the NAND flash memory 2252.

[0186] The storage server 2200 may further include a switch 2230 and a NIC 2240. The switch 2230 may selectively connect the processor 2210 and the storage device 2250 according to the control of the processor 2210, or may selectively connect the NIC 2240 and the storage device 2250. In an example embodiment, the processor 2210 and the NIC 2240 may be integrated into one. In an example embodiment, the storage device 2250 and the NIC 2240 may be integrated into one.

[0187] The storage devices 2150, 2150n, 2250 and 2250m can be the same as those mentioned above. Figures 1 to 20 The controller 2251 may send a command / address CMD / ADDR to the NAND flash memory 2252 in response to a request provided from one of the processors 2110, 2110n, 2210, 2210m. The controller 2251 may send a command / address CMD / ADDR through a pin different from a pin through which the data DATA is sent. Using this, the controller 2251 may receive an operation status signal and / or a noise status signal of a path or plane within the NAND flash memory 2252 during an input / output operation of the data DATA, and may efficiently perform noise detection to improve the overhead of overlapping noise monitoring operations and data input / output operations.

[0188] Any functional blocks shown in the figure and described above can be implemented in a processing circuit, such as hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof. For example, the processing circuit can more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0189] Although some example embodiments have been described in detail above, the scope of the inventive concept is not limited to the disclosed example embodiments, and a person skilled in the art may make various modifications and improvements to the disclosed example embodiments without substantially departing from the spirit or scope of the inventive concept as defined by the claims and their equivalents.

Claims

1. A nonvolatile memory device, comprising: A data pin configured to output a data signal; as well as A command address pin is separated from the data pin, the command address pin is configured to receive a read command corresponding to the data signal and output noise status data during a data output operation in which the data signal is output through the data pin in response to the read command.

2. The nonvolatile memory device according to claim 1, wherein: The command address pins are configured to receive a noise monitoring command for the noise status data after receiving the read command, and output the noise status data in response to the noise monitoring command.

3. The nonvolatile memory device according to claim 2, further comprising: a register unit configured to temporarily store a noise index value of the noise state data, The nonvolatile memory device is configured to output the noise status data based on the noise index value in response to the noise monitoring command.

4. The nonvolatile memory device according to claim 3, wherein: The noise status data includes a flag bit corresponding to a noise detection status.

5. The nonvolatile memory device according to claim 1, further comprising: A memory cell array comprises a first plane and a second plane different from the first plane, a first page buffer, corresponding to the first plane, a second page buffer corresponding to the second plane, and The control logic is configured to collect the noise status data for the first plane and the second plane.

6. The nonvolatile memory device according to claim 5, wherein: The noise status data includes first noise status data for the first plane and second noise status data for the second plane.

7. The nonvolatile memory device according to claim 6, wherein: The first page buffer is configured to perform the data output operation through the data pin, and A read operation is performed in the second plane.

8. The nonvolatile memory device according to claim 6, wherein: The control logic is configured to output at least one of the first noise state data and the second noise state data to the command address pin during the data output operation.

9. The nonvolatile memory device according to claim 6, wherein: The control logic is configured to perform a noise detection operation on a first core voltage applied to the first page buffer and a second core voltage applied to the second page buffer and generate the first noise status data and the second noise status data.

10. The nonvolatile memory device according to claim 1, wherein: The nonvolatile memory device is configured to perform the data output operation within a range of 10 μs to 900 μs, and The nonvolatile memory device is configured to perform an output operation of the noise status data within a range of 10 ns to 900 ns.

11. A storage device, comprising: A first nonvolatile memory device and a second nonvolatile memory device connected to a first channel, wherein the first nonvolatile memory device and the second nonvolatile memory device are configured to perform a data input operation / data output operation through the first channel; as well as Storage controller, configured as: providing a data input / output command for the data input operation / data output operation to the first nonvolatile memory device through a command address pin connected to the first channel, performing the data input operation / data output operation on the first nonvolatile memory device through a data pin connected to the first channel other than the command address pin, and Noise status data on at least one of the first nonvolatile memory device and the second nonvolatile memory device is received in parallel with the data input operation / data output operation through the command address pin.

12. The storage device according to claim 11, wherein: The memory controller is further configured to output a noise monitoring command requesting the noise status data based on a ready / busy map including first ready / busy status data of the first nonvolatile memory device and second ready / busy status data of the second nonvolatile memory device.

13. The storage device according to claim 12, wherein: The second ready / busy status data is configured to be updated through the command address pin during the data input operation / data output operation.

14. The storage device according to claim 12, wherein: The first nonvolatile memory device is configured to perform the data output operation within a range of 10 μs to 900 μs, and The second nonvolatile memory device is configured to output the second ready / busy status data within a range of 10 ns to 900 ns.

15. The storage device according to claim 11, wherein: When the first nonvolatile memory device performs the data input operation / data output operation and the second nonvolatile memory device is in a busy state, The memory controller is configured to output a noise monitoring command for the noise status data through the command address pin.

16. The storage device according to claim 15, wherein: The memory controller is configured to provide the noise monitoring command to the second non-volatile memory device.

17. A method for operating a storage device, comprising: Data input / output commands are provided through command address pins; Based on the data input / output command, performing a data input / output operation through a data pin different from the command address pin; providing a noise monitoring command via the command address pin according to the conditions during the data input / output operation; as well as In response to the noise monitoring command, noise status data is received via the command address pin.

18. The operating method according to claim 17, further comprising: The data input / output operation is verified in response to the noise status data.

19. The operating method according to claim 17, wherein: The situation described is that: A plurality of nonvolatile memory devices are connected to a channel to which the command address pin and the data pin are connected, A first nonvolatile memory device among the plurality of nonvolatile memory devices performs the data input / output operation, and The nonvolatile memory devices other than the first nonvolatile memory device among the plurality of nonvolatile memory devices are in a busy state.

20. The operating method according to claim 17, wherein: The situation described is that: A plurality of planes are connected to the command address pins and the data pins are connected to one channel, A first plane among the plurality of planes performs the data input / output operation, and The other planes among the multiple planes except the first plane are in a busy state.

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